Display panel and display device

Abstract

A display panel and a display device are provided. The display panel comprises: a touch electrode layer located at least partially in a display area of the display panel; an array gate driver located in a peripheral area of the display panel; and a crack detection circuit; wherein at least part of signal lines in the crack detection circuit comprise metal lines located in the same layer as mesh lines of the touch electrode layer.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to a display panel and a display device. Background Technology

[0002] Various types of touch panels have been developed. Examples of touch panels include one-glass-solution (OGS) touch panels, on-cell touch panels, and in-cell touch panels. On-cell touch panels offer high touch accuracy. On-cell touch panels can be further divided into single-layer-on-cell (SLOC) touch panels and multi-layer-on-cell (MLOC) touch panels. In particular, multi-touch can be achieved in MLOC touch panels, which offer excellent touch accuracy and blanking effect. Summary of the Invention

[0003] On one hand, this disclosure provides a display panel, including: a touch electrode layer at least partially located in a display area of ​​the display panel; an array gate driver located in a peripheral area of ​​the display panel; and a crack detection circuit; wherein at least a portion of the signal lines in the crack detection circuit include metal lines located in the same layer as the grid lines of the touch electrode layer.

[0004] Optionally, the crack detection circuit includes an integrated circuit and a first conductive circuit electrically connected to the integrated circuit; and the first conductive circuit includes a first touch crack sub-circuit and a first panel crack sub-circuit connected to each other, wherein at least a portion of the first touch crack sub-circuit is located in the same layer as the grid lines of the touch electrode layer; and at least a portion of the first panel crack sub-circuit is located in the same layer as the gate lines of the display panel.

[0005] Optionally, the display panel further includes a voltage supply line located in a portion of the peripheral region; wherein the display panel includes the following components arranged sequentially in the portion of the peripheral region along a direction perpendicular to the extension direction of the first touch crack sub-circuit and the first panel crack sub-circuit: a signal line of the array gate driver, a portion of the first panel crack sub-circuit, a portion of the voltage supply line, and a portion of the first touch crack sub-circuit.

[0006] Optionally, the signal lines of the gate driver on the array, the portion of the first panel crack sub-circuit, the portion of the voltage supply line, and the portion of the first touch crack sub-circuit are located in the same layer.

[0007] Optionally, the portion of the voltage supply line extends in the peripheral region in a direction substantially parallel to the extension direction of the first touch crack sub-circuit and the first panel crack sub-circuit.

[0008] Optionally, the first touch crack sub-loop includes a first touch crack detection line and a second touch crack detection line located on the same side relative to the display area, the first touch crack detection line spacing the second touch crack detection line from the display area; and the first touch crack detection line includes a first-first portion and a second-first portion located in different layers and connected to each other.

[0009] Optionally, the second-first portion is located in the same layer as the voltage supply line in the surrounding area; and the first-first portion is located in the same layer as the grid lines of the touch electrode layer.

[0010] Optionally, the display panel includes a row of first vias extending through at least the touch insulating layer; wherein the first-first portion is connected to the second-first portion through the first-first via in the row of first vias; and a plurality of grid lines of the grid electrodes of the touch electrode layer are connected to a plurality of touch signal lines through a plurality of first vias in the row of first vias.

[0011] Optionally, the first-first portion and the grid lines of the grid electrodes of the touch electrode layer are located in the same layer; and the second-first portion, the plurality of touch signal lines and the voltage supply lines in the peripheral region are located in a second signal line layer, the second signal line layer being spaced apart from the first-first portion at least by the touch insulating layer.

[0012] Optionally, the first touch crack detection line further includes a third-first portion connected to the second-first portion; the third-first portion includes: a first sub-layer located in the same layer as the second gate metal layer of the display panel; a second sub-layer located on the side of the first sub-layer away from the substrate, the second sub-layer being located in the same layer as the first signal line layer of the display panel; a third sub-layer located on the side of the second sub-layer away from the first sub-layer, the third sub-layer being located in the same layer as the second signal line layer of the display panel; and a fourth sub-layer located on the side of the third sub-layer away from the second sub-layer, the fourth sub-layer being located in the same layer as the grid lines of the touch electrode layer.

[0013] Optionally, the second touch crack detection line includes a first-second portion and a second-second portion located in different layers and connected to each other; wherein, the display panel includes a row of first vias extending at least through the touch insulating layer; the first-second portion is connected to the second-second portion through a second-first via in the row of first vias; the grid lines of the grid electrodes of the touch electrode layer are connected to a plurality of touch signal lines through a plurality of first vias in the row of first vias; the first-second portion and the grid lines of the grid electrodes of the touch electrode layer are located in the same layer; and the second-second portion and the plurality of touch signal lines are located in a second signal line layer, the second signal line layer being spaced apart from the first-first portion at least through the touch insulating layer.

[0014] Optionally, the second touch crack detection line further includes a third portion connected to the second portion; the third portion includes: a fifth sub-layer located in the same layer as the gate lines of the display panel; a sixth sub-layer located on the side of the fifth sub-layer away from the substrate, the sixth sub-layer being in the same layer as the first signal line layer of the display panel; a seventh sub-layer located on the side of the sixth sub-layer away from the fifth sub-layer, the seventh sub-layer being in the same layer as the second signal line layer of the display panel; and an eighth sub-layer located on the side of the seventh sub-layer away from the sixth sub-layer, the eighth sub-layer being in the same layer as the grid lines of the touch electrode layer.

[0015] Optionally, the first panel crack sub-circuit includes a first panel crack detection line and a second panel crack detection line located on the same side relative to the display area, the second panel crack detection line spacing the first panel crack detection line from the display area; and the first panel crack detection line includes a first-third portion, a second-third portion, and a third-third portion, the second-third portion being located in a different layer from the first-third portion and the third-third portion, the second-third portion connecting the first-third portion to the third-third portion.

[0016] Optionally, the first-third portion includes at least one sublayer located in the same layer as the gate lines of the display panel or in the same layer as the second gate metal layer; the second-third portion is located in the same layer as the voltage supply lines in the peripheral region; and the third-third portion includes at least one sublayer located in the same layer as the second gate metal layer.

[0017] Optionally, the second panel crack detection line includes a first-fourth section, a second-fourth section, and a third-fourth section, wherein the second-fourth section is located in a different layer from the first-fourth section and the third-fourth section, and the second-fourth section connects the first-fourth section to the third-fourth section.

[0018] Optionally, the first-fourth portions include at least one sublayer located in the same layer as the gate lines of the display panel or in the same layer as the second gate metal layer; the second-fourth portions are located in the same layer as the voltage supply lines in the peripheral region; and the third-fourth portions include at least one sublayer located in the same layer as the gate lines of the display panel.

[0019] Optionally, the third-fourth portion is connected to the third-second portion of the second touch crack detection line of the first touch crack sub-circuit.

[0020] Optionally, the display panel further includes: a second conductive circuit electrically connected to the integrated circuit; and a connecting line connecting the first conductive circuit and the second conductive circuit; wherein the second conductive circuit includes a second touch crack sub-circuit and a second panel crack sub-circuit connected to each other, at least a portion of the second touch crack sub-circuit being located in the same layer as the grid lines of the touch electrode layer; and at least a portion of the second panel crack sub-circuit being located in the same layer as the gate lines of the display panel.

[0021] On the other hand, this disclosure provides a display device including the display panel described herein and a printed circuit board connected to an integrated circuit in the display panel. Attached Figure Description

[0022] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0023] Figure 1 This is a schematic diagram showing the display area and surrounding area in a display panel according to some embodiments of the present disclosure.

[0024] Figure 2A Detailed structures in display areas of a display panel according to some embodiments of the present disclosure are shown.

[0025] Figure 2B Detailed structures in display areas of a display panel according to some embodiments of the present disclosure are shown.

[0026] Figure 3 This is a schematic diagram illustrating the structure of a display panel with a touch-sensitive structure according to some embodiments of the present disclosure.

[0027] Figure 4A This is a schematic diagram illustrating the structure of a touch structure according to some embodiments of the present disclosure.

[0028] Figure 4B It is along Figure 4A A cross-sectional view of line A-A' in the diagram.

[0029] Figure 4C It is along Figure 4A A cross-sectional view of line B-B' in the diagram.

[0030] Figure 5 This is a schematic diagram illustrating the structure of a display panel according to some embodiments of the present disclosure.

[0031] Figure 6 yes Figure 5 The magnified view in the first magnified region ZR1.

[0032] Figure 7A This is a schematic diagram illustrating the structure of a first touch crack sub-circuit according to some embodiments of the present disclosure.

[0033] Figure 7B This is a schematic diagram illustrating the structure of a first panel crack sub-loop according to some embodiments of the present disclosure.

[0034] Figure 7C This is a schematic diagram illustrating the structure of a second touch crack sub-circuit according to some embodiments of the present disclosure.

[0035] Figure 7D This is a schematic diagram illustrating the structure of a second panel crack sub-loop according to some embodiments of the present disclosure.

[0036] Figure 8 yes Figure 6 The magnified view in the second magnified region ZR2.

[0037] Figure 9 The connection between the grid lines of the touch electrode layer and a plurality of touch signal lines is shown in some embodiments of the present disclosure.

[0038] Figure 10A This is a schematic diagram showing the structure of a portion of a first touch crack detection line located in a portion of the peripheral region of a display panel according to some embodiments of the present disclosure.

[0039] Figure 10B This is a schematic diagram showing the structure of a portion of a second touch crack detection line located in a portion of the peripheral region of a display panel according to some embodiments of the present disclosure.

[0040] Figure 10CThis is a schematic diagram showing the structure of a portion of a first panel crack detection line located in a portion of the peripheral region of a display panel according to some embodiments of the present disclosure.

[0041] Figure 10D This is a schematic diagram illustrating the structure of a portion of a second panel crack detection line located in a portion of the peripheral region of a display panel according to some embodiments of the present disclosure.

[0042] Figure 11A It is along Figure 10A A cross-sectional view of line A-A' in the diagram.

[0043] Figure 11B It is along Figure 10A A cross-sectional view of line B-B' in the diagram.

[0044] Figure 11C It is along Figure 10B A cross-sectional view of the C-C' line in the diagram.

[0045] Figure 11D It is along Figure 10B A cross-sectional view of the D-D' line in the diagram.

[0046] Figure 12 This is an enlarged view of the display panel according to some embodiments of the present disclosure.

[0047] Figure 13 The connection between the grid lines of the touch electrode layer and a plurality of touch signal lines is shown in some embodiments of the present disclosure.

[0048] Figure 14A This is a schematic diagram showing the structure of a portion of a third touch crack detection line located in a portion of the peripheral region of a display panel according to some embodiments of the present disclosure.

[0049] Figure 14B This is a schematic diagram illustrating the structure of a portion of a fourth touch crack detection line located in a portion of the peripheral region of a display panel according to some embodiments of the present disclosure.

[0050] Figure 14C This is a schematic diagram showing the structure of a portion of a third panel crack detection line located in a portion of the peripheral region of a display panel according to some embodiments of the present disclosure.

[0051] Figure 14D This is a schematic diagram showing the structure of a portion of a fourth panel crack detection line located in a portion of the peripheral region of a display panel according to some embodiments of the present disclosure.

[0052] Figure 15A It is along Figure 14A A cross-sectional view of the E-E' line in the diagram.

[0053] Figure 15B It is along Figure 14A A cross-sectional view of line F-F' in the diagram.

[0054] Figure 15C It is along Figure 14B A cross-sectional view of the G-G' line in the diagram.

[0055] Figure 15D It is along Figure 14B A cross-sectional view of the H-H' line in the diagram. Specific Implementation

[0056] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0057] This disclosure provides, in particular, a display panel and a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a display panel. In some embodiments, the display panel includes: a touch electrode layer at least partially located in a display area of ​​the display panel; a gate-on-array driver located in a peripheral area of ​​the display panel; and a crack detection circuit. Optionally, at least a portion of the signal lines in the crack detection circuit include metal lines located in the same layer as the grid lines of the touch electrode layer.

[0058] Figure 1 This is a schematic diagram illustrating the display area and surrounding area of ​​a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 1 In some embodiments, the display device includes a display area DA and a peripheral area PA. Optionally, the display area DA and... Figure 4A The touch area TCA is basically the same as the surrounding PA area. Figure 4A The peripheral regions PA in the display area DA are substantially the same. In some embodiments, the peripheral regions PA include a first sub-region PA1 located on a first side S1 of the display area DA, a second sub-region PA2 located on a second side S2 of the display area DA, a third sub-region PA3 located on a third side S3 of the display area DA, and a fourth sub-region PA4 located on a fourth side S4 of the display area DA. Optionally, the first side S1 and the third side S3 are opposite to each other. Optionally, the second side S2 and the fourth side S4 are opposite to each other. Optionally, the first sub-region PA1 is a sub-region of the integrated circuit for the signal line of the crack detection circuit (e.g., a first conductive loop).

[0059] As used in this disclosure, the term "display area" refers to the area of ​​a display panel that actually displays an image. Optionally, the display area may include subpixel areas and inter-subpixel areas. A subpixel area refers to the light-emitting area of ​​a subpixel, such as the area corresponding to a pixel electrode in a liquid crystal display or the area corresponding to a light-emitting layer in an organic light-emitting diode display panel. An inter-subpixel area refers to the area between adjacent subpixel areas, such as the area corresponding to a black matrix in a liquid crystal display or the area corresponding to a pixel defining layer in an organic light-emitting diode display panel. Optionally, an inter-subpixel area is the area between adjacent subpixel areas within the same pixel. Optionally, an inter-subpixel area is the area between two adjacent subpixel areas of two adjacent pixels.

[0060] In some embodiments, the first sub-region PA1 includes a side region SR and one or more corner regions (e.g., a first corner region CR1 and a second corner region CR2). The one or more corner regions are located at the corners of the display panel. The one or more corner regions connect the side region SR to one or more adjacent sub-regions of the peripheral region PA. For example, the first corner region CR1 connects the side region SR to the second sub-region PA2, while the second corner region CR2 connects the side region SR to the fourth sub-region PA4.

[0061] Various implementations of the display panel disclosed herein can be carried out. Figure 2A Detailed structures in display areas of a display panel according to some embodiments of the present disclosure are shown. (Refer to...) Figure 2AIn some embodiments, the display panel includes, in the display area: a substrate BS (e.g., a flexible substrate); an active layer ACT of each of a plurality of thin-film transistors (TFTs) located on the substrate BS; a gate insulating layer GI located on the side of the active layer ACT away from the substrate BS; a gate G and a first capacitor electrode Ce1 (both being part of a first gate metal layer) located on the side of the gate insulating layer GI away from the substrate BS; an insulating layer IN located on the side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; and an insulating layer IN located on the side of the insulating layer IN away from the substrate BS. The display panel includes a second capacitor electrode Ce2 (part of the second gate metal layer) on one side of the gate insulating layer GI; an interlayer dielectric layer ILD located on the side of the second capacitor electrode Ce2 away from the gate insulating layer GI; source S and drain D (part of the first SD metal layer) located on the side of the interlayer dielectric layer ILD away from the gate insulating layer GI; a planarization layer PLN located on the side of the source S and drain D away from the interlayer dielectric layer ILD; a pixel defining layer PDL defining a sub-pixel opening and located on the side of the planarization layer PLN away from the substrate BS; and a light-emitting element LE located in the sub-pixel opening. The light-emitting element LE includes: an anode AD located on the side of the planarization layer PLN away from the interlayer dielectric layer ILD; a light-emitting layer EL located on the side of the anode AD away from the planarization layer PLN; and a cathode layer CD located on the side of the light-emitting layer EL away from the anode AD. The display panel also includes an encapsulation layer EN in the display area, which encapsulates a pseudo-light-emitting element DLE and is located on the side of the cathode layer CD away from the substrate BS. In some embodiments, the encapsulation layer EN includes: a first inorganic encapsulation sublayer CVD1 located on the side of the cathode layer CD away from the substrate BS; an organic encapsulation sublayer IJP located on the side of the first inorganic encapsulation sublayer CVD1 away from the substrate BS; and a second inorganic encapsulation sublayer CVD2 located on the side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1. The display panel further includes, in the display area: a buffer layer BUF located on the side of the encapsulation layer EN away from the substrate BS; a plurality of second electrode bridges BR2 located on the side of the buffer layer BUF away from the encapsulation layer EN; a touch insulating layer TI located on the side of the plurality of second electrode bridges BR2 away from the buffer layer BUF; a plurality of first touch electrodes TE1 located on the side of the touch insulating layer TI away from the buffer layer BUF; and a protective layer OC located on the side of the plurality of first touch electrodes TE1 away from the touch insulating layer TI.

[0062] Figure 2B Detailed structures in display areas of a display panel according to some embodiments of the present disclosure are shown. (Refer to...) Figure 2BIn some embodiments, the display panel includes, in the display area, a substrate BS (e.g., a flexible substrate); an active layer ACT of each of a plurality of thin-film transistors (TFTs) located on the substrate BS; a gate insulating layer GI located on the side of the active layer ACT away from the substrate BS; a gate G and a first capacitor electrode Ce1 (both being part of a first gate metal layer) located on the side of the gate insulating layer GI away from the substrate BS; an insulating layer IN located on the side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; a second capacitor electrode Ce2 (part of a second gate metal layer) located on the side of the insulating layer IN away from the gate insulating layer GI; and an interlayer located on the side of the second capacitor electrode Ce2 away from the gate insulating layer GI. The interlayer dielectric layer (ILD); source S and drain D (part of the first SD metal layer) located on the side of the interlayer dielectric layer (ILD) away from the gate insulating layer (GI); passivation layer PVX located on the side of the source S and drain D away from the interlayer dielectric layer (ILD); first planarization layer PLN1 located on the side of the passivation layer PVX away from the interlayer dielectric layer (ILD); second planarization layer PLN2 located on the side of the first planarization layer PLN1 away from the passivation layer PVX; relay electrode RE (part of the second SD metal layer) located on the side of the second planarization layer PLN2 away from the first planarization layer PLN1; pixel defining layer PDL defining a sub-pixel opening and located on the side of the second planarization layer PLN2 away from the substrate (BS); and light-emitting element LE located in the sub-pixel opening. The light-emitting element LE includes: an anode AD located on the side of the second planarization layer PLN2 away from the first planarization layer PLN1; a light-emitting layer EL located on the side of the anode AD away from the second planarization layer PLN2; and a cathode layer CD located on the side of the light-emitting layer EL away from the anode AD. The display panel further includes an encapsulation layer EN in the display area, which encapsulates a pseudo-light-emitting element DLE and is located on the side of the cathode layer CD away from the substrate BS. In some embodiments, the encapsulation layer EN includes: a first inorganic encapsulation sublayer CVD1 located on the side of the cathode layer CD away from the substrate BS; an organic encapsulation sublayer IJP located on the side of the first inorganic encapsulation sublayer CVD1 away from the substrate BS; and a second inorganic encapsulation sublayer CVD2 located on the side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1. The display panel further includes: a buffer layer BUF located on the side of the encapsulation layer EN away from the substrate BS; a plurality of second electrode bridges BR2 located on the side of the buffer layer BUF away from the encapsulation layer EN; a touch insulating layer TI located on the side of the plurality of second electrode bridges BR2 away from the buffer layer BUF; a plurality of first touch electrodes TE1 located on the side of the touch insulating layer TI away from the buffer layer BUF; and a protective layer OC located on the side of the plurality of first touch electrodes TE1 away from the touch insulating layer TI.Optionally, the display panel does not include a passivation layer PVX in the display area; for example, the interlayer dielectric layer ILD is in direct contact with the first planarization layer PLN1.

[0063] Reference Figure 2A and Figure 2B The display panel includes a semiconductor material layer SML, a first gate metal layer Gate1, a second gate metal layer Gate2, a first signal line layer SLL1, and a second signal line layer SLL2. The display panel also includes: an insulating layer IN located between the first gate metal layer Gate1 and the second gate metal layer Gate2; an interlayer dielectric layer ILD located between the second gate metal layer Gate2 and the first signal line layer SLL1; and at least one passivation layer PVX or planarization layer PLN located between the first signal line layer SLL1 and the second signal line layer SLL2.

[0064] Figure 3 This is a schematic diagram illustrating the structure of a display panel with a touch structure according to some embodiments of the present disclosure. In some embodiments, the touch structure further includes a plurality of first touch signal lines SL1 respectively connected to a plurality of first grid electrodes TE1, and a plurality of second touch signal lines SL2 respectively connected to a plurality of second grid electrodes TE2. The display panel also includes a touch driver integrated circuit TIC. The plurality of first touch signal lines SL1 and the plurality of second touch signal lines SL2 are connected to the touch driver integrated circuit TIC.

[0065] Figure 4A This is a schematic diagram illustrating the structure of a touch structure in a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 4A In some embodiments, the touch structure includes a plurality of first grid electrodes TE1 arranged in multiple rows and a plurality of second grid electrodes TE2 arranged in multiple columns. Adjacent rows are isolated from each other. Adjacent columns are isolated from each other. Optionally, the touch structure is a mutual capacitance touch structure. Optionally, the plurality of first grid electrodes TE1 are multiple touch sensing electrodes, and the plurality of second grid electrodes TE2 are multiple touch scanning electrodes. Optionally, the plurality of first grid electrodes TE1 are multiple touch scanning electrodes, and the plurality of second grid electrodes TE2 are multiple touch sensing electrodes.

[0066] In some embodiments, each of the plurality of first grid electrodes TE1 extends along a second direction DR2; each of the plurality of second grid electrodes TE2 extends along a first direction DR1. Optionally, the first direction DR1 and the second direction DR2 are two non-parallel directions, for example, the first direction DR1 and the second direction DR2 intersect each other. Optionally, the first direction DR1 and the second direction DR2 are perpendicular to each other. Optionally, the first direction DR1 and the second direction DR2 intersect each other at an angle other than 90 degrees.

[0067] Figure 4B It is along Figure 4A A cross-sectional view of line A-A' in the diagram. Figure 4C It is along Figure 4A A cross-sectional view of line B-B' in the diagram. (See attached image.) Figure 4A , Figure 4B and Figure 4C As shown, in some embodiments, the touch structure includes a plurality of first grid electrodes TE1 arranged in multiple rows and a plurality of second grid electrodes TE2 arranged in multiple columns. The plurality of first grid electrodes TE1 and the plurality of second grid electrodes TE2 are located in a second layer SL2. The touch structure also includes: a plurality of touch electrode bridges EB located in the first layer SL1; and a via Vb extending through the touch insulating layer TI. Optionally, the plurality of touch electrode bridges EB extend through the via Vb respectively to connect to adjacent second grid blocks in each of the plurality of columns of the plurality of second grid electrodes TE2.

[0068] In some embodiments, the display panel of this disclosure further includes a crack detection circuit. The crack detection circuit of this disclosure can detect not only cracks in the thin-film transistor array substrate of the display panel, but also cracks that appear independently in the touch structure or adjacent layers. The inventors of this disclosure have discovered a complex circuit structure capable of accurately detecting cracks in a display panel with extremely high efficiency.

[0069] Figure 5 This is a schematic diagram illustrating the structure of a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 5 In some embodiments, the crack detection circuit includes a first conductive loop CLP1 electrically connected to an integrated circuit IC. In one example, the first conductive loop CLP1 is connected to a first pin PIN1 in the integrated circuit IC. Optionally, the crack detection circuit also includes a second conductive loop CLP2 electrically connected to the integrated circuit IC. In another example, the second conductive loop CLP2 is connected to a second pin PIN2 in the integrated circuit IC. Figure 5 As shown, in some embodiments, the first conductive circuit CLP1 includes a first touch crack sub-circuit TCSLP1 and a first panel crack sub-circuit PCSLP1 connected to each other.

[0070] Figure 6 yes Figure 5 A magnified view of the first magnified region ZR1. (Refer to...) Figure 6In the peripheral region, the display panel includes an on-array gate driver (GOA), a voltage supply line Vss, and a second voltage supply line Vdd. In one example, the voltage supply line Vss is a low-voltage supply line, for example, configured to provide a low voltage to the cathode of a light-emitting element in the display region. In another example, the second voltage supply line Vdd is a high-voltage supply line, for example, configured to provide a high voltage to pixel driving circuitry in the display panel. In one example, the high voltage is provided to the source of the driving transistor in each pixel driving circuitry. Figure 6 The image also shows integrated circuits (ICs) and flexible printed circuit boards (FPCs).

[0071] Figure 7A This is a schematic diagram illustrating the structure of a first touch crack sub-circuit according to some embodiments of the present disclosure. (Refer to...) Figure 7A , Figure 1 and Figure 5 In some embodiments, the first conductive circuit CLP1 includes a first touch crack detection line TCDL1 and a second touch crack detection line TCDL2. The first touch crack detection line TCDL1 and the second touch crack detection line TCDL2 are located on the same side relative to the display area DA. In one example, the first touch crack detection line TCDL1 spaces the second touch crack detection line TCDL2 from the display area DA.

[0072] In some embodiments, the first touch crack detection line TCDL1 and the second touch crack detection line TCDL2 extend from a first sub-region PA1 of the peripheral region PA of the display panel, through a second sub-region PA2, and into a third sub-region PA3, respectively. More specifically, the first touch crack detection line TCDL1 extends from the first sub-region PA1 of the peripheral region PA of the display panel, through a second sub-region PA2, and into a third sub-region PA3; the second touch crack detection line TCDL2 extends from the third sub-region PA3, through the second sub-region PA2, and back into the first sub-region PA1.

[0073] In some embodiments, at least a portion of the first touch crack sub-circuit TCSLP1 is located in the same layer as the grid lines of the touch electrode layer. (Refer to...) Figure 7A , Figure 4B and Figure 4C The first touch crack detection line TCDL1 and the second touch crack detection line TCDL2 are at least partially located in the second layer SL2, which includes a grid of touch electrode layers, such as a grid of multiple first grid electrodes TE1 and multiple second grid electrodes TE2.

[0074] Figure 7B This is a schematic diagram illustrating the structure of a first panel crack sub-loop according to some embodiments of the present disclosure. (Refer to...) Figure 7B , Figure 1 and Figure 5 In some embodiments, the first panel crack sub-loop PCSLP1 includes a first panel crack detection line PCDL1 and a second panel crack detection line PCDL2. The first panel crack detection line PCDL1 and the second panel crack detection line PCDL2 are located on the same side relative to the display area DA. In one example, the second panel crack detection line PCDL2 spaces the first panel crack detection line PCDL1 from the display area DA.

[0075] In some embodiments, the first panel crack detection line PCDL1 and the second panel crack detection line PCDL2 extend from a first sub-region PA1 of the peripheral region PA of the display panel, through a second sub-region PA2, to a third sub-region PA3, respectively. More specifically, the first panel crack detection line PCDL1 extends from the first sub-region PA1 of the peripheral region PA of the display panel, through a second sub-region PA2, to a third sub-region PA3; the second panel crack detection line PCDL2 extends from the third sub-region PA3, through a second sub-region PA2, and back to the first sub-region PA1. In one example, the first terminal of the first panel crack sub-loop PCSLP1 (the terminal of the second panel crack detection line PCDL2) is connected to the second touch crack detection line TCDL2; the second terminal of the first panel crack sub-loop PCSLP1 (the terminal of the first panel crack detection line PCDL1) is connected to the integrated circuit IC.

[0076] In some embodiments, the first touch crack detection line TCDL1 and the second touch crack detection line TCDL2 space the first panel crack sub-circuit PCSLP1 from the display area DA. The first panel crack sub-circuit PCSLP1 is located on the side of the first touch crack detection line TCDL1 and the second touch crack detection line TCDL2 away from the display area DA. Optionally, the first panel crack sub-circuit PCSLP1 (including the first panel crack detection line PCDL1 and the second panel crack detection line PCDL2), the first touch crack detection line TCDL1, and the second touch crack detection line TCDL2 are located on the same side relative to the display area DA.

[0077] In some embodiments, the first touch crack sub-circuit TCSLP1 is configured to detect cracks in a layer adjacent to the touch structure, while the first panel crack sub-circuit PCSLP1 is configured to detect cracks in the thin-film transistor array substrate of the display panel. Optionally, the first panel crack sub-circuit PCSLP1 is located in a layer in the thin-film transistor array substrate.

[0078] Reference Figure 2BIn some embodiments, each thin-film transistor in a plurality of thin-film transistors (TFTs) includes a gate G. The display panel further includes: a first capacitor electrode Ce1 storing capacitance, which is located in the same layer as the gate G; a gate insulating layer GI located on the side of the gate G and the first capacitor electrode Ce1 near the substrate BS; a second capacitor electrode Ce2 storing capacitance, which is located on the side of the gate insulating layer GI near the substrate BS; and an insulating layer IN located on the side of the second capacitor electrode Ce2 away from the substrate BS. In another example, at least a portion of the first panel crack sub-circuit PCSLP1 is located in the same layer as the gate G (and in the same layer as the gate line, which is also in the same layer as the gate G), and is located between the gate insulating layer GI and the insulating layer IN. In another example, at least a portion of the first panel crack sub-circuit PCSLP1 is located in the same layer as the second capacitor electrode Ce2, and is located between the insulating layer IN and the interlayer dielectric layer ILD. In another example, at least a portion of the second panel crack sub-circuit PCSLP2 includes a first sub-layer located in the same layer as the gate G, and a second sub-layer located in the same layer as the second capacitor electrode Ce2.

[0079] Figure 7C This is a schematic diagram illustrating the structure of a second touch crack sub-circuit according to some embodiments of the present disclosure. (Refer to...) Figure 7C , Figure 1 as well as Figure 5 In some embodiments, the second conductive circuit CLP2 includes a third touch crack detection line TCDL3 and a fourth touch crack detection line TCDL4. The third touch crack detection line TCDL3 and the fourth touch crack detection line TCDL4 are located on the same side relative to the display area DA. In one example, the third touch crack detection line TCDL3 spaces the fourth touch crack detection line TCDL4 from the display area DA.

[0080] In some embodiments, the third touch crack detection line TCDL3 and the fourth touch crack detection line TCDL4 extend from the first sub-region PA1 of the peripheral region PA of the display panel, through the fourth sub-region PA4, and into the third sub-region PA3, respectively. More specifically, the third touch crack detection line TCDL3 extends from the first sub-region PA1 of the peripheral region PA of the display panel, through the fourth sub-region PA4, and into the third sub-region PA3; the fourth touch crack detection line TCDL4 extends from the third sub-region PA3, through the fourth sub-region PA4, and back into the first sub-region PA1.

[0081] In some embodiments, at least a portion of the second touch crack sub-circuit TCSLP2 is located in the same layer as the grid lines of the touch electrode layer. (Refer to Figure 7.) Figure 4B and Figure 4CThe third touch crack detection line TCDL3 and the fourth touch crack detection line TCDL4 are at least partially located in the second layer SL2, which includes a grid of touch electrode layers, such as a grid of multiple first grid electrodes TE1 and multiple second grid electrodes TE2.

[0082] Figure 7D This is a schematic diagram illustrating the structure of a second panel crack sub-loop according to some embodiments of the present disclosure. (Refer to...) Figure 7D , Figure 1 and Figure 5 In some embodiments, the second panel crack sub-loop PCSLP2 includes a third panel crack detection line PCDL3 and a fourth panel crack detection line PCDL4. The third panel crack detection line PCDL3 and the fourth panel crack detection line PCDL4 are located on the same side relative to the display area DA. In one example, the fourth panel crack detection line PCDL4 spaces the third panel crack detection line PCDL3 from the display area DA.

[0083] In some embodiments, the third panel crack detection line PCDL3 and the fourth panel crack detection line PCDL4 extend from the first sub-region PA1 of the peripheral region PA of the display panel, through the fourth sub-region PA4, and into the third sub-region PA3, respectively. More specifically, the third panel crack detection line PCDL3 extends from the first sub-region PA1 of the peripheral region PA of the display panel, through the fourth sub-region PA4, and into the third sub-region PA3; the fourth panel crack detection line PCDL4 extends from the third sub-region PA3, through the fourth sub-region PA4, and back into the first sub-region PA1. In one example, the first terminal of the second panel crack sub-loop PCSLP2 (the terminal of the fourth panel crack detection line PCDL4) is connected to the fourth touch crack detection line TCDL4; the second terminal of the second panel crack sub-loop PCSLP2 (the terminal of the third panel crack detection line PCDL3) is connected to the integrated circuit IC.

[0084] In some embodiments, the third touch crack detection line TCDL3 and the fourth touch crack detection line TCDL4 space the second panel crack sub-circuit PCSLP2 from the display area DA. The second panel crack sub-circuit PCSLP2 is located on the side of the third touch crack detection line TCDL3 and the fourth touch crack detection line TCDL4 away from the display area DA. Optionally, the second panel crack sub-circuit PCSLP2 (including the third panel crack detection line PCDL3 and the fourth panel crack detection line PCDL4), the third touch crack detection line TCDL3, and the fourth touch crack detection line TCDL4 are located on the same side relative to the display area DA.

[0085] In some embodiments, the second touch crack sub-circuit TCSLP2 is configured to detect cracks in a layer adjacent to the touch structure, while the second panel crack sub-circuit PCSLP2 is configured to detect cracks in the thin-film transistor array substrate of the display panel. Optionally, the second panel crack sub-circuit PCSLP2 is located in a layer of the thin-film transistor array substrate.

[0086] Reference Figure 2B In some embodiments, each thin-film transistor in a plurality of thin-film transistors (TFTs) includes a gate G. The display panel further includes: a first capacitor electrode Ce1 storing a capacitor, which is located in the same layer as the gate G; a gate insulating layer GI located on the side of the gate G and the first capacitor electrode Ce1 near the substrate BS; a second capacitor electrode Ce2 storing a capacitor, located on the side of the gate insulating layer GI away from the substrate BS; and an insulating layer IN located on the side of the second capacitor electrode Ce2 near the substrate BS. In another example, at least a portion of the second panel crack sub-circuit PCSLP2 is located in the same layer as the gate G (and in the same layer as the gate line, which is also in the same layer as the gate G), and is located between the gate insulating layer GI and the insulating layer IN. In another example, at least a portion of the second panel crack sub-circuit PCSLP2 is located in the same layer as the second capacitor electrode Ce2, and is located between the insulating layer IN and the interlayer dielectric layer ILD. In another example, at least a portion of the second panel crack sub-circuit PCSLP2 includes a first sub-layer located in the same layer as the gate G, and a second sub-layer located in the same layer as the second capacitor electrode Ce2.

[0087] Figure 8 yes Figure 6 A magnified view of the second magnified region, ZR2. (Refer to...) Figure 5 , Figure 6 and Figure 8 In some areas of the surrounding area (e.g., such as...) Figure 1 In the first corner region CR1 shown in the figure, the display panel includes an array gate driver GOA. Figure 8 The diagram illustrates the multiple signal lines SLG of the on-array gate driver GOA. (Refer to...) Figure 6 and Figure 8 In some embodiments, the signal lines of the crack detection circuit are located in at least the side regions of the peripheral area ( Figure 1The signal lines in the crack detection circuit (referred to as SR) do not cross the gate-on-array (GOA) layer. Optionally, in at least the side regions of the peripheral region, the orthographic projections of all signal lines in the crack detection circuit onto the substrate do not overlap with the orthographic projections of the gate-on-array (GOA) layer onto the substrate. Specifically, in some embodiments, at least a portion of the signal lines in the crack detection circuit include metal lines located in the same layer as the grid lines of the touch electrode layer; and, in at least the side regions of the peripheral region, the orthographic projections of a portion of the signal lines in the crack detection circuit onto the substrate do not overlap with the orthographic projections of the gate-on-array (GOA) layer onto the substrate.

[0088] The inventors of this disclosure have discovered that in relevant display panels, at least some signal lines of the crack detection circuit cross the signal lines of the gate on-array (GOA). Particularly when the signal lines of the crack detection circuit include a sublayer located in the same layer as the touch electrode layer, electrostatic discharge (ESD) is prone to occur during the manufacturing process of the display panel. Because the sublayer crosses the GOA, ESD can easily damage the GOA. The crack detection circuit in the display panel of this disclosure has a complex structure that perfectly eliminates the problem in the relevant display panels.

[0089] Reference Figure 6 and Figure 8The display panel includes a voltage supply line Vss located in a portion of the peripheral region. In some embodiments, the display panel includes the following components arranged sequentially in the portion of the peripheral region along a direction perpendicular to the extension direction ED of the first touch crack sub-circuit (first touch crack detection line TCDL1 and second touch crack detection line TCDL2) and the first panel crack sub-circuit (first panel crack detection line PCDL1 and second panel crack detection line PCDL2): a signal line SLG of the on-array gate driver GOA, a portion of the first panel crack sub-circuit (a portion of the first panel crack detection line PCDL1 and second panel crack detection line PCDL2), a portion of the voltage supply line Vss, and a portion of the first touch crack sub-circuit (a portion of the first touch crack detection line TCDL1 and second touch crack detection line TCDL2). Optionally, the display panel includes the following components arranged sequentially in a direction perpendicular to the extension direction ED of the first touch crack sub-circuit (first touch crack detection line TCDL1 and second touch crack detection line TCDL2) and the first panel crack sub-circuit (first panel crack detection line PCDL1 and second panel crack detection line PCDL2) in a portion of the peripheral region: a signal line SLG of the array gate driver GOA, a portion of the first panel crack sub-circuit (a portion of the first panel crack detection line PCDL1 and second panel crack detection line PCDL2), a portion of the voltage supply line Vss, a portion of the first touch crack sub-circuit (a portion of the first touch crack detection line TCDL1 and second touch crack detection line TCDL2), and a plurality of touch signal lines TSL.

[0090] Figure 9 The diagram illustrates the connection between the grid lines of the touch electrode layer and a plurality of touch signal lines according to some embodiments of the present disclosure. (Refer to...) Figure 9 In the touch area TCA, the display panel includes a touch electrode layer TEL. The touch electrode layer TEL includes a plurality of touch electrodes TE. In some embodiments, the plurality of touch electrodes are grid electrodes. The grid lines ML of the touch electrode layer TEL are connected to a plurality of touch signal lines TSL. The plurality of touch signal lines TSL connect the grid electrodes in the touch electrode layer TEL to an integrated circuit (e.g., a touch integrated circuit).

[0091] In some embodiments, the signal line SLG of the on-array gate driver GOA, a portion of the first panel crack sub-loop, a portion of the voltage supply line Vss, and a portion of the first touch crack sub-loop are located in the same layer. In one example, the signal line SLG of the on-array gate driver GOA, a portion of the first panel crack sub-loop, a portion of the voltage supply line Vss, and a portion of the first touch crack sub-loop are located in the second signal line layer. Figure 2BIn SLL2 of the array. Optionally, the signal line SLG of the on-array gate driver GOA, a portion of the first panel crack sub-circuit, a portion of the voltage supply line Vss, a portion of the first touch crack sub-circuit, and multiple touch signal lines TSL are located in the same layer. In another example, the signal line SLG of the on-array gate driver GOA, a portion of the first panel crack sub-circuit, a portion of the voltage supply line Vss, a portion of the first touch crack sub-circuit, and multiple touch signal lines TSL are located in the second signal line layer ( Figure 2B In SLL2).

[0092] Reference Figure 8 In some embodiments, a portion of the voltage supply line Vss extends in a portion of the peripheral region in a direction substantially parallel to the extension direction ED of the first touch crack sub-circuit and the first panel crack sub-circuit.

[0093] Figure 10A This is a schematic diagram illustrating the structure of a portion of a first touch crack detection line located in a portion of the peripheral region of a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 10A , Figure 8 , Figure 9 , Figure 7A as well as Figure 5 In some embodiments, the first touch crack detection line TCDL1 includes a first-first portion P11 and a second-first portion P21 located in different layers and connected to each other. In one example, the first-first portion P11 is located in the same layer as the grid line ML of the touch electrode layer TEL, for example, with... Figure 2A and Figure 2B Multiple first touch electrodes TE1 are located in the same layer. In another example, the second-first portion P21 is located in the same layer as the voltage supply line Vss in the surrounding area, for example, with... Figure 2B The second signal line layer SLL2 is located in the same layer.

[0094] Reference Figure 9 In some embodiments, the display panel includes at least one row of first vias v1 extending through the touch insulating layer. Multiple grid lines ML of the grid electrodes of the touch electrode layer TEL are respectively connected to multiple touch signal lines TSL through multiple first vias in the row of first vias v1. (See also...) Figure 9 and Figure 10A The first-first part P11 is connected to the second-first part P21 through the first-first via v11 in the first row of the first via v1.

[0095] Figure 11A It is along Figure 10A The cross-sectional view of line A-A' in the diagram. (Refer to...) Figure 11A and Figure 10A The first-first via v11 extends through the touch insulating layer TI and the second planarization layer PLN2. The first-first portion P11 is connected to the second-first portion P21 through the first-first via v11.

[0096] In some embodiments, the first portion P11 and the grid lines ML of the touch electrode layer TEL are located in the same layer. The second portion P21, the plurality of touch signal lines TSL, and the voltage supply lines Vss in the surrounding area are located in the second signal line layer. Figure 2B In SLL2), the second signal line layer is at least through the touch insulating layer ( Figure 2B The TI in the first part is separated from the first part P11.

[0097] In some embodiments, the first touch crack detection line TCDL1 further includes a third-first portion P31 connected to the second-first portion P21. Figure 11B It is along Figure 10A Cross-sectional view of line B-B' in the diagram. See also... Figure 11B In some embodiments, the third-first portion P31 includes: a second gate metal layer of the display panel ( Figure 2A and Figure 2B Gate2 is located in the same layer as the first sublayer SUB1; the second sublayer SUB2 is located on the side of the first sublayer SUB1 away from the substrate BS, and the second sublayer SUB2 is connected to the first signal line layer of the display panel. Figure 2A and Figure 2B SLL1) is located in the same layer; the third sublayer SUB3 is located on the side of the second sublayer SUB2 away from the first sublayer SUB1, and this third sublayer SUB3 is connected to the second signal line layer of the display panel ( Figure 2B SLL2 is located in the same layer as the second sublayer SUB2; and a fourth sublayer SUB4 is located on the side of the third sublayer SUB3 away from the second sublayer SUB2, which is in the same layer as the grid lines of the touch electrode layer. See also Figure 11B The second sublayer SUB2 connects the first sublayer SUB1 to the third sublayer SUB3; the third sublayer SUB3 connects the second sublayer SUB2 to the fourth sublayer SUB4.

[0098] Figure 10B This is a schematic diagram illustrating the structure of a portion of a second touch crack detection line located in a portion of the peripheral region of a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 10B , Figure 8 , Figure 9 , Figure 7A as well as Figure 5In some embodiments, the second touch crack detection line TCDL2 includes a first-second portion P12 and a second-second portion P22 located in different layers and connected to each other. In one example, the first-second P12 is located in the same layer as the grid line ML of the touch electrode layer TEL, for example, with... Figure 2A and Figure 2B Multiple first touch electrodes TE1 are located in the same layer. In another example, the second-second portion P22 is located in the same layer as the voltage supply line Vss in the surrounding area, for example, with... Figure 2B The second signal line layer SLL2 is located in the same layer.

[0099] Reference Figure 9 In some embodiments, the display panel includes at least one row of first vias v1 extending through the touch insulating layer. Multiple grid lines ML of the grid electrodes of the touch electrode layer TEL are respectively connected to multiple touch signal lines TSL through multiple first vias in the row of first vias v1. (See also...) Figure 9 and Figure 10B The first-second part P12 is connected to the second-second part P22 through the second-first via v21 in the first via v1.

[0100] Figure 11C It is along Figure 10B A cross-sectional view of line C-C' in the diagram. (Refer to...) Figure 11C and Figure 10B The second-first via v21 extends through the touch insulating layer TI and the second planarization layer PLN2. The first-second portion P12 is connected to the second-second portion P22 through the second-first via v21.

[0101] In some embodiments, the first-second portion P12 and the grid lines ML of the touch electrode layer TEL are located in the same layer. The second-second portion P22, the second-first portion P21, the plurality of touch signal lines TSL, and the voltage supply lines Vss in the surrounding area are located in the second signal line layer. Figure 2B In SLL2), the second signal line layer is at least through the touch insulating layer ( Figure 2B The TI in the text is separated from the first-second part P12 and the first-first part P11.

[0102] In some embodiments, the second touch crack detection line TCDL2 further includes a third portion P32 connected to the second portion P22. Figure 11D It is along Figure 10B A cross-sectional view of line D-D' in the diagram. See also... Figure 11D In some embodiments, the third-second portion P32 includes: a grid line connecting the display panel ( Figure 2A and Figure 2BGate 1 is located in the same layer as the fifth sublayer SUB5; the sixth sublayer SUB6 is located on the side of the fifth sublayer SUB5 away from the substrate BS, and the sixth sublayer SUB6 is connected to the first signal line layer of the display panel. Figure 2A and Figure 2B SLL1) is located in the same layer; the seventh sublayer SUB7 is located on the side of the sixth sublayer SUB6 away from the fifth sublayer SUB5, and this seventh sublayer SUB7 is connected to the second signal line layer of the display panel ( Figure 2B SLL2) is located in the same layer; and the eighth sublayer SUB8 is located on the side of the seventh sublayer SUB7 away from the sixth sublayer SUB6, and this eighth sublayer SUB8 is located in the same layer as the grid lines of the touch electrode layer. See also Figure 11D The sixth sublayer SUB6 connects the fifth sublayer SUB5 to the seventh sublayer SUB7; the seventh sublayer SUB7 connects the sixth sublayer SUB6 to the eighth sublayer SUB8.

[0103] Figure 10C This is a schematic diagram illustrating a portion of the structure of a first panel crack detection line located in a portion of the peripheral region of a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 10C , Figure 8 , Figure 9 , Figure 7B and Figure 5 In some embodiments, the first panel crack detection line PCDL1 includes a first-third portion P13, a second-third portion P23, and a third-third portion P33. The second-third portion P23 is located in a different layer from the first-third portion P13 and the third-third portion P33. The second-third portion P23 connects the first-third portion P13 to the third-third portion P33.

[0104] In some embodiments, the first-third portions P13 include grid lines with the display panel ( Figure 2A and Figure 2B Gate 1 is located in the same layer as or with the second gate metal layer of the display panel. Figure 2A and Figure 2B Gate 2) is located in at least one sublayer within the same layer. Optionally, the first-third portion P13 includes a sublayer located in the same layer as the gate lines of the display panel, and a sublayer located in the same layer as the second gate metal layer of the display panel. In some embodiments, the second-third portion P23 is located in the same layer as the voltage supply line Vss in the peripheral region. In some embodiments, the third-third portion P33 includes at least one sublayer located in the same layer as the second gate metal layer of the display panel.

[0105] Figure 10DThis is a schematic diagram illustrating a portion of the structure of a second panel crack detection line located in a portion of the peripheral region of a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 10D , Figure 8 , Figure 9 , Figure 7B and Figure 5 In some embodiments, the second panel crack detection line PCDL2 includes a first-fourth portion P14, a second-fourth portion P24, and a third-fourth portion P34. The second-fourth portion P24 is located in a different layer from the first-fourth portion P14 and the third-fourth portion P34. The second-fourth portion P24 connects the first-fourth portion P14 to the third-fourth portion P34.

[0106] In some embodiments, the first-fourth portions P14 include grid lines with the display panel ( Figure 2A and Figure 2B Gate 1 is located in the same layer as or with the second gate metal layer of the display panel. Figure 2A and Figure 2B Gate 2) is located in at least one sublayer within the same layer. Optionally, the first-fourth portion P14 includes a sublayer located in the same layer as the gate lines of the display panel, and a sublayer located in the same layer as the second gate metal layer of the display panel. In some embodiments, the second-fourth portion P24 is located in the same layer as the voltage supply line Vss in the peripheral region. In some embodiments, the third-fourth portion P34 includes at least one sublayer located in the same layer as the gate lines of the display panel.

[0107] Reference Figure 5 , Figure 7A , Figure 7B , Figures 10A to 10D In some embodiments, the third-fourth portion P34 is connected to the third-second portion P32 of the second touch crack detection line TCDL2 of the first touch crack sub-circuit TCSLP1.

[0108] Reference Figure 5 as well as Figures 7A to 7D In some embodiments, the display panel further includes a connecting line that connects the first conductive circuit CLP1 and the second conductive circuit CLP2.

[0109] Figure 12 This is an enlarged view of a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 5 and Figure 12 In some areas of the surrounding area (e.g.) Figure 1 In the illustrated second corner region CR2, the display panel includes an array gate driver. Figure 12 The diagram illustrates the multiple signal lines SLG of the gate driver on the array. (Refer to...) Figure 5 , Figure 8 and Figure 12 The signal lines of the crack detection circuit are located at least in the side region of the surrounding area. Figure 1 The signal lines in the crack detection circuit (referred to as SR) do not cross the on-array gate driver. In the display panel of this disclosure, in at least the side regions of the peripheral area, the orthographic projection of all signal lines in the crack detection circuit onto the substrate does not overlap with the orthographic projection of the on-array gate driver onto the array substrate. Specifically, in some embodiments, at least a portion of the signal lines in the crack detection circuit include metal lines located in the same layer as the grid lines of the touch electrode layer; and, in at least the side regions of the peripheral area, the orthographic projection of a portion of the signal lines in the crack detection circuit having metal lines located in the same layer as the grid lines of the touch electrode layer onto the substrate does not overlap with the orthographic projection of the on-array gate driver onto the substrate.

[0110] Reference Figure 12 The display panel includes the following components arranged sequentially in a direction perpendicular to the extension direction ED of the second touch crack sub-circuit (the third touch crack detection line TCDL3 and the fourth touch crack detection line TCDL4) and the second panel crack sub-circuit (the third panel crack detection line PCDL3 and the fourth panel crack detection line PCDL4) in a portion of the peripheral area: the signal line SLG of the on-array gate driver, a portion of the second panel crack sub-circuit (a portion of the third panel crack detection line PCDL3 and the fourth panel crack detection line PCDL4), a portion of the voltage supply line Vss, and a portion of the second touch crack sub-circuit (a portion of the third touch crack detection line TCDL3 and the fourth touch crack detection line TCDL4). Optionally, the display panel includes the following components arranged sequentially in a direction perpendicular to the extension direction ED of the second touch crack sub-circuit (the third touch crack detection line TCDL3 and the fourth touch crack detection line TCDL4) and the second panel crack sub-circuit (the third panel crack detection line PCDL3 and the fourth panel crack detection line PCDL4) in a portion of the peripheral region: a signal line SLG of the on-array gate driver, a portion of the second panel crack sub-circuit (a portion of the third panel crack detection line PCDL3 and the fourth panel crack detection line PCDL4), a portion of the voltage supply line Vss, a portion of the second touch crack sub-circuit (a portion of the third touch crack detection line TCDL3 and the fourth touch crack detection line TCDL4), and a plurality of touch signal lines TSL.

[0111] Figure 13 The diagram illustrates the connection between the grid lines of the touch electrode layer and a plurality of touch signal lines according to some embodiments of the present disclosure. (Refer to...) Figure 13In the touch area TCA, the display panel includes a touch electrode layer TEL. The touch electrode layer TEL includes a plurality of touch electrodes TE. In some embodiments, the plurality of touch electrodes are grid electrodes. The grid lines ML of the touch electrode layer TEL are connected to a plurality of touch signal lines TSL. The plurality of touch signal lines TSL connect the grid electrodes in the touch electrode layer TEL to an integrated circuit (e.g., a touch integrated circuit).

[0112] In some embodiments, the signal line SLG of the on-array gate driver, a portion of the second panel crack sub-loop, a portion of the voltage supply line Vss, and a portion of the second touch crack sub-loop are located in the same layer. In one example, the signal line SLG of the on-array gate driver, a portion of the second panel crack sub-loop, a portion of the voltage supply line Vss, and a portion of the second touch crack sub-loop are located in the second signal line layer ( Figure 2B In SLL2 of the array. Optionally, the signal line SLG of the on-array gate driver, a portion of the second panel crack sub-circuit, a portion of the voltage supply line Vss, a portion of the second touch crack sub-circuit, and multiple touch signal lines TSL are located in the same layer. In another example, the signal line SLG of the on-array gate driver GOA, a portion of the second panel crack sub-circuit, a portion of the voltage supply line Vss, a portion of the second touch crack sub-circuit, and multiple touch signal lines TSL are located in the second signal line layer ( Figure 2B In SLL2).

[0113] Reference Figure 12 In some embodiments, a portion of the voltage supply line Vss extends in a portion of the peripheral region in a direction substantially parallel to the extension direction ED of the second touch crack sub-circuit and the second panel crack sub-circuit.

[0114] Figure 14A This is a schematic diagram illustrating the structure of a portion of a third touch crack detection line located in a portion of the peripheral region of a display panel in some embodiments according to this disclosure. (Refer to...) Figure 14A , Figure 12 , Figure 13 , Figure 7D and Figure 5 In some embodiments, the third touch crack detection line TCDL3 includes a first-fifth portion P15 and a second-fifth portion P25 located in different layers and connected to each other. In one example, the first-fifth portion P15 is located in the same layer as the grid line ML of the touch electrode layer TEL, for example, with... Figure 2A and Figure 2B Multiple first touch electrodes TE1 are located in the same layer. In another example, the second-fifth portions P25 are located in the same layer as the voltage supply line Vss in the surrounding area, for example, with... Figure 2BThe second signal line layer SLL2 is located in the same layer.

[0115] Reference Figure 13 In some embodiments, the display panel includes at least one row of second vias v2 extending through the touch insulating layer. Multiple grid lines ML of the grid electrodes of the touch electrode layer TEL are respectively connected to multiple touch signal lines TSL through multiple first vias in the row of second vias v2. (See also...) Figure 13 and Figure 14A The first-fifth section P15 is connected to the second-fifth section P25 through the first-second via v21 in the second via v2 of a row.

[0116] Figure 15A It is along Figure 14A A cross-sectional view of line E-E' in the diagram. (Refer to...) Figure 15A and Figure 14A The first-second via v21 extends through the touch insulating layer TI and the second planarization layer PLN2. The first-fifth portion P15 is connected to the second-fifth portion P25 through the first-second via v21.

[0117] In some embodiments, the first to fifth portions P15 are located in the same layer as the grid lines ML of the touch electrode layer TEL. The second to fifth portions P25, the plurality of touch signal lines TSL, and the voltage supply lines Vss in the surrounding area are located in the second signal line layer. Figure 2B In SLL2), the second signal line layer is at least through the touch insulating layer ( Figure 2B The TI in the text is separated from the first to fifth parts P15.

[0118] In some embodiments, the third touch crack detection line TCDL3 further includes a third-fifth portion P35 connected to the second-first portion P21. Figure 15B It is along Figure 14A A cross-sectional view of line F-F' in the diagram. See also... Figure 15B In some embodiments, the third-fifth portions P35 include: a second gate metal layer of the display panel ( Figure 2A and Figure 2B Gate 2 is located in the same layer as the ninth sublayer SUB9; the tenth sublayer SUB10 is located on the side of the ninth sublayer SUB9 away from the substrate BS, and the tenth sublayer SUB10 is connected to the first signal line layer of the display panel ( Figure 2A and Figure 2B SLL1) is located in the same layer; the eleventh sublayer SUB11 is located on the side of the tenth sublayer SUB10 away from the ninth sublayer SUB9, and this eleventh sublayer SUB11 is connected to the second signal line layer of the display panel ( Figure 2BSLL2) is located in the same layer; and a twelfth sublayer SUB12 is located on the side of the eleventh sublayer SUB11 away from the tenth sublayer SUB10, which is in the same layer as the grid lines of the touch electrode layer. See also Figure 15B The tenth sublayer SUB10 connects the ninth sublayer SUB9 to the eleventh sublayer SUB11; the eleventh sublayer SUB11 connects the tenth sublayer SUB10 to the twelfth sublayer SUB12.

[0119] Figure 14B This is a schematic diagram illustrating the structure of a portion of a fourth touch crack detection line located in a portion of the peripheral region of a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 14B , Figure 12 , Figure 13 , Figure 7D and Figure 5 In some embodiments, the fourth touch crack detection line TCDL4 includes a first-sixth portion P16 and a second-sixth portion P26 located in different layers and connected to each other. In one example, the first-sixth portion P16 is located in the same layer as the grid line ML of the touch electrode layer TEL, for example, with Figure 2A and Figure 2B Multiple first touch electrodes TE1 are located in the same layer. In another example, the second-sixth portions P26 are located in the same layer as the voltage supply line Vss in the surrounding area, for example, with... Figure 2B The second signal line layer SLL2 is located in the same layer.

[0120] Reference Figure 13 In some embodiments, the display panel includes at least one row of second vias v2 extending through the touch insulating layer. Multiple grid lines ML of the grid electrodes of the touch electrode layer TEL are respectively connected to multiple touch signal lines TSL through multiple second vias in the row of second vias v2. (See also...) Figure 13 and Figure 14B The first-sixth section P16 is connected to the second-sixth section P26 through the second-second via v22 in the second via v2 of the row.

[0121] Figure 15C It is along Figure 14B A cross-sectional view of the G-G' line. (Refer to...) Figure 15C and Figure 14B The second-second via v22 extends through the touch insulating layer TI and the second planarization layer PLN2. The first-sixth portion P16 is connected to the second-sixth portion P26 through the second-second via v22.

[0122] In some embodiments, the first-sixth portions P16 are located in the same layer as the grid lines ML of the touch electrode layer TEL. The second-sixth portions P26, the second-fifth portions P25, the plurality of touch signal lines TSL, and the voltage supply lines Vss in the surrounding area are located in the second signal line layer. Figure 2B In SLL2), the second signal line layer is at least through the touch insulating layer ( Figure 2B The TI in the text is separated from the first-sixth part P16 and the first-fifth part P15.

[0123] In some embodiments, the fourth touch crack detection line TCDL4 further includes a third-sixth portion P36 connected to the second-sixth portion P26. Figure 15D It is along Figure 14B A cross-sectional view of the H-H' line in the diagram. See also... Figure 15D In some embodiments, the third-sixth portions P36 include: grid lines with the display panel ( Figure 2A and Figure 2B Gate 1 is located in the same layer as the thirteenth sublayer SUB13; the fourteenth sublayer SUB14 is located on the side of the thirteenth sublayer SUB13 away from the substrate BS, and the fourteenth sublayer SUB14 is connected to the first signal line layer of the display panel. Figure 2A and Figure 2B SLL1) is located in the same layer; the fifteenth sublayer SUB15 is located on the side of the fourteenth sublayer SUB14 away from the thirteenth sublayer SUB13, and this fifteenth sublayer SUB15 is connected to the second signal line layer of the display panel ( Figure 2B SLL2) is located in the same layer; and the sixteenth sublayer SUB16 is located on the side of the fifteenth sublayer SUB15 away from the fourteenth sublayer SUB14, and this sixteenth sublayer SUB16 is located in the same layer as the grid lines of the touch electrode layer. See also Figure 15D The fourteenth sublayer SUB14 connects the thirteenth sublayer SUB13 to the fifteenth sublayer SUB15; the fifteenth sublayer SUB15 connects the fourteenth sublayer SUB14 to the sixteenth sublayer SUB16.

[0124] Figure 14C This is a schematic diagram illustrating a portion of the structure of a third panel crack detection line located in a partial area of ​​the peripheral region of a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 14C , Figure 12 , Figure 13 , Figure 7C and Figure 5In some embodiments, the third panel crack detection line PCDL3 includes a first-seventh portion P17, a second-seventh portion P27, and a third-seventh portion P37. The second-seventh portion P27 is located in a different layer from the first-seventh portion P17 and the third-seventh portion P37. The second-seventh portion P27 connects the first-seventh portion P17 to the third-seventh portion P37.

[0125] In some embodiments, the first to seventh portions P17 include grid lines with the display panel ( Figure 2A and Figure 2B Gate 1 is located in the same layer as or with the second gate metal layer of the display panel. Figure 2A and Figure 2B Gate 2) is located in at least one sublayer within the same layer. Optionally, the first-seventh portion P17 includes a sublayer located in the same layer as the gate lines of the display panel, and a sublayer located in the same layer as the second gate metal layer of the display panel. In some embodiments, the second-seventh portion P27 is located in the same layer as the voltage supply line Vss in the peripheral region. In some embodiments, the third-seventh portion P37 includes at least one sublayer located in the same layer as the second gate metal layer of the display panel.

[0126] Figure 14D This is a schematic diagram illustrating a portion of the structure of a fourth panel crack detection line located in a portion of the peripheral region of a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 14D , Figure 12 , Figure 13 , Figure 7C and Figure 5 In some embodiments, the fourth panel crack detection line PCDL4 includes a first-eighth portion P18, a second-eighth portion P28, and a third-eighth portion P38. The second-eighth portion P28 is located in a different layer from the first-eighth portion P18 and the third-eighth portion P38. The second-eighth portion P28 connects the first-eighth portion P18 to the third-eighth portion P38.

[0127] In some embodiments, the first-eighth portions P18 include grid lines with the display panel ( Figure 2A and Figure 2B Gate 1 is located in the same layer as or with the second gate metal layer of the display panel. Figure 2A and Figure 2BGate 2) is located in at least one sublayer within the same layer. Optionally, the first-eighth portion P18 includes a sublayer located in the same layer as the gate lines of the display panel, and a sublayer located in the same layer as the second gate metal layer of the display panel. In some embodiments, the second-eighth portion P28 is located in the same layer as the voltage supply line VSS in the peripheral region. In some embodiments, the third-eighth portion P38 includes at least one sublayer located in the same layer as the gate lines of the display panel.

[0128] Reference Figure 5 , Figure 7A , Figure 7C , Figures 14A to 14D In some embodiments, the third to eighth portions P38 are connected to the third to sixth portions P36 of the fourth touch crack detection line TCDL4 of the second touch crack sub-circuit TCSLP2.

[0129] On the other hand, this disclosure provides a display device. In some embodiments, the display device includes a display panel as described herein and a printed circuit board connected to an integrated circuit in the display panel. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptops, digital photo albums, GPS devices, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a liquid crystal display (LCD) device.

[0130] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. A display panel, comprising: The touch electrode layer is located at least partially in the display area of ​​the display panel; On-array gate driver located in the peripheral area of ​​the display panel; as well as Crack detection circuit; Wherein, at least a portion of the signal lines in the crack detection circuit include metal lines located in the same layer as the grid lines of the touch electrode layer; at least a portion of the signal lines in the crack detection circuit include metal lines located in the same layer as the grid lines of the touch electrode layer, and in at least the side region of the peripheral area, a portion of the signal lines of the metal lines in the crack detection circuit located in the same layer as the grid lines of the touch electrode layer, whose orthogonal projection on the substrate does not overlap with the orthogonal projection of the gate driver on the array on the substrate.

2. The display panel according to claim 1, wherein, The crack detection circuit includes an integrated circuit and a first conductive loop electrically connected to the integrated circuit; and The first conductive circuit includes a first touch crack sub-circuit and a first panel crack sub-circuit connected to each other. At least a portion of the first touch crack sub-circuit is located in the same layer as the grid lines of the touch electrode layer; at least a portion of the first panel crack sub-circuit is located in the same layer as the gate lines of the display panel.

3. The display panel according to claim 2, further comprising a voltage supply line located in a portion of the peripheral area; in, The display panel includes the following components arranged sequentially in the peripheral region along a direction perpendicular to the extension direction of the first touch crack sub-circuit and the first panel crack sub-circuit: the signal line of the array gate driver, a portion of the first panel crack sub-circuit, a portion of the voltage supply line, and a portion of the first touch crack sub-circuit.

4. The display panel according to claim 3, wherein, The signal lines of the gate driver on the array, the portion of the first panel crack sub-circuit, the portion of the voltage supply line, and the portion of the first touch crack sub-circuit are located in the same layer.

5. The display panel according to claim 3, wherein, The portion of the voltage supply line extends in the peripheral region in a direction substantially parallel to the extension direction of the first touch crack sub-circuit and the first panel crack sub-circuit.

6. The display panel according to claim 2, wherein, The first touch crack sub-circuit includes a first touch crack detection line and a second touch crack detection line located on the same side relative to the display area, wherein the first touch crack detection line separates the second touch crack detection line from the display area; as well as The first touch crack detection line includes a first-first part and a second-first part located in different layers and connected to each other.

7. The display panel according to claim 6, wherein, The second-first part is located on the same layer as the voltage supply line in the surrounding area; as well as The first portion and the grid lines of the touch electrode layer are located in the same layer.

8. The display panel of claim 6, comprising at least one row of first vias extending through the touch insulating layer; in, The first-first portion is connected to the second-first portion through the first-first via in the first row of the first vias; as well as The multiple grid lines of the grid electrode of the touch electrode layer are respectively connected to multiple touch signal lines through multiple first vias in the row of first vias.

9. The display panel according to claim 8, wherein, The first portion and the grid lines of the grid electrodes of the touch electrode layer are located in the same layer; as well as The second-first portion, the plurality of touch signal lines, and the voltage supply lines in the peripheral area are located in a second signal line layer, which is spaced apart from the first-first portion at least by the touch insulating layer.

10. The display panel according to any one of claims 6 to 9, wherein, The first touch crack detection line also includes a third-first portion connected to the second-first portion; The third-first part includes: The first sub-layer is located in the same layer as the second gate metal layer of the display panel; A second sublayer is located on the side of the first sublayer away from the substrate, and the second sublayer is located in the same layer as the first signal line layer of the display panel; A third sub-layer located on the side of the second sub-layer away from the first sub-layer, the third sub-layer being in the same layer as the second signal line layer of the display panel; and A fourth sublayer is located on the side of the third sublayer away from the second sublayer, and the fourth sublayer is in the same layer as the grid lines of the touch electrode layer.

11. The display panel according to claim 6, wherein, The second touch crack detection line includes a first-second part and a second-second part located in different layers and connected to each other; The display panel includes at least one row of first vias extending through the touch insulating layer; The first-second portion is connected to the second-second portion via the second-first via in the first via of the row; The grid lines of the grid electrodes of the touch electrode layer are connected to multiple touch signal lines through multiple first vias in the row of first vias; The first and second portions are located in the same layer as the grid lines of the grid electrodes of the touch electrode layer; and The second portion and the plurality of touch signal lines are located in a second signal line layer, which is spaced apart from the first portion at least by the touch insulating layer.

12. The display panel according to claim 11, wherein, The second touch crack detection line also includes a third-second portion connected to the second-second portion; The third-second part includes: The fifth sub-layer is located in the same layer as the grid lines of the display panel; The sixth sublayer is located on the side of the fifth sublayer away from the substrate, and the sixth sublayer is located in the same layer as the first signal line layer of the display panel; A seventh sublayer located on the side of the sixth sublayer away from the fifth sublayer, the seventh sublayer being in the same layer as the second signal line layer of the display panel; and The eighth sublayer is located on the side of the seventh sublayer away from the sixth sublayer, and the grid lines of the eighth sublayer are located in the same layer as the touch electrode layer.

13. The display panel according to claim 2, wherein, The first panel crack sub-circuit includes a first panel crack detection line and a second panel crack detection line located on the same side relative to the display area, wherein the second panel crack detection line separates the first panel crack detection line from the display area. as well as The first panel crack detection line includes a first-third section, a second-third section, and a third-third section. The second-third section is located in a different layer from the first-third section and the third-third section. The second-third section connects the first-third section to the third-third section.

14. The display panel according to claim 13, wherein, The first-third portion includes at least one sublayer located in the same layer as the gate lines of the display panel or in the same layer as the second gate metal layer; The second and third portions are located on the same layer as the voltage supply lines in the surrounding area; as well as The third-third portion includes at least one sublayer located in the same layer as the second gate metal layer.

15. The display panel according to claim 13, wherein, The second panel crack detection line includes a first-fourth section, a second-fourth section, and a third-fourth section. The second-fourth section is located in a different layer from the first-fourth section and the third-fourth section. The second-fourth section connects the first-fourth section to the third-fourth section.

16. The display panel according to claim 15, wherein, The first to fourth portions include at least one sublayer located in the same layer as the gate lines of the display panel or in the same layer as the second gate metal layer; The second and fourth sections are located on the same layer as the voltage supply lines in the surrounding area; as well as The third and fourth portions include at least one sublayer located in the same layer as the grid lines of the display panel.

17. The display panel according to claim 15, wherein, The third-fourth part is connected to the third-second part of the second touch crack detection line of the first touch crack sub-circuit.

18. The display panel according to claim 2, further comprising: Electrically connected to the second conductive circuit of the integrated circuit; as well as A connecting line that connects the first conductive loop and the second conductive loop; The second conductive circuit includes a second touch crack sub-circuit and a second panel crack sub-circuit connected to each other. At least a portion of the second touch crack sub-circuit is located in the same layer as the grid lines of the touch electrode layer; at least a portion of the second panel crack sub-circuit is located in the same layer as the gate lines of the display panel.

19. A display device comprising a display panel according to any one of claims 1 to 18, and a printed circuit board connected to an integrated circuit in the display panel.

Images