Method, circuit, receiver and integrated circuit for common mode voltage rebiasing

Abstract

This invention provides a method for common-mode voltage rebiasing in the analog front-end circuit of a receiver, a related common-mode voltage rebiasing circuit, a receiver, and a related integrated circuit. The common-mode voltage rebiasing circuit may include a control circuit and a plurality of switchable common-mode voltage rebiasing sub-circuits. The control circuit generates at least one control signal according to a command to control the common-mode voltage rebiasing circuit to operate in a selected circuit configuration. The plurality of switchable common-mode voltage rebiasing sub-circuits respectively select a predetermined circuit configuration from a first predetermined circuit configuration and a second predetermined circuit configuration as the selected circuit configuration according to the at least one control signal, to perform a common-mode voltage rebiasing operation corresponding to the selected circuit configuration.

Description

Technical Field

[0001] This invention application relates to circuit design, specifically to a method, circuit, receiver, and integrated circuit for common-mode voltage re-biasing, and more particularly to a method for re-biasing common-mode voltage in the analog front-end circuit of a receiver, a related common-mode voltage re-biasing circuit, the receiver, and the related integrated circuit (IC). Background Technology

[0002] According to relevant technologies, different stages of circuits in traditional analog front-end circuits can each have different common-mode voltages to allow subsequent circuits to operate within a suitable voltage range. However, certain problems may occur. For example, when system manufacturers attempt to implement electronic products compliant with newer communication specifications, the existing circuit characteristics of the traditional analog front-end circuit may prevent the entire system from simultaneously meeting various requirements, leading to test failures. Therefore, a novel method and related architecture are needed to implement electronic products compliant with newer communication specifications without or without the possibility of causing side effects. Summary of the Invention

[0003] One object of the present invention is to provide a method for common-mode voltage rebiasing of the analog front-end circuit of a receiver, a related common-mode voltage rebiasing circuit, the receiver, and related integrated circuits to solve the above-mentioned problems.

[0004] Another object of the present invention is to provide a method for common-mode voltage rebiasing in the analog front-end circuit of a receiver, a related common-mode voltage rebiasing circuit, the receiver, and related integrated circuits to achieve optimized performance of electronic products.

[0005] At least one embodiment of the present invention provides a common-mode voltage rebias circuit for performing common-mode voltage rebiasing in the analog front-end circuitry of a receiver. The common-mode voltage rebias circuit may include a control circuit and a plurality of switchable common-mode voltage rebias sub-circuits coupled to the control circuit, wherein the plurality of switchable common-mode voltage rebias sub-circuits may include a first switchable common-mode voltage rebias sub-circuit and a second switchable common-mode voltage rebias sub-circuit. The control circuit may be used to generate at least one control signal according to a command to control the common-mode voltage rebias circuit to operate in a selected circuit configuration. Furthermore, the plurality of switchable common-mode voltage rebias sub-circuits may be used to select a predetermined circuit configuration from a first predetermined circuit configuration and a second predetermined circuit configuration respectively, according to the at least one control signal, to perform a common-mode voltage rebiasing operation corresponding to the selected circuit configuration. For example, the first switchable common-mode voltage rebias sub-circuit may be located in the analog front-end circuit of the receiver and coupled to the first differential input terminal of the receiver, and the second switchable common-mode voltage rebias sub-circuit may be located in the analog front-end circuit of the receiver and coupled to the second differential input terminal of the receiver.

[0006] According to certain embodiments, the present invention further provides a receiver including the above-described common-mode voltage rebias circuit, wherein the receiver may include: a physical layer (PHY) circuit, wherein the physical layer circuit includes the common-mode voltage rebias circuit; and an upper layer circuit for selecting a predetermined communication mode from a plurality of predetermined communication modes as the selected communication mode, and sending a command according to the selected communication mode to cause the selected circuit configuration to correspond to the selected communication mode.

[0007] According to certain embodiments, the present invention also provides an integrated circuit comprising the above-described receiver.

[0008] At least one embodiment of the present invention provides a method for performing common-mode voltage rebiasing in the analog front-end circuit of a receiver. The method may include: generating at least one control signal according to a command to control a common-mode voltage rebiasing circuit to operate in a selected circuit configuration; and utilizing a plurality of switchable common-mode voltage rebiasing sub-circuits of the common-mode voltage rebiasing circuit to select a predetermined circuit configuration from a first predetermined circuit configuration and a second predetermined circuit configuration as the selected circuit configuration according to the at least one control signal, to perform a common-mode voltage rebiasing operation corresponding to the selected circuit configuration, wherein the plurality of switchable common-mode voltage rebiasing sub-circuits includes a first switchable common-mode voltage rebiasing sub-circuit and a second switchable common-mode voltage rebiasing sub-circuit, and the first switchable common-mode voltage rebiasing sub-circuit and the second switchable common-mode voltage rebiasing sub-circuit are respectively located in the analog front-end circuit of the receiver and respectively coupled to a first differential input terminal and a second differential input terminal of the receiver.

[0009] One advantage of this invention is that, through a carefully designed control mechanism, the method, common-mode voltage rebias circuit, receiver, and integrated circuit of this invention can dynamically control the common-mode voltage rebias operation to correspond to the currently selected circuit configuration. In particular, by utilizing a higher-level circuit, such as a Media Access Control layer (MAClayer), to send the command according to the selected communication mode, the selected circuit configuration corresponds to the selected communication mode, thereby ensuring the communication quality of each of the multiple predetermined communication modes. Compared to related technologies, the method, common-mode voltage rebias circuit, receiver, and integrated circuit of this invention can achieve optimized performance of electronic products with no or minimal side effects. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a common-mode voltage rebias circuit for performing common-mode voltage rebiasing in the analog front-end circuit of a receiver, according to an embodiment of the present invention.

[0011] Figure 2 An embodiment of the present invention illustrates a method for use in a receiver such as Figure 1 The first predetermined circuit configuration involved in the dynamic circuit configuration control scheme of the method for common-mode voltage rebiasing of the analog front-end circuit of the receiver shown.

[0012] Figure 3 The second predetermined circuit configuration involved in the dynamic circuit configuration control scheme is illustrated according to an embodiment of the present invention.

[0013] Figure 4 A first switching scheme of the method is illustrated according to an embodiment of the present invention.

[0014] Figure 5 A second switching scheme of the method is illustrated according to an embodiment of the present invention.

[0015] Figure 6 A switching scheme for minimizing parasitic capacitance according to an embodiment of the present invention is illustrated.

[0016] Figure 7 An integrated circuit operating according to the method is illustrated according to an embodiment of the present invention.

[0017] Figure 8 The workflow of the method is illustrated according to an embodiment of the present invention.

[0018] Symbol explanation:

[0019] 10: Integrated Circuits (ICs)

[0020] 10R: Receiver

[0021] 10U: Upper-level circuit

[0022] 10. PHY: Physical Layer (PHY) Circuit

[0023] 10AF: Analog front-end circuit

[0024] 10DP: Data processing circuit

[0025] 11,12: Terminal components

[0026] 14: Differential Amplifier

[0027] PAD_P, PAD_N, Input_pair1_P, Input_pair1_N, Input_pair2_P, Input_pair2_N: Differential input terminals

[0028] DATA_P, DATA_N: Differential input signals

[0029] VCM1, VCM2, VCM_LP, VCM_HP: Common-mode voltage

[0030] VDC1, VDC2: Reference voltages

[0031] 100: Common-mode voltage rebias circuit

[0032] 110: Control Circuit

[0033] 121, 122: Switchable common-mode voltage rebiasing sub-circuit

[0034] 121A, 122A: Type I common-mode voltage rebiasing sub-circuit

[0035] 121B, 122B: Type II common-mode voltage rebiasing sub-circuit

[0036] R11~R13, R21~R23, R1, R2: Resistors

[0037] C10, C20: Capacitors

[0038] SW10~SW12, SW20~SW22, SW30, SW1~SW8: Switches

[0039] CTRL1, CTRL2: Control signals

[0040] CMD: Commands

[0041] 600: Input stage circuit

[0042] 610: Current source

[0043] M1~M4: Transistors

[0044] S10, S20~S22: Steps Detailed Implementation

[0045] Figure 1 This is a schematic diagram of a common-mode voltage rebiasing circuit 100 for common-mode voltage rebiasing in the analog front-end circuit 10AF of a receiver 10R, according to an embodiment of the present invention. The receiver 10R may include the analog front-end circuit 10AF and the data processing circuit 10DP. The analog front-end circuit 10AF may include a set of differential input terminals of the receiver 10R, such as differential input terminals PAD_P and PAD_N (which can be regarded as the positive and negative input terminals in this set of differential input terminals, respectively), and includes termination components 11 and 12, the common-mode voltage rebiasing circuit 100, and a differential amplifier 14. For example, termination components 11 and 12 may be implemented by resistors (e.g., two resistors with the same resistance value), but the present invention is not limited thereto. In some examples, termination components 11 and 12 may be implemented by resistors, capacitors, inductors, etc.

[0046] like Figure 1As shown, the common-mode voltage rebias circuit 100 may include a control circuit 110 and a plurality of switchable common-mode voltage rebias sub-circuits coupled to the control circuit 110, such as switchable common-mode voltage rebias sub-circuits 121 and 122. The switchable common-mode voltage rebias sub-circuit 121 may include a first-type common-mode voltage rebias sub-circuit 121A and a second-type common-mode voltage rebias sub-circuit 121B, which belong to the first type and the second type, respectively. The switchable common-mode voltage rebias sub-circuit 122 may include a first-type common-mode voltage rebias sub-circuit 122A and a second-type common-mode voltage rebias sub-circuit 122B, which belong to the first type and the second type, respectively. In particular, the switchable common-mode voltage rebias sub-circuit 121 may be located in the analog front-end circuit 10AF of the receiver 10R and coupled to the differential input terminal PAD_P of the receiver 10R, and the switchable common-mode voltage rebias sub-circuit 122 may be located in the analog front-end circuit 10AF of the receiver 10R and coupled to the differential input terminal PAD_N of the receiver 10R.

[0047] In this architecture, the control circuit 110 can generate at least one control signal, such as control signals CTRL1 and CTRL2, according to the command CMD to control the common-mode voltage rebias circuit 100 to operate in the selected circuit configuration. Additionally, the plurality of switchable common-mode voltage rebias sub-circuits, such as switchable common-mode voltage rebias sub-circuits 121 and 122, can respectively select a predetermined circuit configuration from a first predetermined circuit configuration and a second predetermined circuit configuration as the selected circuit configuration based on the aforementioned at least one control signal, such as control signals CTRL1 and CTRL2, to perform a common-mode voltage rebias operation corresponding to the selected circuit configuration.

[0048] For ease of understanding, the first type common-mode voltage rebiasing sub-circuit 121A and the second type common-mode voltage rebiasing sub-circuit 121 in the switchable common-mode voltage rebiasing sub-circuit 121 may have a first circuit architecture and a second circuit architecture, respectively. Similarly, the first type common-mode voltage rebiasing sub-circuit 122A and the second type common-mode voltage rebiasing sub-circuit 122B in the switchable common-mode voltage rebiasing sub-circuit 122 may have a third circuit architecture identical to the first circuit architecture and a fourth circuit architecture identical to the second circuit architecture, respectively, wherein the second circuit architecture differs from the first circuit architecture. Furthermore, the control circuit 110 can selectively enable the first type common-mode voltage rebiasing sub-circuit 121A and 122A, or enable the second type common-mode voltage rebiasing sub-circuit 121B and 122B, via at least one control signal such as control signals CTRL1 and CTRL2. For example, when the first type common-mode voltage rebiasing sub-circuits 121A and 122A are enabled, the control circuit 110 can disable the second type common-mode voltage rebiasing sub-circuits 121B and 122B. As another example, when the second type common-mode voltage rebiasing sub-circuits 121B and 122B are enabled, the control circuit 110 can disable the first type common-mode voltage rebiasing sub-circuits 121A and 122A.

[0049] The differential input signals DATA_P and DATA_N on the differential input terminals PAD_P and PAD_N may have a common-mode voltage VCM1 (denoted as "VCM1" on the two right-hand paths from the differential input terminals PAD_P and PAD_N, respectively, for simplicity), which is equal to the common-mode voltage VCM1 at the node between terminal components 11 and 12, such as a predetermined common-mode voltage input to this node. In this case, the common-mode voltage rebias circuit 100 can rebias the differential input signals DATA_P and DATA_N using the common-mode voltage, specifically, establishing a common-mode voltage VCM2 (denoted as "VCM2" on the two right-hand paths from the switchable common-mode voltage rebias sub-circuits 121 and 122, respectively, for simplicity), such as another predetermined common-mode voltage, to replace the common-mode voltage VCM1. While maintaining the common-mode voltage VCM2, the common-mode voltage rebias circuit 100 can dynamically control the common-mode voltage rebias operation to correspond to the currently selected circuit configuration to ensure the communication quality of various communication modes.

[0050] For example, in various communication modes, the analog front-end circuit 10AF can correctly perform analog front-end processing. In particular, the differential amplifier 14 can correctly receive the adjusted differential input signal (e.g., adjusted versions of the differential input signals DATA_P and DATA_N, located on the two right-hand paths from the switchable common-mode voltage rebiasing sub-circuits 121 and 122 to the differential amplifier 14) that has been rebiased to have a common-mode voltage VCM2, to obtain the series of logic values ​​carried by the differential input signals DATA_P and DATA_N. The data processing circuit 10DP can process this series of logic values ​​to allow the entire system, including the receiver 10R, to operate correctly. Therefore, the common-mode voltage rebiasing circuit 100, the receiver 10R, and the associated integrated circuits of the present invention can achieve optimized performance of electronic products without side effects or with a low probability of causing side effects.

[0051] According to certain embodiments, for a set of differential input signals received by receiver 10R, such as differential input signals DATA_P and DATA_N, the first frequency response of any one of the switchable common-mode voltage rebiasing sub-circuits 121 and 122 when operating in the first predetermined circuit configuration and the second frequency response of any one of the switchable common-mode voltage rebiasing sub-circuits when operating in the second predetermined circuit configuration are different from each other. For example, for this set of differential input signals such as differential input signals DATA_P and DATA_N, the first circuit architecture and the third circuit architecture may act as low-pass filters, while the second circuit architecture and the fourth circuit architecture may act as high-pass filters, but the invention is not limited thereto.

[0052] According to some embodiments, either the first circuit architecture or the third circuit architecture may include a first resistor and a second resistor, while either the second circuit architecture or the fourth circuit architecture may include a third resistor and a capacitor, but the invention is not limited thereto. In some embodiments, these first circuit architectures and / or these second circuit architectures may be varied.

[0053] Figure 2 An embodiment of the present invention illustrates a method for use in a receiver such as Figure 1The first predetermined circuit configuration involved in the dynamic circuit configuration control scheme of the common-mode voltage rebiasing method of the analog front-end circuit 10AF of the receiver 10R shown is described. This method can be applied to the common-mode voltage rebiasing circuit 100 (e.g., components therein), the receiver 10R, and related integrated circuits. The reference voltage VDC1 can represent a predetermined reference voltage. Resistors R11 and R12 can be examples of the first and second resistors, respectively, and resistors R21 and R22 can also be examples of the first and second resistors, respectively. Since resistors R12 and R22 are typically large, resistor R12 and the parasitic capacitance on the right-hand path from resistor R12 to the differential amplifier 14 can form a low-pass filter, and resistor R22 and the parasitic capacitance on the right-hand path from resistor R22 to the differential amplifier 14 can also form a low-pass filter. For simplicity, similar details are not repeated here in this embodiment.

[0054] Figure 3 According to an embodiment of the present invention, the second predetermined circuit configuration involved in the dynamic circuit configuration control scheme is illustrated. Resistor R13 and capacitor C10 can be examples of the third resistor and the capacitor, respectively, and resistor R23 and capacitor C20 can also be examples of the third resistor and the capacitor, respectively. Resistor R13 and capacitor C10 can form a high-pass filter, and resistor R23 and capacitor C20 can also form a high-pass filter. The common-mode voltage VCM2 on the right-hand path from capacitors C10 and C20 to the differential amplifier 14 can be equal to the common-mode voltage VCM2 at the node between resistors R13 and R23, such as a predetermined common-mode voltage input to this node, which can be generated based on the bandgap reference voltage. For the sake of simplicity, similar content is not repeated here in this embodiment.

[0055] Figure 4A first switching scheme of the method is illustrated according to an embodiment of the present invention. The switchable common-mode voltage rebiasing sub-circuit 121 may further include switches SW10-SW12 and SW30, and the switchable common-mode voltage rebiasing sub-circuit 122 may further include switches SW20-SW22 and SW30, wherein the switchable common-mode voltage rebiasing sub-circuits 121 and 122 may share switch SW30. When the control circuit 110 enables the first type of common-mode voltage rebiasing sub-circuits 121A and 122A via control signal CTRL1 and disables the second type of common-mode voltage rebiasing sub-circuits 121B and 122B via control signal CTRL2, control signal CTRL1 is in an enabled state to turn on switches SW10, SW11, SW20, and SW21, and control signal CTRL2 is in a disabled state to turn off switches SW12, SW22, and SW30. In this case, the common-mode voltage VCM2 can also be written as common-mode voltage VCM_LP to indicate that these first circuit architectures acting as low-pass filters are enabled. When the control circuit 110 disables the first type of common-mode voltage rebiasing sub-circuits 121A and 122A via control signal CTRL1 and enables the second type of common-mode voltage rebiasing sub-circuits 121B and 122B via control signal CTRL2, control signal CTRL1 is in a disabled state to close switches SW10, SW11, SW20, and SW21, and control signal CTRL2 is in an enabled state to open switches SW12, SW22, and SW30. In this case, the common-mode voltage VCM2 can also be written as common-mode voltage VCM_HP to indicate that these second circuit architectures acting as high-pass filters are enabled. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0056] Figure 5 A second switching scheme of the method is illustrated according to an embodiment of the present invention. In this embodiment, the switches SW11, SW12, SW21 and SW22 described above can be omitted. For the sake of simplicity, similar details will not be repeated here.

[0057] Figure 6A parasitic capacitance minimization switching scheme of the method is illustrated according to an embodiment of the present invention. The input stage circuit 600 in the differential amplifier 14 may include a current source 610, multiple resistors R1 and R2 coupled to a reference voltage VDC2, multiple transistors M1 to M4, and multiple switches SW1 to SW8, wherein the gates of transistors M1 to M4 are respectively coupled to the differential input terminals Input_pair1_P, Input_pair1_N, Input_pair2_P, and Input_pair2_N of the differential amplifier 14, and the reference voltage VDC2 may represent a predetermined reference voltage. Since the common-mode voltage rebias circuit 100 and the input stage circuit 600 can be switched simultaneously according to at least one control signal, such as control signals CTRL1 and CTRL2, the receiver 10R can minimize the effects of parasitic effects between the various architectures to ensure signal quality for high-speed transmission. For simplicity, similar details are not repeated here in this embodiment.

[0058] Figure 7 An integrated circuit (IC) 10 operating according to the method is illustrated according to an embodiment of the present invention, wherein the IC 10 may include Figure 1 The receiver 10R is shown. According to this embodiment, the receiver 10R may include a physical layer (PHY) circuit 10PHY and an upper-layer circuit 10U such as a Media Access Control (MAC) layer circuit, wherein the PHY circuit 10PHY may include a common-mode voltage rebias circuit 100. The upper-layer circuit 10U may select a predetermined communication mode from a plurality of predetermined communication modes as the selected communication mode, and send a command CMD according to the selected communication mode to make the selected circuit configuration correspond to the selected communication mode. For example, the control circuit 110 may selectively enable the first type of common-mode voltage rebias sub-circuit 121A and 122A, or the second type of common-mode voltage rebias sub-circuit 121B and 122B, through at least one of the above-mentioned control signals such as control signals CTRL1 and CTRL2, to conform to the selected communication mode of the receiver 10R, wherein the selected communication mode is selected from the plurality of predetermined communication modes, and the communication speed (e.g., transfer rate) of the plurality of predetermined communication modes is different from each other. Therefore, the common-mode voltage rebias circuit 100 can simultaneously ensure signal quality for both high-speed and low-speed transmission. For the sake of simplicity, similar details will not be repeated in this embodiment.

[0059] According to some embodiments, the plurality of predetermined communication modes may include communication modes of different generations (Gen) of the Peripheral Component Interconnect Express (PCIe) standard, such as PCIe Gen 1 to Gen 5, where the transmission rates of PCIe Gen 1 to Gen 5 may be 2.5 Gigabits per second (Gbps), 5 Gbps, 8 Gbps, 16 Gbps, and 32 Gbps, respectively, but the present invention is not limited thereto. Additionally, the common-mode voltage rebias circuit 100 can switch between different types of circuit architectures when the receiver 10R operates at different generation transmission rates. When the receiver 10R operates at a lower transmission rate, such as 2.5 Gbps of PCIe Gen 1, the common-mode voltage rebias circuit 100 can use these first circuit architectures with low-pass effects (e.g., Figure 2 The circuit architecture shown in the first predetermined circuit configuration, wherein resistors R11, R12, R21, and R22 can be designed with large resistance values ​​to achieve power saving. When the receiver 10R operates at a higher transmission rate such as 32Gbps PCIe Gen 5, the common-mode voltage rebias circuit 100 can use these second circuit architectures with high-pass effect (e.g., Figure 3 The circuit architecture in the second predetermined circuit configuration shown can be configured such that capacitors C10 and C20 have small capacitance values ​​to save on bare die area. For the sake of simplicity, similar details in these embodiments will not be repeated here.

[0060] Figure 8 The workflow of the method is illustrated according to an embodiment of the present invention. Steps S10 and S20 can be repeated to dynamically adjust the circuit configuration of the common-mode voltage rebias circuit 100, and step S20 may include multiple sub-steps such as steps S21 and S22, which can be performed in parallel.

[0061] In step S10, the common-mode voltage rebias circuit 100 may use the control circuit 110 to generate at least one control signal, such as control signals CTRL1 and CTRL2, according to the command CMD, to control the common-mode voltage rebias circuit 100 to operate in a selected circuit configuration, such as the selected circuit configuration described above.

[0062] In step S20, the common-mode voltage rebias circuit 100 can utilize the plurality of switchable common-mode voltage rebias sub-circuits (e.g., switchable common-mode voltage rebias sub-circuits 121 and 122) of the common-mode voltage rebias circuit 100 to select a predetermined circuit configuration such as the above-mentioned predetermined circuit configuration from the first predetermined circuit configuration and the second predetermined circuit configuration according to at least one control signal such as control signal CTRL1 and CTRL2 as the selected circuit configuration, so as to perform a common-mode voltage rebias operation corresponding to the selected circuit configuration.

[0063] In step S21, the common-mode voltage rebias circuit 100 may use a switchable common-mode voltage rebias sub-circuit 121 to select the predetermined circuit configuration from the first predetermined circuit configuration and the second predetermined circuit configuration as the selected circuit configuration based on at least one control signal such as control signals CTRL1 and CTRL2, so as to perform a first common-mode voltage rebias operation corresponding to the selected circuit configuration.

[0064] In step S22, the common-mode voltage rebias circuit 100 may use a switchable common-mode voltage rebias sub-circuit 122 to select the predetermined circuit configuration from the first predetermined circuit configuration and the second predetermined circuit configuration as the selected circuit configuration based on at least one control signal such as control signals CTRL1 and CTRL2, so as to perform a second common-mode voltage rebias operation corresponding to the selected circuit configuration.

[0065] During the maintenance of the common-mode voltage VCM2, the common-mode voltage rebias circuit 100 can dynamically control the common-mode voltage rebias operation to correspond to the currently selected circuit configuration, thereby ensuring the communication quality of various communication modes. Therefore, the method of the present invention, the common-mode voltage rebias circuit 100, the receiver 10R, and the integrated circuit 10 can achieve optimized performance of electronic products with little or no side effects. For the sake of simplicity, similar details are not repeated in this embodiment.

[0066] To better understand, this method is available Figure 8 The workflow shown is for illustrative purposes only, but the invention is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 8 Add, delete, or modify in the workflow shown.

[0067] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should fall within the scope of the present invention.

Claims

1. A common-mode voltage re-biasing circuit for performing common-mode voltage re-biasing in the analog front-end circuit of a receiver, characterized in that, The common-mode voltage rebias circuit includes: A control circuit is used to generate at least one control signal according to a command to control the common-mode voltage rebias circuit to operate in a selected circuit configuration. as well as Multiple switchable common-mode voltage rebiasing sub-circuits are coupled to the control circuit and are used to select a predetermined circuit configuration from a first predetermined circuit configuration and a second predetermined circuit configuration respectively according to the at least one control signal, so as to perform a common-mode voltage rebiasing operation corresponding to the selected circuit configuration. The multiple switchable common-mode voltage rebiasing sub-circuits include: A first switchable common-mode voltage rebias sub-circuit is located in the analog front-end circuit of the receiver and coupled to the first differential input terminal of the receiver; and The second switchable common-mode voltage rebias sub-circuit is located in the analog front-end circuit of the receiver and coupled to the second differential input terminal of the receiver. The first switchable common-mode voltage rebiasing sub-circuit includes: The first type of common-mode voltage rebias sub-circuit has a first circuit architecture; and A second type of common-mode voltage rebias sub-circuit has a second circuit architecture, wherein the second circuit architecture differs from the first circuit architecture; and The second switchable common-mode voltage rebias sub-circuit includes: The third type of common-mode voltage rebiasing sub-circuit has the same third circuit architecture as the first circuit architecture; and The fourth type of common-mode voltage rebias sub-circuit has the same fourth circuit architecture as the second circuit architecture; The control circuit selectively enables the first type of common-mode voltage re-biasing sub-circuit and the third type of common-mode voltage re-biasing sub-circuit, or enables the second type of common-mode voltage re-biasing sub-circuit and the fourth type of common-mode voltage re-biasing sub-circuit, through at least one control signal. Either the first circuit architecture or the third circuit architecture includes a first resistor and a second resistor, and either the second circuit architecture or the fourth circuit architecture includes a third resistor and a capacitor.

2. The common-mode voltage re-bias circuit as described in claim 1, characterized in that, When the first type of common-mode voltage rebiasing sub-circuit and the third type of common-mode voltage rebiasing sub-circuit are enabled, the control circuit disables the second type of common-mode voltage rebiasing sub-circuit and the fourth type of common-mode voltage rebiasing sub-circuit; and when the second type of common-mode voltage rebiasing sub-circuit and the fourth type of common-mode voltage rebiasing sub-circuit are enabled, the control circuit disables the first type of common-mode voltage rebiasing sub-circuit and the third type of common-mode voltage rebiasing sub-circuit.

3. The common-mode voltage rebias circuit as described in claim 1, wherein, The control circuit selectively enables the first type common-mode voltage rebiasing sub-circuit and the third type common-mode voltage rebiasing sub-circuit, or enables the second type common-mode voltage rebiasing sub-circuit and the fourth type common-mode voltage rebiasing sub-circuit, through the at least one control signal, to conform to the communication mode selected by the receiver.

4. The common-mode voltage re-bias circuit as described in claim 3, characterized in that, The selected communication mode is chosen from a plurality of predetermined communication modes, wherein the communication speeds of the plurality of predetermined communication modes are different from each other.

5. The common-mode voltage re-bias circuit as described in claim 1, characterized in that, For a set of differential input signals received by the receiver, the first frequency response of any one of the first switchable common-mode voltage rebias sub-circuit and the second switchable common-mode voltage rebias sub-circuit when operating in the first predetermined circuit configuration and the second frequency response of any one of the switchable common-mode voltage rebias sub-circuit when operating in the second predetermined circuit configuration are different from each other.

6. A receiver comprising the common-mode voltage rebias circuit as described in claim 1, characterized in that, The receiver includes: Physical layer circuitry, wherein the physical layer circuitry includes the common-mode voltage rebias circuitry; and The upper-level circuit is used to select a predetermined communication mode from a plurality of predetermined communication modes as the selected communication mode, and to send the command according to the selected communication mode, so that the selected circuit configuration corresponds to the selected communication mode.

7. An integrated circuit comprising the receiver as described in claim 6.

8. A method for common-mode voltage re-biasing in the analog front-end circuit of a receiver, characterized in that, The method includes: Generate at least one control signal according to the command to control the common-mode voltage rebias circuit to operate in the selected circuit configuration; and The common-mode voltage rebiasing circuit utilizes multiple switchable common-mode voltage rebiasing sub-circuits to select a predetermined circuit configuration from a first predetermined circuit configuration and a second predetermined circuit configuration based on at least one control signal, thereby performing a common-mode voltage rebiasing operation corresponding to the selected circuit configuration. The multiple switchable common-mode voltage rebiasing sub-circuits include a first switchable common-mode voltage rebiasing sub-circuit and a second switchable common-mode voltage rebiasing sub-circuit. The first and second switchable common-mode voltage rebiasing sub-circuits are respectively located in the analog front-end circuit of the receiver and respectively coupled to the first and second differential input terminals of the receiver. The first switchable common-mode voltage rebiasing sub-circuit includes: The first type of common-mode voltage rebias sub-circuit has a first circuit architecture; and A second type of common-mode voltage rebias sub-circuit has a second circuit architecture, wherein the second circuit architecture differs from the first circuit architecture; and The second switchable common-mode voltage rebias sub-circuit includes: The third type of common-mode voltage rebiasing sub-circuit has the same third circuit architecture as the first circuit architecture; and The fourth type of common-mode voltage rebias sub-circuit has the same fourth circuit architecture as the second circuit architecture; The control circuit selectively enables the first type of common-mode voltage re-biasing sub-circuit and the third type of common-mode voltage re-biasing sub-circuit, or enables the second type of common-mode voltage re-biasing sub-circuit and the fourth type of common-mode voltage re-biasing sub-circuit, through at least one control signal. Either the first circuit architecture or the third circuit architecture includes a first resistor and a second resistor, and either the second circuit architecture or the fourth circuit architecture includes a third resistor and a capacitor.

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