Voltage regulator, chip and device

Abstract

The application relates to a voltage stabilizer, a chip and a device, the voltage stabilizer comprising an error amplifier, a voltage dividing circuit, a power tube and a compensation circuit, the error amplifier comprising a current mirror circuit and a differential pair tube circuit, the differential pair tube circuit comprising differential pair tubes in multiple stages in series, the gates of first transistors in the differential pair tubes in the multiple stages being connected with the voltage dividing circuit, the gates of second transistors in the differential pair tubes in the multiple stages being connected with a reference voltage source, the current mirror circuit being connected with the gates of a first-stage differential pair tube in the differential pair tube circuit and the power tube, the drain of the power tube being connected with the compensation circuit and the voltage dividing circuit, and the compensation circuit being connected with the source of the second transistor in the first-stage differential pair tube and the voltage dividing circuit. The difficulty in realizing the voltage stabilizer is reduced, the right half plane zero is avoided, and the stability of a loop is improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a voltage regulator, chip, and device. Background Technology

[0002] In IoT chip systems, many systems reduce power consumption by converting lithium batteries or other power sources into a lower output voltage. This output voltage is then used to power some low dropout regulators (LDOs) on the chip. The lower the output voltage, the less current is consumed at the battery terminal, and therefore the longer the battery can power the device.

[0003] Current LDOs include cascode circuits and error amplifiers. For example, a cascode circuit includes two pairs of transistors, each pair of transistors forming a cascode circuit, and the cascode bias voltage of one pair of transistors is generated by an additional bias circuit.

[0004] However, current LDOs require additional bias circuitry, making them difficult to implement. Summary of the Invention

[0005] Therefore, it is necessary to provide a voltage regulator, chip, and device that can reduce the implementation difficulty of bias circuits to address the above-mentioned technical problems.

[0006] In a first aspect, this application provides a voltage regulator, which includes an error amplifier, a voltage divider circuit, a power transistor, and a compensation circuit. The error amplifier includes a current mirror circuit and a differential pair circuit. The differential pair circuit includes multiple differential pairs connected in series. The gate of the first transistor in each stage of the differential pair is connected to the voltage divider circuit, and the gate of the second transistor in each stage of the differential pair is connected to a reference voltage source. The current mirror circuit is connected to the gates of the first stage differential pair and the power transistor in the differential pair circuit. The drain of the power transistor is connected to the compensation circuit and the voltage divider circuit. The compensation circuit is connected to the source of the second transistor in the first stage differential pair and the voltage divider circuit.

[0007] The error amplifier is used to control the current of the power transistor based on the reference voltage provided by the reference voltage source and the output voltage of the voltage divider circuit, so that the output voltage of the regulator is within a preset voltage range.

[0008] In one embodiment, the compensation circuit is used to lower the pole of the gate of the power transistor and raise the pole of the drain of the power transistor.

[0009] In one embodiment, the compensation circuit includes a compensation capacitor, a first terminal of which is connected to the source of the second transistor in the first stage differential pair, and a second terminal of which is connected to the voltage divider circuit.

[0010] The compensation capacitor is used to lower the pole of the gate of the power transistor and raise the pole of the drain of the power transistor.

[0011] In one embodiment, the differential pair circuit includes a first-stage differential pair and at least one second-stage differential pair, wherein the source of the first-stage differential pair is connected to the drain of an adjacent second-stage differential pair, and the sources of the two transistors in the last of the at least one second-stage differential pair are connected.

[0012] In one embodiment, the number of second-stage differential pairs is multiple, and the multiple second-stage differential pairs include intermediate-stage differential pairs and a last second-stage differential pair;

[0013] In two adjacent intermediate stage differential pairs, the source of the first intermediate stage differential pair is connected to the drain of the second intermediate stage differential pair, and the source of the last intermediate stage differential pair is connected to the drain of the last second stage differential pair.

[0014] In one embodiment, the error amplifier further includes a bias current source, wherein the source of the last stage differential pair in the differential pair circuit is connected to a first terminal of the bias current source, and a second terminal of the bias current source is grounded.

[0015] The bias current source is used to provide current to the error amplifier.

[0016] In one embodiment, the voltage divider circuit includes a first resistor and a second resistor;

[0017] The compensation circuit is connected to the first end of the first resistor and the power transistor. The second end of the first resistor is connected to the first end of the second resistor and the gate of each first transistor in the differential pair circuit. The second end of the second resistor is grounded.

[0018] In one embodiment, the voltage regulator further includes a power supply, and the current mirror circuit and the power transistor are connected to the power supply.

[0019] Secondly, this application also provides a chip, including the aforementioned voltage regulator.

[0020] Thirdly, this application also provides a device, including the aforementioned chip.

[0021] In the aforementioned voltage regulator, chip, and device, since the gate of the first transistor in each differential pair is connected to a voltage divider circuit, the output voltage of the voltage divider circuit is fed back to the gate of the first transistor in each differential pair, and the gate of the first transistor in each differential pair serves as the non-inverting input of the voltage regulator. The gate of the second transistor in each differential pair is connected to a reference voltage source, meaning the reference voltage source provides a reference voltage to the gate of the second transistor in each differential pair, and the gate of the second transistor in each differential pair serves as the inverting input of the voltage regulator. Because the gate of the first transistor in each differential pair is connected to a voltage divider circuit, and the gate of the second transistor in each differential pair is connected to a reference voltage source, no additional bias circuit is needed to provide the gate voltage to the transistors in the differential pair of the error amplifier; that is, no additional bias circuit is required. Therefore, the implementation difficulty of the voltage regulator is reduced. Furthermore, since the compensation circuit is connected to the source of the second transistor in the first-stage differential pair and the voltage divider circuit, there is no obvious direct path from the gate of the power transistor through the compensation circuit to the output terminal in the circuit, thus avoiding the right half-plane zero point and improving the stability of the loop. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a general LDO structure provided in an embodiment of this application;

[0023] Figure 2 This is a schematic diagram of the structure of a general-purpose low-voltage LDO provided in the embodiments of this application;

[0024] Figure 3 for Figure 2 A schematic diagram of the specific structure of the LDO is shown;

[0025] Figure 4 This is a schematic diagram of an LDO circuit structure using a common source and common gate circuit.

[0026] Figure 5 This is a schematic diagram of the structure of a voltage regulator provided in an embodiment of this application;

[0027] Figure 6 This is a schematic diagram of the structure of a voltage regulator provided in an embodiment of this application;

[0028] Figure 7 This is the loop small-signal model of the voltage regulator provided in the embodiments of this application;

[0029] Figure 8 This is the small-signal model for open-loop PSRR analysis of the voltage regulator provided in the embodiments of this application;

[0030] Figure 9 Is it like this? Figure 3 The open-loop PSRR analysis small-signal model of the voltage regulator is shown.

[0031] Figure 10 A schematic diagram of the PSRR simulation effect provided for an embodiment of this application.

[0032] Explanation of reference numerals in the attached figures:

[0033] 501. Error amplifier; 502. Voltage divider circuit; 503. Power transistor;

[0034] 504. Compensation circuit; 5011. Current mirror circuit; 5012. Differential pair transistor circuit;

[0035] 601. Compensation capacitor. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0037] Figure 1 This is a schematic diagram of a general LDO structure provided in an embodiment of this application. The entire LDO loop forms a negative feedback structure. The LDO includes an error amplifier (EA), a compensation capacitor Cc, a buffer, and a power transistor M. POW Resistors R1 and R2, power transistor M POW This refers to a PMOS transistor, short for Positive Channel Metal Oxide Semiconductor. A PMOS transistor is an n-type substrate, p-channel MOSFET that relies on the flow of holes to carry current. Due to the presence of a high-gain negative feedback loop, the output voltage V... OUT The voltage V after voltage division FB Locked at reference voltage V REF The buffer gain is approximately 1, its purpose being to provide high input impedance and low output impedance, thereby controlling the power transistor M. POW The large input capacitance raises the zeros and poles beyond the unit bandwidth, ensuring the LDO loop remains stable under both light and heavy loads. Due to the significant variation in load impedance, a compensation capacitor C is typically required. C Perform loop compensation.

[0038] At lower supply voltages, the aforementioned LDO circuit struggles to achieve high performance for the following reasons: First, the non-cascode EA op-amp struggles to achieve significant gain, resulting in a low loop gain and insufficient low-frequency PSRR. Furthermore, the compensation capacitor is directly connected to the power transistor's gate or the buffer input, leading to poor high-frequency PSRR. Second, the buffer circuit consumes voltage margin; for example, if VIN is 1.0V, V... OUT When a voltage of 0.8V is required, the threshold voltage Vth of the power transistor PMOS is equal to 0.5V. Therefore, the output voltage of the buffer must be lower than 0.5V, otherwise the power transistor will have difficulty conducting, which results in a very small design margin for the error amplifier.

[0039] In order to solve Figure 1 The problems with LDOs in China, currently adopted Figure 2 and Figure 3 The structure, Figure 2 This is a schematic diagram of the structure of a general-purpose low-voltage LDO provided in an embodiment of this application. Figure 2 exist Figure 1 The buffer that required voltage margin was removed from the basic design. Figure 3 for Figure 2 The diagram shows the specific structure of the LDO. Figure 3 In this case, since complex EA circuits cannot be designed under low voltage, only M can be used. N0 ~M N2 M P1 ~M P2 The simplest five-transistor op-amp is equivalent to Figure 2 Error amplifier EA, power transistor M POW It is directly used as the driver stage, eliminating the buffer stage that consumes voltage margin. Meeting loop stability requirements at low supply voltages is already quite difficult because the error amplifier has a simple structure and fewer connection points. Figure 2 Medium compensation capacitor C C Directly connected to power transistor M POW The gate introduces a right-half-plane zero, reducing loop stability. Even with... Figure 2 The compensation method in this paper can ensure that the phase margin of the loop is sufficient under all set loads, but its compensation capacitor C C It is connected across the power transistor M POW Between the gate and drain, therefore, under a fixed load current, V GS It also needs to remain unchanged, therefore, the power transistor M POW The gate voltage will follow the power supply voltage V IN It changes with the power transistor M. POWThe gate's PSRR is 0 dB. Since the capacitor's impedance is negatively correlated with frequency, the compensation capacitor's impedance is very low at mid-to-high frequencies, resulting in V... IN The noise on will be directly fed into V. OUT This results in poor PSRR. To ensure the compensation effect, the compensation capacitor C... C The value should not be too small, as this will further worsen PSRR.

[0040] To improve PSRR, currently, the following are provided: Figure 4 The LDO shown. Figure 4 This is a schematic diagram of an LDO circuit structure employing a common-source, common-gate transistor. The LDO includes an error amplifier EA and a power transistor M. POW Compensation capacitor C C Resistors R1 and R2, and the error amplifier includes transistor M. P1 M P2 M N12 M N22 M N11 M N2 M N0 It should be noted that transistors with an N subscript in the figures of this application's embodiments are NMOS transistors, where NMOS is short for N-Metal-Oxide-Semiconductor. Transistors with an N subscript in the figures of this application's embodiments are PMOS transistors. N12 and M N11 To form a common source cascode circuit, M N22 and M N21 To form a common source cascode circuit, V BN2 This is the common-source, common-gate bias voltage, generated by an additional bias circuit. Capacitor C C The left side connects to M N22 The source pole. M N11 M N12 M N21 M N22 Both operate in the saturation region. Because it is necessary to ensure M... N11 and M N21 Both must be in the saturation region, which requires V BN2 Need to follow V REF The changes in bias circuitry present challenges due to the high requirements for the bias circuitry and the difficulty in its implementation.

[0041] The embodiments of this application are intended to solve... Figure 4 To address the challenges of high requirements for bias circuitry and the difficulty in implementation of traditional LDOs, a voltage regulator is provided. For example... Figure 5 As shown, Figure 5This is a schematic diagram of a voltage regulator provided in an embodiment of this application. The voltage regulator includes an error amplifier 501, a voltage divider circuit 502, a power transistor 503, and a compensation circuit 504. The error amplifier includes a current mirror circuit 5011 and a differential pair circuit 5012. The differential pair circuit includes multiple differential pairs connected in series. The gate of the first transistor in each differential pair is connected to the voltage divider circuit, and the gate of the second transistor in each differential pair is connected to a reference voltage source. The current mirror circuit is connected to the gates of the first-stage differential pair and the power transistor in the differential pair circuit. The drain of the power transistor is connected to the compensation circuit and the voltage divider circuit. The compensation circuit is connected to the source of the second transistor in the first-stage differential pair and the voltage divider circuit.

[0042] An error amplifier is used to control the current of the power transistor based on the reference voltage provided by the reference voltage source and the output voltage of the voltage divider circuit, so that the output voltage of the regulator is within a preset voltage range. For example, Figure 4 As shown, the reference voltage source can provide a reference voltage V to the inverting input of the error amplifier. REF .

[0043] The error amplifier can control the output voltage of the regulator to be within a preset voltage range based on the reference voltage provided by the reference voltage source and the output voltage of the voltage divider circuit. For example, in a balanced state, the output voltage V of the voltage divider circuit... FB With V REF Approximately equal, in the output voltage V of the voltage divider circuit FB When the voltage is reduced, the error amplifier compares the output voltage V. FB and reference voltage V REF Afterwards, the internal energy storage capacitor can discharge, thereby increasing the output current of the voltage regulator, which in turn increases the output voltage of the voltage regulator, controlling the output voltage of the voltage regulator to be within the preset voltage range.

[0044] In this embodiment, each differential pair includes two transistors: a first transistor and a second transistor. For example... Figure 5 As shown, the first differential pair viewed from top to bottom is the first-stage differential pair, which includes M. N1M and M N2M The first-stage differential pair has N differential pairs below it. The diagram only shows the last two differential pairs out of the N, namely differential pair M. N12 and M N22 And it shows the differential pair tube M N11 and M N21 Where M equals N+1.

[0045] The voltage regulator provided in this embodiment has the following characteristics: The gates of the first transistors in each differential pair are connected to a voltage divider circuit, meaning the output voltage of the voltage divider circuit is fed back to the gates of the first transistors in each differential pair, which serve as the non-inverting input of the regulator. The gates of the second transistors in each differential pair are connected to a reference voltage source, meaning the reference voltage source provides a reference voltage to the gates of the second transistors in each differential pair, which serve as the inverting input of the regulator. Because the gates of the first transistors in each differential pair are connected to the voltage divider circuit, and the gates of the second transistors in each differential pair are connected to the reference voltage source, no additional bias circuit is needed to provide gate voltages to the transistors in the differential pair of the error amplifier. This eliminates the need for an additional bias circuit, thus reducing the implementation difficulty of the voltage regulator. Furthermore, since the compensation circuit is connected to the source of the second transistor in the first-stage differential pair and the voltage divider circuit, there is no obvious direct path from the gate of the power transistor through the compensation circuit to the output terminal in the circuit, thus avoiding the right half-plane zero point and improving the stability of the loop.

[0046] Figure 6 This is a schematic diagram of a voltage regulator provided in an embodiment of this application. The current mirror circuit 5011 can be configured to... Figure 6 transistor M in P1 Transistor M P2 The circuit is composed of transistor M. Optionally, transistor M can also be used. P1 The source of the transistor is connected to a resistor, and in the transistor M P2 A current mirror circuit 5011 is formed by connecting a resistor to the source of transistor M. This application does not limit the implementation method of the current mirror. It should be noted that in transistor M... P1 The source of the transistor is connected to a resistor, and in the transistor M P2 The current mirror circuit 5011, which is formed by connecting a resistor to the source of the LDO, can reduce the noise of the LDO.

[0047] For example, in the output voltage V of the voltage divider circuit FB When the voltage is reduced, the error amplifier compares the output voltage V. FB and reference voltage V REF Then, the current of the power transistor can be increased, thereby increasing the output voltage of the regulator and keeping it within a preset voltage range. This improves the loop stability of the low-dropout linear regulator.

[0048] like Figure 5 As shown, the compensation circuit 504 is used to lower the pole of the gate of the power transistor and raise the pole of the drain of the power transistor.

[0049] The compensation circuit 504 can be implemented with a single capacitor, or with multiple capacitors connected in series, or with two capacitors connected in parallel and then connected in series with another capacitor, etc. The embodiments of this application do not limit this.

[0050] Figure 4 The LDO shown will cause two paths of opposite polarity from node V1 to VOUT, one of which goes through power transistor M. POW The common-source amplifier constructed has a negative gain, while another path directly passes through the compensation capacitor CC, resulting in a positive gain. The sum of these two paths leads to a right-half-plane zero in the transfer function, threatening the stability of the loop.

[0051] In this embodiment of the application, due to M N11 ~M N1N Operating in the linear region, M N1M Operating in the saturation region, therefore M N11 ~M N1N It can be considered as a resistor. M N21 ~M N2N Both operate in the linear region and can be treated as resistors. M N2M It operates in the saturation region. For ease of explanation, as... Figure 6 As shown, M N2M The source pole is denoted as node V. x Power transistor M POW The gate is denoted as node V1, and the compensation circuit is connected to M. N2M The source, due to M N2M The system operates in the saturation region, therefore changes in node V1 will only affect node V. x The voltage changes very little, therefore, Figure 6 There is no obvious flow from node V1 through the compensation circuit to V OUT The direct path avoids the zero point in the right half-plane, thereby improving the stability of the loop.

[0052] and, Figure 4 The power supply voltage of the LDO shown is also a problem, because it is necessary to simultaneously ensure M N12 M N22 M N11 M N21 When operating in the saturation region, the voltage at node V1 cannot be too low. This requires that the power supply voltage cannot be too low, making it difficult to achieve a low power supply voltage. Figure 4 Medium power transistor M POW The gate is denoted as node V1, M N22 The source pole is denoted as node V. xIn this embodiment, since the gates of the first transistors in each differential pair are connected to the voltage divider circuit, and the gates of the second transistors in each differential pair are connected to the reference voltage source, the first-stage differential pair operates in the saturation region, while the remaining N differential pairs operate in the linear region. Therefore, a lower power supply voltage can be achieved.

[0053] like Figure 6 As shown, the compensation circuit 504 includes the following: Figure 6 The compensation capacitor 601 shown has its first terminal connected to the source of the second transistor in the first-stage differential pair, and its second terminal connected to the voltage divider circuit.

[0054] Compensation capacitor 601 is used to lower the gate pole of the power transistor and raise the drain pole. Specifically, it lowers the parasitic pole at node V1, making it the dominant pole of the loop, thus lowering the output node V... OUT The poles are raised to become secondary poles, achieving pole splitting and improving loop stability.

[0055] Figure 4 The LDO shown has node V1 voltage following the supply voltage V. IN Therefore, the power supply rejection ratio (PSRR) of node V1 is almost 0 dB. IN The noise will pass directly through node V1 and then through C. C Feedthrough to V OUT Above, the PSRR is very poor, and the larger the capacitance value C is... C This will improve the compensation effect, but worsen the PSRR. The voltage regulator provided in this application embodiment, due to M... N2M The source voltage is not sensitive to the voltage at node V1, therefore V IN Only a very small component of the noise will pass through C. C Feedthrough to V OUT Even if C C Increasing the size can also result in a better PSRR.

[0056] like Figure 6 As shown, the differential pair circuit includes a first-stage differential pair and at least one second-stage differential pair. The source of the first-stage differential pair is connected to the drain of the adjacent second-stage differential pair. The sources of the two transistors in the last second-stage differential pair are connected.

[0057] For example, Figure 6 The second-stage differential pair shown is except for M. N1M and M N2M Differential pairs other than those.

[0058] In one embodiment, such as Figure 6 As shown, there are multiple second-stage differential pairs, including intermediate-stage differential pairs and the last second-stage differential pair.

[0059] In two adjacent intermediate stage differential pairs, the source of the first intermediate stage differential pair is connected to the drain of the second intermediate stage differential pair, and the source of the last intermediate stage differential pair is connected to the drain of the last second stage differential pair.

[0060] In this embodiment of the application, the last second-stage differential pair transistor includes M. N11 and M N21 .

[0061] It should be noted that the length and width of the channel of the transistor in the differential pair can be increased. By increasing the length and width of the channel of the transistor in the differential pair, the noise of the LDO can be further reduced.

[0062] like Figure 6 As shown, the error amplifier also includes a bias current source. The source of the last stage of the differential pair in the differential pair circuit is connected to the first terminal of the bias current source, and the second terminal of the bias current source is grounded.

[0063] The bias current source is used to supply current to the error amplifier.

[0064] like Figure 6 As shown, the bias current source can be obtained through, as... Figure 6 The transistor M shown N0 This can be achieved using a constant current source, or alternatively, using other constant current sources. Transistor M N0 The gate of the transistor is connected to a voltage source, which is transistor M. N0 Provides gate voltage, transistor M N0 The source is grounded, transistor M N0 The drain of the transistor is connected to the source of the last second-stage differential pair.

[0065] In one embodiment, such as Figure 6 As shown, the voltage divider circuit includes a first resistor R1 and a second resistor R2;

[0066] The compensation circuit is connected to the first end of the first resistor and the power transistor. The second end of the first resistor is connected to the first end of the second resistor and the gate of each first transistor in the differential pair circuit. The second end of the second resistor is grounded.

[0067] Wherein, the first resistor R1 is the voltage divider resistor in this voltage divider circuit, and the voltage V shared by the first resistor R1 is... FB equals V OUTMultiply by the ratio of the resistance value of the first resistor to the target resistance value, the target resistance value is equal to the sum of the resistance values ​​of the first resistor R1 and the second resistor R2.

[0068] The compensation circuit includes, for example, a compensation capacitor C. C In this case, the compensation capacitor C C The first terminal of the first resistor R1 is connected to the first terminal of the first resistor R1 and the drain of the power transistor. The second terminal of the first resistor R1 is connected to the first terminal of the second resistor R2 and the gate of each first transistor in the differential pair circuit. The second terminal of the second resistor R2 is grounded. The compensation capacitor C... C The second terminal is connected to the source of the first-stage transistor.

[0069] It should be noted that a voltage divider circuit can include at least two resistors, and its design can be similar to that of a voltage divider circuit in a current LDO. For example, a voltage divider circuit can include four resistors: the first and second resistors are connected in parallel, and then the third resistor is connected in series to form a voltage divider resistor. This voltage divider resistor is then connected in series with a fourth resistor to form the voltage divider circuit.

[0070] In one embodiment, the regulator also includes a power supply, with the current mirror circuit 5011 and power transistor 503 connected to the power supply.

[0071] To provide a detailed explanation of the high PSRR achieved by the voltage regulator provided in this application embodiment, this document will combine... Figure 7 , Figure 8 , Figure 9 To introduce, Figure 7 This is the loop small-signal model of the voltage regulator provided in the embodiments of this application. Figure 8 This is the small-signal model for open-loop PSRR analysis of the voltage regulator provided in the embodiments of this application. Figure 9 Is it like this? Figure 3 The small-signal model of the open-loop PSRR analysis of the voltage regulator is shown.

[0072] For loop compensation, M N21 ~M N2N Similar to N resistors r ds Connected to the communication point, from V OUT The feedback signal is fed into node V. x After passing through M N2M The common-gate amplifier is supplied to node V1. Node V x The equivalent impedance to ground is 1 / g mn Parallel N*r ds , where g mn For M N1M Or M N2M The transconductance. Because M N11 ~M N1NCurrent and size with M N1M The current and size are the same, therefore, M N1M transconductance g mn With M N11 ~M N1N-1 r ds The relation is g mn =1 / r ds .

[0073] Figure 7 It gave its Figure 6 The small-signal model of the loop. r0 is... Figure 6 The equivalent resistance of node V1 to ground; g ds For N*r ds The equivalent conductance, and satisfying g ds =1 / (N*r ds ) = g mn / N;g mp for Figure 6 Medium power transistor M POW Equivalent transconductance; R L and C L These represent the resistive load to ground and the capacitive load of the LDO, respectively; v o for Figure 6 V in OUT Small signal components; v fb for Figure 6 V in FB Small signal components; v1 is Figure 6 The small signal component of V1. According to Figure 7 The small-signal model yields three nodal equations:

[0074]

[0075] g mn v x +g ds v x =SC c (v o -v x )

[0076]

[0077] Omitted from V OUT To V FB After gaining, the loop from V is obtained. FB To V OUT The open-loop transfer function is denoted by formula (2):

[0078]

[0079] Based on the above open-loop transfer function, it can be analyzed that it contains one left-half-plane zero and two poles, as shown in the following formula (3):

[0080]

[0081]

[0082]

[0083]

[0084] Where, ω z ω is the zero point of the left half-plane. p1 Principal pole, ω p2 This is a secondary pole. A V1 For the low-frequency gain of the error amplifier: A V1 =g mn r o A V2 For the low-frequency gain of the power transistor: A V2 =g mp R L GBW represents unity-gain bandwidth. There are no zeros in the right half-plane, only zeros in the left half-plane, thus ensuring loop stability. Because A... V1 With A V2 The product of ω and ω is very large, thus achieving pole splitting. p1 Much lower than ω p2 As long as GBW is lower than ω p2 Then the stability of the loop is guaranteed, which can be achieved by increasing C. c To achieve this. Only g ds =g mn The smaller the value of / N, the greater the distance between the two poles, the better the pole splitting effect, and the better the loop stability. Figure 6 For circuit applications, it is recommended to set N to be greater than or equal to 1.

[0085] Figure 8 Given Figure 6 Open-loop small-signal model for PSRR analysis of the circuit. For simplicity, assume R... L R ds Much smaller, so only calculation from v is needed x to v o The feed current. v dd to v o The open-loop transfer function is shown in equation (4):

[0086]

[0087] Due to the negative feedback of the loop, its v dd to vo The closed-loop transfer function needs to be divided by the open-loop transfer function of the LDO loop using formula (4), that is, PSRR1 can be expressed as:

[0088]

[0089] Where Av(s) is the open-loop transfer function of the LDO loop.

[0090] To compare the PSRR of the voltage regulator provided in the embodiments of this application, the following is given: Figure 3 Open-loop small-signal model for PSRR analysis corresponding to the circuit structure. Figure 3 The open-loop small-signal model corresponding to the circuit structure is as follows: Figure 9 As shown. For simplicity, assume R L Compared to N×r ds Much smaller, so only calculation from v is needed x to v o The feed current. Figure 3 The corresponding v of the circuit dd to v o The open-loop transfer function is shown in the following formula (6):

[0091]

[0092] Due to the negative feedback of the loop, its v dd to v o The closed-loop transfer function needs to be divided by the open-loop transfer function of the LDO loop using formula (3), that is, PSRR0 can be expressed as shown in formula (7):

[0093]

[0094] Assumption Figure 3 and Figure 6 The device parameters of the LDO are the same, except for C. C The feedback points are different. Comparing formulas (5) and (7), it can be seen that the two PSRRs are the same at low frequencies. As the frequency increases, the PSRRs show different upward trends. The only difference between the two formulas is the component sC in the denominator of formula (7). c r op The component in the denominator of formula (5) is sC c N×r ds r op The output equivalent resistance of EA is typically greater than 1M ohms; r ds The channel resistance of an NMOS transistor in the linear region is typically small, and with proper settings, it can be reduced to below 10k ohms. Therefore, if N is not particularly large, N×r ds Far below r opConsequently, PSRR1 increases very slowly with increasing frequency, while PSRR0 increases sharply. Therefore, the voltage regulator provided in this application not only achieves a lower power supply voltage but also ensures loop stability and improves PSRR.

[0095] For example, such as Figure 10 As shown, Figure 10 A schematic diagram of the PSRR simulation effect provided for an embodiment of this application. Figure 10 The horizontal axis represents frequency, and the vertical axis represents PSRR. Figure 10 The simulation platform built in the actual simulation is given. Figure 3 and Figure 6 Simulation comparison of the circuits, Figure 3 and Figure 6 The only difference in the dimensions of the two LDO structures provided is in the error amplifier, and the equivalent width and length of the differential pair transistors in the error amplifier are the same. Therefore, it can be considered that the device dimensions of the two circuits are completely identical. Figure 10 The dashed line in the middle corresponds to Figure 3 The simulation effect of the circuit, with the solid line corresponding to... Figure 6 The simulation effect of the circuit shown is by Figure 10 It can be seen that the PSRR is the same at low frequencies, but at 100kHz, Figure 3 The PSRR of the LDO is approximately -45.6641 dB, while Figure 6 The PSRR of the LDO is approximately -64.5652 dB, meaning the PSRR is increased from -45.6641 dB to -64.5652 dB. In other words, the PSRR of the LDO provided in this embodiment is relative to... Figure 3 The PSRR of the LDO is improved by approximately 20dB. The small circle on the left of the dashed line represents the position when the PSRR is -45.6641dB and the frequency is 100kHz, while the small circle on the left of the solid line represents the position when the PSRR is -64.5652dB and the frequency is 100kHz. For example, at a frequency of 1MHz... Figure 3 The PSRR of the LDO is approximately -26.6143 dB, while Figure 6 The PSRR of the LDO is approximately -56.2215 dB, meaning the PSRR is increased from -26.6143 dB to -56.2215 dB, and from -26.5 dB to 56 dB. In other words, the PSRR of the LDO provided in this embodiment is relative to... Figure 3 The PSRR of the LDO is improved by approximately 30dB. The position of the small circle on the right side of the dashed line corresponds to a PSRR of -26.6143dB and a frequency of 1MHz, while the position of the small circle on the right side of the solid line corresponds to a PSRR of -56.2215dB and a frequency of 1MHz.

[0096] It should be noted that PSRR is represented in dB and is a negative number, corresponding to a decimal much lower than 1. This indicates that changes in the power supply voltage result in very small changes in the output voltage. The larger the absolute value of PSRR, the better; that is, the smaller the decimal, the smaller the output voltage change caused by power supply voltage fluctuations.

[0097] In one embodiment, a chip is provided, including the voltage regulator provided in the above embodiments.

[0098] In one embodiment, a device is provided that includes the chip described in the above embodiment.

[0099] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0100] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A voltage regulator, characterized in that, The voltage regulator includes an error amplifier, a voltage divider circuit, a power transistor, and a compensation circuit. The error amplifier includes a current mirror circuit and a differential pair circuit. The differential pair circuit includes multiple series-connected differential pairs. Each stage of the differential pair includes a first transistor and a second transistor. The gate of the first transistor in each stage of the differential pair is connected to the voltage divider circuit. The gate of the second transistor in each stage of the differential pair is connected to a reference voltage source. The current mirror circuit is connected to the drain of the first stage differential pair in the differential pair circuit and the gate of the power transistor. The drain of the power transistor is connected to the compensation circuit and the voltage divider circuit. The compensation circuit is connected to the source of the second transistor in the first stage differential pair and the voltage divider circuit. The error amplifier is used to control the current of the power transistor based on the reference voltage provided by the reference voltage source and the output voltage of the voltage divider circuit, so that the output voltage of the regulator is within a preset voltage range; In two adjacent first transistors, the source of the first transistor closer to the current mirror circuit is connected to the drain of the first transistor farther from the current mirror circuit. In two adjacent second transistors, the source of the second transistor closer to the current mirror circuit is connected to the drain of the second transistor farther from the current mirror circuit. In the last stage differential pair transistor, the source of the first transistor is connected to the source of the second transistor in the last stage differential pair transistor.

2. The voltage regulator according to claim 1, characterized in that, The compensation circuit is used to lower the pole of the gate of the power transistor and raise the pole of the drain of the power transistor.

3. The voltage regulator according to claim 2, characterized in that, The compensation circuit includes a compensation capacitor, the first end of which is connected to the source of the second transistor in the first stage differential pair, and the second end of which is connected to the voltage divider circuit. The compensation capacitor is used to lower the pole of the gate of the power transistor and raise the pole of the drain of the power transistor.

4. The voltage regulator according to any one of claims 1-3, characterized in that, The differential pair circuit includes a first-stage differential pair and at least one second-stage differential pair. The source of the first-stage differential pair is connected to the drain of the adjacent second-stage differential pair. The sources of the two transistors in the last second-stage differential pair are connected.

5. The voltage regulator according to claim 4, characterized in that, The number of second-stage differential pairs is multiple, including intermediate-stage differential pairs and a last second-stage differential pair; In two adjacent intermediate stage differential pairs, the source of the first intermediate stage differential pair is connected to the drain of the second intermediate stage differential pair, and the source of the last intermediate stage differential pair is connected to the drain of the last second stage differential pair.

6. The voltage regulator according to any one of claims 1-3, characterized in that, The error amplifier further includes a bias current source, wherein the source of the last stage differential pair in the differential pair circuit is connected to the first terminal of the bias current source, and the second terminal of the bias current source is grounded. The bias current source is used to provide current to the error amplifier.

7. The voltage regulator according to any one of claims 1-3, characterized in that, The voltage divider circuit includes a first resistor and a second resistor; The compensation circuit is connected to the first end of the first resistor and the power transistor. The second end of the first resistor is connected to the first end of the second resistor and the gate of each first transistor in the differential pair circuit. The second end of the second resistor is grounded.

8. The voltage regulator according to any one of claims 1-3, characterized in that, The voltage regulator also includes a power supply, and the current mirror circuit and the power transistor are connected to the power supply.

9. A chip, characterized in that, Includes the voltage regulator as described in any one of claims 1-8.

10. A device, characterized in that, Includes the chip as described in claim 9.

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