A display panel and display device

Abstract

The application discloses a display panel and a display device, wherein the display panel of one embodiment comprises: a plurality of sub-pixel units arranged in an array on a substrate, a pixel circuit for driving the plurality of sub-pixel units, a gate driving circuit, and at least two clock signal lines, the gate driving circuit outputs a gate driving signal to the pixel circuit in response to a clock signal transmitted by the at least two clock signal lines, the at least two clock signal lines are sequentially arranged and spaced apart in the same wiring direction on a first conductive layer and a second conductive layer, and the projection of the adjacent two clock signal lines on the substrate overlaps. The embodiment provided by the application effectively reduces the space occupied by the clock signal lines on the basis of overlapping and insulating the at least two input clock signal lines of the gate driving signal on different wiring layers at the frame position of the non-display area, thereby realizing the narrow-frame design of the display panel and having practical application value.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel and a display device. Background Technology

[0002] Currently, with the rapid development of display technology, users have increasingly higher demands for narrow bezels in display panels. However, because the Gate Driver on Array (GOA) circuit and multiple clock signals input to the gate driver circuit are usually located in the peripheral area of ​​the display panel, the peripheral area of ​​the display panel occupies a relatively large area.

[0003] Therefore, how to achieve a narrow bezel design for display panels has become a pressing technical problem that needs to be solved. Summary of the Invention

[0004] To solve at least one of the above problems, a first aspect of the present invention provides a display panel, including a substrate, a plurality of sub-pixel units arranged in an array on the substrate, a pixel circuit for driving the plurality of sub-pixel units, a gate driving circuit, and at least two clock signal lines, wherein the gate driving circuit outputs a gate driving signal to the pixel circuit in response to a clock signal transmitted by the at least two clock signal lines.

[0005] The at least two clock signal lines are arranged sequentially along the same wiring direction and spaced apart in the first conductive layer and the second conductive layer, with the orthogonal projection portions of two adjacent clock signal lines overlapping on the substrate.

[0006] For example, in some embodiments of the present application, the display panel also includes auxiliary signal lines that correspond one-to-one with each of the clock signal lines, for transmitting each clock signal to the gate driving circuit;

[0007] The auxiliary signal line includes at least one auxiliary sub-signal line disposed on the first conductive layer or the second conductive layer, and two adjacent auxiliary sub-signal lines belonging to the same auxiliary signal line are connected by vias.

[0008] For example, in some embodiments of the present application, a portion of the at least two clock signal lines includes an opening, and the orthographic projection of the via on the substrate falls into the orthographic projection of the opening on the substrate.

[0009] For example, in some embodiments of the present application, the opening is located on the side of the clock signal line that is closer to or farther from the gate drive circuit.

[0010] For example, in the display panel provided in some embodiments of this application, the at least two clock signal lines include m clock signal lines, and the auxiliary signal lines include the clock signal line furthest from the gate driving circuit and the first auxiliary sub-signal line connecting the gate driving circuit;

[0011] The clock signal line that is furthest from the gate drive circuit among the m clock signal lines is located in a different conductive layer or the same conductive layer as the first auxiliary sub-signal line.

[0012] For example, in the display panel provided in some embodiments of this application, when the clock signal line farthest from the gate driving circuit among the m clock signal lines is located in a different conductive layer from the first auxiliary sub-signal line, the auxiliary signal line corresponding to the nth clock signal line includes n auxiliary sub-signal lines, where m is an integer greater than or equal to 2 and n is an integer greater than or equal to 1 and less than or equal to m.

[0013] For example, in the display panel provided in some embodiments of this application, when the clock signal line farthest from the gate driving circuit among the m clock signal lines is located in the same conductive layer as the first auxiliary sub-signal line, the auxiliary signal line corresponding to the nth clock signal line includes n-1 auxiliary sub-signal lines, where m is an integer greater than or equal to 2 and n is an integer greater than or equal to 2 and less than or equal to m.

[0014] For example, in some embodiments of the display panel provided in this application, the at least two clock signal lines include a third clock signal line furthest from the gate driving circuit and a fourth clock signal line closest to the gate driving circuit. The display panel also includes a first pseudo-clock signal line disposed on the side of the third clock signal line away from the gate driving circuit and a second pseudo-clock signal line disposed on the side of the fourth clock signal line close to the gate driving circuit.

[0015] The first pseudo-clock signal line and the third clock signal line are located in different conductive layers, and the orthographic projection of the first pseudo-clock signal line on the substrate and the orthographic projection of the third clock signal line on the substrate partially overlap.

[0016] The second pseudo-clock signal line and the fourth clock signal line are located on different conductive layers, and the orthographic projection of the second pseudo-clock signal line on the substrate overlaps with the orthographic projection of the fourth clock signal line on the substrate.

[0017] For example, in some embodiments of the display panel provided in this application, the at least two clock signal lines include a fifth clock signal line furthest from the gate driving circuit and a sixth clock signal line closest to the gate driving circuit. The display panel also includes a first power signal line disposed on the side of the fifth clock signal line away from the gate driving circuit and a second power signal line disposed on the side of the sixth clock signal line close to the gate driving circuit.

[0018] The first power signal line and the fifth clock signal line are located on different conductive layers, and the orthographic projection of the first power signal line on the substrate and the orthographic projection of the fifth clock signal line on the substrate partially overlap.

[0019] The second power signal line and the sixth clock signal line are located on different conductive layers, and the orthographic projection of the second power signal line on the substrate overlaps with the orthographic projection of the sixth clock signal line on the substrate.

[0020] For example, in some embodiments of the display panel provided in this application, the at least two clock signal lines include a first startup clock signal line for starting the gate drive circuit.

[0021] When there are at least two or more clock signal lines, the first start clock signal line is located on the side of the clock signal line furthest from the gate driving circuit that is closer to the gate driving circuit, and on the side of the clock signal line closest to the gate driving circuit that is farther away from the gate driving circuit.

[0022] For example, in some embodiments of the display panel provided in this application, in a direction perpendicular to the wiring direction, the overlap width of the orthographic projection of two adjacent clock signal lines on the substrate is less than or equal to 20% of the line width of the clock signal lines.

[0023] For example, in some embodiments of the display panel provided in this application, one of the first conductive layer and the second conductive layer is disposed on the same layer as the gate of the thin film transistor of the gate driving circuit, and the other of the first conductive layer and the second conductive layer is disposed on the same layer as the source and drain of the thin film transistor of the gate driving circuit.

[0024] A second aspect of the present invention provides a display device including a display panel as described in the first aspect.

[0025] A third aspect of the present invention provides a method for manufacturing the display panel described in the first aspect, comprising:

[0026] At least two clock signal lines for transmitting clock signals to a gate drive circuit are formed on a substrate. The at least two clock signal lines are arranged sequentially along the same wiring direction and spaced apart in a first conductive layer and a second conductive layer. The orthogonal projection portions of two adjacent clock signal lines on the substrate overlap.

[0027] For example, in some embodiments of this application, the manufacturing method further includes forming auxiliary signal lines that correspond one-to-one with each clock signal line and transmit each clock signal to the gate driving circuit, including auxiliary sub-signal lines formed on the first conductive layer or the second conductive layer, and forming vias connecting two adjacent auxiliary sub-signal lines connected to the same auxiliary signal line.

[0028] The beneficial effects of this invention are as follows:

[0029] This invention addresses existing problems by providing a display panel and display device. The display panel overlaps at least two input clock signals for the gate drive signal on different trace layers at the bezel location of the non-display area. Utilizing the spatial overlap and mutual insulation characteristics, it significantly reduces the wiring space occupied by multiple clock signals. This embodiment solves the problem of large bezel space occupation in related technologies. Furthermore, the clock signals are transmitted to the gate drive circuit via auxiliary signal lines disposed on different trace layers. These auxiliary signal lines include at least one auxiliary sub-signal line disposed on the first or second conductive layer. Adjacent auxiliary sub-signal lines belonging to the same auxiliary signal line are connected through vias, thereby ensuring stable clock signal transmission from the overlapping clock signal lines. This invention has practical application value. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This diagram illustrates the structure of a display panel in the relevant art.

[0032] Figure 2 This diagram illustrates the structure of a display panel according to an embodiment of the present invention.

[0033] Figure 3 A partial cross-sectional schematic diagram of the auxiliary signal lines of the display panel according to an embodiment of the present invention is shown;

[0034] Figure 4 A schematic diagram of the structure of the display panel according to another embodiment of the present invention is shown;

[0035] Figure 5 A schematic diagram of the structure of the display panel according to another embodiment of the present invention is shown;

[0036] Figure 6 A schematic diagram of the structure of the display panel according to another embodiment of the present invention is shown;

[0037] Figure 7 A schematic diagram of the structure of the display panel according to another embodiment of the present invention is shown. Detailed Implementation

[0038] To more clearly illustrate the present invention, the following description, in conjunction with preferred embodiments and accompanying drawings, further explains the invention. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of the present invention.

[0039] It should be noted that the terms "on," "formed on," and "set on" used in this document can indicate that one layer is directly formed or set on another layer, or that one layer is indirectly formed or set on another layer, meaning that there are other layers between the two layers. In this document, unless otherwise stated, the term "located on the same layer" means that two layers, components, elements, or parts can be formed through the same patterning process, and that these two layers, components, elements, or parts are generally formed of the same material. In this document, unless otherwise stated, the description of "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, and photoresist stripping. The description of "one-time patterning process" refers to a process that uses a single photomask to form patterned layers, components, elements, etc.

[0040] In related technologies, such as Figure 1 As shown, the display panel includes multiple clock signal lines CLK1-CLK6 that transmit clock signals to the gate drive circuit GOA. These clock signal lines are sequentially laid on the same metal layer, with a 10% linewidth spacing between adjacent clock signal lines to ensure mutual insulation. The clock signals transmitted from each clock signal line are transmitted to the gate drive circuit via vias and transmission signal lines TCLK1-TCLK6 located on another metal layer. For example, if the linewidth of the clock signal lines is 100μm and the spacing is 10μm, then... Figure 1 The clock signal line shown occupies an area of ​​650 μm.

[0041] To address the issue of multiple clock signals occupying a significant amount of border space in related technologies, such as Figure 2As shown, an embodiment of the present invention provides a display panel including a substrate, a plurality of sub-pixel units 10 arranged in an array on the substrate, a pixel circuit for driving the plurality of sub-pixel units, a gate driving circuit GOA20, and at least two clock signal lines. The gate driving circuit outputs a gate driving signal to the pixel circuit in response to a clock signal transmitted by the at least two clock signal lines.

[0042] The at least two clock signal lines are arranged sequentially along the same wiring direction and spaced apart in the first conductive layer and the second conductive layer, with the orthogonal projection portions of two adjacent clock signal lines overlapping on the substrate.

[0043] In this embodiment, there are six clock signal lines, CLK1-CLK6. Clock signal lines CLK1, CLK3 and CLK5 are disposed on the first conductive layer, and clock signal lines CLK2, CLK4 and CLK6 are disposed on the second conductive layer. The clock signal lines are insulated from each other. Specifically, the orthographic projection of clock signal line CLK1 on the substrate near the gate driving circuit overlaps with the orthographic projection of clock signal line CLK2 on the substrate away from the gate driving circuit. The overlap width of the two clock signal lines in the orthographic projection is less than or equal to 20% of the line width of the clock signal lines. Similarly, the adjacent sides of clock signal lines CLK2 and CLK3 on the second conductive layer overlap, the adjacent sides of clock signal lines CLK3 and CLK4 on the first conductive layer overlap, the adjacent sides of clock signal lines CLK4 and CLK5 on the second conductive layer overlap, and the adjacent sides of clock signal lines CLK5 and CLK6 on the second conductive layer overlap.

[0044] For example, in this embodiment, the clock signal lines are respectively arranged on the same layer as the gate of the thin-film transistor in the gate driving circuit, and on the same layer as the source and drain of the thin-film transistor in the gate driving circuit. For example, clock signal lines CLK1, CLK3, and CLK5 are arranged on the same layer as the gate, and clock signal lines CLK2, CLK4, and CLK6 are arranged on the same layer as the source and drain. That is, by using existing fabrication steps to realize the routing of clock signal lines, the fabrication process can be simplified and the fabrication cost can be reduced. Specifically, the line width of the clock signal line is 100μm, then the overlap of clock signal lines CLK1 and CLK2 is less than or equal to 20μm, the overlap of clock signal lines CLK2 and CLK3 is less than or equal to 20μm, the overlap on both sides of clock signal line CLK2 is less than or equal to 40μm, and the area occupied by each clock signal line is 500μm.

[0045] Compared to Figure 1 The clock signal lines in the related technologies shown are arranged in an overlapping manner on different trace layers in the non-display area bezel position. By adopting the characteristics of spatial overlap and mutual insulation, the wiring space occupied by multiple clock signals is greatly reduced. That is, the display panel of this embodiment can solve the problem of large bezel space occupation in the related technologies and effectively reduce the bezel width.

[0046] Considering how to stably and easily transmit clock signals to the gate driving circuit when clock signal lines are overlapped, in an optional embodiment, the display panel further includes auxiliary signal lines corresponding one-to-one with each of the clock signal lines, for transmitting each clock signal to the gate driving circuit; the auxiliary signal lines include at least one auxiliary sub-signal line disposed on the first conductive layer or the second conductive layer, and two adjacent auxiliary sub-signal lines belonging to the same auxiliary signal line are connected through vias.

[0047] In this embodiment, as Figure 3 As shown, Figure 2 The schematic diagram of the cross-section A-A' shown is as follows: Figure 2 As shown, it includes three vias B, C, and D, namely the auxiliary signal line FCLK1 corresponding to the clock signal line CLK1, which transmits the clock signal to the gate drive circuit. FCLK1 includes multiple auxiliary sub-signal lines connected by vias in different layers. Specifically, as... Figure 3 As shown, the system includes a substrate 100, a gate insulating layer 110 disposed on the substrate 100, an auxiliary sub-signal line disposed on the gate insulating layer 110 and disposed on the same layer as the first conductive layer 120, an insulating layer 130 disposed on the first conductive layer 120, an auxiliary sub-signal line disposed on the insulating layer 130 and disposed on the same layer as the second conductive layer 140, and a planarization layer 150 covering the second conductive layer 140 and the exposed insulating layer 130. The auxiliary signal line includes auxiliary sub-signal lines disposed on different layers and connected by vias.

[0048] In this embodiment, as Figure 3As shown, the auxiliary signal line FCLK1 includes auxiliary sub-signal lines 1, 2, 3, and 4, CLK3 is disposed on the first conductive layer 120, and CLK4 is disposed on the second conductive layer 140. Auxiliary sub-signal line 1 is disposed on the same layer as the clock signal line CLK1 on the first conductive layer 120. At via B, through via B, auxiliary sub-signal line 1 is electrically connected to auxiliary sub-signal line 2 disposed on the second conductive layer 140. At via C, through via C, auxiliary sub-signal line 2 is electrically connected to auxiliary sub-signal line 3. At via D, through via D, auxiliary sub-signal line 3 is electrically connected to auxiliary sub-signal line 4. Auxiliary sub-signal lines 1, 2, 3, and 4 are electrically connected through vias B, C, and D to transmit the clock signal of the clock signal line CLK1. In this embodiment, the auxiliary signal lines are connected through vias by auxiliary sub-signal lines disposed on different layers, achieving electrical connection between each auxiliary signal line and the clock signal line of the transmitted clock signal, while remaining insulated from other clock signal lines, thereby stably and easily transmitting the clock signal to the gate drive circuit.

[0049] It is worth noting that, considering the insulation between the via locations and the clock signal lines, such as Figure 2 As shown, a portion of the at least two clock signal lines includes an opening 1401, and the orthogonal projection of the via on the substrate falls into the orthogonal projection of the opening 1401 on the substrate. That is, the clock signal lines have openings at the locations where vias exist in the overlapping portions, thereby ensuring that the clock signal lines are insulated from the vias, and that the clock signal lines are insulated from the auxiliary sub-signal lines.

[0050] In an alternative embodiment, the opening is located on the side of the clock signal line that is closer to or farther from the gate drive circuit.

[0051] This embodiment does not specifically limit the orientation of the opening of the clock signal line. The design principle is to allow for layer-switching connections of the auxiliary sub-signal lines via vias located at the opening positions, whether close to or far from the gate drive circuit. Furthermore, this application does not specifically limit the opening position of the clock signal line; those skilled in the art should select appropriate opening positions and orientations based on actual application requirements, which will not be elaborated further here.

[0052] In an optional embodiment, the at least two clock signal lines include m clock signal lines, and the auxiliary signal lines include the clock signal line furthest from the gate driving circuit and a first auxiliary sub-signal line connecting the gate driving circuit.

[0053] The clock signal line that is furthest from the gate drive circuit among the m clock signal lines is located in a different conductive layer or the same conductive layer as the first auxiliary sub-signal line.

[0054] In this embodiment, the wiring position of the last-stage auxiliary sub-signal line connected to the gate driving circuit in the auxiliary signal line is set to the same conductive layer and a different conductive layer as the clock signal line farthest from the gate driving circuit. Both can achieve the transmission of the clock signal transmitted by each clock signal line to the gate driving circuit through the auxiliary signal line.

[0055] In an optional embodiment, when the clock signal line furthest from the gate driving circuit among the m clock signal lines is located on a different conductive layer from the first auxiliary sub-signal line, the auxiliary signal line corresponding to the nth clock signal line includes n auxiliary sub-signal lines, where m is an integer greater than or equal to 2 and n is an integer greater than or equal to 1 and less than or equal to m.

[0056] In this embodiment, as Figure 2 As shown, there are 6 clock signal lines CLK1-CLK6. The clock signal line farthest from the gate drive circuit is the first clock signal line. The first clock signal line CLK1 is located in the first conductor layer 120 and is the 6th clock signal line from the gate drive circuit. The auxiliary sub-signal lines transmitted to the gate drive circuit are located in the second conductor layer 140. That is, the clock signal line CLK1 and the last stage auxiliary sub-signal line are located in different layers. The auxiliary signal lines electrically connected to the clock signal line CLK1 include 6 auxiliary sub-signal lines. The clock signal transmitted by the clock signal line CLK1 is transmitted to the gate drive circuit through 5 vias. Similarly, clock signal line CLK2 is located in the second conductor layer 140 and is the fifth clock signal line from the gate drive circuit. The auxiliary signal line connected to clock signal line CLK2 includes five auxiliary sub-signal lines. The clock signal transmitted by clock signal line CLK2 is transmitted to the gate drive circuit through four vias. The auxiliary signal line connected to the fourth clock signal line CLK3 from the gate drive circuit includes four auxiliary sub-signal lines. The auxiliary signal line connected to the third clock signal line CLK4 from the gate drive circuit includes three auxiliary sub-signal lines. The auxiliary signal line connected to the second clock signal line CLK5 from the gate drive circuit includes two auxiliary sub-signal lines. The auxiliary signal line connected to the first clock signal line CLK6 closest to the gate drive circuit includes one auxiliary sub-signal line.

[0057] In another optional embodiment, when the clock signal line furthest from the gate driving circuit among the m clock signal lines is located on the same conductive layer as the first auxiliary sub-signal line, the auxiliary signal line corresponding to the nth clock signal line includes n-1 auxiliary sub-signal lines, where m is an integer greater than or equal to 2, and n is an integer greater than or equal to 2 and less than or equal to m. In this embodiment, as... Figure 4As shown, the system includes six clock signal lines CLK1-CLK6. The clock signal line furthest from the gate drive circuit is the second clock signal line. The second clock signal line CLK1 is located in the first conductor layer 120 and is the sixth clock signal line from the gate drive circuit. The auxiliary sub-signal lines transmitted to the gate drive circuit are also located in the first conductor layer 120. That is, the clock signal line CLK1 and the last-stage auxiliary sub-signal line are located in the same layer. Therefore, the auxiliary signal lines electrically connected to the clock signal line CLK1 include five auxiliary sub-signal lines. The clock signal transmitted by the clock signal line CLK1 is transmitted to the gate drive circuit through four vias. By setting the last-stage auxiliary sub-signal line in the same layer as the furthest clock signal line, this embodiment can effectively reduce one cross-layer operation and one via, further simplifying the fabrication process. Similarly, clock signal line CLK2 is located in the second conductor layer 140 and is the fifth clock signal line from the gate driving circuit. The auxiliary signal lines connected to clock signal line CLK2 include four auxiliary sub-signal lines, and the clock signal transmitted by clock signal line CLK2 is transmitted to the gate driving circuit through three vias. The auxiliary signal lines connected to the fourth clock signal line CLK3 from the gate driving circuit include three auxiliary sub-signal lines; the auxiliary signal lines connected to the third clock signal line CLK4 from the gate driving circuit include two auxiliary sub-signal lines; and the auxiliary signal lines connected to the second clock signal line CLK5 from the gate driving circuit include one auxiliary sub-signal line. It is worth noting that in this embodiment, the auxiliary signal line connected to the first clock signal line CLK6, which is closest to the gate driving circuit, also includes one auxiliary sub-signal line.

[0058] Considering that the clock signal lines on both sides overlap only on one side, in an optional embodiment, such as Figure 5 As shown, the at least two clock signal lines include a third clock signal line CLK1, which is furthest from the gate driving circuit, and a fourth clock signal line CLK6, which is closest to the gate driving circuit. The display panel also includes a first pseudo-clock signal line DUM1 disposed on the side of the third clock signal line CLK1 furthest from the gate driving circuit, and a second pseudo-clock signal line DUM2 disposed on the side of the fourth clock signal line CLK6 close to the gate driving circuit.

[0059] The first pseudo clock signal line DUM1 and the third clock signal line CLK1 are located in different conductive layers, and the orthographic projection of the first pseudo clock signal line on the substrate overlaps with the orthographic projection of the third clock signal line CLK1 on the substrate.

[0060] The second pseudo clock signal line DUM2 and the fourth clock signal line CLK6 are located on different conductive layers, and the orthographic projection of the second pseudo clock signal line DUM2 on the substrate overlaps with the orthographic projection of the fourth clock signal line CLK6 on the substrate.

[0061] In this embodiment, as Figure 5 As shown, pseudo-clock signal lines DUM1 and DUM2 are respectively set on the outer side of clock signal lines CLK1 and CLK6, i.e., on the non-overlapping side. This ensures that the overlapping area of ​​each clock signal line is equal and that the signal quality of the clock signals transmitted by each clock signal line is the same, thereby further stabilizing the operation of the display panel. In this embodiment, the clock signal transmitted in the first pseudo-clock signal line DUM1 is the clock signal of clock signal line CLK6, and the clock signal transmitted in the second pseudo-clock signal line DUM2 is the clock signal of clock signal line CLK1. This minimizes the signal differences caused by different overlaps and effectively improves the uniformity of clock signal transmission.

[0062] To further reduce the space required for the border area, in one alternative embodiment, such as Figure 6 As shown, the at least two clock signal lines include a fifth clock signal line CLK1, which is furthest from the gate driving circuit, and a sixth clock signal line CLK6, which is closest to the gate driving circuit. The display panel also includes a first power signal line VDD disposed on the side of the fifth clock signal line CLK1 furthest from the gate driving circuit, and a second power signal line STU disposed on the side of the sixth clock signal line CLK6 closest to the gate driving circuit.

[0063] The first power signal line VDD and the fifth clock signal line CLK1 are located on different conductive layers, and the orthographic projection of the first power signal line VDD on the substrate overlaps with the orthographic projection of the fifth clock signal line CLK1 on the substrate.

[0064] The second power signal line STU and the sixth clock signal line CLK6 are located on different conductive layers, and the orthographic projection of the second power signal line STU on the substrate overlaps with the orthographic projection of the sixth clock signal line CLK6 on the substrate.

[0065] In this embodiment, as Figure 6As shown, to further save bezel area, this embodiment sets low-frequency power signal lines VDD and STU on the outer side of clock signal lines CLK1 and CLK6, i.e., on the non-overlapping side, to ensure that the overlapping area of ​​each clock signal line is equal and to ensure that the signal quality of the clock signal transmitted by each clock signal line is the same. On the basis of stabilizing the working condition of the display panel, by further setting low-frequency power signals VDD and STU on the outer side of the clock signal lines on both sides, the signal difference caused by different overlap is minimized, and the transmission uniformity of each clock signal is effectively improved.

[0066] It should be noted that this embodiment is only used to illustrate the specific implementation of this application, and does not specifically limit the power signal used. Those skilled in the art should select appropriate low-frequency power signal lines and clock signal lines to overlap according to actual application requirements, with the design principle of unifying the signal quality of each clock signal. This will not be elaborated here.

[0067] Considering that the gate drive circuit starts in response to the first startup clock signal, in an optional embodiment, such as Figure 7 As shown, the at least two clock signal lines include a first startup clock signal line for starting the gate drive circuit.

[0068] When there are at least two or more clock signal lines, the first start clock signal line is located on the side of the clock signal line furthest from the gate driving circuit that is closer to the gate driving circuit, and on the side of the clock signal line closest to the gate driving circuit that is farther away from the gate driving circuit.

[0069] In this embodiment, as Figure 7 As shown, placing the first startup clock signal line CLK1, which transmits the first startup clock signal, at the center of multiple clock signal lines can improve the operational stability of the gate drive circuit. It is worth noting that this embodiment is only used to illustrate a specific implementation of this application. This application is not limited to placing the first startup clock signal at the center; it can also be placed on the side of the clock signal line furthest from the gate drive circuit, closer to the gate drive circuit, and on the side of the clock signal line closest to the gate drive circuit, farther from the gate drive circuit. In other words, it avoids placing it at the position furthest from the gate drive circuit or the position closest to the gate drive circuit; thereby further improving the stable operation of the gate drive circuit and effectively improving the working stability of the display panel.

[0070] It is worth noting that the first start clock signal line CLK1 is placed inside multiple clock signal lines in this embodiment, which can be applied to the above embodiments. Those skilled in the art should select the appropriate application method according to actual application needs, and will not be elaborated here.

[0071] Corresponding to the display panel provided in the above embodiments, one embodiment of this application also provides a method for manufacturing the above display panel, comprising:

[0072] At least two clock signal lines for transmitting clock signals to a gate drive circuit are formed on a substrate. The at least two clock signal lines are arranged sequentially along the same wiring direction and spaced apart in a first conductive layer and a second conductive layer. The orthogonal projection portions of two adjacent clock signal lines on the substrate overlap.

[0073] This embodiment overlaps at least two input clock signals of the gate drive signal on different trace layers at the bezel location of the non-display area. Utilizing the spatial overlap and mutual insulation characteristics, the wiring space occupied by multiple clock signals is significantly reduced. The display panel of this embodiment solves the problem of large bezel space occupation in related technologies. Since the manufacturing method provided in this application corresponds to the display panels provided in the above embodiments, the preceding embodiments are also applicable to the manufacturing method provided in this embodiment, and will not be described in detail here.

[0074] In an optional embodiment, the fabrication method further includes forming auxiliary signal lines that correspond one-to-one with each clock signal line and transmit each clock signal to the gate drive circuit, including auxiliary sub-signal lines formed on the first conductive layer or the second conductive layer, and forming vias connecting two adjacent auxiliary sub-signal lines connected to the same auxiliary signal line.

[0075] In this embodiment, the clock signal is transmitted to the gate drive circuit through auxiliary signal lines disposed on different trace layers. The auxiliary signal lines include at least one auxiliary sub-signal line disposed on the first conductive layer or the second conductive layer. Two adjacent auxiliary sub-signal lines belonging to the same auxiliary signal line are connected through vias, thereby ensuring that the overlapping clock signal lines transmit the clock signal stably.

[0076] Based on the display panel of the foregoing embodiments, another embodiment of the present invention provides a display device including the aforementioned display panel, wherein the display device is a liquid crystal display device or an electroluminescent diode display device. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0077] This invention addresses existing problems by providing a display panel and display device. The display panel overlaps at least two input clock signals for the gate drive signal on different trace layers at the bezel location of the non-display area. Utilizing the spatial overlap and mutual insulation characteristics, it significantly reduces the wiring space occupied by multiple clock signals. This embodiment solves the problem of large bezel space occupation in related technologies. Furthermore, the clock signals are transmitted to the gate drive circuit via auxiliary signal lines disposed on different trace layers. These auxiliary signal lines include at least one auxiliary sub-signal line disposed on the first or second conductive layer. Adjacent auxiliary sub-signal lines belonging to the same auxiliary signal line are connected through vias, thereby ensuring stable clock signal transmission from the overlapping clock signal lines. This invention has practical application value.

[0078] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.

Claims

1. A display panel, characterized in that, The device includes a substrate, a plurality of sub-pixel units arranged in an array on the substrate, a pixel circuit for driving the plurality of sub-pixel units, a gate driving circuit, and at least two clock signal lines. The gate driving circuit outputs a gate driving signal to the pixel circuit in response to a clock signal transmitted by the at least two clock signal lines. The at least two clock signal lines are arranged sequentially along the same wiring direction and are spaced apart in the first conductive layer and the second conductive layer, and the orthogonal projection portions of two adjacent clock signal lines on the substrate overlap. The display panel also includes auxiliary signal lines that correspond one-to-one with each of the clock signal lines, for transmitting each clock signal to the gate drive circuit; The auxiliary signal line includes at least one auxiliary sub-signal line disposed on the first conductive layer or the second conductive layer. One of two adjacent auxiliary sub-signal lines belonging to the same auxiliary signal line is disposed on the first conductive layer and the other is disposed on the second conductive layer. The two adjacent auxiliary sub-signal lines are connected by vias. The at least two clock signal lines include a third clock signal line furthest from the gate driving circuit and a fourth clock signal line closest to the gate driving circuit. The display panel further includes a first pseudo-clock signal line disposed on the side of the third clock signal line away from the gate driving circuit and a second pseudo-clock signal line disposed on the side of the fourth clock signal line close to the gate driving circuit. The first pseudo-clock signal line and the third clock signal line are located in different conductive layers, and the orthographic projection of the first pseudo-clock signal line on the substrate overlaps with the orthographic projection of the third clock signal line on the substrate. The second pseudo-clock signal line and the fourth clock signal line are located in different conductive layers, and the orthographic projection of the second pseudo-clock signal line on the substrate overlaps with the orthographic projection of the fourth clock signal line on the substrate. or The at least two clock signal lines include a fifth clock signal line furthest from the gate driving circuit and a sixth clock signal line closest to the gate driving circuit. The display panel also includes a first power signal line disposed on the side of the fifth clock signal line away from the gate driving circuit and a second power signal line disposed on the side of the sixth clock signal line close to the gate driving circuit. The first power signal line and the fifth clock signal line are located in different conductive layers, and the orthographic projection of the first power signal line on the substrate overlaps with the orthographic projection of the fifth clock signal line on the substrate. The second power signal line and the sixth clock signal line are located in different conductive layers, and the orthographic projection of the second power signal line on the substrate overlaps with the orthographic projection of the sixth clock signal line on the substrate.

2. The display panel according to claim 1, characterized in that, A portion of the at least two clock signal lines includes an opening, and the orthogonal projection of the via on the substrate falls into the orthogonal projection of the opening on the substrate.

3. The display panel according to claim 2, characterized in that, The opening is located on the side of the clock signal line that is closer to or farther from the gate drive circuit.

4. The display panel according to claim 1, characterized in that, The at least two clock signal lines include m clock signal lines, and the auxiliary signal lines include the clock signal line furthest from the gate driving circuit and the first auxiliary sub-signal line connecting the gate driving circuit; The clock signal line that is furthest from the gate drive circuit among the m clock signal lines is located in a different conductive layer or the same conductive layer as the first auxiliary sub-signal line.

5. The display panel according to claim 4, characterized in that, When the clock signal line furthest from the gate drive circuit among the m clock signal lines is located in a different conductive layer from the first auxiliary sub-signal line, the auxiliary signal line corresponding to the nth clock signal line includes n auxiliary sub-signal lines, where m is an integer greater than or equal to 2 and n is an integer greater than or equal to 1 and less than or equal to m.

6. The display panel according to claim 4, characterized in that, When the clock signal line furthest from the gate driving circuit among the m clock signal lines is located in the same conductive layer as the first auxiliary sub-signal line, the auxiliary signal line corresponding to the nth clock signal line includes n-1 auxiliary sub-signal lines, where m is an integer greater than or equal to 2 and n is an integer greater than or equal to 2 and less than or equal to m.

7. The display panel according to any one of claims 1-6, characterized in that, The at least two clock signal lines include a first startup clock signal line for starting the gate drive circuit. When there are at least two or more clock signal lines, the first start clock signal line is located on the side of the clock signal line furthest from the gate driving circuit that is closer to the gate driving circuit, and on the side of the clock signal line closest to the gate driving circuit that is farther away from the gate driving circuit.

8. The display panel according to claim 1, characterized in that, In a direction perpendicular to the wiring direction, the overlap width of the orthographic projection of two adjacent clock signal lines onto the substrate is less than or equal to 20% of the line width of the clock signal line; and / or One of the first conductive layer and the second conductive layer is disposed on the same layer as the gate of the thin-film transistor of the gate driving circuit, and the other of the first conductive layer and the second conductive layer is disposed on the same layer as the source and drain of the thin-film transistor of the gate driving circuit.

9. A display device, characterized in that, Includes the display panel as described in any one of claims 1-8.

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