A Method for Encoder Frequency Multiplication with Arbitrary Number of Lines Output through Two-way PWM

Abstract

The present invention discloses a method for frequency doubling an encoder with any number of lines through two-way PWM output, which relates to the technical field of frequency doubling the number of encoder lines of a spindle servo controller. The method includes the following steps: S1: Collect the number of pulse difference quantities Pluse0 of the encoder within a unit time, including the direction, where a positive number indicates up counting and a negative number indicates down counting. Calculate the number of pulse difference quantities Pluse1 after frequency doubling through the original number of encoder lines Number0 and the number of encoder lines Number1 after frequency doubling; S2: Calculate the pulse period time T after frequency doubling through the number of pulses Pluse1 calculated in step 1 and the unit time T pluse and the remainder T of the pulse period time rem . The difference between the present invention and the prior art is that by recording the number of pulses Pluse0 of the encoder captured by the chip within a unit time (T), through the frequency doubling factor (M), and then outputting the number of pulses Pluse1 after frequency doubling in the next unit time, frequency doubling is achieved. While achieving frequency doubling adjustment for any number of lines, the hardware cost and software management cost of the product are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of spindle servo controller frequency multiplication encoder line numbers, and specifically provides an encoder frequency multiplication method with arbitrary line numbers through two-way PWM output. Background Art

[0002] In the field of encoder frequency multiplication output, most numerical control systems used in the machine tool industry receive the ABZ signals fed back by the servo or the PLC receives the encoder position fed back by the servo. Traditional encoder frequency multiplication methods are as follows: 1. Achieving frequency multiplication output by building a hardware circuit; 2. Achieving encoder frequency multiplication output through an FPGA.

[0003] For the first method, the multiple of the frequency multiplication output is fixed, and the lead of the AB phase cannot be changed either. It is difficult to achieve frequency multiplication with arbitrary line numbers on-site. For the second method, it can achieve frequency multiplication with arbitrary line numbers and the phase between AB can also be adjusted by the FPGA, but an additional FPGA chip needs to be added to the original circuit, which leads to a significant increase in both the hardware cost and software management cost of the product. Summary of the Invention

[0004] The purpose of the present invention is to provide an encoder frequency multiplication method with arbitrary line numbers through two-way PWM output to solve the problems raised in the above background art.

[0005] To achieve the above purpose, the present invention provides the following technical solution: An encoder frequency multiplication method with arbitrary line numbers through two-way PWM output, including the following steps:

[0006] S1: Collect the number of pulse differences Pluse0 of the encoder within a unit time, including the direction, where a positive number indicates up counting and a negative number indicates down counting. Calculate the number of pulse differences Pluse1 after frequency multiplication through the original encoder line number Number0 and the encoder line number Number1 after frequency multiplication.

[0007] S2: Calculate the pulse period time T after frequency multiplication through the number of pulses Pluse1 calculated in step 1 and the unit time T pluse and the remainder T of the pulse period time rem ;

[0008] S3: Obtain the comparison value Cmp of the PWM comparison register through the pulse period time T pluse and the clock signal T of the PWM clk ;

[0009] S4: Determine which of the AB levels will jump first at the next moment based on the direction of Pluse1, the high and low levels of the previous AB signal, and whether there is an AB direction inversion flag in the software.

[0010] S5: During the cycle time remainder T rem time, the comparison value Cmp of the PWM comparison register is incremented by one, and the comparison value Cmp remains the same at other times within the unit time;

[0011] S6: Refresh the values of the two-channel PWM comparison registers CmpA and CmpB according to step S5, where CmpA = CmpB = Cmp;

[0012] S7: Refresh the clock calculation values of the two-channel PWM according to the result of step S4. If the A level jumps first, update the PWM clock count value of the first channel to update the PWM clock count value of the second channel to 0. If the B level jumps first, update the PWM clock count value of the first channel to 0 and update the PWM clock count value of the second channel to

[0013] Furthermore, in step S1, the calculation formula of Pluse1 is as follows:

[0014] Furthermore, in step S2, T rem The calculation formula is as follows:

[0015] Furthermore, in step S3, the calculation formula of Cmp is as follows:

[0016] Compared with the prior art, the beneficial effects of the present invention are:

[0017] The method for encoder frequency multiplication with arbitrary number of lines output by two-channel PWM is different from the prior art in that by recording the number of encoder pulses Pluse0 captured by the chip within a unit time (T), through the multiplication factor (M), and then outputting the multiplied number of pulses Pluse1 in the next unit time, so as to achieve frequency multiplication, and then calculate the multiplied pulse cycle time T through the following formula pluse : Pluse1 = Pluse0 * M, While achieving frequency multiplication adjustment for any number of lines, the hardware cost and software management cost of the product are reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is the schematic diagram of the AB level jump logic of the present invention;

[0019] Figure 2 is the schematic diagram of the value of Cmp of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0020] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0021] As Figure 1 - Figure 2 shown, the present invention provides a technical solution: a method for doubling the frequency of an encoder with any number of lines through two-way PWM output. This method can achieve frequency doubling of any number of lines, and the direction of the output AB quadrature square wave can be adjusted. Thus, it can meet the requirements of the numerical control system or PLC to receive the pulses fed back by the servo driver.

[0022] The specific implementation steps are as follows:

[0023] (1) Collect the number of pulse difference counts Pluse0 of the encoder within a unit time, including the direction. A positive number indicates increasing count, and a negative number indicates decreasing count. Calculate the number of pulse difference counts Pluse1 after frequency doubling through the original encoder line number Number0 and the encoder line number Number1 after frequency doubling. The calculation formula is as follows:

[0024]

[0025] (2) Calculate the pulse period time T after frequency doubling and the remainder T of the pulse period time through the number of pulses Pluse1 calculated in step 1 and the unit time T. The calculation formula is as follows: pluse and the remainder T of the pulse period time rem . The calculation formula is as follows:

[0026]

[0027] (3) Obtain the comparison value Cmp of the PWM comparison register through the pulse period time T pluse and the clock signal T of the PWM clk . The calculation formula is as follows

[0028]

[0029] (4) Determine which of the AB levels will jump first at the next moment based on the direction of Pluse1, the high and low levels of the previous AB signal, and whether there is an AB direction inversion flag in the software. The specific AB level jump logic is as Figure 1 shown;

[0030] (5) Within the period time remainder T rem time, increment the comparison value Cmp of the PWM comparison register by one, and the comparison value Cmp remains the same at other times within the unit time. The value of Cmp is as Figure 2 shown;

[0031] (6) Refresh the values of the two PWM comparison registers CmpA and CmpB according to Step 5: CmpA = CmpB = Cmp;

[0032] (7) Refresh the clock calculation values of the two PWMs according to the result of Step 4. If the A level jumps first, update the PWM clock count value of the first path to Update the PWM clock count value of the second path to 0; if the B level jumps first, update the PWM clock count value of the first path to 0 and update the PWM clock count value of the second path to

[0033] Although the embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended embodiments and their equivalents.

Claims

1. A method for encoder frequency multiplication with arbitrary number of lines through two-way PWM output, characterized in that, Including the following steps: S1: Collect the number of pulse difference counts Pluse0 of the encoder within a unit time, including the direction. A positive number indicates an increasing count, and a negative number indicates a decreasing count. Calculate the number of pulse difference counts Pluse1 after frequency doubling through the original encoder line number Number0 and the encoder line number Number1 after frequency doubling; S2: Calculate the pulse cycle time T after frequency multiplication based on the number of pulse difference quantities Pluse1 calculated in step 1 and the unit time T pluse and the remainder T of the pulse cycle time rem ; S3: Through the pulse period time T pluse and the clock signal T of PWM clk , obtain the comparison value Cmp of the comparison register of PWM; S4: Determine which of the AB levels will change first at the next moment based on the direction of Pluse1, the high and low levels of the AB signal at the previous moment, and whether there is an AB direction inversion flag in the software; S5: During the pulse cycle time remainder T rem time, the comparison value Cmp of the PWM comparison register is incremented by one, and the comparison value Cmp remains the same at other times within the unit time; S6: Refresh the values of the two PWM comparison registers CmpA and CmpB according to step S5, CmpA = CmpB = Cmp; S7: Refresh the clock calculation values of the two PWM signals according to the result of step S4. If the A level jumps first, update the PWM clock count value of the first path to update the PWM clock count value of the second path to 0. If the B level jumps first, update the PWM clock count value of the first path to 0 and update the PWM clock count value of the second path to 2. A method for encoder frequency multiplication with arbitrary number of lines through two-way PWM output according to claim 1, characterized in that: In step S1, the calculation formula for Pluse1 is as follows:

3. A method for encoder frequency multiplication with arbitrary number of lines through two-way PWM output according to claim 1, characterized in that: In step S2, T rem The calculation formula is as follows: T rem = T% Pluse1.

4. A method for encoder frequency multiplication with arbitrary number of lines through two-way PWM output according to claim 1, characterized in that: In step S3, the calculation formula of Cmp is as follows:

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