Multi-phase serial data sampling clock signal generation circuit

Abstract

The present invention discloses a circuit for generating a multi-phase serial data sampling clock signal, which belongs to the technical field of frequency division circuits, and includes a four-phase clock signal generating circuit for generating a first-phase clock signal, a second-phase clock signal, a third-phase clock signal and a fourth-phase clock signal; a first four-to-one selector, the input end of which respectively inputs the first-phase clock signal, the second-phase clock signal, the third-phase clock signal and the fourth-phase clock signal, the control end respectively inputs the first control signal and the second control signal, and the output end outputs the first clock signal; a two-to-one selector; a first sampling circuit; a second sampling circuit; a third sampling circuit; a fourth sampling circuit; a fifth sampling circuit; a sixth sampling circuit; a second four-to-one selector; a first four-frequency division circuit; and a second four-frequency division circuit. The present invention has a simple structure, uses fewer signals, is more convenient to implement logic circuits, has lower power consumption, and requires a smaller layout area, which can reduce costs.

Description

Technical Field

[0001] The invention relates to a frequency division circuit, in particular to a circuit for generating a multi-phase serial data sampling clock signal. Background Art

[0002] In the applications of low voltage differential signal mobile industry processor interface (mipi-LVDS) and low voltage differential signal camera / display interface (LVDS Camera / Display), it is necessary to output a clock with 16 optional phases within a 1-bit data cycle. For example, if the serial data rate reaches 1Gbps, then 1ns / 16=62.5ps step adjustment is required.

[0003] Usually, when the serial data rate is 1Gbps, the existing technology generates a 4GHz 4-phase clock through a phase-locked loop (PLL), and then generates a 4GHz multi-phase clock through a corresponding logic circuit, uses the 4GHz multi-phase clock to sample the double data rate clock, and selects the required phase clock. However, the circuit structure of this method in the existing technology is relatively complex, the power consumption is large, the layout area is large, and the cost is high. Summary of the invention

[0004] The purpose of the present invention is to provide a circuit for generating a multi-phase serial data sampling clock signal, which can output a sampling clock with 16 selectable gears, thereby realizing the function of having 16 selectable gears in the phase within a 1-bit data period.

[0005] The present invention is achieved through the following technical solutions:

[0006] A circuit for generating a multi-phase serial data sampling clock signal, comprising:

[0007] A four-phase clock signal generating circuit, which is used to generate a first-phase clock signal, a second-phase clock signal, a third-phase clock signal and a fourth-phase clock signal; wherein the first-phase clock signal and the third-phase clock signal are a pair of differential clock signals, and the second-phase clock signal and the fourth-phase clock signal are another pair of differential clock signals;

[0008] A first four-to-one selector, whose input terminals are respectively input with a first phase clock signal, a second phase clock signal, a third phase clock signal and a fourth phase clock signal, whose control terminals are respectively input with a first control signal and a second control signal, and whose output terminal outputs the first clock signal;

[0009] A two-to-one selector, wherein the second phase clock signal and the fourth phase clock signal are input to its input terminal respectively, the second bit control signal is input to its control terminal, and the second clock signal is output to its output terminal;

[0010] A first sampling circuit, which is used for sampling the third clock signal with a fourth phase clock signal to obtain a fourth clock signal;

[0011] A second sampling circuit, which is used for sampling the fourth clock signal with the second clock signal to obtain a fifth clock signal;

[0012] A third sampling circuit, which is used for sampling the fifth clock signal with the first clock signal to obtain a sixth clock signal;

[0013] A fourth sampling circuit, configured to sample the sixth clock signal using the first clock signal to obtain a seventh clock signal;

[0014] A fifth sampling circuit, configured to use the first clock signal to sample the seventh clock signal to obtain an eighth clock signal;

[0015] A sixth sampling circuit, configured to sample the eighth clock signal using the first clock signal to obtain a ninth clock signal;

[0016] A second four-to-one selector, whose input terminals are respectively input with the sixth clock signal, the seventh clock signal, the eighth clock signal and the ninth clock signal, whose control terminals are respectively input with the third control signal and the fourth control signal, and whose output terminal outputs the switch control signal;

[0017] A first frequency-dividing circuit, which divides the first clock signal by four under the control of the switch control signal to obtain a first frequency-dividing signal;

[0018] A second frequency-dividing circuit divides the first frequency-dividing signal by four under the control of the switch control signal to obtain a second frequency-dividing signal;

[0019] The circuit control signal includes four control signals, which are the first control signal, the second control signal, the third control signal and the fourth control signal.

[0020] The four-phase clock signal generating circuit is a voltage-controlled oscillator.

[0021] The first sampling circuit, the second sampling circuit, the third sampling circuit, the fourth sampling circuit, the fifth sampling circuit, and the sixth sampling circuit are all D flip-flops.

[0022] The third clock signal is generated by a lock detection circuit.

[0023] Compared with the prior art, the present invention has the following beneficial technical effects:

[0024] The present invention has a simple structure, uses fewer signals, is more convenient to implement the logic circuit, has lower power consumption, requires a smaller layout area, and can reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is the circuit principle diagram of the present invention;

[0026] Figure 2 This is the signal timing diagram when PHASE_SEL〈3:0〉=0000. DETAILED DESCRIPTION

[0027] All features disclosed in this specification, or all steps in the disclosed methods or processes, except mutually exclusive features and / or steps, may be combined in any manner and, unless otherwise stated, may be replaced by other equivalent or alternative features having similar purposes, that is, unless otherwise stated, each feature is merely an embodiment of a series of equivalent or similar features.

[0028] See also Figure 1 A multi-phase serial data sampling clock signal generating circuit of the present invention includes a four-phase clock signal generating circuit, a first four-to-one selector mux1, a two-to-one selector mux3, a first sampling circuit D1, a second sampling circuit D2, a third sampling circuit D3, a fourth sampling circuit D4, a fifth sampling circuit D5, a sixth sampling circuit D6, a second four-to-one selector mux2, a first four-dividing frequency circuit and a second four-dividing frequency circuit.

[0029] The four-phase clock signal generating circuit is used to generate a first phase clock signal ck1, a second phase clock signal ck2, a third phase clock signal ck3 and a fourth phase clock signal ck4. The first phase clock signal ck1 and the third phase clock signal ck3 are a pair of differential clock signals, and the second phase clock signal ck2 and the fourth phase clock signal ck4 are another pair of differential clock signals. Figure 1 In the presented embodiment, the four-phase clock signal generating circuit is a voltage-controlled oscillator. The frequencies of the first-phase clock signal ck1, the second-phase clock signal ck2, the third-phase clock signal ck3 and the fourth-phase clock signal ck4 are determined according to the serial data rate, and have a specific multiple relationship. For example, the frequencies of the first-phase clock signal ck1, the second-phase clock signal ck2, the third-phase clock signal ck3 and the fourth-phase clock signal ck4 can be four times the serial data rate. For example, in this embodiment, the serial data rate is less than or equal to 1Gbps, then the frequencies of the first-phase clock signal ck1, the second-phase clock signal ck2, the third-phase clock signal ck3 and the fourth-phase clock signal ck4 are determined based on the highest serial data rate of 1Gbps, that is, the frequencies of the first-phase clock signal ck1, the second-phase clock signal ck2, the third-phase clock signal ck3 and the fourth-phase clock signal ck4 are 4GHz.

[0030] The input ends of the first four-to-one selector mux1 are respectively input with the first phase clock signal ck1, the second phase clock signal ck2, the third phase clock signal ck3 and the fourth phase clock signal ck4, the control ends of the first four-to-one selector mux1 are respectively input with the first control signal PHASE_SEL〈0〉 and the second control signal PHASE_SEL〈1〉, and the output end of the first four-to-one selector mux1 outputs the first clock signal ckn. Figure 1 In the embodiment, PHASE_SEL<1:0> refers to the first control signal PHASE_SEL<0> and the second control signal PHASE_SEL<1>.

[0031] The input terminals of the two-to-one selector mux3 are respectively input with the second phase clock signal ck2 and the fourth phase clock signal ck4, the control terminal of the two-to-one selector mux3 is input with the second bit control signal PHASE_SEL〈1〉, and the output terminal of the two-to-one selector mux3 outputs the second clock signal ckm.

[0032] The first sampling circuit D1 is used for sampling the third clock signal LCK with the fourth phase clock signal ck4 to obtain the fourth clock signal LOCK.

[0033] The second sampling circuit D2 is used for sampling the fourth clock signal LOCK with the second clock signal ckm to obtain the fifth clock signal rstn_pre.

[0034] The third sampling circuit D3 is used for sampling the fifth clock signal rstn_pre with the first clock signal ckn to obtain the sixth clock signal q0.

[0035] The fourth sampling circuit D4 is used for sampling the sixth clock signal q0 with the first clock signal ckn to obtain the seventh clock signal q1.

[0036] The fifth sampling circuit D5 is used for sampling the seventh clock signal q1 with the first clock signal ckn to obtain the eighth clock signal q2.

[0037] The sixth sampling circuit D6 is used for sampling the eighth clock signal q2 with the first clock signal ckn to obtain a ninth clock signal q3.

[0038] The input ends of the second four-to-one selector mux2 are respectively input with the sixth clock signal q0, the seventh clock signal q1, the eighth clock signal q2 and the ninth clock signal q3, the control ends of the second four-to-one selector mux2 are respectively input with the third control signal PHASE_SEL〈2〉 and the fourth control signal PHASE_SEL〈3〉, and the output end of the second four-to-one selector mux2 outputs the switch control signal rstn. Figure 1In the embodiment, PHASE_SEL<3:2> refers to the third control signal PHASE_SEL<2> and the fourth control signal PHASE_SEL<3>.

[0039] The first frequency-dividing circuit divides the first clock signal ckn by four under the control of the switch control signal rstn to obtain a first frequency-dividing signal CKSEL.

[0040] The second frequency-dividing circuit divides the first frequency-dividing signal CKSEL by four under the control of the switch control signal rstn to obtain the second frequency-dividing signal PCK.

[0041] Figure 1 In the embodiment, the circuit control signal PHASE_SEL〈3:0〉 includes four control signals, and the four control signals are respectively a first control signal PHASE_SEL〈0〉, a second control signal PHASE_SEL〈1〉, a third control signal PHASE_SEL〈2〉, and a fourth control signal PHASE_SEL〈3〉. For example, when PHASE_SEL〈0〉=0, PHASE_SEL〈1〉=1, PHASE_SEL〈2〉=0, and PHASE_SEL〈3〉=1, PHASE_SEL〈3:0〉=1010; when PHASE_SEL〈0〉=1, PHASE_SEL〈1〉=1, PHASE_SEL〈2〉=0, and PHASE_SEL〈3〉=1, PHASE_SEL〈3:0〉=1011; and the same applies to the others.

[0042] In the above embodiments, the first sampling circuit D1 , the second sampling circuit D2 , the third sampling circuit D3 , the fourth sampling circuit D4 , the fifth sampling circuit D5 , and the sixth sampling circuit D6 are all D flip-flops.

[0043] In the aforementioned embodiment, the third clock signal LCK is generated by the lock detection circuit.

[0044] The working principle of the present invention is as follows:

[0045] See also Figure 1 , a four-phase clock with a frequency of 4 GHz is generated from a voltage-controlled oscillator, which are a first-phase clock signal ck1, a second-phase clock signal ck2, a third-phase clock signal ck3 and a fourth-phase clock signal ck4, wherein the first-phase clock signal ck1 and the third-phase clock signal ck3 are a pair of differential clock signals, and the second-phase clock signal ck2 and the second-phase clock signal ck4 are another pair of differential clock signals.

[0046] See also Figure 1 , Figure 2The first phase clock signal ck1, the second phase clock signal ck2, the third phase clock signal ck3 and the fourth phase clock signal ck4 are respectively input into the first four-to-one selector mux1, and the output of the first four-to-one selector mux1 is controlled by the second control signal PHASE_SEL〈1〉 and the first control signal PHASE_SEL〈0〉, i.e. PHASE_SEL〈1:0〉, and the output end of the first four-to-one selector mux1 outputs the first clock signal ckn. For example, when PHASE_SEL〈1〉=1, PHASE_SEL〈0〉=1, that is, PHASE_SEL〈1:0〉=11, the first phase clock signal ck1 outputted from the output end of the first four-to-one selector mux1 is used as the first clock signal ckn; when PHASE_SEL〈1:0〉=10, the second phase clock signal ck2 outputted from the output end of the first four-to-one selector mux1 is used as the first clock signal ckn; when PHASE_SEL〈1:0〉=01, the third phase clock signal ck3 outputted from the output end of the first four-to-one selector mux1 is used as the first clock signal ckn; when PHASE_SEL〈1:0〉=00, the fourth phase clock signal ck4 outputted from the output end of the first four-to-one selector mux1 is used as the first clock signal ckn.

[0047] The second phase clock signal ck2 and the fourth phase clock signal ck4 are input into the two-to-one selector mux3, and the output of the two-to-one selector mux3 is controlled by the second control signal PHASE_SEL〈1〉, and the output end of the two-to-one selector mux3 outputs the second clock signal ckm. For example, when PHASE_SEL〈1〉=1, the second phase clock signal ck2 output from the output end of the two-to-one selector mux3 is used as the second clock signal ckm; when PHASE_SEL〈1〉=0, the output end of the two-to-one selector mux3 outputs the fourth phase clock signal ck4 as the second clock signal ckm. The fourth phase clock signal ck4 is input into the first sampling circuit D1, and the third clock signal LCK is sampled to obtain the fourth clock signal LOCK. The second clock signal ckm is input into the second sampling circuit D2, and the fourth clock signal LOCK is sampled to obtain the fourth and fifth clock signals rstn_pre. In this way, the second clock signal ckm and the fifth clock signal rstn_pre have a certain timing relationship.

[0048] Then, the first clock signal ckn is input into the third sampling circuit D3, and the fifth clock signal rstn_pre is sampled to obtain the sixth clock signal q0; the first clock signal ckn is input into the fourth sampling circuit D4, and the sixth clock signal q0 is sampled by the first clock signal ckn to obtain the seventh clock signal q1; the first clock signal ckn is input into the fifth sampling circuit D5, and the seventh clock signal q1 is sampled by the first clock signal ckn to obtain the eighth clock signal q2; the first clock signal ckn is input into the sixth sampling circuit D6, and the eighth clock signal q2 is sampled by the first clock signal ckn to obtain the ninth clock signal q3. The sixth clock signal q0, the seventh clock signal q1, the eighth clock signal q2 and the ninth clock signal q3 generated in this way have a phase difference of Tckn between two adjacent clock signals, where Tckn represents the period of the first clock signal ckn. The sixth clock signal q0, the seventh clock signal q1, the eighth clock signal q2 and the ninth clock signal q3 are input to the second four-to-one selector mux2, and the output of the second four-to-one selector mux2 is controlled by the fourth bit PHASE_SEL〈3〉 and the third bit control signal PHASE_SEL〈2〉, i.e., PHASE_SEL〈3:2〉, and the output end of the second four-to-one selector mux2 outputs the switch control signal rstn. For example, when PHASE_SEL〈3:2〉=11, the output end of the second four-to-one selector mux2 outputs the ninth clock signal q3; when PHASE_SEL〈3:2〉=10, the output end of the second four-to-one selector mux2 outputs the eighth clock signal q2; when PHASE_SEL〈3:2〉=01, the output end of the second four-to-one selector mux2 outputs the seventh clock signal q1; when PHASE_SEL〈3:2〉=00, the output end of the second four-to-one selector mux2 outputs the sixth clock signal q0.

[0049] The first clock signal ckn is input into the first four-division circuit, and the first four-division circuit divides the first clock signal ckn by four under the control of the switch control signal rstn to obtain the first frequency-division signal CKSEL; the first frequency-division signal CKSEL is input into the second four-division circuit, and the second four-division circuit divides the first frequency-division signal CKSEL by four under the control of the switch control signal rstn to obtain the second frequency-division signal PCK. The second frequency-division signal PCK is the clock signal finally output by the present invention. In this way, by selecting the circuit control signal PHASE_SEL〈3:0〉, the second frequency-division signal PCK with 16 optional gears in the phase within a 1-bit data cycle can be obtained, and the second frequency-division signal PCK is the required double data rate clock (DDR Clock). Figure 2In the figure, data refers to serial data, and the portion indicated by the dotted arrow is a data cycle. The dotted arrows represent the 16 phases of the second frequency-divided signal PCK with dotted lines, and the circuit control signal PHASE_SEL〈3:0〉 is used to select the second frequency-divided signal PCK with different phases for output.

[0050] It can be seen that the present invention only uses 6 D flip-flops, 2 4-to-1 selectors, 1 2-to-1 selector and 2 4-divider circuits, the structure is concise and clear, no complex logic transformation is involved, and the signal path is clear and easy to understand. Fewer logic devices are used, and the clock frequency is not high, so the power consumption is also small, and the area occupied by the layout corresponding to the entire invention is also small, which can reduce costs.

[0051] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A circuit for generating a multi-phase serial data sampling clock signal, characterized in that: include: A four-phase clock signal generating circuit, which is used to generate a first-phase clock signal, a second-phase clock signal, a third-phase clock signal and a fourth-phase clock signal; wherein the first-phase clock signal and the third-phase clock signal are a pair of differential clock signals, and the second-phase clock signal and the fourth-phase clock signal are another pair of differential clock signals; A first four-to-one selector, whose input terminals are respectively input with a first phase clock signal, a second phase clock signal, a third phase clock signal and a fourth phase clock signal, whose control terminals are respectively input with a first control signal and a second control signal, and whose output terminal outputs the first clock signal; A two-to-one selector, wherein the second phase clock signal and the fourth phase clock signal are input to its input terminal respectively, the second bit control signal is input to its control terminal, and the second clock signal is output to its output terminal; A first sampling circuit, which is used for sampling the third clock signal with a fourth phase clock signal to obtain a fourth clock signal; the third clock signal is generated by a lock detection circuit; A second sampling circuit, which is used for sampling the fourth clock signal with the second clock signal to obtain a fifth clock signal; A third sampling circuit, which is used for sampling the fifth clock signal with the first clock signal to obtain a sixth clock signal; A fourth sampling circuit, configured to sample the sixth clock signal using the first clock signal to obtain a seventh clock signal; A fifth sampling circuit, configured to use the first clock signal to sample the seventh clock signal to obtain an eighth clock signal; A sixth sampling circuit, configured to sample the eighth clock signal using the first clock signal to obtain a ninth clock signal; A second four-to-one selector, whose input terminals are respectively input with the sixth clock signal, the seventh clock signal, the eighth clock signal and the ninth clock signal, whose control terminals are respectively input with the third control signal and the fourth control signal, and whose output terminal outputs the switch control signal; A first frequency-dividing circuit, which divides the first clock signal by four under the control of the switch control signal to obtain a first frequency-dividing signal; A second frequency-dividing circuit divides the first frequency-dividing signal by four under the control of the switch control signal to obtain a second frequency-dividing signal; The circuit control signal includes four control signals, which are the first control signal, the second control signal, the third control signal and the fourth control signal.

2. The circuit for generating a multi-phase serial data sampling clock signal according to claim 1, characterized in that: The four-phase clock signal generating circuit is a voltage-controlled oscillator.

3. The circuit for generating a multi-phase serial data sampling clock signal according to claim 1, characterized in that: The first sampling circuit, the second sampling circuit, the third sampling circuit, the fourth sampling circuit, the fifth sampling circuit, and the sixth sampling circuit are all D flip-flops.

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