I / o hot spot detection using exponential moving average

Abstract

A computer-implemented method includes accessing data stored in a memory of a computer system, wherein the memory includes a faster access storage medium and a slower access storage medium; determining respective exponential moving averages of a number of access operations performed on respective memory locations of the memory; and transferring a portion of the data into the faster access storage medium and transferring a portion of the data into the slower access storage medium in accordance with the determined exponential moving averages.

Description

Technical Field

[0001] This application relates to the field of storage, and in particular to an I / O hotspot detection method using an exponential moving average. Background Technology

[0002] A computing system comprises one or more processors that operate on data stored within it. Processors do not access stored data equally; in a given application, some data is needed more frequently than others. The most frequently accessed data can be termed a "hotspot" because of the large number of memory accesses to that data. When hotspots are identified, computing devices can perform data management to address the high utilization of certain memory locations. Traditionally, hotspots are determined by simply counting the number of memory address hits. Summary of the Invention

[0003] Various examples will now be described to briefly introduce some concepts, which will be further described in the detailed embodiments. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0004] According to one aspect of the present invention, a computer-implemented method for managing data stored in a computer system is provided. The method includes: accessing data stored in a memory of the computer system, wherein the memory includes a faster access storage medium and a slower access storage medium; determining a corresponding exponential moving average of the number of access operations performed at corresponding memory locations in the memory; and transferring a first portion of the data to the faster access storage medium and a second portion of the data to the slower access storage medium based on the determined exponential moving average.

[0005] Alternatively, in the foregoing aspect, another implementation of the aspect provides: determining a count of the number of access operations to the memory location; and weighting the determined count using an exponential factor calculated by means of the duration since the last refresh of the count.

[0006] Alternatively, in the foregoing aspect, another implementation of the aspect provides to further calculate the exponential factor using a predetermined lookback duration and the duration since the last refresh of the count.

[0007] Alternatively, in the foregoing aspect, another implementation of the aspect provides to further calculate the exponential factor using the cache memory size, the predetermined lookback duration, and the duration since the last refresh of the count.

[0008] Optionally, in any of the foregoing aspects, another implementation of the aspect provides a performance metric for calculating the memory access frequency to one or both of the faster access storage medium and the slower access storage medium; and based on the calculated performance metric, automatically adjusting one or more of the exponential factor, the duration since the last refresh of the count, and the predetermined lookback duration using the processing circuitry of the computer system.

[0009] Alternatively, in the foregoing aspect, another implementation of the aspect provides a performance metric that includes one or both of multiple cache misses and multiple cache hits.

[0010] Optionally, in any of the foregoing aspects, another implementation of said aspect provides that: the faster access storage medium is a cache memory, and determining the exponential moving average includes determining a count of the number of access operations to the memory location; the weighted count of the memory location is determined as... C' = (n / t – C / T) ((1 + log 2 (M / (C T / t))) Tt / (T+t)) + C , in C It is a definite count of the number of access operations. C' It is a definite weighted count. T This is the scheduled playback duration. t It is the duration since the last access to the memory location. n The duration is t The number of cache hits during the period. M It is the size of the cache memory.

[0011] Alternatively, in any of the foregoing aspects, another implementation of the aspect provides storing an exponentially moving average determined for the memory location along with the data in the memory location.

[0012] Alternatively, in any of the foregoing aspects, another implementation of the aspect provides storing the determined corresponding exponential moving average as a memory-mapped data structure in the memory.

[0013] According to another aspect of the present invention, a memory system is provided. The memory system includes a first memory array, a second memory array, and a memory controller. Access to the first memory array is faster than access to the second memory array. The memory controller includes a processing circuitry system that counts the number of access operations to memory locations in the first and second memory arrays; determines an exponential moving average of the number of access operations to the memory locations using the number of access operations; and transfers a portion of the data stored in the second memory array to the first memory array based on the determined exponential moving average.

[0014] Alternatively, in the foregoing aspect, another implementation of the aspect provides a processing circuitry system for calculating an exponential factor using the duration since the last access to the memory location; and for determining the exponential moving average of the memory location by weighting the number of access operations to the memory location using the exponential factor.

[0015] Alternatively, in the foregoing aspect, another implementation of the aspect provides a processing circuitry system for calculating the exponential factor using a predetermined lookback duration and the duration since the last access to the memory location.

[0016] Optionally, in the foregoing aspect, another implementation of the aspect provides a cache memory, in which the first memory array is included; and a processing circuitry system for calculating the exponential factor using the size of the cache memory, the predetermined lookback duration, and the duration since the last access to the memory location.

[0017] Optionally, in the foregoing aspect, another implementation of the aspect provides a processing circuitry system for monitoring one or both of cache misses and cache hits; and adjusting one or more of the exponential factor, the duration since the last refresh of the count, and the predetermined lookback duration based on a determined number of the one or both of the cache misses and cache hits.

[0018] Alternatively, in any of the foregoing aspects, another implementation of the aspect provides a processing circuitry system for storing an exponentially moving average determined for a memory location along with data in the memory location.

[0019] Optionally, in any of the foregoing aspects, another implementation of the aspect provides a processing circuit system for storing the determined corresponding exponential moving average as a memory-mapped data structure in the memory of the memory system.

[0020] According to another aspect of the present invention, a network node device for a communication network is provided. The network node device includes a processing circuitry system that determines an exponentially moving average of the number of network access operations transmitted to a plurality of endpoint devices of the communication network; and initiates the transmission of a portion of data stored in a first endpoint device among the plurality of endpoint devices to a second endpoint device among the plurality of endpoint devices, to achieve the determined exponentially moving average.

[0021] Optionally, in the foregoing aspect, another implementation of the aspect provides a processing circuit system for calculating an exponential factor using the duration since the last access to the memory storage location; and for determining the exponential moving average of the memory storage location by weighting the number of access operations to the memory storage location using the exponential factor.

[0022] Alternatively, in the foregoing aspect, another implementation of the aspect provides a processing circuitry system for calculating the exponential factor using a predetermined lookback duration and a self-counting duration since the last refresh.

[0023] Optionally, in any of the foregoing aspects, another implementation of the aspect provides that the network node device is a content caching router for the communication network, and the processing circuitry is used to determine an exponential moving average of the number of network access operations transmitted to a plurality of servers of the communication network. Attached Figure Description

[0024] The accompanying drawings illustrate exemplary embodiments, and the textual descriptions can be found in the detailed embodiments.

[0025] Figure 1 A flowchart illustrating a computer-implemented method for managing data stored in a computer system to implement one or more exemplary embodiments.

[0026] Figure 2 A block diagram of a memory system for implementing one or more exemplary embodiments.

[0027] Figure 3 A diagram illustrating memory locations for implementing one or more exemplary embodiments.

[0028] Figure 4 A schematic diagram of a network device for implementing one or more exemplary embodiments.

[0029] Figure 5 A schematic block diagram of a computer system for implementing one or more exemplary embodiments. Detailed Implementation

[0030] In the following description, reference is made to the accompanying drawings, which form a part of this document, and specific embodiments that may be practiced are illustrated by description in the drawings. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the invention. Therefore, the following description of exemplary embodiments is not intended to be limiting, and the scope of the invention is defined by the appended claims.

[0031] In one embodiment, the functions or algorithms described herein may be implemented in software. This software may consist of computer-executable instructions stored in a computer-readable medium or storage device, such as one or more non-transitory memories or other types of hardware-based local or networked storage devices. Furthermore, these functions correspond to modules that may be software, hardware, firmware, or any combination thereof. Multiple functions may be executed in one or more modules as needed; the described embodiments are merely examples. The software may execute on a digital signal processor, an application-specific integrated circuit (ASIC), a microprocessor, or other type of processor running on a computer system, such as a personal computer, server, or other computer system, thereby turning such a computer system into a specifically programmed machine.

[0032] This function can be used to perform operations using, for example, software, hardware, firmware, etc. For example, the phrase "for" can refer to the logic circuit structure of a hardware element used to implement the associated function. The phrase "for" can also refer to the logic circuit structure of a hardware element used in a coded design to implement the associated function of firmware or software. The term "module" refers to a structural element that can be implemented using any suitable hardware (e.g., a processor), software (e.g., an application program), firmware, or any combination of hardware, software, and firmware. The term "logic" includes any function used to perform a task. For example, each operation shown in the flowchart corresponds to the logic that performs that operation. Operations can be performed using software, hardware, firmware, etc. The terms "component," "system," etc., can refer to computer-related entities, hardware, and executing software, firmware, or combinations thereof. A component can be a process, object, execution, program, function, subroutine, computer, or a combination of software and hardware running on a processor. The term "processor" can refer to a hardware component, such as the processing unit of a computer system.

[0033] Furthermore, the claimed subject matter can be implemented as a method, apparatus, or article of manufacture using standard programming and engineering techniques to produce software, firmware, hardware, or any combination thereof to control a computing device to realize the disclosed subject matter. The term "article of manufacture" as used herein is intended to include computer programs accessible from any computer-readable storage device or medium. Computer-readable storage media can include, but is not limited to, magnetic storage devices such as hard disks, floppy disks, magnetic stripes, optical discs, compact disks (CDs), digital versatile disks (DVDs), smart cards, flash memory devices, etc. Conversely, computer-readable media (i.e., not limited to storage media) can also include communication media, such as transmission media for wireless signals, etc.

[0034] A computing system includes processing resources (e.g., processing units) and data storage resources (e.g., various forms of memory or memory devices). Processing resources may be physically or logically located together with data storage resources (e.g., when the computing system is a processing node, a personal computer (PC), a laptop, a smartphone, etc.), or processing resources may be located separately from data storage resources (e.g., a distributed database system, a cloud computing system, etc.).

[0035] Hotspots in storage resources refer to memory locations or storage devices that experience a high volume of access operations. In many storage and networking applications, such as enterprise storage, cloud services, and network content caching, detecting hotspots in the memory locations of computing devices or the storage devices of computer networks is crucial. More accurate detection of storage hotspots can improve the caching and tiering of stored data.

[0036] Figure 1 A flowchart of a method 100 for managing data stored in a computer system. The location of the stored data can be moved to optimize access to the data, for example, by reducing access time to hotspots detected in the system, or by eliminating bottlenecks when accessing the data.

[0037] At block 105 of the flowchart, data stored in the computer system's memory is accessed. This access is performed using the computer system's processing resources. These resources can be one or more processors (e.g., a central processing unit or CPU). Memory includes faster-access and slower-access storage media. In some examples, faster-access storage media is dynamic random access memory (DRAM), and slower-access storage media is non-volatile memory (NVM). In some examples, faster-access storage media is cache memory, and slower-access storage media is shared memory. Cache memory can be processor-local to provide low latency for memory operations, while shared memory may have longer latency due to the protocols used to access it.

[0038] At block 110, an exponential moving average of access operations to one or both memory locations on faster and slower access storage media is determined. A count of the number of access operations to the memory locations can be determined, and this count is used to determine the exponential moving average of the memory locations. Based on the exponential moving average, it is determined whether a memory location is a hotspot. This calculation can be used to identify hotspots in memory. Based on the identified hotspots, data can be reallocated to improve efficiency.

[0039] At block 115, data in memory locations designated as hotspots can be transferred and stored on faster access storage media. This reduces latency when accessing hotspots. Memory locations in faster access storage media that are not hotspots can be transferred and stored on slower access storage media. The exponential moving average can also be used to identify memory locations in access storage media that are considered "cold" points, meaning they don't receive much traffic even with access. Data from these cold points can be moved to slower access storage media. Hotspots and colds can be identified by comparing the exponential moving average to one or both of the hotspot and coldspot thresholds.

[0040] When calculating the exponential moving average, a weighted count of memory location access operations can be used, with more recent memory access operations given higher weights. This provides a faster response time for hotspot changes compared to a simple moving average (SMA) alone.

[0041] In some examples, the weighted count is calculated as C' = (n / t – C / T) ((1 + log 2 (M / (C T / t))) Tt / (T+t)) + C , in C It is a definite count of the number of access operations. C' It is a definite weighted count. T This is the scheduled playback duration. t It is the duration since the last time the counter data was refreshed. n It is the duration t The number of cache hits during the period. M This refers to the size of the memory. The symbol "" is used here. "" is used as the multiplication operator, and " / " is used as the division operator. Then, the weighted exponential moving average is determined. Value X = (1 + log 2 (M / (C T / t)) It can be called an exponential factor. X The exponential factor is initialized to X=1 The behavior is based on the initial match and the unweighted average.

[0042] The aggressiveness of an exponential moving average can be adjusted by modifying the parameters. X , T and t The value is adjusted accordingly. Machine learning or artificial intelligence (AI) can be used to dynamically adjust the exponential moving average to optimize performance by changing parameters. The processing circuitry of a computer system can calculate performance metrics for memory operations and adjust the parameters of the exponential moving average accordingly to improve performance.

[0043] Performance metrics can be correlated with the frequency of accesses to one or both of faster and slower access storage media. Machine learning or AI algorithms can modify the parameters of an exponential moving average to converge to a solution. For example, if the number of memory operations on faster access storage media is decreasing, the processing circuitry can change the value of a parameter to increase the number of accesses to faster access storage media. This can be achieved by reducing the parameter "...". t "to achieve, because t It is the interval between counter data refreshes. t A smaller numerical value means a higher refresh rate for the counter data, and a larger value... t Used for less aggressive methods. Change the lookup period. T The value of also affects the response. Smaller values T This results in shorter review periods and increases the offensive capabilities of machine algorithms.

[0044] To facilitate the convergence of machine learning or AI algorithms, positive feedback to performance metrics can be established. For example, stochastic gradient descent (SGD) can be used as feedback to memory performance. In SGD, the true gradient is determined by the gradient ( ) in a single example. w Approximately, where , in, η It's the step length. Q i It is the cost function that is minimized.

[0045] When the computer system's processing circuitry scans the training set for a machine learning or AI algorithm, it performs the gradient update described above for each training example. Several passes can be made on the training set until the algorithm converges. The data can be shuffled at each pass to prevent loops. An adaptive learning rate can be used to facilitate algorithm convergence.

[0046] For the stochastic gradient descent technique, SGD can be determined as follows: ●Select parameters ( X , T , t The initial vector and the learning rate initialized to 1.

[0047] ● Repeat the following steps until you obtain an approximate minimum value: ○ Randomly shuffle the examples in the training set.

[0048] ○ For transmission I = 1, 2, 3... m Therefore, we can conclude that: ○ .

[0049] Stochastic gradient descent is just one option to measure memory performance. Other options include adaptive gradient algorithms (AdaGrad), root mean square propagation (RMSProp), adaptive moment estimation (Adam), and second-order optimizers (e.g., the Newton-Raphson algorithm).

[0050] Figure 2 To be executable Figure 1This is an example of a portion of an exemplary method for a memory system. Memory system 210 includes a first memory array 215, a second memory array 220, and a memory controller 225. Memory system 210 can be included in a computer system including host device 205. Memory controller 225 processes memory requests from host device 205. Access to the first memory array is faster than access to the second memory array. In some examples, the first memory array includes DRAM, and the second memory array includes NVM.

[0051] The memory controller includes processing circuitry for calculating an exponential moving average of memory locations within the memory array. In response to detecting memory hotspots using the calculated moving average, memory controller 225 can transfer a portion of data from slower access memory array 220 to faster access memory array 215. Memory controller 225 can also transfer cold spots from the faster access memory array 215 to the slower access memory array 220. This improves system performance by moving more frequent operations to the faster memory.

[0052] The exponential moving average can be stored as a memory-mapped data structure 230 in one of the memory arrays. Which memory array is used to store the memory map may depend on the update frequency of the memory map. Figure 3 One variation is shown in which the exponential moving average (EMA) determined for memory location 335 is stored along with the data in the memory location.

[0053] In some examples, the faster access memory array is included in the cache memory of the memory system, and the slower access memory array is included in the main memory of the memory system. The cache memory is used to store information frequently used by the host device 205. The main memory is used to store information used less frequently and can be shared by the host device 205 and other host devices. In response to detecting memory hotspots using a calculated moving average, the memory controller 225 may transfer a portion of data from the slower main memory to the faster cache memory. Performance metrics may include one or both of the number of cache hits and cache misses in the cache memory. The memory controller executes machine learning or AI algorithms to pass data to the cache memory to improve the cache hit rate of the memory system.

[0054] Besides improving the performance of memory devices and systems, exponential moving averages can also be used in conjunction with machine language or AI algorithms to enhance the performance of communication networks. A communication network comprises multiple network node devices that transmit information using communication channels. Network node devices are computing devices capable of receiving, sending, forwarding, and processing information to other nodes in the network using paths provided by the network. Some examples of network node devices include network servers, network routers, network hubs, and host computers. Network node devices can be physical or virtual devices. Traditionally, the routing of packet data in a network uses shortest path routing. Proxy and connected nodes can be formed using "hello" protocols between neighboring nodes in the network, and links throughout the network can be advertised using flooding processes. Shortest path first (SFB) routing algorithms can be used to calculate the next hop (NH) for all advertised routes in the network.

[0055] A content distribution network (CDN) is a geographically distributed network consisting of proxy servers and data centers including those servers. CDNs are used to distribute requested content to end users with high availability and high performance. An example of a CDN is enterprise storage. Enterprise storage is designed to handle large volumes of data and a large number of concurrent users. Enterprise storage systems can include storage area networks (SNRs). In a content cache, data is delivered from the server geographically closest to the requester. When content is needed, it can be retrieved from any cached location based on the network's geographic location, performance, and bandwidth. Detecting hotspots can trigger data movement, thereby optimizing performance.

[0056] CDN node devices are typically deployed in multiple locations, usually across multiple internet backbones. Requests for content are algorithmically routed to the network node device that is best suited to the request to some extent. The location best suited for serving content to a specific user can be selected to provide optimal performance. The optimal source of content can be measured by selecting the location with the fewest hops from the requesting client, the fewest network seconds from the requesting client, or the highest availability to the user. An adaptive exponential moving average algorithm can be used to identify "hot" content in the CDN's storage devices.

[0057] Figure 4 This is a schematic diagram of an example of a network node device 400 used to implement machine learning or AI algorithms for identifying "hot" data content in CDN endpoints (e.g., storage servers). The network node device 400 can be a device that transmits electrical and / or optical signals over a network, such as a switch, router, bridge, gateway, etc. In some cases, the network node device 400 can operate independently or in conjunction with other network node devices 400 to operate a virtual network device with the functionality described herein. Figure 4 As shown, network node device 400 may include transceiver (Tx / Rx) 410, which may be a transmitter, a receiver, or a combination thereof. Tx / Rx 410 may be coupled to multiple downlink ports 420 (e.g., downlink interfaces) for transmitting and / or receiving frames from other nodes, and Tx / Rx 410 may be coupled to multiple uplink ports 450 (e.g., uplink interfaces) for transmitting and / or receiving frames from other nodes respectively. Processor 430 may be coupled to Tx / Rx 410 to process data signals and / or determine which nodes to send data signals to.

[0058] Processor 430 may be implemented as a general-purpose processor or may be part of one or more ASICs and / or digital signal processors (DSPs). Network node device 400 may include a packet encoding module 414, which may be used to encode packets using PPR-ID. Packet encoding module 414 may be implemented in a general-purpose processor, a field-programmable gate array (FPGA), an ASIC, a DSP, a microcontroller, etc. In an alternative embodiment, packet encoding module 414 may be implemented in processor 430 as computer-executable instructions (e.g., as a computer program product stored in a non-transitory computer-readable medium) stored in memory device 432, which may be executed by processor 430 and / or implemented partly in processor 430 and partly in memory device 432. According to embodiments, downlink port 420 and / or uplink port 450 may include wireless, electrical, and / or optical transmitting and / or receiving components.

[0059] Network node device 400 can be a content caching router for a communication network or CDN. The processing circuitry of network node device 400 monitors network traffic to track requests to endpoint devices on the network and determines an exponential moving average of the number of network access operations transmitted to the endpoint devices. The exponential moving average can detect storage devices (e.g., storage servers) that store "hot" data content and experience high traffic. The more recent the transmission, the greater the weight given to the exponential moving average. This allows for a rapid response to changes in the network. In response, the network node device can move some data (or initiate transmissions via requests) to better locations or multiple locations to improve data access speed or reduce any network bottlenecks that slow down data access. For example, data can be moved to one or more storage servers to shorten the path from the requesting device to the data.

[0060] The processing circuitry of network node device 400 can adjust the identification of endpoint hotspots by using one of the machine learning or AI algorithms described herein to adjust the parameters of the exponential moving average calculation. This algorithm monitors network performance metrics and adjusts parameters to optimize those metrics. In some examples, the performance metric is the length of the network path or the number of hops in network traffic. This algorithm can adjust the calculation of the exponential moving average to respond more quickly to increases in network path length or hop count.

[0061] Figure 5 This is a block diagram of a computer system 500 for performing methods and algorithms according to exemplary embodiments. Not all components need to be used in each embodiment.

[0062] One example is a computing device that may include a processing unit 502, a memory 503, a removable storage device 510, and a non-removable storage device 512. Although the exemplary computing device is shown and described as computer system 500, the computing device may take different forms in different embodiments. For example, the computing device may be a server, a router, or a virtual router.

[0063] Furthermore, although various data storage elements are shown as part of computer system 500, the storage device may also include, or alternatively include, cloud-based storage devices accessible via a network (e.g., the Internet or server-based storage devices). Also note that the SSD may include a processor capable of running a parser, allowing parsed, filtered data to be transferred via the I / O channel between the SSD and main memory.

[0064] Memory 503 may include volatile memory 514 and non-volatile memory 508. Computer system 500 may include various computer-readable media or computing environments that access various computer-readable media, such as volatile memory 514 and non-volatile memory 508, removable storage device 510, and non-removable storage device 512. Computer storage devices include random-access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) or electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD ROM), digital versatile disk (DVD) or other optical disc storage devices, magnetic tape cassettes, magnetic tape, disk storage devices or other magnetic storage devices, or any other medium capable of storing computer-readable instructions.

[0065] Computer system 500 may include or access a computing environment including input interface 506, output interface 504, and communication interface 516. Output interface 504 may include a display device, such as a touchscreen, which can also be used as an input device. Input interface 506 may include one or more of the following: touchscreen, touchpad, mouse, keyboard, camera, one or more device-specific buttons, one or more sensors integrated into computer system 500 or coupled to the computer via a wired or wireless data connection, and other input devices. Computer system 500 can operate in a networked environment using a communication connection to connect to one or more remote computers, such as a database server. Remote computers may include personal computers (PCs), servers, routers, network PCs, peer-to-peer devices, or other common data stream network switches. Communication connections may include local area networks (LANs), wide area networks (WANs), cellular networks, Wi-Fi, Bluetooth, or other networks. According to one embodiment, various components of computer system 500 are connected to system bus 520.

[0066] Computer-readable instructions (e.g., program 518) stored on a computer-readable medium may be executed by a processing unit 502 of a computer system 500. In some embodiments, program 518 includes software for implementing one or more methods described herein. Hard disk drives, CD-ROMs, and RAM are some examples of articles of manufacture that include non-transitory computer-readable media such as storage devices. The terms "computer-readable medium" and "storage device" do not include carrier waves that are considered too transient. Memory may also include networked storage devices, such as storage area networks (SANs). Computer program 518, together with workspace manager 522, may be used to cause processing unit 502 to execute one or more methods or algorithms described herein.

[0067] While several embodiments have been described in detail above, other modifications are possible. For example, the logical flow depicted in the figures does not require the specific or sequential order shown to achieve the desired result. Other steps may be provided, steps may be removed from the described flow, and other components may be added to or removed from the described system. Other embodiments are within the scope of the appended claims.

Claims

1. A method executed by a computer system, characterized in that, The computer system includes one or more processing resources, memory, and a memory controller; the method includes: The one or more processing resources are used to access data stored in the memory, wherein the memory includes faster access storage media and slower access storage media; The memory controller is used to determine the count of the number of access operations performed at the corresponding memory locations in the memory; The determined count is weighted using an exponential factor calculated based on the duration since the last refresh of the count; The weighted count determines the exponential moving average; and Based on a determined exponential moving average, the memory controller is used to transfer a first portion of the data to the faster access storage medium and a second portion of the data to the slower access storage medium.

2. The method according to claim 1, characterized in that, The index factor is also calculated using a predetermined lookback duration and the duration since the last refresh of the count.

3. The method according to claim 2, characterized in that, The exponential factor is also calculated using the cache memory size, the predetermined lookback duration, and the duration since the last refresh of the count.

4. The method according to claim 2 or 3, characterized in that, include: Calculate the performance metrics of memory access frequency for one or both of the faster access storage medium and the slower access storage medium; as well as Based on the calculated performance metrics, the processing circuitry of the computer system automatically adjusts one or more of the exponential factor, the duration since the last refresh of the count, and the predetermined review duration.

5. The method according to claim 4, characterized in that, The performance metrics include multiple cache misses and one or two of multiple cache hits.

6. The method according to claim 1, 2, 3 or 5, characterized in that, The faster access storage medium is a cache memory, and determining the exponential moving average includes: A count of the number of access operations to the memory location; and The weighted count of the memory location is determined as follows: C' = (n / t – C / T) ((1 + log 2 (M / (C T / t))) Tt / (T+t)) + C ,in C It is a definite count of the number of access operations. C' It is a definite weighted count. T This is the scheduled playback duration. t It is the duration since the last access to the memory location. n The duration is t The number of cache hits during the period. M It is the size of the cache memory.

7. The method according to claim 1, 2, 3 or 5, characterized in that, This includes storing an exponentially moving average determined for a memory location along with the data at that memory location.

8. The method according to claim 1, 2, 3 or 5, characterized in that, This includes storing the determined corresponding exponential moving average as a memory-mapped data structure in the memory.

9. A memory system, characterized in that, include: A first memory array and a second memory array, wherein access to the first memory array is faster than access to the second memory array; as well as A memory controller, operatively coupled to the first and second memory arrays and including a processing circuitry system for: The number of access operations to memory locations in the first memory array and the second memory array is counted. The exponential factor is calculated using the duration since the last access to the memory location; The exponential moving average of the memory location is determined by weighting the number of access operations to the memory location using the exponential factor; and Based on the determined exponential moving average, a portion of the data stored in the second memory array is transferred to the first memory array.

10. The memory system according to claim 9, characterized in that, The processing circuitry of the memory controller is used to calculate the exponential factor using a predetermined lookback duration and the duration since the last access to the memory location.

11. The memory system according to claim 10, characterized in that, include: A cache memory, wherein the first memory array is included in the cache memory; The processing circuitry of the memory controller is used to calculate the exponential factor using the size of the cache memory, the predetermined lookback duration, and the duration since the last access to the memory location.

12. The memory system according to claim 11, characterized in that, The processing circuitry system of the memory controller is used for: Monitor one or both cache misses and cache hits; and Based on a determined number of one or both of the cache misses and cache hits, adjust one or more of the exponential factor, the duration since the last refresh of the count, and the predetermined lookback duration.

13. The memory system according to any one of claims 9 to 12, characterized in that, The processing circuitry of the memory controller is used to store the exponentially moving average determined for the memory location along with the data in the memory location.

14. The memory system according to any one of claims 9 to 12, characterized in that, The processing circuitry of the memory controller is used to store the determined corresponding exponential moving average as a memory-mapped data structure in the memory of the memory system.

15. A network node device for a communication network, characterized in that, The network node device includes: Processing circuitry system, used for: Determine the number of network access operations transmitted to multiple endpoint devices of the communication network; The exponential factor is calculated using the duration since the last access to the memory storage location; and The exponential moving average of the number is determined by weighting the number using the exponential factor; and Initiate the transfer of a portion of the data stored in the plurality of endpoint devices from a first endpoint device to a second endpoint device in the plurality of endpoint devices to achieve a determined exponential moving average.

16. The network node device according to claim 15, characterized in that, The processing circuitry is also used to calculate the exponential factor using a predetermined lookback duration and a self-counting duration since the last refresh.

17. The network node device according to claim 15 or 16, characterized in that, The network node device is a content cache router for the communication network, and the processing circuitry is used to determine the exponential moving average of the number of network access operations transmitted to multiple servers of the communication network.

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