A Smart Testing Method for FPGA Interconnect Resources with Hundreds of Millions of Gates

Abstract

This invention discloses an intelligent testing method for FPGA interconnect resources at the billion-gate level, belonging to the field of FPGA testing. The method involves identifying the module under test (DUT) of the internal interconnect resources of the FPGA; extracting its physical connection point information from the XDLRC resource file of the DUT; modeling and parameterizing the physical connection points, presenting the results in a graph dictionary; searching for the optimal routing path based on the graph dictionary, generating a configuration graph, and performing ATE testing to determine if the tested path has any faults. This invention extracts the FPGA's XDLRC resource file, analyzes the structural characteristics of the interconnects, and optimizes the modeling process based on the determinacy of the interconnect metal lines' positions, transforming the interconnect metal lines into points in a mathematical graph model. Compared to the previous modeling optimization, the modeling space is compressed by nearly 50%, and the routing search time is also reduced accordingly. An improved depth-first search algorithm is used, enabling the search function to be implemented with concise code, and parameterized information is added to the search dictionary object.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of FPGA detection technology, and in particular to a method for intelligently testing interconnection resources of a billion-gate FPGA. BACKGROUND

[0002] With the continuous landing of new application scenarios such as artificial intelligence, big data, and industrial Internet of Things, the market's performance requirements for chips are increasing, and FPGAs (Field Programmable Gate Array) are widely used due to their high performance, low power consumption, programmability, and other advantages. As application scenarios become more complex, the required FPGA size also becomes larger, and currently it has generally reached the level of a billion gates. The area of FPGA interconnection resources has accounted for more than 80% of the total chip area, and the structure has become more complex. When a fault occurs, the probability of failure of interconnection resources is much higher than that of other resources, so testing the interconnection resources within the FPGA is very important.

[0003] Foreign research on FPGA interconnection resource testing started early, and the main research results are concentrated in the testing field of CLB (Configurable Logic Blocks) and RAM (Random Access Memory), as well as the research on testing methods. However, the early methods are not suitable for larger and more complex FPGAs of current scale arrays. In recent years, some testing research on interconnection resources has gradually appeared in China, and some modeling methods and algorithms based on directed graph theory are used by all of them; some foreign methods based on BIST (Built-in Self Test) are also used. These methods abstract the metal interconnection lines and switch matrix into a directed graph model, and apply path search algorithms based on directed graphs to realize automatic testing of the switch matrix. For example, network maximum flow algorithm, depth-first search algorithm, and breadth-first search algorithm. However, there is no universal test model, and there are few methods for fault type judgment and positioning. There are also some testing research based on deep learning methods, but this method needs to be carried out on the premise of having a large number of training sets, and there are problems of long code running time and uncontrollable testing cost. SUMMARY

[0004] The purpose of the present application is to provide a method for intelligently testing interconnection resources of a billion-gate FPGA to solve the problems of low testing efficiency, high testing configuration frequency, and poor universality of existing billion-gate FPGA internal resource testing.

[0005] To solve the above technical problems, the present application provides a method for intelligently testing interconnection resources of a billion-gate FPGA, comprising:

[0006] extracting the interconnection resources of the FPGA and modeling them;

[0007] generating a configuration path according to the search algorithm;

[0008] testing on the ATE according to the configuration result to make fault judgment.

[0009] In an embodiment, the extraction of the interconnection resources of the FPGA and the modeling include extraction and parameterization processing of the interconnection resources in the XDLRC report resource file, and conversion of points in the FPGA bottom architecture into points in graph theory.

[0010] In an embodiment, the extraction of the interconnection resources of the FPGA and the modeling specifically include:

[0011] According to the test requirement, the measured module of the internal interconnection resources of the FPGA to be tested is analyzed and determined;

[0012] According to the determined measured module, the physical connection point information thereof is extracted in the XDLRC report resource file;

[0013] The extracted physical connection points are subjected to modeling processing and parameterization processing, and the results are exhibited in the form of a graph dictionary.

[0014] In an embodiment, the modeling processing and parameterization processing of the extracted physical connection points and the exhibition of the results in the form of a graph dictionary include:

[0015] The interconnection points and the interconnection lines in the FPGA interconnection resources exist in dependence on the switch matrix, the interconnection lines are divided into two kinds of interconnection metal lines and programmable interconnection lines, and the two kinds of interconnection lines are transferred by the interconnection points on the switch matrix;

[0016] Firstly, the information of each switch matrix tile and the required module tile is extracted, and secondly, the required interconnection lines are extracted from the extracted information according to the naming features of the interconnection lines, the interconnection metal lines are processed as points in a mathematical graph, the adjacent points of the point are screened out according to the connection relationship of the programmable interconnection lines, the point is subjected to parameterization processing according to the number of the adjacent points, a parameter out-degree and a parameter flag are added and written into a file, and finally, the point and its adjacent points are stored in the file in the form of a dictionary, facilitating subsequent routing search and query.

[0017] In an embodiment, the generation of the configuration path according to the search algorithm includes optimal routing path search according to the modeled graph dictionary, and generation of a configuration graph.

[0018] In an embodiment, the optimal routing path search includes: setting the first root interconnection metal line after the input IOB is led out as a start point in the mathematical graph, and setting the last interconnection metal line entering the output IOB as an end point in the mathematical graph for routing search; using an improved depth-first algorithm to connect the modeled graph points into a test path, and proposing the concepts of out-degree and marking for each point on the original depth-first algorithm, and constraining the machine to preferentially search the points with large out-degree in the path search process to prevent the occurrence of breakpoints when the end point is not searched, and marking each point in one configuration to prevent repeated traversal of the points.

[0019] In an embodiment, the fault judgment according to the configuration result includes: the ATE test platform calls the configuration vector to configure the FPGA chip, and calls the test vector to test the internal interconnection resources of the FPGA chip and judges whether there is a fault.

[0020] In an embodiment, the ATE test platform uses the V93000 test machine of Advantest.

[0021] The intelligent test method for the interconnection resources of the FPGA with hundreds of millions of gates provided by the application has the following beneficial effects:

[0022] (1) The application extracts the XDLRC resource report file of the FPGA, analyzes the structural characteristics of the interconnection lines, determines the certainty of the interconnection metal lines, optimizes the interconnection metal lines during modeling to convert the interconnection metal lines into points in the mathematical graph model, and compared with before the modeling optimization, the modeling space is compressed by nearly 50%, and the routing search time is also reduced;

[0023] (2) The interconnection resource test needs to connect the points in the modeled mathematical graph to form a test path, but the underlying architecture of the FPGA is large, the iteration times of the traditional method are easily limited by the compiler, and the traversal points are more, and the traversal time is longer; the application uses an improved depth-first algorithm to complete, and the depth-first algorithm for path search can realize the search function through a short code, and the parameterized information is added to the search dictionary object. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a principle block diagram of an intelligent test method for interconnection resources of a FPGA with hundreds of millions of gates proposed by the application;

[0025] Figure 2 is a modeling schematic diagram of a switch matrix;

[0026] Figure 3 is a modeling flow schematic diagram;

[0027] Figure 4 is a routing search flow schematic diagram. DETAILED DESCRIPTION

[0028] The application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the application will be more apparent according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, only for the purpose of conveniently and clearly assisting the description of the embodiments of the application.

[0029] The application provides a method for testing interconnection resources of a tera-gate FPGA, the principle of which is shown in Figure 1 The method comprises the following steps:

[0030] Step 1: According to the test requirements, the measured module of the internal interconnection resources of the FPGA to be tested is determined.

[0031] Step 2: The physical connection point information of the determined measured module is extracted in the XDLRC report resource file.

[0032] Step 3: The extracted physical connection points are modeled and parameterized, and the results are displayed in the form of a graph dictionary.

[0033] Step 4: The optimal routing path is searched according to the modeled graph dictionary, a configuration graph is generated, and ATE testing is performed to determine whether the measured path has a fault.

[0034] The method for testing interconnection resources of a tera-gate FPGA is used for fault detection and judgment of PIPs (programmable interconnection lines) and wires (interconnection metal lines) in the FPGA circuit. The testing method comprises FPGA interconnection resource modeling, FPGA interconnection resource routing search, configuration file, bit stream file, and ATE testing program, wherein:

[0035] The FPGA interconnection resources include the switch matrix, CLB (Configurable Logic Block, programmable logic module), and IOB (Input Output Block, programmable input output unit) in the FPGA underlying architecture, as well as the wires connecting these modules.

[0036] The configuration file XDL (Xilinx Design Language) is a text file containing routing path information, IOB and CLB module information in the path, and configuration information, and can be converted with the configuration graph file through corresponding commands.

[0037] The bit stream file is a binary file generated after the FPGA is configured, which is the internal configuration state file of the FPGA, and contains the settings of routing, logic resources, and IO.

[0038] Modeling is the process of transforming interconnect points and interconnects in FPGA interconnect resources into point-edge relationships in a mathematical graph model. Interconnect points and interconnects exist within a switch matrix. Interconnects are divided into two types: metal interconnects (outside the switch matrix) and programmable interconnects (inside the switch matrix). Both types of interconnects are derived from interconnect points on the switch matrix, such as... Figure 2 The left side of the image shows a schematic diagram of a switch matrix with interconnect points and interconnect lines. Because interconnect metal lines and programmable interconnect lines appear alternately, and the interconnect metal lines have fixed routing characteristics, during modeling, the interconnect metal lines are treated as points in a mathematical graph. Based on the routing relationships of the programmable interconnect lines, they are transformed into edges in the mathematical graph, as shown below. Figure 2 The diagram on the right illustrates the processing of the switch matrix during modeling. The specific modeling operation process is as follows: Figure 3 As shown, firstly, the information of each switch matrix tile and the required module tile is extracted. Secondly, the required interconnects are extracted from the extracted information according to the naming characteristics of the interconnects. The interconnect metal lines are processed into points in a mathematical graph. Based on the connection relationship of the programmable interconnects, the adjacent points of the point are selected. The point is parameterized according to the number of adjacent points, and parameter out-degree and parameter flags are added and written to a file. Finally, the point and its adjacent points are stored in the file in the form of a dictionary for easy subsequent wiring search and query.

[0039] Routing search, based on modeling, connects specified starting points into lines according to the point-edge relationships in the mathematical graph. Due to the large size of FPGA interconnect resources and the requirements for high test coverage and low cost, routing should aim to make the connections between specified starting points the longest possible. For example... Figure 4 The diagram illustrates the routing search process. At the start of routing, the first interconnect wire leading out of the input IOB is set as the start point in the mathematical graph, and the last interconnect wire entering the output IOB is set as the end point in the mathematical graph for routing search. The routing search algorithm employs an improved depth-first search algorithm, connecting the modeled graph points to form a test path. By introducing the concepts of out-degree and label for each point in the original depth-first algorithm, the machine is constrained to prioritize searching points with large out-degrees during the path search process to prevent breakpoints when the destination is not reached. Each point is also labeled during each configuration to prevent repeated traversal. Routing constraints must be satisfied during the routing search process; when the next traversal point is found, it is set as the new start point until the search is complete. The improved depth-first algorithm reduces the number of iterations of the depth-first algorithm itself, shortening the running time.

[0040] The ATE test platform is built by using the V93000 tester of Advantest, and the ATE test program is a tester program which calls a configuration vector to configure the FPGA chip, calls a test vector to test the internal interconnection resources of the FPGA chip and judges whether there is a fault.

[0041] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any modification or change made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A method for intelligent testing of interconnection resources of a billion-gate FPGA, characterized in that, The application relates to a method for testing FPGA (Field Programmable Gate Array) internal interconnection resources. The method comprises the following steps: interconnection resource extraction and modeling of the FPGA; generating a configuration path according to a search algorithm; fault judgment according to a configuration result on an ATE (Automatic Test Equipment); wherein the modeling is a process of converting the interconnection points and interconnection lines in the FPGA interconnection resources into point-edge relationships in a mathematical graph model, and the interconnection points and interconnection lines exist in dependence on a switch matrix, the interconnection lines are divided into two types, i.e. interconnection metal lines outside the switch matrix and programmable interconnection lines inside the switch matrix, and the two types of interconnection lines are connected by the interconnection points on the switch matrix; the interconnection metal lines and the programmable interconnection lines appear alternately, and the interconnection metal lines have fixed wiring, in the modeling process, the interconnection metal lines are regarded as points in the mathematical graph, and the programmable interconnection lines are converted into edges in the mathematical graph according to the wiring relationship; 2. The method of claim 1, wherein the method further comprises: the specific modeling operation process comprises the following steps: firstly, tile information of each switch matrix and required module tile information is extracted; secondly, the required interconnection lines are extracted from the extracted information according to naming characteristics of the interconnection lines, the interconnection metal lines are processed into points in the mathematical graph, adjacent points of the point are screened out according to the connection relationship of the programmable interconnection lines, the point is parameterized processed according to the number of the adjacent points, a parameter out-degree and a parameter mark are added and written into a file, and finally the point and the adjacent points are stored in the file in a dictionary form, so that subsequent wiring search and query are facilitated.

3. The method of claim 2, wherein the method further comprises: The interconnection resource extraction and modeling of the FPGA comprises extraction and parameterization processing of the interconnection resources in an XDLRC report resource file, and converting the points in a FPGA bottom architecture into points in graph theory. The interconnection resource extraction and modeling of the FPGA specifically comprises the following steps: according to test requirements, analyzing and determining a measured module of the internal interconnection resources of a to-be-tested FPGA; extracting physical connection point information of the determined measured module in an XDLRC report resource file; 4. The method of claim 3, wherein the method further comprises: modeling and parameterization processing of the extracted physical connection points, and the result is displayed in a graph dictionary form.

5. The method of claim 3, wherein the method further comprises: The configuration path generated according to the search algorithm comprises the following steps: performing optimal wiring path search according to the graph dictionary after modeling, and generating a configuration graph.

6. The method of claim 3, wherein the method further comprises: The optimal wiring path search comprises the following steps: when wiring starts, a first root interconnection metal line after an input IOB (Input / Output Buffer) is led out is set as a start point in the mathematical graph, and a last interconnection metal line entering an output IOB is set as an end point in the mathematical graph for wiring search; an improved depth-first algorithm is adopted to connect the graph points after modeling into a test path, the concept of out-degree and mark is proposed for each point on the original depth-first algorithm, a point with large out-degree is preferentially searched in the path search process, so that the breakpoint condition is prevented when the end point is not searched, and each point is marked in one configuration to prevent repeated traversal of the point.

7. The method of claim 5, wherein the method further comprises: The fault judgment according to the configuration result on the ATE comprises the following steps: an ATE test platform calls a configuration vector to configure the FPGA chip, and calls a test vector to test the internal interconnection resources of the FPGA chip and judges whether there is a fault. The ATE test platform is built by using a V93000 test machine of Advantest.

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