Communication device, communication system and data transmission method
By using a higher-frequency second clock signal to control data transmission and reception, the communication error problem caused by the edge difference between the clock signal and the data signal is solved, thereby improving the stability and reliability of data transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ACTIONS ZHUHAI TECH CO
- Filing Date
- 2022-02-23
- Publication Date
- 2026-06-09
Smart Images
Figure CN116684021B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technology, specifically to communication equipment, communication systems, and data transmission methods. Background Technology
[0002] Data signal transmission between devices follows specific communication protocols. The signal transmitting device sends data according to the protocol, while the signal receiving device samples the transmitted data according to the protocol to receive the signal. During synchronous signal transmission, the transmitting and receiving devices synchronize using a clock signal.
[0003] Please refer to Figure 1 This is a schematic diagram of signal transmission between master and slave devices in the standard I2S protocol.
[0004] The I2S master device sends the sampling clock BCLK and the left and right channel clocks LRCLK to the I2S slave device to synchronize their clocks. The left and right channel clock LRCLK is used to switch between left and right channel data, while the clock BCLK is used to control the transmission and sampling of data DATA.
[0005] Please refer to Figure 2 This is a timing diagram for data transmission and sampling in the I2S protocol. The I2S protocol specifies that the transmitting device sends data DATA at the falling edge of the sampling clock BCLK, and the DATA level changes, toggling from high to low. The receiving device samples the data at the rising edge of the sampling clock BCLK. Alternatively, the transmitting device can be configured to send data at the rising edge of the sampling clock BCLK, and the receiving device at the falling edge.
[0006] When there is a large equivalent capacitance in the path between two or more communicating devices, the rising and falling edges of the clock and data signals will be slower. Alternatively, when there is a difference in the trace delay between the clock and data signals, the data signal level may not have stabilized when the rising edge of the clock signal (sampling time) arrives, leading to errors in the sampled data. Please refer to [reference needed]. Figure 3 When the timing of the data DATA relative to the sampling clock BCLK exceeds the range specified in the protocol, the receiving device will be unable to sample the data normally, resulting in communication errors.
[0007] How to avoid the above situations and further improve communication reliability is an urgent problem to be solved. Summary of the Invention
[0008] In view of this, this application provides a communication device, a communication system, and a data transmission method to solve the problem that existing communication methods are prone to errors.
[0009] This application provides a communication device comprising: a data communication module, a detection module, and a control module; the data communication module is used to send and / or receive data signals; the detection module is connected to the control module and is used to detect the pulse edge of a first clock signal and output a corresponding enable signal to the control module, the first clock signal having a first frequency, and the enable signal enabling the control module when a receiving edge is detected; the control module is connected to the data communication module and is used to detect the edge of a second clock signal after being enabled by the enable signal, the second clock signal having a second frequency greater than the first frequency; the control module is used to control the data communication module to send a data signal at the y-th specified edge of the second clock signal, or to control the data communication module to receive a data signal at the x-th specified edge of the second clock signal; wherein x and y are both integers greater than or equal to 0, and both are less than 1 / 2 of the ratio of the second frequency to the first frequency.
[0010] Optionally, the detection module includes: a trigger unit, a delay unit, and a processing unit; the clock terminal of the trigger unit is used to receive the second clock signal, the input terminal of the trigger unit is used to input the first clock signal, and the trigger unit is used to latch the current level of the first clock signal and output it at the trigger edge of the second clock signal; the delay unit is connected to the output terminal of the trigger unit and is used to delay the output signal of the trigger unit at the trigger edge of the second clock signal, with the delay time being the period of the second clock signal; the processing unit is connected to the output terminal of the delay unit and the output terminal of the trigger unit, and is used to invert one of the current level of the first clock signal output by the trigger unit and the delayed level of the previous period output by the delay unit, and then perform an AND operation with the other level.
[0011] Optionally, the delay unit includes a register.
[0012] Optionally, the arithmetic unit includes a NOT gate and an AND gate, with one input of the AND gate and the input of the NOT gate respectively connected to the output of the trigger unit and the output of the delay unit, and the output of the NOT gate connected to the other input of the AND gate.
[0013] Optionally, the control module includes a counter, the enable terminal of which is connected to the detection module, the input terminal of which is used to input the second clock signal, and the counter is used to count a specified edge of the second clock signal after receiving the enable signal output by the detection module, and output the count value.
[0014] Optionally, the control module further includes a register and a comparator. The register is used to store the values of y and / or x. The comparator is connected to the register and the output of the counter, and is used to compare the count value output by the counter with the values of y and / or x. When the count value reaches the value of y or x, the corresponding data is output to send a control signal or to receive a control signal.
[0015] Optionally, the ratio of the second frequency to the first frequency is greater than or equal to 2.
[0016] This application also provides a data transmission method, comprising: after detecting the receiving edge of a pulse of a first clock signal, detecting a specified edge of a second clock signal, wherein the second clock has a second frequency, the first clock has a first frequency, and the second frequency is greater than the first frequency; transmitting data at the y-th specified edge of the second clock signal, wherein y is an integer greater than or equal to 0, and the y is less than 1 / 2 of the ratio of the second frequency to the first frequency; or receiving data at the x-th specified edge of the second clock signal, wherein x is an integer greater than or equal to 0, and the x is less than 1 / 2 of the ratio of the second frequency to the first frequency.
[0017] Optionally, the second frequency is greater than or equal to twice the first frequency.
[0018] Optionally, the method for detecting the receiving edge of the first clock signal includes: latching and outputting the current level of the first clock signal at the trigger edge of the second clock signal; delaying the current level of the first clock signal at the trigger edge of the second clock signal and then outputting it, with the delay time being the period of the second clock signal; inverting one of the levels of the first clock signal in the current period and the delayed level of the first clock signal in the previous period, and then performing an AND operation with the other level, using the result of the AND operation as the detection result.
[0019] This application also provides a communication system, including: a communication device as described in any of the preceding claims.
[0020] Optionally, when the communication device is used to send data, the communication system further includes: a data receiving device, signal-connected to the communication device, for receiving the data signal sent by the communication device at the receiving edge of the first clock signal.
[0021] Optionally, when the communication device is used to receive data, the communication system further includes: a data transmission device, signal-connected to the communication device, used to transmit a data signal to the communication device at the transmission edge of the first clock signal.
[0022] The communication device of the present invention controls the transmission and reception of data through two clock signals, including a second clock signal with a higher frequency and a first clock signal with a lower frequency. The first clock signal is the sampling clock for data reception. After the first clock signal generates the receiving edge corresponding to the data sampling reception, a specified number of edges of the second clock signal are calculated. Before the first clock signal flips, the data is sent early or received after the receiving edge of the first clock signal, thereby increasing the stabilization time of the transmitted data and improving the reliability of communication. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a schematic diagram of signal transmission between master and slave devices in the standard I2S protocol.
[0025] Figure 2 This is a timing diagram of data transmission and sampling for the standard I2S protocol;
[0026] Figure 3 This is a timing diagram of the sampling clock and data signals when a standard I2S protocol communication error occurs;
[0027] Figure 4 This is a schematic diagram of the structure of a communication device according to an embodiment of this application;
[0028] Figure 5 This is a schematic diagram of the structure of a communication device according to another embodiment of this application;
[0029] Figure 6a This is a schematic diagram of the structure of the detection module of a communication device according to an embodiment of this application;
[0030] Figure 6b This is a schematic diagram of the structure of the detection module of a communication device according to an embodiment of this application;
[0031] Figure 7 This is a schematic diagram of the structure of the control module of a communication device according to an embodiment of this application;
[0032] Figure 8 This is a schematic diagram of the structure of the control module of a communication device according to another embodiment of this application;
[0033] Figure 9 This is a schematic diagram of the structure of a communication device according to another embodiment of this application;
[0034] Figure 10 This is a schematic diagram of the structure of a communication device according to another embodiment of this application;
[0035] Figure 11 This is a schematic diagram of the structure of a communication device according to another embodiment of this application;
[0036] Figure 12 This is a schematic diagram of the structure of the control module of a communication device according to another embodiment of this application;
[0037] Figure 13 This is a schematic diagram of the structure of a communication device according to another embodiment of this application;
[0038] Figure 14 This is a schematic diagram of the structure of a communication device according to another embodiment of this application;
[0039] Figure 15 This is a signal timing diagram of a data transmission process according to an embodiment of this application;
[0040] Figure 16 This is a signal timing diagram of a data transmission process according to an embodiment of this application. Detailed Implementation
[0041] As described in the background section, communication errors are prone to occur in existing communication processes due to timing differences between clock and data signals. According to standard communication protocols, the interval between data transmission and sampling is half a clock cycle; therefore, the data must stabilize rapidly within half a cycle after the edge of the corresponding transmitted clock signal. However, in practical applications, various factors such as external traces and parasitic impedance often cause the data stabilization time to exceed half a clock cycle, leading to communication errors.
[0042] Based on the above technical analysis, this invention proposes a communication device, a communication system, and a data transmission method that can increase the stabilization time of transmitted data, so that the data is already stable when the receiving device performs data sampling, thereby improving the reliability of communication.
[0043] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.
[0044] The communication device of the present invention includes a detection module, a control module, and a data communication module. The communication device has data transmission and / or reception functions, and the corresponding communication module is used to transmit and / or receive data. The communication device may also simultaneously have data transmission and reception functions, and can be used as a data transmission device or a data reception device. During communication, the communication device can act as a master device or a slave device.
[0045] Please refer to Figure 4 This is a schematic diagram of a communication device according to an embodiment of the present invention. In this embodiment, the communication device is a data transmission device, and the data communication module includes a data transmission module.
[0046] The communication device includes a detection module 110, a control module 120, and a data transmission module 130.
[0047] The data transmission module 130 is used to transmit data signals.
[0048] The detection module 110, connected to the control module 120, is used to detect the pulse edge of the first clock signal BCLK and output a corresponding enable signal Pos_edge to the control module 120. The first clock signal BCLK has a first frequency f1. When a receive edge of the first clock signal BCLK is detected, the enable signal Pos_edge enables the control module 120. The clock signal is typically a rectangular pulse signal, with each pulse having a rising edge and a falling edge. The rising edge refers to the pulse edge that transitions from a low level to a high level, and the falling edge refers to the pulse edge that transitions from a high level to a low level. In the communication protocol, one edge of the first clock signal BCLK pulse is designated as the receive edge, used to control the data transmission operation; the other edge is designated as the transmit edge, used to control the data reception operation.
[0049] The control module 120, connected to the data transmission module 130, is used to detect the edge of the second clock signal MCLK after being enabled by the enable signal Pos_edge, and control the data transmission module 130 to transmit a data signal at the y-th specified edge of the second clock signal MCLK, where y is an integer greater than or equal to 0, the second clock signal MCLK has a second frequency f2, the second frequency f2 is greater than the first frequency f1, and y is less than 1 / 2 of the ratio of the second frequency to the first frequency, i.e., y ≤ f2 / 2f1. When y = 0, it means that after detecting the pulse edge of the first clock signal BCLK, the data transmission module 130 is immediately controlled to transmit the data signal without waiting for the generation of the specified edge of the second clock signal MCLK. The specified edge refers to one of the rising or falling edges of the pulse edge of the second clock signal MCLK; either the rising edge or the falling edge can be used as the specified edge, which can be set according to the circuit logic requirements.
[0050] The communication device transmits data at the y-th specified edge of the second clock signal MCLK, following the receive edge of the first clock signal BCLK. Since y is less than half the ratio of the second frequency f2 to the first frequency f1, at the y-th specified edge of the second clock signal MCLK, the other edge of the first clock signal BCLK pulse, i.e., the transmit edge, has not yet occurred, ensuring that the data transmission time is before the level of the first clock signal BCLK flips again. When the receiving device samples data at the next receive edge, the data settling time is greater than half a cycle of the first clock signal BCLK, improving the data settling time and thus reducing the probability of communication errors.
[0051] In some embodiments, the enable signal Pos_edge can be a digital signal with high and low levels. Typically, when the enable signal Pos_edge is high, the control module 120 is enabled; that is, when the receive edge of the first clock signal BCLK is detected, a high level of the enable signal Pos_edge is generated. In other embodiments, the control module 120 can also be enabled by a low level. The receive edge of the first clock signal BCLK can be a rising edge or a falling edge. The correspondence between the receive edge and the high / low level of the enable signal can be set as needed, and this receive edge also serves as the edge that triggers the receiving device to receive data.
[0052] Taking the I2S communication protocol as an example, the first clock signal BCLK can be a sampling clock signal, and the receiving device will sample data at the receiving edge of the first clock signal BCLK.
[0053] In other embodiments, the communication device may also support other communication protocols that support the same first clock signal BCLK as the sampling clock signal, such as the SPI protocol, the I2C protocol, etc.
[0054] Please refer to Figure 5 This is a schematic diagram of the structure of a communication device according to another embodiment of the present invention.
[0055] In this embodiment, the detection module 110 simultaneously receives the first clock signal BCLK and the second clock signal MCLK. Using the first clock signal BCLK as the input signal and the second clock signal MCLK as the sampling clock, the first clock signal BCLK is sampled to detect its edges. For example, if the sampled level changes from 0 to 1 between two consecutive samples, a rising edge is detected; if the sampled level changes from 1 to 0 between two consecutive samples, a falling edge is detected.
[0056] According to the sampling theorem, the frequency of the sampling clock needs to be greater than or equal to twice the frequency of the sampled clock. Therefore, in the embodiments of the present invention, in order to accurately detect the edge of the first clock signal BCLK, the second frequency f2 of the second clock signal MCLK is greater than or equal to twice the first frequency f1, that is, f2 ≥ 2f1.
[0057] When the first clock signal BCLK and the second clock signal MCLK are synchronous clock signals, MCLK and BCLK have the same phase, meaning that each rising / falling edge of BCLK corresponds to the rising or falling edge of MCLK. Therefore, MCLK does not need to sample and synchronize with BCLK to know the edge generation time of BCLK, so only f2 ≥ 2f1 is required to meet the requirement.
[0058] When the first clock signal BCLK and the second clock signal MCLK are asynchronous clock signals spanning clock domains, it is necessary to capture the first clock signal BCLK twice using the second clock signal MCLK for detection to reduce metastability in the digital circuit. In this case, f2 ≥ 4f1 is required.
[0059] Please refer to Figure 6a This is a schematic diagram of the detection module according to an embodiment of the present invention.
[0060] In this embodiment, the detection module 110 includes a triggering unit 111, a delay unit 112, and a calculation unit 113.
[0061] The clock terminal clk of the trigger unit 111 is used to receive the second clock signal MCLK, the input terminal in of the trigger unit 111 is used to input the first clock signal BCLK, and the trigger unit 111 is used to latch the current level BCLK_VAL of the first clock signal BCLK at the trigger edge of the second clock signal MCLK and output it.
[0062] The delay unit 112 is connected to the output terminal out of the trigger unit 111, and is used to delay the output signal of the trigger unit 111 and output the delayed level BCLK_VAL at the trigger edge of the second clock signal MCLK. delay The delay time is the period of the second clock signal MCLK.
[0063] The arithmetic unit 113 is connected to the output terminal of the delay unit 112 and the output terminal out of the trigger unit 111, and is used to adjust the current level BCLK_VAL of the first clock signal BCLK output by the trigger unit and the delay level BCLK_VAL of the previous cycle output by the delay unit 112. delay Invert one of them and then AND it with the other: (-BCLK_VAL) delay )&BCLK_VAL or BCLK_VAL delay &(-BCLK_VAL).
[0064] In one specific embodiment, the trigger unit 111 can be a D flip-flop. The rising edge of the second clock signal MCLK is used to trigger the D flip-flop to output data. That is, when the rising edge of the second clock signal MCLK arrives, the output terminal of the trigger unit 111 outputs and maintains the current level of the first clock signal BCLK. In other embodiments, the falling edge of the second clock signal MCLK can also be used to trigger the flip-flop to output data by adding logic devices or using other flip-flop structures.
[0065] The delay unit 112 can be a register, controlled by the second clock signal MCLK. It receives the current level BCLK_VAL output by the trigger unit 111 at the first rising edge of the second clock signal MCLK, and outputs this level value at the next rising edge of the second clock signal MCLK. The input and output are delayed by one cycle of the second clock signal MCLK. Therefore, when the trigger unit 111 outputs the current level BCLK_VAL, the delay unit outputs the delayed level BCLK_VAL simultaneously. delay Delay level BCLK_VAL delay This corresponds to the level of BCLK at the rising edge of the second clock signal MCLK in the previous cycle.
[0066] The arithmetic unit 113 includes a NOT gate INV and an AND gate &. In this embodiment, one input of the AND gate & is connected to the output of the trigger unit 111, the input of the NOT gate INV is connected to the output of the delay unit 112, and the output of the NOT gate INV is connected to the other input of the AND gate &. The delay level BCLK_VAL output by the delay unit 112 is... delay After being inverted by the NOT gate INV, it becomes (-BCLK_VAL). delay The current level BCLK_VAL output by trigger unit 111 is ANDed with the current level BCLK_VAL to output the enable signal Pos_edge.
[0067] Pos_edge = (-BCLK_VAL) delay )&BCLK_VAL.
[0068] The current rising edge of MCLK samples a value of 0, and the next sample samples a value of 1. At this point, BCLK_VAL... delay =0, BCLK_VAL=1, the BCLK level changes from 0 to 1, corresponding to the rising edge of BCLK, at which time Pos_edge=1. In this application, logic 0 represents a low level and logic 1 represents a high level. In other cases, Pos_edge=(-BCLK_VAL) delay &BCLK_VAL = 0. In this embodiment, the rising edge of the first clock signal BCLK is used as the receiving edge. When the rising edge is detected, the calculation result Pos_edge = 1, and the control enable signal Pos_edge controls the control module 120 to be enabled.
[0069] In other embodiments, please refer to Figure 6b Alternatively, the NOT gate INV can be connected to the output of the trigger unit 111, and the output of the delay unit 112 can be directly connected to the AND gate &. In this case, the enable signal Pos_edge = BCLK_VAL. delay &(-BCLK_VAL). The value sampled at the rising edge of the current MCLK is 1, and the next sampled value is 0; at this point, BCLK_VAL... delay =1, BCLK_VAL=0, the BCLK level changes from 1 to 0, corresponding to the falling edge of BCLK. At this time, Pos_edge=1, enabling the control module 120. In this embodiment, the falling edge of the first clock signal BCLK is used as the receiving edge.
[0070] In other embodiments, the NOT gate INV can also be set at the input terminal in of the trigger unit 111 to invert the first clock signal BCLK before detection, which can also realize the detection of the falling edge of BCLK.
[0071] Please refer to Figure 7 This is a schematic diagram of the structure of the control module 120 according to an embodiment of the present invention.
[0072] In this embodiment, the control module 120 has an enable terminal EN for receiving the enable signal Pos_edge output by the detection module 110, an input terminal IN for inputting the second clock signal MCLK, a value input terminal THRES for inputting the value of y, and an output terminal out for outputting data to send a control signal when the specified edge of the y-th MCLK is detected.
[0073] Please refer to Figure 8 The diagram below shows the internal structure of the control module 120 in one embodiment.
[0074] The control module 120 includes a counter 121. The enable terminal EN of the counter 121 is connected to the detection module 110. The input terminal IN of the counter 121 serves as the input terminal of the control module 120, used to input the second clock signal MCLK. The counter 121 is used to count the specified edge of the second clock signal MCLK when enabled by the enable signal Pos_edge output by the detection module 110, and outputs the count value.
[0075] The control module 120 further includes a register 122 and a comparator 123. The register 122 stores the value of y. The comparator 123 is connected to the register 122 and the output of the counter 121, and is used to compare the count value output by the counter 121 with the value of y. When the count value reaches the value of y, the comparator 123 sends a data transmission control signal to the data transmission module 130. The data transmission control signal corresponds to a high level of the output signal of the control module 120.
[0076] After receiving the data transmission control signal, the data transmission module 130 transmits a data signal.
[0077] Please refer to Figure 9 The diagram below illustrates the structure of a communication device according to another embodiment of the present invention. In this embodiment, the communication device further includes a data receiving module 140. The communication device can be used to receive data and send data, or it can operate in full-duplex mode, simultaneously receiving and sending data.
[0078] The data receiving module 140 is used to receive the data signal transmitted by the external transmitting end at the receiving edge of the first clock signal BCLK. The transmitting edge and receiving edge of the first clock signal BCLK are the pulse edges of a single pulse in two different directions.
[0079] Please refer to Figure 10 and Figure 11 The diagram below shows the structure of a communication device according to two other embodiments of the present invention. Figure 10 and Figure 11 The communication device is a data receiving device, and the data communication module includes a data receiving module 230.
[0080] The communication device includes a detection module 110, a control module 220, and a data receiving module 230. Unlike the previous embodiment, besides the data communication module being the data receiving module 230, the control module 220, after being enabled by the enable signal Pos_edge, detects the edge of the second clock signal MCLK, and controls the data receiving module 230 to receive a data signal at the x-th specified edge of the second clock signal MCLK, where x is an integer greater than or equal to 0, and x is less than 1 / 2 of the ratio of the second frequency to the first frequency, i.e., y ≤ f2 / 2f1.
[0081] The communication device receives data at the x-th specified edge of the second clock signal MCLK, following the receive edge of the first clock signal BCLK. Since x is less than half the ratio of the second frequency f2 to the first frequency f1, at the x-th specified edge of the second clock signal MCLK, the other edge (i.e., the transmit edge) of the first clock signal BCLK pulse has not yet occurred, ensuring that the data reception time is before the level of the first clock signal BCLK flips again. The external transmitting device transmits data at the transmit edge of the first clock signal BCLK. In this embodiment, the communication device receives data at the x-th specified edge of the second clock signal MCLK, following the receive edge of the first clock signal BCLK. This makes the settling time of the data transmitted by the transmitting end greater than half a cycle of the first clock signal BCLK, improving the data settling time and reducing the probability of communication errors. Preferably, x is greater than or equal to 1, ensuring that the data reception time is delayed after the transmit edge of the first clock signal BCLK, thereby improving the data settling time. In some embodiments, x can also be equal to 0, meaning that data reception begins immediately after the receive edge of the first clock signal BCLK is detected.
[0082] Please refer to Figure 12 This is a schematic diagram of one implementation structure of the control module 220 when the communication device is used as a data transmission device.
[0083] In this embodiment, the control module 220 has an enable terminal EN for receiving the enable signal Pos_edge output by the detection module 110, an input terminal IN for inputting the second clock signal MCLK, a value input terminal THRES for inputting the value of x, and an output terminal out for outputting a data receiving control signal when the specified edge of the xth MCLK is detected.
[0084] The internal structure diagram of the control module 220 can be adopted. Figure 8 The structure shown has a register for storing data x. The comparator compares the count value output by the counter with the value of x. When the count value reaches the value of x, a data receiving control signal is sent to the data sending module 230.
[0085] Please refer to Figure 13 The diagram below illustrates the structure of a communication device according to another embodiment of the present invention. In this embodiment, the communication device further includes a data transmission module 240. The communication device can be used to receive data and send data, or it can operate in full-duplex mode, simultaneously receiving and sending data.
[0086] The data transmission module 240 is used to transmit a data signal at the transmission edge of the first clock signal BCLK.
[0087] Please refer to Figure 14 This is a schematic diagram of the structure of a communication device according to another embodiment of the present invention.
[0088] In this embodiment, the data communication module of the communication device includes a data sending module 130 and a data receiving module 230, as well as corresponding control modules 120 and 220.
[0089] After being enabled by Pos_edge, the control module 120 outputs a data transmission control signal CTR1 to the data transmission module 130 at the y-th specified edge of the second clock signal MCLK, thereby controlling the data transmission module 130 to transmit data.
[0090] After being enabled by Pos_edge, the control module 220 outputs a data receiving control signal CTR2 to the data sending module 230 at the x-th specified edge of the second clock signal MCLK, thereby controlling the data receiving module 230 to receive data signals and perform sampling.
[0091] Depending on the situation, one of the transmission or reception paths can be selected to work, or both paths can work simultaneously, corresponding to the receiving device, the transmitting device, or both data receiving and transmitting devices respectively. This communication device can improve the reliability of the communication process in all situations.
[0092] An embodiment of the present invention also provides a data transmission method, comprising: detecting a specified edge of a second clock signal MCLK after detecting a receiving edge of a pulse of a first clock signal BCLK; transmitting data at the y-th specified edge of the second clock signal; or receiving data at the x-th specified edge; wherein y is an integer greater than or equal to 0, and x is an integer greater than or equal to 0; the first clock signal BCLK has a first frequency f1, the second clock signal has a second frequency f2, f1 > f2, and x and y are both less than f2 / 2f1.
[0093] In some embodiments, when the first clock signal BCLK and the second clock signal MCLK are synchronous clock signals, f2 ≥ 2f1; when the first clock signal BCLK and the second clock signal MCLK are asynchronous clock signals spanning clock domains, it is necessary to use the second clock signal MCLK to capture the first clock signal BCLK twice for detection to reduce metastability in the digital circuit. In this case, f2 ≥ 4f1 is required.
[0094] In some embodiments, the method for detecting the reception edge of the first clock signal includes: latching and outputting the current level BCLK_VAL of the first clock signal BCLK at the trigger edge of the second clock signal MCLK; and delaying the current level of the first clock signal BCLK and outputting the delayed level BCLK_VAL at the trigger edge of the second clock signal MCLK. delay The delay time is the period of the second clock signal MCLK; the current level BCLK_VAL of the first clock signal BCLK within the current period and the delayed level BCLK_VAL of the previous period after the delay. delay Invert one level and then AND it with the other level: (-BCLK_VAL) delay )&BCLK_VAL or BCLK_VAL delay &(-BCLK_VAL), the result of the AND operation is used as the detection result.
[0095] When the receiving edge of the first clock signal is a rising edge, the operation (-BCLK_VAL) is performed. delay When the first clock signal is received, the result of the operation is 1 only if a rising edge occurs; when the receiving edge of the first clock signal is a falling edge, the operation of BCLK_VAL is performed. delay The operation &(-BCLK_VAL) returns 1 only when a rising edge occurs. Therefore, the result can be used to determine whether a receiving edge has occurred on the first clock signal.
[0096] The above communication method can be implemented using the communication device in the foregoing embodiments, and the relevant features can be referenced in each other, which will not be repeated here.
[0097] Embodiments of the present invention also provide a communication system, including: the communication device described in any of the above embodiments.
[0098] In some embodiments, when the communication device in the communication system acts as a transmitter for transmitting data, the communication system may further include a data receiving device at the other end. The data receiving device is signal-connected to the communication device and is used to receive the data signal transmitted by the communication device at the receiving edge of the first clock signal.
[0099] When the communication device used for data transmission acts as the master device, it synchronously sends a first clock signal BCLK to the data receiving device. When the data receiving device acts as the master device, the communication device receives the first clock signal BCLK sent by the data receiving device.
[0100] In some embodiments, the communication device also includes a data receiving module, which has data sending and receiving functions. The communication system may employ two communication devices as described in the above embodiments, one as a sending device and the other as a receiving device.
[0101] In some embodiments, when the communication device in the communication system acts as a receiving end to receive data, the communication system may further include a data transmitting device at the other end, the data transmitting device being signal-connected to the communication device and used to transmit a data signal to the communication device at the transmission edge of the first clock signal.
[0102] The aforementioned communication system includes the communication device described in the above embodiments. This communication device can send data signals in advance or delay receiving data signals, improving data stabilization time and thus avoiding data reception sampling errors. During communication, no adjustments are needed to the data receiving or sending device on the other side; it can be adapted to data receiving or sending devices that communicate according to standard protocols.
[0103] Embodiments of the present invention also provide a data transmission method, comprising: transmitting and / or receiving data signals using the data transmission method described in the above embodiments. The above data transmission method improves communication reliability by changing the data transmission and / or reception method.
[0104] Please refer to Figure 15 This is a signal timing diagram of a data transmission process according to an embodiment of the present invention.
[0105] Figure 15In this context, DATA_a indicates that the parasitic parameters of the I2S connection line in a certain product are large, causing the data DATA level to flip more slowly relative to the rising edge of the first clock signal BCLK. According to the protocol, data is sampled on the rising edge of the first clock signal BCLK and transmitted on the falling edge. However, this results in data instability and errors in the sampled data when sampling occurs on the rising edge.
[0106] DATA_b is the data transmitted using the data transmission method of this invention: after adding a second clock signal MCLK with a higher frequency than the first clock signal BCLK, the rising edge of the first clock signal BCLK is detected in the first and second cycles of the second clock signal MCLK. Specifically, the rising edges of MCLKs numbered 1 and 2 are used to detect the rising edge of BCLK. In this embodiment, the transmission method is improved by setting the frequency of the second clock signal MCLK to 10 times that of the first clock signal BCLK, configuring y=2. That is, the transmitting end sends new data at the second rising edge of MCLK after the rising edge of the first clock signal BCLK (corresponding to the rising edge of MCLK number 4). Therefore, DATA_b is transmitted at the rising edge of MCLK number 4.
[0107] Comparing DATA_a and DATA_b, we can see that the data in DATA_b is sent △t1 time earlier, giving it (△t1+T1 / 2) time to stabilize the data. T1 is the period of the first clock signal BCLK, so the data can be stably sampled when the rising edge of BCLK arrives (see bold dashed line).
[0108] Alternatively, you can set y = 1 (see reference). Figure 15 In the second BCLK cycle shown, data is sent after the first MCLK rising edge (i.e., the rising edge of MCLK in sequence 9) is detected within the rising edge cycle of MCLK in sequence 7 and 8. At this time, we can see that the data has a longer settling time △t2.
[0109] In other embodiments, y can be set to 0, or y = 3, or other values less than or equal to f2 / 2f1. During communication, y can be configured to different values, and its value can be adjusted at any time during communication based on changes in external parasitic impedance and the required settling time of the data. Since the MCLK frequency is much higher than the BCLK frequency, the transmitted data DATA can be ensured to quickly flip to the next new value after being sampled, thereby greatly increasing the settling time.
[0110] Please refer to Figure 16 This is a signal timing diagram of a data transmission process according to an embodiment of the present invention.
[0111] DATA refers to the data transmitted using the data transmission method of this invention. This method improves the data reception process by detecting the rising edge of the first clock signal BCLK within the period of the rising edges of the second clock signal MCLK (numbers 7 and 8). The frequency of the second clock signal MCLK is configured to be 10 times that of the first clock signal BCLK, and x is configured to be 1. That is, after detecting and determining the rising edge of the first clock signal BCLK, the transmitting end delays receiving data until the next rising edge of MCLK (corresponding to the rising edge of MCLK number 9), increasing the data settling time by Δt3. Thus, by delaying data reception, the data settling time is improved, thereby enhancing the reliability of communication.
[0112] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A communication device, characterized in that, include: Data communication module, detection module, and control module; The data communication module is used to send and / or receive data signals; The detection module is connected to the control module and is used to detect the pulse edge of the first clock signal and output a corresponding enable signal to the control module. The first clock signal has a first frequency. When a receiving edge is detected, the enable signal is used to enable the control module. The control module is connected to the data communication module. After being enabled by the enable signal, the control module detects the edge of a second clock signal, the second clock signal having a second frequency greater than the first frequency. The control module controls the data communication module to send a data signal at the y-th specified edge of the second clock signal, or controls the data communication module to receive a data signal at the x-th specified edge of the second clock signal; wherein x and y are both integers greater than or equal to 0, and both are less than 1 / 2 of the ratio of the second frequency to the first frequency.
2. The communication device according to claim 1, characterized in that, The detection module includes: a triggering unit, a delay unit, and a processing unit; The clock terminal of the trigger unit is used to receive the second clock signal, the input terminal of the trigger unit is used to input the first clock signal, and the trigger unit is used to latch the current level of the first clock signal and output it at the trigger edge of the second clock signal. The delay unit is connected to the output terminal of the trigger unit and is used to delay the output signal of the trigger unit at the trigger edge of the second clock signal, and the delay time is the period of the second clock signal. The arithmetic unit is connected to the output of the delay unit and the output of the trigger unit, and is used to invert one of the current level of the first clock signal output by the trigger unit and the delay level of the previous cycle output by the delay unit, and then perform an AND operation with the other level.
3. The communication device according to claim 2, characterized in that, The delay unit includes a register.
4. The communication device according to claim 2, characterized in that, The arithmetic unit includes a NOT gate and an AND gate. One input of the AND gate and the input of the NOT gate are respectively connected to the output of the trigger unit and the output of the delay unit. The output of the NOT gate is connected to the other input of the AND gate.
5. The communication device according to claim 1, characterized in that, The control module includes a counter, the enable terminal of which is connected to the detection module, and the input terminal of which is used to input the second clock signal. After receiving the enable signal output by the detection module, the counter counts a specified edge of the second clock signal and outputs a count value.
6. The communication device according to claim 5, characterized in that, The control module further includes a register and a comparator. The register is used to store the values of y and / or x. The comparator is connected to the register and the output of the counter. It is used to compare the count value output by the counter with the values of y and / or x. When the count value reaches the value of y or x, the corresponding data is output to send a control signal or to receive a control signal.
7. The communication device according to claim 1, characterized in that, The ratio of the second frequency to the first frequency is greater than or equal to 2.
8. A data transmission method, characterized in that, include: After detecting the receiving edge of the pulse of the first clock signal, a specified edge of the second clock signal is detected. The second clock has a second frequency, the first clock has a first frequency, and the second frequency is greater than the first frequency. Data is transmitted at the y-th specified edge of the second clock signal, where y is an integer greater than or equal to 0, and y is less than 1 / 2 of the ratio of the second frequency to the first frequency; or, Data is received at the x-th specified edge of the second clock signal, where x is an integer greater than or equal to 0, and x is less than 1 / 2 of the ratio of the second frequency to the first frequency.
9. The data transmission method according to claim 8, characterized in that, The second frequency is greater than or equal to twice the first frequency.
10. The data transmission method according to claim 8, characterized in that, The method for detecting the receiving edge of the first clock signal includes: latching and outputting the current level of the first clock signal at the trigger edge of the second clock signal; delaying the current level of the first clock signal at the trigger edge of the second clock signal and outputting it, with the delay time being the period of the second clock signal; inverting one of the levels of the first clock signal in the current period and the delayed level of the first clock signal in the previous period, and then performing an AND operation with the other level, using the result of the AND operation as the detection result.
11. A communication system, characterized in that, include: The communication device as described in any one of claims 1 to 7.
12. The communication system according to claim 11, characterized in that, When the communication device is used to send data, the communication system further includes: a data receiving device, which is signal-connected to the communication device, for receiving the data signal sent by the communication device at the receiving edge of the first clock signal.
13. The communication system according to claim 11, characterized in that, When the communication device is used to receive data, the communication system further includes: a data transmission device, which is signal-connected to the communication device and is used to transmit a data signal to the communication device at the transmission edge of the first clock signal.