A method of manufacturing a semiconductor device, a semiconductor device, and a stacked device
By constructing multiple conductive and dielectric layers in a semiconductor device, the capacitor extends in two directions, solving the problems of small capacitor surface area and low storage density, achieving greater charge storage capacity and higher storage density, and simplifying the manufacturing process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-02-21
- Publication Date
- 2026-06-26
AI Technical Summary
In existing semiconductor devices, capacitors have small surface areas, low charge storage capacity, and relatively low capacitance per unit volume, resulting in low storage density.
By forming an isolation layer and a sacrificial layer on a substrate, etching multiple trenches extending in different directions, and constructing multiple conductive and dielectric layers within them, a capacitor structure is formed, allowing the capacitor to extend in two directions, increasing the surface area and reducing the depth.
This increases the charge storage capacity of capacitors and the storage density of semiconductor devices, while simplifying the manufacturing process and avoiding the need for additional support structures.
Smart Images
Figure CN116685140B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a method for manufacturing a semiconductor device, a semiconductor device, and a stacked device. Background Technology
[0002] Semiconductor devices, such as dynamic random access memory (DRAM), typically include a substrate, transistors located within the substrate, and capacitors located on the substrate, the capacitors being used to store charge, the transistors and the capacitors constituting a memory cell.
[0003] However, in related technologies, the capacitor typically extends in a fixed direction, has a small surface area, resulting in a low charge storage capacity; furthermore, the capacitor often has a large depth, which means that less capacitance can be accommodated per unit volume, leading to a low storage density of the semiconductor device. Summary of the Invention
[0004] This disclosure provides a method for manufacturing a semiconductor device, including:
[0005] Provide substrate;
[0006] A common lower electrode plate is formed on the substrate;
[0007] An isolation layer and a plurality of sacrificial layers extending in a first direction, defined by the isolation layer, are formed on the common lower electrode plate, and the plurality of sacrificial layers are arranged and distributed in a second direction;
[0008] Multiple first conductive layers extending along the first direction are formed on the multiple sacrificial layers;
[0009] A first insulating layer is formed on the first conductive layer, the sacrificial layer, and the isolation layer;
[0010] The first insulating layer is etched to form a first trench extending along the second direction, the first trench exposing a plurality of the sacrificial layers;
[0011] Multiple sacrificial layers are removed through the first trench to form multiple hole structures communicating with the first trench;
[0012] A first dielectric layer is formed within the plurality of said porous structures, and a second dielectric layer is formed within the first trench;
[0013] The first insulating layer is etched to form a plurality of second trenches exposing the first dielectric layer and a plurality of third trenches exposing the common lower electrode plate, the second trenches and the third trenches being disposed on both sides of the second dielectric layer;
[0014] A second conductive layer and a third conductive layer are formed in the second trench and the third trench, respectively.
[0015] In some embodiments, removing a plurality of the sacrificial layers through the first trench includes: introducing an etchant into the first trench, the etchant removing the plurality of the sacrificial layers; wherein the etching rate of the sacrificial layers is greater than the etching rate of the isolation layers.
[0016] In some embodiments, after forming the first insulating layer, the method further includes:
[0017] A plurality of trench layers extending along the first direction and a buried layer located between the plurality of trench layers are formed on the first insulating layer, the plurality of trench layers being arranged along the second direction.
[0018] In some embodiments, the trench layer and the burial layer are formed before the first trench is formed, and the first trench, the second trench, and the third trench all penetrate the trench layer; the method further includes:
[0019] A first separating layer is formed within the trench layer and the burial layer, extending in the second direction and cutting off the trench layer. The first separating layer and the first trench divide the trench layer into discrete active regions.
[0020] In some embodiments, the trench layer and the buried layer are formed after the second conductive layer and the third conductive layer are formed, the trench layer and the buried layer covering the first insulating layer, the second conductive layer, the third conductive layer and the second dielectric layer, and the trench layer is in contact with the second conductive layer and the third conductive layer; the method further includes:
[0021] A first partition layer and a second partition layer are formed within the trench layer and the buried layer, extending along the second direction and cutting through the plurality of trench layers. The first partition layer and the second partition layer divide the trench layer into discrete active regions. The second partition layer covers the second dielectric layer.
[0022] In some embodiments, the method further includes:
[0023] A third dielectric layer is formed on the trench layer and the buried layer, and a word line material layer is formed on the third dielectric layer;
[0024] The word line material layer is etched to form a word line layer extending along the second direction;
[0025] A fourth dielectric layer is formed on the substrate, the fourth dielectric layer covering the third dielectric layer and the word line layer.
[0026] In some embodiments, the method further includes:
[0027] A second insulating layer is formed on the fourth dielectric layer;
[0028] The second insulating layer, the fourth dielectric layer, and the third dielectric layer are etched to expose the channel layer, forming a plurality of bit line contact holes arranged along the second direction;
[0029] A bit line contact plug is formed inside the bit line contact hole;
[0030] Multiple bit line layers extending along the first direction are formed on the bit line contact plug and the second insulating layer, and the multiple bit line layers are arranged along the second direction.
[0031] This disclosure also provides a semiconductor device, including:
[0032] Substrate and a common lower electrode plate located on the substrate;
[0033] An isolation layer located on the common lower electrode plate and a plurality of first dielectric layers extending in a first direction defined by the isolation layer, wherein the plurality of first dielectric layers are arranged and distributed in a second direction;
[0034] Multiple first conductive layers are respectively located on multiple first dielectric layers and extend along the first direction;
[0035] A first insulating layer covers the first conductive layer, the first dielectric layer, and the isolation layer; the first insulating layer has a first trench extending along the second direction, and a plurality of second trenches and a plurality of third trenches disposed on both sides of the first trench; wherein the second trenches expose the first dielectric layer, and the third trenches expose the common lower electrode plate;
[0036] The second dielectric layer, the second conductive layer, and the third conductive layer are located in the first trench, the second trench, and the third trench, respectively.
[0037] In some embodiments, in the first direction, the two ends of the first conductive layer are recessed inward relative to the two ends of the first dielectric layer; in the second direction, the two ends of the first conductive layer protrude outward relative to the two ends of the first dielectric layer.
[0038] In some embodiments, the semiconductor device further includes: a plurality of channel layers extending along the first direction on the first insulating layer and a buried layer between the plurality of channel layers, the plurality of channel layers being arranged along the second direction.
[0039] In some embodiments, the first trench, the second trench, and the third trench all penetrate the channel layer; the semiconductor device further includes: a first separator layer extending along the second direction, the first separator layer being located within the channel layer and the buried layer and cutting off the plurality of channel layers, the first separator layer and the first trench separating the channel layer into discrete active regions.
[0040] In some embodiments, the channel layer is located above the second conductive layer, the third conductive layer, and the second dielectric layer, and the channel layer is in contact with the second conductive layer and the third conductive layer; the semiconductor device further includes: a first separator layer and a second separator layer extending along the second direction, the first separator layer and the second separator layer being located within the channel layer and the buried layer and cutting off multiple channel layers, the first separator layer and the second separator layer dividing the channel layer into multiple active regions; wherein, the second separator layer covers the second dielectric layer.
[0041] In some embodiments, the semiconductor device further includes: a third dielectric layer covering the channel layer and the buried layer; a word line layer extending along the second direction, the word line layer being located on the third dielectric layer; and a fourth dielectric layer covering the third dielectric layer and the word line layer.
[0042] In some embodiments, the semiconductor device further includes: a second insulating layer covering the fourth dielectric layer; a plurality of bit line layers extending along the first direction, located on the second insulating layer and arranged along the second direction; and bit line contact plugs connected to the bit line layers and the channel layer.
[0043] This disclosure also provides a stacked device, including:
[0044] Substrate and multiple storage structures stacked on the substrate;
[0045] The storage structure includes:
[0046] Shared lower electrode plate;
[0047] An isolation layer located on the common lower electrode plate and a plurality of first dielectric layers extending in a first direction defined by the isolation layer, wherein the plurality of first dielectric layers are arranged and distributed in a second direction;
[0048] Multiple first conductive layers are respectively located on multiple first dielectric layers and extend along the first direction;
[0049] A first insulating layer covers the first conductive layer, the first dielectric layer, and the isolation layer; the first insulating layer has a first trench extending along the second direction, and a plurality of second trenches and a plurality of third trenches disposed on both sides of the first trench; wherein the second trenches expose the first conductive layer, and the third trenches expose the common lower electrode plate;
[0050] The second dielectric layer, the second conductive layer, and the third conductive layer are located in the first trench, the second trench, and the third trench, respectively.
[0051] This disclosure provides a method for manufacturing a semiconductor device, a semiconductor device, and a stacked device. The manufacturing method includes: providing a substrate; forming a common lower electrode on the substrate; forming an isolation layer and a plurality of sacrificial layers extending along a first direction defined by the isolation layer on the common lower electrode, the plurality of sacrificial layers being arranged along a second direction; forming a plurality of first conductive layers extending along the first direction on the plurality of sacrificial layers; forming a first insulating layer on the first conductive layer, the sacrificial layers, and the isolation layer; etching the first insulating layer to form a first trench extending along the second direction, the first trench exposing the plurality of sacrificial layers; removing the plurality of sacrificial layers through the first trench to form a plurality of hole structures communicating with the first trench; forming a first dielectric layer within the plurality of hole structures and a second dielectric layer within the first trench; etching the first insulating layer to form a plurality of second trenches exposing the first dielectric layers and a plurality of third trenches exposing the common lower electrode, the second trenches and the third trenches being disposed on opposite sides of the second dielectric layer; and forming a second conductive layer and a third conductive layer within the second trenches and the third trenches, respectively. The common lower electrode, first conductive layer, second conductive layer, third conductive layer, first dielectric layer, and second dielectric layer provided in this embodiment constitute a capacitor for storing charge. The first conductive layer extends in different directions than the second and third conductive layers; that is, the capacitor in this embodiment extends in two different directions. Compared with capacitors in related technologies that extend in only one direction, the capacitor provided in this embodiment has a larger surface area, thus enabling it to store a larger amount of charge. Simultaneously, compared with capacitors in related technologies, the capacitor in this embodiment can have a smaller depth, allowing the semiconductor device to accommodate more capacitance per unit volume, thereby increasing the storage density of the semiconductor device. Furthermore, this embodiment eliminates the need for a support structure to support the capacitor, simplifying the semiconductor device manufacturing process.
[0052] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the accompanying drawings and claims. Attached Figure Description
[0053] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0054] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;
[0055] Figures 2a to 18b A process flow diagram of a semiconductor device provided in the embodiments of this disclosure;
[0056] Figures 19a to 25b A process flow diagram of a semiconductor device provided for another embodiment of this disclosure;
[0057] Figure 26 This is a schematic diagram of a stacked device provided in an embodiment of this disclosure. Detailed Implementation
[0058] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0059] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.
[0060] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.
[0061] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.
[0062] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0063] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0064] Semiconductor devices, such as dynamic random access memory (DRAM), typically include a substrate, transistors located within the substrate, and capacitors located on the substrate, the capacitors being used to store charge, the transistors and the capacitors constituting a memory cell.
[0065] However, in related technologies, the capacitor typically extends in a fixed direction, has a small surface area, resulting in a low charge storage capacity; furthermore, the capacitor often has a large depth, which means that less capacitance can be accommodated per unit volume, leading to a low storage density of the semiconductor device.
[0066] Based on this, the following technical solutions are proposed for embodiments of this disclosure:
[0067] This disclosure provides a method for manufacturing a semiconductor device; please refer to the following for details. Figure 1 As shown in the figure, the method includes the following steps:
[0068] Step 101: Provide a substrate;
[0069] Step 102: Form a common lower electrode plate on the substrate;
[0070] Step 103: An isolation layer and a plurality of sacrificial layers extending in a first direction, defined by the isolation layer, are formed on the common lower electrode plate; the plurality of sacrificial layers are arranged and distributed in a second direction.
[0071] Step 104: Form a plurality of first conductive layers extending along the first direction on the plurality of sacrificial layers;
[0072] Step 105: Form a first insulating layer on the first conductive layer, the sacrificial layer, and the isolation layer;
[0073] Step 106: Etch the first insulating layer to form a first trench extending along the second direction, the first trench exposing a plurality of the sacrificial layers;
[0074] Step 107: Remove multiple sacrificial layers through the first trench to form multiple hole structures communicating with the first trench;
[0075] Step 108: Form a first dielectric layer within the plurality of said porous structures, and form a second dielectric layer within the first trench;
[0076] Step 109: Etch the first insulating layer to form a plurality of second trenches exposing the first dielectric layer and a plurality of third trenches exposing the common lower electrode plate, wherein the second trenches and the third trenches are disposed on both sides of the second dielectric layer;
[0077] Step 110: A second conductive layer and a third conductive layer are formed in the second trench and the third trench, respectively.
[0078] The common lower electrode, first conductive layer, second conductive layer, third conductive layer, first dielectric layer, and second dielectric layer provided in this embodiment constitute a capacitor for storing charge. The first conductive layer extends in different directions than the second and third conductive layers; that is, the capacitor in this embodiment extends in two different directions. Compared with capacitors in related technologies that extend in only one direction, the capacitor provided in this embodiment has a larger surface area, thereby enabling it to store a larger amount of charge. Simultaneously, the capacitor in this embodiment can have a smaller depth, allowing the semiconductor device to accommodate more capacitance per unit volume, thus increasing the storage density of the semiconductor device. Furthermore, this embodiment eliminates the need for a support structure to support the capacitor, simplifying the semiconductor device manufacturing process.
[0079] The manufacturing method provided in this disclosure can be used to manufacture dynamic random access memory (DRAM), but is not limited thereto. Any semiconductor device with capacitors can be manufactured using the method provided in this application.
[0080] The specific embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, the schematic diagrams may be partially enlarged without adhering to the usual proportions for ease of explanation, and the schematic diagrams are merely examples and should not be construed as limiting the scope of protection of this disclosure.
[0081] Figures 2a to 18b This is a process flow diagram of a semiconductor device provided in an embodiment of this disclosure. Figures 19a to 25b This is a process flow diagram of a semiconductor device provided in another embodiment of the present disclosure; wherein, Figure 2a , Figure 3a , Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Figure 10a , Figure 11a , Figure 12a , Figure 13a , Figure 14a , Figure 15a , Figure 16a , Figure 17a , Figure 18a This is a top view schematic diagram of different process steps in the manufacturing method of the semiconductor device provided in the embodiments of this disclosure. Figure 2b , Figure 3b , Figure 4b , Figure 5b , Figure 6b , Figure 7b , Figure 8b , Figure 9b , Figure 10b , Figure 11b , Figure 12b , Figure 13b , Figure 14b , Figure 15b , Figure 16b , Figure 17b , Figure 18b respectively along Figure 2a , Figure 3a , Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Figure 10a , Figure 11a , Figure 12a , Figure 13a , Figure 14a , Figure 15a , Figure 16a , Figure 17a , Figure 18a A schematic diagram of the cross-sectional structure taken by line AA'; Figure 19a , Figure 20a , Figure 21a , Figure 22a , Figure 23a , Figure 24a , Figure 25a This is a top view schematic diagram of a semiconductor device manufacturing method according to another embodiment of the present disclosure at different process steps. Figure 19b , Figure 20b , Figure 21b , Figure 22b , Figure 23b , Figure 24b , Figure 25b respectively along Figure 19a , Figure 20a , Figure 21a , Figure 22a , Figure 23a , Figure 24a , Figure 25a A schematic diagram of the cross-sectional structure taken by line AA'. The following is combined with... Figures 2a to 25b The method for manufacturing a semiconductor device provided in the embodiments of this disclosure will be described in further detail.
[0082] First, perform step 101, as follows: Figures 2a to 2b As shown, a substrate 20 is provided.
[0083] The substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.
[0084] Next, proceed to step 102, as follows: Figures 3a to 3b As shown, a common lower electrode plate 32 is formed on the substrate 20.
[0085] The material of the common lower electrode plate 32 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys, such as titanium nitride (TiN).
[0086] Refer again Figure 3b In one embodiment, before forming a common lower electrode 32 on the substrate 20, the method further includes forming an interlayer insulating layer 31 on the substrate 20, the interlayer insulating layer 31 being located below the common lower electrode 32 for electrically isolating the substrate 20 and the common lower electrode 32. The interlayer insulating layer 31 can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). Optionally, after forming the interlayer insulating layer 31, planarization processes, such as chemical mechanical polishing (CMP) and / or etching processes, can be used to make the upper surface of the interlayer insulating layer 31 flatter. The material of the interlayer insulating layer 31 can be an oxide, for example, silicon oxide.
[0087] Next, proceed to step 103, as follows: Figures 4a to 4b As shown, an isolation layer 33 and a plurality of sacrificial layers 34 extending along a first direction and defined by the isolation layer 33 are formed on the common lower electrode plate 32, and the plurality of sacrificial layers 34 are arranged and distributed along a second direction.
[0088] In one embodiment, the first direction and the second direction are parallel to the surface of the substrate 20. In some embodiments, the first direction is perpendicular to the second direction. However, it is not limited to this; the first direction may also be oblique to the second direction.
[0089] It should be noted that the number and arrangement of the multiple sacrificial layers 34 are not limited to... Figure 4aAs shown, the number of sacrificial layers 34 can be greater, and the multiple sacrificial layers 34 can be arranged in an array. In one embodiment, the multiple sacrificial layers 34 are arranged in an array along the first direction and the second direction, respectively.
[0090] like Figure 4b As shown, the lower surface of the sacrificial layer 34 is in contact with the common lower electrode 32, and the upper surface of the sacrificial layer 34 is flush with the upper surface of the isolation layer 33. The isolation layer 33 and the sacrificial layer 34 can be formed, for example, by: first, forming the isolation layer 33 on the common lower electrode 32; then, forming a plurality of openings (unmarked) on the isolation layer 33 that expose the common lower electrode 32 and extend along the first direction, with the plurality of openings (unmarked) arranged along the second direction; and finally, forming the sacrificial layer 34 within the openings (unmarked). The material of the isolation layer 33 is an insulating material. A subsequent etching process will remove the sacrificial layer 34 and retain the isolation layer 33. Therefore, under preset etching conditions, the etching rate of the sacrificial layer 34 should be much greater than the etching rate of the isolation layer 33, i.e., the sacrificial layer 34 and the isolation layer 33 have a large etching selectivity ratio, thereby enabling the removal of only the sacrificial layer 34 and the retention of the isolation layer 33 in subsequent processes. In one specific embodiment, the etching selectivity range is greater than 10, for example, between 20 and 100, the material of the sacrificial layer 34 is, for example, polysilicon, and the material of the isolation layer 33 is, for example, silicon nitride.
[0091] Next, proceed to step 104, as follows: Figures 5a to 5b As shown, a plurality of first conductive layers 35 extending along the first direction are formed on the plurality of sacrificial layers 34.
[0092] In some embodiments, in the first direction, the two ends of the first conductive layer 35 are recessed inward relative to the two ends of the sacrificial layer 34, thereby preventing the two ends of the first conductive layer 35 from contacting other conductive layers; in the second direction, the two ends of the first conductive layer 35 protrude outward relative to the two ends of the sacrificial layer 34, thereby giving the first conductive layer 35 a larger surface area and increasing the capacitance C formed in subsequent processes (see...). Figures 11a to 11b The surface area of the first conductive layer 35 can be increased, thereby improving the charge storage capacity of the capacitor C. The material of the first conductive layer 35 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys, such as titanium nitride (TiN). In one embodiment, the material of the first conductive layer 35 is the same as the material of the common lower electrode 32.
[0093] Next, proceed to step 105, as follows: Figures 6a to 6bAs shown, a first insulating layer 36 is formed on the first conductive layer 35, the sacrificial layer 34 and the isolation layer 33.
[0094] The first insulating layer 36 may be made of an oxide, such as silicon oxide. In one embodiment, the material of the first insulating layer 36 is the same as the material of the interlayer insulating layer 31.
[0095] Next, proceed to step 106, as follows: Figures 7a to 7b As shown, the first insulating layer 36 is etched to form a first trench T1 extending along the second direction, the first trench T1 exposing a plurality of the sacrificial layers 34.
[0096] In one embodiment, the first insulating layer 36 is etched from top to bottom in a direction perpendicular to the surface of the substrate 20 to form the first trench T1, the first trench T1 extending downward in a direction perpendicular to the surface of the substrate 20.
[0097] In one embodiment, during the formation of the first trench T1, after etching the first insulating layer 36, the etching process further includes etching a portion of the sacrificial layer 34 and / or a portion of the insulating layer 33 to expose the common lower electrode 32. The sidewalls of the first trench T1 expose a plurality of the sacrificial layers 34, and simultaneously expose the insulating layer 33 located between the plurality of sacrificial layers 34. In some embodiments, the sidewalls of the first trench T1 expose one of the two ends of the sacrificial layer 34 in the first direction.
[0098] Next, proceed to step 107, as follows: Figures 8a to 8b As shown, multiple sacrificial layers 34 are removed through the first trench T1 to form multiple hole structures S1 that communicate with the first trench T1.
[0099] In one embodiment, removing a plurality of sacrificial layers 34 through the first trench T1 includes: introducing an etching solution into the first trench T1, wherein the etching solution removes a plurality of sacrificial layers 34; wherein the etching rate of the sacrificial layers 34 is greater than the etching rate of the isolation layer 33, so that the isolation layer 33 is retained while the sacrificial layers 34 are removed to form a plurality of hole structures S1, the plurality of hole structures S1 extend along a first direction and are arranged along a second direction, and the plurality of hole structures S1 are separated from each other by the isolation layer 33.
[0100] Next, proceed to step 108, as follows: Figures 9a to 9b As shown, a first dielectric layer 41 is formed within the plurality of hole structures S1, and a second dielectric layer 42 is formed within the first trench T1.
[0101] Here, there are multiple first dielectric layers 41, which extend along the first direction and are arranged along the second direction; the second dielectric layer 42 extends along the second direction and is connected to the multiple first dielectric layers 41. The materials of the first dielectric layer 41 and the second dielectric layer 42 can be high dielectric constant materials, such as tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate. In a more specific embodiment, the materials of the first dielectric layer 41 and the second dielectric layer 42 are the same.
[0102] Next, proceed to step 109, as follows: Figures 10a to 10b As shown, the first insulating layer 36 is etched to form a plurality of second trenches T2 that expose the first dielectric layer 41 and a plurality of third trenches T3 that expose the common lower electrode plate 32, the second trenches T2 and the third trenches T3 being disposed on both sides of the second dielectric layer 42.
[0103] like Figure 10b As shown, the bottom of the second trench T2 exposes the first dielectric layer 41, and the sidewalls of the second trench T2 expose the first conductive layer 35; during the formation of the third trench T3, after etching the first insulating layer 36, the process also includes etching the isolation layer 33 to expose the common lower electrode 32.
[0104] In one embodiment, the plurality of second trenches T2 and the plurality of third trenches T3 are all perpendicular to the surface of the substrate 20 and are all arranged along the second direction. In some embodiments, the second trenches T2 and the third trenches T3 are symmetrically disposed on both sides of the second dielectric layer 42.
[0105] Next, proceed to step 110, as follows: Figures 11a to 11b As shown, a second conductive layer 43 and a third conductive layer 44 are formed in the second trench T2 and the third trench T3, respectively.
[0106] The number of the second conductive layer 43 and the number of the third conductive layer 44 are both multiple. The multiple second conductive layers 43 and the multiple third conductive layers 44 are respectively arranged on both sides of the second dielectric layer 42 along the second direction. The multiple second conductive layers 43 are connected to the multiple first conductive layers 35 in a one-to-one correspondence. The multiple third conductive layers 44 are connected to the common lower electrode plate 32.
[0107] This embodiment of the present disclosure forms the first dielectric layer 41 and the second dielectric layer 42 within the first trench T1, and then forms the second conductive layer 43 connected to the first conductive layer 35 and the third conductive layer 44 connected to the common lower electrode 32 on both sides of the second dielectric layer 42, instead of forming the second conductive layer 43 within the first trench T1 first. This avoids the second conductive layer 43 being simultaneously connected to both the first conductive layer 35 and the common lower electrode 32 when the common lower electrode 32 is exposed at the bottom of the first trench T1, thus preventing short circuits. The common lower electrode 32, multiple first conductive layers 35, multiple second conductive layers 43, multiple third conductive layers 44, multiple first dielectric layers 41, and multiple second dielectric layers 42 constitute multiple capacitors C for storing charge, and the multiple capacitors C are arranged along a second direction. The first conductive layer 35 extends in different directions from the second conductive layer 43 and the third conductive layer 44. That is, the capacitor C in this embodiment extends in two different directions. Compared to capacitors in related technologies that extend in only one direction, the capacitor C provided in this embodiment has a larger surface area, thus allowing for greater charge storage. Simultaneously, compared to capacitors in related technologies, the capacitor C in this embodiment can have a smaller depth, enabling the semiconductor device to accommodate more capacitors C per unit volume, thereby increasing the storage density of the semiconductor device. Furthermore, the capacitor C provided in this embodiment is buried by the first insulating layer 36, making the structure of the capacitor C more robust. No additional support structure is needed for the capacitor C, and multiple capacitors C share the same common lower electrode 32, simplifying the manufacturing process of the semiconductor device.
[0108] It should be noted that the number and arrangement of the capacitors C are not limited to... Figure 11a As shown, the number of capacitors C can be greater, and multiple capacitors C can be arranged in an array. In one embodiment, multiple capacitors C are arranged in an array along the first direction and the second direction, respectively. In some embodiments, in the first direction, the two ends of the first conductive layer 35 are recessed inward relative to the two ends of the first dielectric layer 41, thereby preventing the first conductive layer 35 of one of two adjacent capacitors C in the first direction from being connected to the third conductive layer 44 of the other, thereby reducing leakage current.
[0109] The materials of the second conductive layer 43 and the third conductive layer 44 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys. In one embodiment, the materials of the second conductive layer 43 and the third conductive layer 44 are the same as the material of the common lower electrode 32, for example, titanium nitride (TiN).
[0110] In one embodiment, after forming the first insulating layer 36, the method further includes: forming a plurality of trench layers 37 extending along a first direction and a buried layer 38 located between the plurality of trench layers 37 on the first insulating layer 36, the plurality of trench layers 37 being arranged along a second direction, such as... Figures 12a to 12b As shown.
[0111] In one embodiment, the channel layer 37 is made of one or more of silicon, germanium, silicon-germanium, indium oxide, tin oxide, indium zinc oxide, tin zinc oxide, aluminum zinc oxide, indium gallium oxide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, tin gallium zinc oxide, aluminum gallium zinc oxide, and tin aluminum zinc oxide. The channel layer 37 may be doped or undoped. When indium gallium zinc oxide (IGZO) is used as the channel layer 37, electron mobility can be improved, thereby increasing the write speed.
[0112] See you again Figures 12a to 12b In one specific embodiment, after forming the second conductive layer 43 and the third conductive layer 44, the channel layer 37 and the buried layer 38 are formed. The channel layer 37 and the buried layer 38 cover the first insulating layer 36, the second conductive layer 43, the third conductive layer 44, and the second dielectric layer 42. The channel layer 37 is in contact with the second conductive layer 43 and the third conductive layer 44. The method further includes forming a first partition layer 39 and a second partition layer 53 extending along the second direction and cutting through a plurality of the channel layers 37 within the channel layer 37 and the buried layer 38. The first partition layer 39 and the second partition layer 53 divide the channel layer 37 into discrete active regions AA. The second partition layer 53 covers the second dielectric layer 42 and is in contact with the second dielectric layer 42. There are multiple active regions AA, and the multiple active regions AA are arranged along the second direction. In a more specific embodiment, the projections of the second partition layer 53 and the second dielectric layer 42 in a direction perpendicular to the substrate 20 overlap.
[0113] In one embodiment, the active region AA includes a first source / drain doped region (unidentified) located at one end of the active region AA and adjacent to the first separator layer 39, and a second source / drain doped region (unidentified) located at the other end of the active region AA and in contact with the second conductive layer 43. The first source / drain doped region (unidentified) and the second source / drain doped region (unidentified) can be formed in the active region AA by ion implantation. In a specific embodiment, the first source / drain doped region (unidentified) and the second source / drain doped region (unidentified) have the same conductivity type, such as n-type. In a more specific embodiment, the middle region of the active region AA has p-type doping.
[0114] In one embodiment, the method further includes:
[0115] A third dielectric layer 45 is formed on the trench layer 37 and the buried layer 38, and a word line material layer 46 is formed on the third dielectric layer 45, such as... Figures 13a to 13b As shown;
[0116] Etching the word line material layer 46 forms a word line layer 47 extending along the second direction, such as... Figures 14a to 14b As shown;
[0117] A fourth dielectric layer 48 is formed on the substrate 20, the fourth dielectric layer 48 covering the third dielectric layer 45 and the word line layer 47, as shown below. Figures 15a to 15b As shown.
[0118] The word line material layer 46 may include one or more of the following: tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys. (See again) Figures 13a to 13b In one embodiment, the word line material layer 46 includes a first sublayer 461 and a second sublayer 462 located on the first sublayer 461, wherein the first sublayer 461 and the second sublayer 462 are made of different materials; etching the word line material layer 46 to form the word line layer 47 includes: etching the second sublayer 462 to form the second word line sublayer 472; etching the first sublayer 461 to form the first word line sublayer 471, as shown. Figures 14a to 14b As shown. In some embodiments, using a metallic material as the word line layer 47 can reduce resistance.
[0119] In one embodiment, the word line layer 47 is formed between the first separator layer 39 and the second conductive layer 43, with the first conductive layer 35 and the first dielectric layer 41 located below the word line layer 47. This utilizes the space below the word line layer 47, improving the space utilization of the semiconductor device and further increasing its storage density. In some embodiments, the word line layer 47 is disposed above the middle region of the active region AA, separating the first source / drain doped region (unidentified) and the second source / drain doped region (unidentified).
[0120] In one embodiment, the third dielectric layer 45 simultaneously covers both the first separator layer 39 and the second separator layer 53. The material of the third dielectric layer 45 may include oxides, such as silicon oxide. The material of the fourth dielectric layer 48 includes, but is not limited to, nitrides, such as silicon nitride, for protecting the third dielectric layer 45 and the word line layer 47.
[0121] In one embodiment, the method further includes:
[0122] A second insulating layer 49 is formed on the fourth dielectric layer 48; the second insulating layer 49, the fourth dielectric layer 48, and the third dielectric layer 45 are etched to expose the channel layer 37, forming a plurality of bit line contact holes S2 arranged along the second direction, such as... Figures 16a to 16b As shown;
[0123] A bit line contact plug 51 is formed within the bit line contact hole S2, such as... Figures 17a to 17b As shown;
[0124] Multiple bit line layers 52 extending along the first direction are formed on the bit line contact plug 51 and the second insulating layer 49, and the multiple bit line layers 52 are arranged along the second direction, such as... Figures 18a to 18b As shown.
[0125] Here, the bit line contact hole S2 is located between the first separator layer 39 and the word line layer 47, exposing the active region AA. The bit line layer 52 contacts the active region AA through the bit line contact plug 51. In one embodiment, in the first direction, there are multiple active regions AA, and each bit line layer 52 is connected to multiple active regions AA. In a specific embodiment, the bit line layer 52 is connected to the first source / drain doped region (unidentified). The materials of the bit line layer 52 and the bit line contact plug 51 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys.
[0126] Figures 12a to 18bThe trench layer 37 and the buried layer 38 shown are formed after the formation of the second conductive layer 43 and the third conductive layer 44. In another embodiment of this disclosure, the trench layer 37 and the buried layer 38 are formed before the formation of the first trench T1, and the first trench T1, the second trench T2, and the third trench T3 all penetrate the trench layer 37, as shown. Figures 19a to 25b As shown.
[0127] Specifically, such as Figures 19a to 19b As shown, before the first trench T1 is formed, a plurality of trench layers 37 extending along the first direction and arranged along the second direction, and a buried layer 38 located between the plurality of trench layers 37 are formed on the first insulating layer 36.
[0128] Next, as Figures 20a to 20b As shown, the trench layer 37, the buried layer 38 and the first insulating layer 36 are etched to form a first trench T1 extending along the second direction, the first trench T1 exposing a plurality of the sacrificial layers 34.
[0129] Refer again Figures 19a to 20b In one embodiment, the method further includes: forming a first partition layer 39 extending along the second direction and cutting off the trench layer 37 within the trench layer 37 and the buried layer 38, the first partition layer 39 and the first trench T1 dividing the trench layer 37 into discrete active regions AA.
[0130] Next, as Figures 21a to 21b As shown, multiple sacrificial layers 34 are removed through the first trench T1 to form multiple hole structures S1 that communicate with the first trench T1.
[0131] Next, as Figures 22a to 22b As shown, a first dielectric layer 41 is formed within the plurality of hole structures S1, and a second dielectric layer 42 is formed within the first trench T1.
[0132] Next, as Figures 23a to 23b As shown, the channel layer 37 and the first insulating layer 36 are etched to form a plurality of second trenches T2 that expose the first dielectric layer 41 and a plurality of third trenches T3 that expose the common lower electrode plate 32. The second trenches T2 and the third trenches T3 are disposed on both sides of the second dielectric layer 42.
[0133] Next, as Figures 24a to 24b As shown, a second conductive layer 43 and a third conductive layer 44 are formed in the second trench T2 and the third trench T3, respectively.
[0134] Finally, as Figures 25a to 25bAs shown, the third dielectric layer 45, the word line layer 47, the fourth dielectric layer 48, the second insulating layer 49, the bit line contact hole S2, the bit line contact plug 51, and the bit line layer 52 are formed in the same manner as in the previous embodiments. The third dielectric layer 45 covers the channel layer 37, the buried layer 38, the first separator layer 39, the second conductive layer 43, the third conductive layer 44, and the second dielectric layer 42. All of the above layers have been described in the previous embodiments and will not be repeated here.
[0135] It should be noted that those skilled in the art can change the order of the above steps without departing from the scope of protection of this disclosure.
[0136] This disclosure also provides a semiconductor device, such as... Figures 18a to 18b As shown, the system includes: a substrate 20 and a common lower electrode plate 32 located on the substrate 20; an isolation layer 33 located on the common lower electrode plate 32 and a plurality of first dielectric layers 41 extending along a first direction defined by the isolation layer 33, the plurality of first dielectric layers 41 being arranged along a second direction; a plurality of first conductive layers 35 respectively located on the plurality of first dielectric layers 41 and extending along the first direction; a first insulating layer 36 covering the first conductive layers 35, the first dielectric layers 41 and the isolation layer 33; the first insulating layer 36 having a first trench T1 extending along the second direction, and a plurality of second trenches T2 and a plurality of third trenches T3 disposed on both sides of the first trench T1; wherein the second trenches T2 expose the first dielectric layers 41, and the third trenches T3 expose the common lower electrode plate 32; the second dielectric layers 42, the second conductive layers 43 and the third conductive layers 44 are respectively located in the first trenches T1, the second trenches T2 and the third trenches T3.
[0137] The substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.
[0138] In one embodiment, the first direction and the second direction are parallel to the surface of the substrate 20. In some embodiments, the first direction is perpendicular to the second direction. However, it is not limited to this; the first direction may also be oblique to the second direction.
[0139] like Figure 18bAs shown, the lower surface of the first dielectric layer 41 is in contact with the common lower electrode plate 32, and the upper surface of the first dielectric layer 41 is flush with the upper surface of the isolation layer 33. The isolation layer 33 is made of an insulating material, such as silicon oxide.
[0140] In one embodiment, the common lower electrode plate 32 is exposed at the bottom of the first trench T1, and a plurality of first dielectric layers 41 are exposed on the sidewalls of the first trench T1. A second dielectric layer 42 located within the first trench T1 extends along the second direction and is connected to the plurality of first dielectric layers 41. In a specific embodiment, one of the two ends of the first dielectric layer 41 in the first direction is exposed on the sidewalls of the first trench T1. The materials of the first dielectric layer 41 and the second dielectric layer 42 can be high dielectric constant materials, such as tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate. In one embodiment, the materials of the first dielectric layer 41 and the second dielectric layer 42 are the same.
[0141] In one embodiment, the first trench T1, the plurality of second trenches T2, and the plurality of third trenches T3 are all perpendicular to the surface of the substrate 20, and the second dielectric layer 42, the second conductive layer 43, and the third conductive layer 44 are also perpendicular to the surface of the substrate 20.
[0142] Multiple second trenches T2 and multiple third trenches T3 are respectively arranged on both sides of the first trench T1 along the second direction; the number of second conductive layers 43 and the number of third conductive layers 44 are both multiple, and the multiple second conductive layers 43 and the multiple third conductive layers 44 are respectively arranged on both sides of the second dielectric layer 42 along the second direction, and the multiple second conductive layers 43 are connected to the multiple first conductive layers 35 in a one-to-one correspondence, and the multiple third conductive layers 44 are connected to the common lower electrode plate 32. In one embodiment, the second trenches T2 and the third trenches T3 are symmetrically arranged on both sides of the first trench T1, and the second conductive layers 43 and the third conductive layers 44 are symmetrically arranged on both sides of the second dielectric layer 42. The materials of the common lower electrode plate 32, the first conductive layer 35, the second conductive layer 43 and the third conductive layer 44 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys. In one embodiment, the materials of the first conductive layer 35, the second conductive layer 43, and the third conductive layer 44 are the same as the material of the common lower electrode 32, for example, titanium nitride (TiN).
[0143] The shared lower electrode 32, multiple first conductive layers 35, multiple second conductive layers 43, multiple third conductive layers 44, multiple first dielectric layers 41, and the second dielectric layer 42 constitute multiple capacitors C for storing charge, and the multiple capacitors C are arranged along a second direction. The first conductive layer 35 extends in different directions from the second conductive layer 43 and the third conductive layer 44, that is, the capacitors C in this embodiment extend in two different directions. Compared with capacitors in related technologies that extend in only one direction, the capacitors C provided in this embodiment have a larger surface area, thereby enabling them to store a larger amount of charge. At the same time, compared with capacitors in related technologies, the capacitors C in this embodiment can have a smaller depth, allowing the semiconductor device to accommodate more capacitors C per unit volume, thereby increasing the storage density of the semiconductor device. In addition, this embodiment does not require a support structure for supporting the capacitors C, and the multiple capacitors C have the same shared lower electrode 32, simplifying the manufacturing process of the semiconductor device.
[0144] The plurality of capacitors C may also be arranged in an array. In one embodiment, the plurality of capacitors C are arranged in an array along the first direction and the second direction, respectively. In some embodiments, in the first direction, the two ends of the first conductive layer 35 are recessed inward relative to the two ends of the first dielectric layer 41, thereby preventing the first conductive layer 35 of one of two adjacent capacitors C in the first direction from being connected to the third conductive layer 44 of the other; in the second direction, the two ends of the first conductive layer 35 protrude outward relative to the two ends of the first dielectric layer 41, thereby giving the first conductive layer 35 a larger surface area and increasing the charge storage capacity of the capacitor C.
[0145] In one embodiment, the semiconductor device further includes an interlayer insulating layer 31 located below the common lower electrode 32 for electrically isolating the substrate 20 and the common lower electrode 32. The interlayer insulating layer 31 may be made of an oxide, such as silicon oxide.
[0146] In one embodiment, the semiconductor device further includes: a plurality of channel layers 37 extending along the first direction on the first insulating layer 36 and a buried layer 38 located between the plurality of channel layers 37, the plurality of channel layers 37 being arranged along the second direction.
[0147] As shown in the figure, in a specific embodiment, the channel layer 37 is located above the second conductive layer 43, the third conductive layer 44, and the second dielectric layer 42, and the channel layer 37 is in contact with the second conductive layer 43 and the third conductive layer 44. The semiconductor device further includes a first separator layer 39 and a second separator layer 53 extending along the second direction. The first separator layer 39 and the second separator layer 53 are located within the channel layer 37 and the buried layer 38 and cut off multiple channels 37. The first separator layer 39 and the second separator layer 53 divide the channel layer 37 into multiple active regions AA. The second separator layer 53 covers the second dielectric layer 42. There are multiple active regions AA, and the multiple active regions AA are arranged along the second direction. In a more specific embodiment, the projections of the second separator layer 53 and the second dielectric layer 42 in a direction perpendicular to the substrate 20 overlap.
[0148] In one embodiment, the active region AA includes a first source / drain doped region (unidentified) located at one end of the active region AA and adjacent to the first separator layer 39, and a second source / drain doped region (unidentified) located at the other end of the active region AA and in contact with the second conductive layer 43. The first source / drain doped region (unidentified) and the second source / drain doped region (unidentified) can be formed in the active region AA by ion implantation. In a specific embodiment, the first source / drain doped region (unidentified) and the second source / drain doped region (unidentified) have the same conductivity type, such as n-type. In a more specific embodiment, the middle region of the active region AA has p-type doping.
[0149] In one embodiment, the semiconductor device further includes: a third dielectric layer 45 covering the channel layer 37 and the buried layer 38; a word line layer 47 extending along the second direction, the word line layer 47 being located on the third dielectric layer 45; and a fourth dielectric layer 48 covering the third dielectric layer 45 and the word line layer 47.
[0150] In one embodiment, the third dielectric layer 45 simultaneously covers both the first separator layer 39 and the second separator layer 53. The material of the third dielectric layer 45 may include oxides, such as silicon oxide.
[0151] In one embodiment, the word line layer 47 is located between the first separator layer 39 and the second conductive layer 43, with the first conductive layer 35 and the first dielectric layer 41 located below the word line layer 47. This utilizes the space below the word line layer 47, improving the space utilization of the semiconductor device and further increasing its storage density. In a specific embodiment, the word line layer 47 is disposed above the middle region of the active region AA, separating the first source / drain doped region (unidentified) and the second source / drain doped region (unidentified). The material of the word line layer 47 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys. In one embodiment, the word line layer 47 includes a first word line sublayer 471 and a second word line sublayer 472 located on the first word line sublayer 471, wherein the first word line sublayer 471 and the second word line sublayer 472 are made of different materials. The material of the fourth dielectric layer 48 includes, but is not limited to, nitrides, such as silicon nitride, for protecting the third dielectric layer 45 and the word line layer 47.
[0152] In one embodiment, the semiconductor device further includes: a second insulating layer 49 covering the fourth dielectric layer 48; a plurality of bit line layers 52 extending along the first direction, located on the second insulating layer 49 and arranged along the second direction; and bit line contact plugs 51 connected to the bit line layers 52 and the channel layer 37.
[0153] Here, the bit line contact plug 51 is located between the first separator layer 39 and the word line layer 47, and the bit line layer 52 contacts the active region AA through the bit line contact plug 51. In one embodiment, in the first direction, there are multiple active regions AA, and each bit line layer 52 is connected to multiple active regions AA. In a specific embodiment, the bit line layer 52 is connected to the first source / drain doped region (not identified). The materials of the bit line layer 52 and the bit line contact plug 51 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, and metal alloys.
[0154] Figures 18a to 18b The trench layer 37 and the buried layer 38 shown are formed after the formation of the second conductive layer 43 and the third conductive layer 44. In another embodiment of this disclosure, the trench layer 37 and the buried layer 38 may also be formed before the formation of the first trench T1, such as... Figures 25a to 25bAs shown. In this embodiment, before forming the first trench T1, the channel layer 37 and the buried layer 38 are formed on the first insulating layer 36, followed by the formation of the first trench T1, the first dielectric layer 41, the second dielectric layer 42, the second trench T2, the third trench T3, the second conductive layer 43, and the third conductive layer 44. The first trench T1, the second trench T2, and the third trench T3 all penetrate the channel layer 37. The semiconductor device further includes a first separator layer 39 extending along the second direction, the first separator layer 39 being located in the channel layer 36. Within the buried layer 38, multiple channel layers 37 are cut off. The first separator layer 39 and the first trench T1 divide the channel layer 37 into discrete active regions AA. Finally, the third dielectric layer 45, the word line layer 47, the fourth dielectric layer 48, the second insulating layer 49, the bit line contact plug 51, and the bit line layer 52 are formed in the same manner as in the previous embodiments. The third dielectric layer 45 covers the channel layer 37, the buried layer 38, the first separator layer 39, the second conductive layer 43, the third conductive layer 44, and the second dielectric layer 42. All of the above layers have been described in the previous embodiments and will not be repeated here.
[0155] This disclosure also provides a stacked device, such as... Figure 26 As shown, the device includes: a substrate 20 and a plurality of memory structures 30 stacked on the substrate 20; the memory structure 30 includes: a common lower electrode 32; an isolation layer 33 located on the common lower electrode 32 and a plurality of first dielectric layers 41 extending along a first direction defined by the isolation layer 33, the plurality of first dielectric layers 41 being arranged along a second direction; a plurality of first conductive layers 35 respectively located on the plurality of first dielectric layers 41 and extending along the first direction; a first insulating layer 36 covering the first conductive layers 35, the first dielectric layers 41 and the isolation layer 33; the first insulating layer 36 has a first trench T1 extending along the second direction, and a plurality of second trenches T2 and a plurality of third trenches T3 disposed on both sides of the first trench T1; wherein the second trenches T2 expose the first dielectric layers 41, and the third trenches T3 expose the common lower electrode 32; the second dielectric layers 42, the second conductive layers 43 and the third conductive layers 44 are respectively located in the first trenches T1, the second trenches T2 and the third trenches T3. The embodiments of this disclosure improve the integration and storage density of memory devices by stacking multiple memory structures 30 on a substrate 20, with the multiple memory structures 30 separated by an interlayer insulating layer 31 (e.g., a silicon oxide layer).
[0156] It should be noted that the above description is only an optional embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: Provide substrate; A common lower electrode plate is formed on the substrate; An isolation layer and a plurality of sacrificial layers extending in a first direction, defined by the isolation layer, are formed on the common lower electrode plate, and the plurality of sacrificial layers are arranged and distributed in a second direction; Multiple first conductive layers extending along the first direction are formed on the multiple sacrificial layers; A first insulating layer is formed on the first conductive layer, the sacrificial layer, and the isolation layer; The first insulating layer is etched to form a first trench extending along the second direction, the first trench exposing a plurality of the sacrificial layers; Multiple sacrificial layers are removed through the first trench to form multiple hole structures communicating with the first trench; A first dielectric layer is formed within the plurality of said porous structures, and a second dielectric layer is formed within the first trench; The first insulating layer is etched to form a plurality of second trenches exposing the first dielectric layer and a plurality of third trenches exposing the common lower electrode plate, the second trenches and the third trenches being disposed on both sides of the second dielectric layer; A second conductive layer and a third conductive layer are formed in the second trench and the third trench, respectively.
2. The manufacturing method according to claim 1, characterized in that, Removing multiple sacrificial layers through the first trench includes: introducing an etchant into the first trench, wherein the etchant removes multiple sacrificial layers; wherein the etching rate of the sacrificial layers is greater than the etching rate of the isolation layers.
3. The manufacturing method according to claim 1, characterized in that, After forming the first insulating layer, the method further includes: A plurality of trench layers extending along the first direction and a buried layer located between the plurality of trench layers are formed on the first insulating layer, the plurality of trench layers being arranged along the second direction.
4. The manufacturing method according to claim 3, characterized in that, The trench layer and the burial layer are formed before the first trench is formed, and the first trench, the second trench, and the third trench all penetrate the trench layer; the method further includes: A first separating layer is formed within the trench layer and the burial layer, extending in the second direction and cutting off the trench layer. The first separating layer and the first trench divide the trench layer into discrete active regions.
5. The manufacturing method according to claim 3, characterized in that, After forming the second conductive layer and the third conductive layer, the trench layer and the buried layer are formed, the trench layer and the buried layer covering the first insulating layer, the second conductive layer, the third conductive layer and the second dielectric layer, the trench layer being in contact with the second conductive layer and the third conductive layer; the method further includes: A first partition layer and a second partition layer are formed within the trench layer and the buried layer, extending along the second direction and cutting through the plurality of trench layers. The first partition layer and the second partition layer divide the trench layer into discrete active regions. The second partition layer covers the second dielectric layer.
6. The manufacturing method according to claim 3, characterized in that, The method further includes: A third dielectric layer is formed on the trench layer and the buried layer, and a word line material layer is formed on the third dielectric layer; The word line material layer is etched to form a word line layer extending along the second direction; A fourth dielectric layer is formed on the substrate, the fourth dielectric layer covering the third dielectric layer and the word line layer.
7. The manufacturing method according to claim 6, characterized in that, The method further includes: A second insulating layer is formed on the fourth dielectric layer; The second insulating layer, the fourth dielectric layer, and the third dielectric layer are etched to expose the channel layer, forming a plurality of bit line contact holes arranged along the second direction; A bit line contact plug is formed inside the bit line contact hole; Multiple bit line layers extending along the first direction are formed on the bit line contact plug and the second insulating layer, and the multiple bit line layers are arranged along the second direction.
8. A semiconductor device, characterized in that, The semiconductor device includes: Substrate and a common lower electrode plate located on the substrate; An isolation layer located on the common lower electrode plate and a plurality of first dielectric layers extending in a first direction defined by the isolation layer, wherein the plurality of first dielectric layers are arranged and distributed in a second direction; Multiple first conductive layers are respectively located on multiple first dielectric layers and extend along the first direction; A first insulating layer covers the first conductive layer, the first dielectric layer, and the isolation layer; the first insulating layer has a first trench extending along the second direction, and a plurality of second trenches and a plurality of third trenches disposed on both sides of the first trench; wherein the second trenches expose the first dielectric layer, and the third trenches expose the common lower electrode plate; The second dielectric layer, the second conductive layer, and the third conductive layer are located in the first trench, the second trench, and the third trench, respectively.
9. The semiconductor device according to claim 8, characterized in that, In the first direction, the two ends of the first conductive layer are recessed inward relative to the two ends of the first dielectric layer; in the second direction, the two ends of the first conductive layer protrude outward relative to the two ends of the first dielectric layer.
10. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes: a plurality of channel layers extending along the first direction on the first insulating layer and a buried layer between the plurality of channel layers, the plurality of channel layers being arranged along the second direction.
11. The semiconductor device according to claim 10, characterized in that, The first trench, the second trench, and the third trench all penetrate the channel layer; the semiconductor device further includes: a first separator layer extending along the second direction, the first separator layer being located within the channel layer and the buried layer and cutting off multiple channel layers, the first separator layer and the first trench separating the channel layer into discrete active regions.
12. The semiconductor device according to claim 10, characterized in that, The channel layer is located above the second conductive layer, the third conductive layer, and the second dielectric layer, and the channel layer is in contact with the second conductive layer and the third conductive layer; the semiconductor device further includes: a first separator layer and a second separator layer extending along the second direction, the first separator layer and the second separator layer being located within the channel layer and the buried layer and cutting off multiple channel layers, the first separator layer and the second separator layer dividing the channel layer into multiple active regions; wherein, the second separator layer covers the second dielectric layer.
13. The semiconductor device according to claim 10, characterized in that, The semiconductor device further includes: a third dielectric layer covering the channel layer and the buried layer; a word line layer extending along the second direction, the word line layer being located on the third dielectric layer; and a fourth dielectric layer covering the third dielectric layer and the word line layer.
14. The semiconductor device according to claim 13, characterized in that, The semiconductor device further includes: a second insulating layer covering the fourth dielectric layer; a plurality of bit line layers extending along the first direction, located on the second insulating layer and arranged along the second direction; and bit line contact plugs connected to the bit line layers and the channel layer.
15. A stacked device, characterized in that, The stacked device includes: Substrate and multiple storage structures stacked on the substrate; The storage structure includes: Shared lower electrode plate; An isolation layer located on the common lower electrode plate and a plurality of first dielectric layers extending in a first direction defined by the isolation layer, wherein the plurality of first dielectric layers are arranged and distributed in a second direction; Multiple first conductive layers are respectively located on multiple first dielectric layers and extend along the first direction; A first insulating layer covers the first conductive layer, the first dielectric layer, and the isolation layer; the first insulating layer has a first trench extending along the second direction, and a plurality of second trenches and a plurality of third trenches disposed on both sides of the first trench; wherein the second trenches expose the first conductive layer, and the third trenches expose the common lower electrode plate; The second dielectric layer, the second conductive layer, and the third conductive layer are located in the first trench, the second trench, and the third trench, respectively.