Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a semiconductor material region having a major surface and a first conductivity type; and a shield gate trench structure. The shield gate trench structure includes an active trench, an insulating shield electrode in a lower portion of the active trench, an insulating gate electrode in an upper portion of the active trench adjacent to a gate dielectric, and an interpad dielectric (IPD) interposed between the gate electrode and the shield electrode. An interlayer dielectric (ILD) structure is over the major surface. A conductive region is within the active trench and extends through the ILD structure, gate electrode, and IPD, and is electrically connected to the shield electrode. The conductive region is electrically isolated from the gate electrode by a dielectric spacer. The gate electrode includes a shape in a top view that surrounds the conductive region such that the gate electrode is uninterrupted by the conductive region and the dielectric spacer.

Description

Technical Field

[0001] This disclosure relates generally to semiconductor devices, and more specifically to semiconductor device structures and methods of forming semiconductor devices. Background Technology

[0002] Existing semiconductor devices and methods for forming them are inappropriate, resulting in, for example, excessive cost, reduced reliability, relatively low performance (including poor switching performance), or excessive size. Further limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art by comparing such methods with this disclosure and referring to the accompanying drawings. Summary of the Invention

[0003] To address the above problems, the present invention provides a semiconductor device.

[0004] According to one aspect, a semiconductor device is provided, the semiconductor device comprising: a semiconductor material region having a first main surface and a first conductivity type; a shielded gate trench structure comprising: an active trench, a shielded dielectric layer, a shielded electrode, a gate dielectric, a gate electrode, and an inter-pad dielectric (IPD), the active trench extending from the first main surface into the semiconductor material region, the shielded dielectric layer being adjacent to a lower portion of the active trench, the shielded electrode being adjacent to the shielded dielectric layer in the lower portion of the active trench, the gate dielectric being adjacent to an upper portion of the active trench, the gate electrode being adjacent to the gate dielectric in the upper portion of the active trench, and the IPD being interposed between the gate electrode and the shielded electrode; and a body region having a conductivity type opposite to the first conductivity type. A second conductivity type, the main body region being located in the semiconductor material region and extending from the first main surface adjacent to the shielding gate trench structure; a source region having the first conductivity type, the source region being located in the main body region adjacent to the shielding gate trench structure; an interlayer dielectric (ILD) structure being located above the first main surface; and a first conductive region being located within the active trench and extending through the ILD structure, the gate electrode, and the IPD, wherein: the first conductive region is coupled to the shielding electrode; the first conductive region is electrically isolated from the gate electrode by a first dielectric spacer; and the gate electrode includes a shape in the top view surrounding the first conductive region in the top view such that the gate electrode is not interrupted by the first conductive region and the first dielectric spacer.

[0005] According to one aspect, a semiconductor device is provided, the semiconductor device comprising: a semiconductor material region having a first main surface and a first conductivity type; a shielded gate trench structure comprising: an active trench, a shielded dielectric layer, a shielded electrode, a gate dielectric, a gate electrode, and an inter-pad dielectric (IPD), the active trench extending from the first main surface into the semiconductor material region and having a first side and a second side opposite to the first side, the shielded dielectric layer being adjacent to a lower portion of the active trench, the shielded electrode being adjacent to the shielded dielectric layer in the lower portion of the active trench, the gate dielectric being adjacent to an upper portion of the active trench, the gate electrode being adjacent to the gate dielectric in the upper portion of the active trench, and the IPD being interposed between the gate electrode and the shielded electrode; and a body region having a first conductivity type. The opposite second conductivity type, the body region being located in the semiconductor material region, extending from the first main surface adjacent to the first and second sides of the active trench; the source region having the first conductivity type, the source region being located in the body region adjacent to the first and second sides of the active trench; the interlayer dielectric (ILD) structure being located above the first main surface; the first conductive region being located within the active trench and extending through the ILD structure, the gate electrode, and the IPD; and the second conductive region being extending through the ILD structure and the source region, wherein: the first conductive region is coupled to the shielding electrode; the first conductive region is electrically isolated from the gate electrode by a first dielectric spacer; and the gate electrode includes a shape in the top view surrounding each side of the first conductive region in the top view. Attached Figure Description

[0006] Figure 1 A cross-sectional view of a semiconductor device according to this specification is shown;

[0007] Figure 2 The following is shown according to this specification: Figure 1 A top view of a portion of a semiconductor device;

[0008] Figure 3 A flowchart of a method for providing a semiconductor device according to this specification is shown;

[0009] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 It shows that according to Figure 3 Cross-sectional views of semiconductor devices at various processing stages of the method;

[0010] Figure 11 A flowchart of a method for providing a semiconductor device according to this specification is shown;

[0011] Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 It shows that according to Figure 11 Cross-sectional views of semiconductor devices at various processing stages of the method;

[0012] Figure 17 A flowchart of a method for providing a semiconductor device according to this specification is shown;

[0013] Figure 18 , Figure 19 , Figure 20 , Figure 21 and Figure 22 It shows that according to Figure 17 The method provides cross-sectional views of semiconductor devices at various processing stages; and

[0014] Figure 23 A top view of a portion of a semiconductor device according to this specification is shown. Detailed Implementation

[0015] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. These examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0016] To keep the illustrations simple and clear, the components in the diagrams may not be drawn to scale, and the same reference numerals in different diagrams indicate the same components. Furthermore, to simplify the descriptions, descriptions and details of well-known steps and components have been omitted.

[0017] For clarity of the accompanying drawings, certain regions of the device structure, such as doped or dielectric regions, may be shown as having generally straight edges and corners with precise angles. However, those skilled in the art will understand that the edges of such regions may not typically be straight and the corners may not have precise angles due to dopant diffusion and activation or layer formation.

[0018] Although semiconductor devices are interpreted herein as having certain N-type conductive regions and certain P-type conductive regions, those skilled in the art will understand that the conductivity type can be reversed, and that, in accordance with this specification, any necessary reversal of voltage polarity, transistor type, and / or current direction can also be taken into account.

[0019] Furthermore, the terminology used herein is for the purpose of describing particular examples only and is not intended to limit this disclosure. As used herein, the singular form is intended to also include the plural form unless otherwise expressly indicated in the context.

[0020] As used herein, “current-carrying electrode” refers to a component within a device that carries current through the device, such as the source or drain of a MOS transistor, the emitter or collector of a bipolar transistor, or the cathode or anode of a diode, and “control electrode” refers to a component within a device that controls the current flowing through the device, such as the gate of a MOS transistor or the base of a bipolar transistor.

[0021] Additionally, when used in conjunction with a semiconductor region, wafer, or substrate, the term "master surface" refers to the surface of a semiconductor region, wafer, or substrate that forms an interface with another material such as a dielectric, insulator, conductor, or polycrystalline semiconductor. The master surface may have morphological features that vary along the x, y, and z directions.

[0022] When used in this specification, the terms “comprising,” “including,” “having,” and / or “containing” are open-ended terms that specify the presence of the stated features, numbers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or groups thereof.

[0023] The term "or" refers to any one or more items in a list connected by "or". For example, "x or y" refers to any element in the three-element group {(x),(y),(x,y)}. Similarly, "x, y or z" refers to any element in the seven-element group {(x),(y),(z),(x,y),(x,z),(y,z),(x,y,z)}.

[0024] Although the terms “first,” “second,” etc., may be used herein to describe various components, elements, regions, layers, and / or segments, these components, elements, regions, layers, and / or segments should not be limited by these terms. These terms are only used to distinguish one component, element, region, layer, and / or segment from another component, element, region, layer, and / or segment. Therefore, without departing from the teachings of this invention, for example, the first component, first element, first region, first layer, and / or first segment discussed below may be referred to as a second component, second element, second region, second layer, and / or second segment.

[0025] Those skilled in the art will understand that the phrases “during,” “at the same time,” and “when” used herein in relation to circuit operation do not precisely refer to an action occurring immediately after the initial action is initiated, but rather to a possible small but reasonable delay, such as a propagation delay, between the responses triggered by the initial action. Furthermore, the term “at the same time” means that an action occurs at least for a period of time during the duration of the initial action.

[0026] The terms “about,” “approximately,” or “basically” are used to indicate that the value of a component is expected to be close to the declared value or position. However, it is well known in the art that there are always some small deviations that prevent the value or position from being exactly the declared value or position.

[0027] Unless otherwise specified, the phrases “above” or “on” as used herein include the orientation, placement, or relationship in which the specified element may be in direct or indirect physical contact.

[0028] Unless otherwise specified, as used herein, the phrase “overlapping with” includes the orientation, placement, or relationship in which the specified elements can at least partially or completely coincide or align on the same or different planes.

[0029] It should also be understood that the examples exemplified and described below may have examples lacking any elements not explicitly disclosed herein, and / or may be implemented without any elements not explicitly disclosed herein. Insulated-gate field-effect transistor (IGFET) devices are widely used in power applications. Trench metal-oxide-semiconductor FET (MOSFET) devices are one type of IGFET device used in such applications. Some trench MOSFET devices include a shielded electrode electrically isolated from the gate electrode within the same trench (shielded gate trench MOSFET) and can be used in power conversion applications such as synchronous buck converter circuits. The power conversion efficiency in a circuit (such as a synchronous buck converter) depends on many factors, including the switching frequency of the trench MOSFET used in the application. As the frequency of the buck converter increases, the shielding resistance (lower is better) and overall capacitance (lower is better) of the MOSFET become increasingly important in the desired device efficiency. The opposite problem of low shielding resistance (R-shield or Rs) and low overall capacitance (QOSS, Qg, Qgd) is an undesirable increase in switching node ringing, caused by, for example, the high-frequency switching speed of high-side MOSFET devices. The ability to independently control the R-shield by its location within the trench MOSFET device helps to reduce this effect.

[0030] Therefore, what is needed is a cost-effective method and structure for balancing lower shield resistance (Rs) with gate resistance (Rgate or Rg) by adding numerous gate and shield feeds to the MOSFET design (as a way to reduce Rg and Rs). Achieving this without significantly increasing device capacitance would be advantageous. Additionally, it is advantageous to be able to tune Rs to more closely match Rg for a given application, and to be able to address efficiency and ringing issues within a given device by controlling the higher and lower Rs regions at local levels.

[0031] Typically, this example relates to semiconductor device structures and methods for fabricating semiconductor devices with reduced shielding resistance, thereby improving the switching performance of the semiconductor device. Additionally, the structures and methods provide a controlled reduction in shielding electrode resistance, which does not necessarily have to be uniform across the active region of the semiconductor device. The shielding resistance can be tuned according to specific application and design requirements. These structures and methods are cost-effective to implement, requiring only a mask layer and etching step in some examples. It has been empirically found that the structures and methods in this specification have lower shielding resistance compared to previous devices, which improves power conversion efficiency in power conversion applications such as buck converters.

[0032] According to this specification, the contact for the shielding electrode is formed by intercalation between the source metal regions of the MOSFET device. In some examples, the contact for the shielding electrode is formed by forming an electrically isolated contact in the active region of the MOSFET device via the gate conductor. In some examples, recesses are periodically provided along the gate conductor structure (such as a striped gate conductor) in a manner that does not interrupt the electrical continuity of the gate conductor structure. More specifically, insulating shielding contact regions are arranged at predetermined locations in the gate conductor structure and may include recesses extending through the gate conductor to the shielding electrode. In a cross-sectional view, a portion of the gate conductor remains on at least one side of the recess. Thus, the gate conductor is only partially interrupted by the shielding conductor. In some examples, in a cross-sectional view, a sufficient amount of gate conductor remains on both sides of the recess. Thus, the gate conductor provides channel control on both sides of the trench containing the source region and the body region. The shielding conductor is then disposed within the recess and isolated from the gate conductor by an insulator. In some examples, the insulator includes spacers.

[0033] More specifically, in one example, a semiconductor device is provided, comprising: a semiconductor material region including a first main surface and a first conductivity type; and a shielded gate trench structure. The shielded gate trench structure includes: an active trench extending from the first main surface into the semiconductor material region; a shielding dielectric layer adjacent to a lower portion of the active trench; a shielding electrode adjacent to the shielding dielectric layer in the lower portion of the active trench; a gate dielectric adjacent to an upper portion of the active trench; a gate electrode adjacent to the gate dielectric in the upper portion of the active trench; and an inter-pad dielectric (IPD) inserted between the gate electrode and the shielding electrode. A body region having a second conductivity type opposite to the first conductivity type is located in the semiconductor material region and extends from the first main surface adjacent to the shielded gate trench structure. A source region having the first conductivity type is located adjacent to the body region of the shielded gate trench structure. An interlayer dielectric (ILD) structure is located above the first main surface; and a first conductive region is located within the active trench and extends through the ILD structure, the gate electrode, and the IPD, wherein the first conductive region is coupled to the shielding electrode; the first conductive region is electrically isolated from the gate electrode by a first dielectric spacer; and the gate electrode includes a shape surrounding the first conductive region in the top view such that the gate electrode is not interrupted by the first conductive region and the first dielectric spacer.

[0034] In one example, a semiconductor device is provided, comprising: a semiconductor material region having a first main surface and a first conductivity type; and a shielded gate trench structure. The shielded gate trench structure includes: an active trench extending from the first main surface into the semiconductor material region and having a first side and a second side opposite to the first side; a shielding dielectric layer adjacent to a lower portion of the active trench; a shielding electrode adjacent to the shielding dielectric layer in the lower portion of the active trench; a gate dielectric adjacent to an upper portion of the active trench; a gate electrode adjacent to the gate dielectric in the upper portion of the active trench; and an inter-pad dielectric (IPD) inserted between the gate electrode and the shielding electrode. A body region having a second conductivity type opposite to the first conductivity type is located in the semiconductor material region, adjacent to the first and second sides of the active trench, extending from the first main surface. A source region having the first conductivity type is located in the body region adjacent to the first and second sides of the active trench. An interlayer dielectric (ILD) structure is located above the first main surface. A first conductive region is located within the active trench and extends through the ILD structure, the gate electrode, and the IPD. A second conductive region extends through the ILD structure and the source region. The first conductive region is coupled to the shielding electrode; the first conductive region is electrically isolated from the gate electrode by a first dielectric spacer; and the gate electrode includes a shape in the top view surrounding each side of the first conductive region in the top view.

[0035] In one example, a method of forming a semiconductor device is provided, the method comprising: providing a semiconductor material region including a first main surface and a first conductivity type. The method includes providing a shielded gate trench structure including: an active trench extending from the first main surface into the semiconductor material region and having a first side and a second side opposite to the first side; a shielding dielectric layer adjacent to a lower portion of the active trench; a shielding electrode adjacent to the shielding dielectric layer in the lower portion of the active trench; a gate dielectric adjacent to an upper portion of the active trench; a gate electrode adjacent to the gate dielectric in the upper portion of the active trench; and an inter-pad dielectric (IPD) inserted between the gate electrode and the shielding electrode. The method includes providing a body region having a second conductivity type opposite to the first conductivity type, the body region being located in the semiconductor material region and extending from a main surface adjacent to a first side and a second side of the active trench; the method includes providing a source region having the first conductivity type, the source region being located in the body region adjacent to the first side and the second side of the active trench. The method includes providing an interlayer dielectric (ILD) structure above the first main surface. The method includes providing a first conductive region located within the active trench and extending through the ILD structure, the gate electrode, and the IPD. The method includes providing a second conductive region extending through the ILD structure and the source region, wherein the first conductive region is coupled to the shielding electrode; the first conductive region is electrically isolated from the gate electrode by a first dielectric spacer; and the gate electrode includes a shape surrounding each side of the first conductive region in a top view.

[0036] Other examples are included in this disclosure. Such examples can be seen in the drawings, the claims, and / or the description of this disclosure.

[0037] Figure 1An enlarged cross-sectional view of an electronic device 10, semiconductor device 10, or shielded gate trench MOSFET 10 having a shielded gate trench structure 13 according to this specification is shown. In some examples, the shielded gate trench structure 13 may be placed in an active region of the semiconductor device 10. In some examples, the semiconductor device 10 includes a workpiece 11, such as a semiconductor material region 11 having a main surface 18 and an opposing main surface 19. In some examples, the main surface 18 is configured as an active surface of the semiconductor device 10. The semiconductor material region 11 may include a bulk semiconductor substrate 12, such as an N-type conductive silicon substrate having a resistivity in the range of about 0.001 ohm-cm to about 0.005 ohm-cm. By way of example, the substrate 12 may be doped with phosphorus, arsenic, or antimony. In the examples shown, the substrate 12 typically provides a drain region, drain contact, or first current-carrying contact for the device 10 at the main surface 19. In some examples, a drain contact may be formed at the main surface 18. In this example, semiconductor device 10 is configured as a vertical MOSFET structure, but this specification also applies to insulated gate bipolar transistors (IGBTs), MOS gate-controlled semiconductor thyristors, and other related or equivalent structures known to those skilled in the art.

[0038] In some examples, the semiconductor material region 11 further includes a semiconductor layer 14, a doped region 14, one or more doped layers 14, which may be formed in, on, or covering the substrate 12. In one example, when the substrate 12 is N-type conductive, the doped layer 14 may be an N-type conductive region or layer, and may be formed using epitaxial growth techniques, ion implantation and diffusion techniques, other techniques known to those skilled in the art, or combinations thereof. In one example, the semiconductor layer 14 includes the main surface 18 of the semiconductor material region 11. It should be understood that the semiconductor material region 11, the semiconductor substrate 12, and / or the semiconductor layer 14 may include other types of materials, including but not limited to heterojunction semiconductor materials, and the semiconductor substrate 12 and the semiconductor layer 14 may each include different materials. Such materials may include SiGe, SiGeC, SiC, GaN, AlGaN, or other similar materials known to those skilled in the art.

[0039] In some examples, semiconductor layer 14 has a dopant concentration lower than that of substrate 12. The dopant concentration and thickness of semiconductor layer 14 can be determined according to, for example, the desired breakdown (BV) of semiconductor device 10. DSS The ratings and layout design may increase or decrease. In some examples, the semiconductor layer 14 may have a dopant distribution that varies beyond its depth from the main surface 18 inwards. Such variations may include linear and nonlinear distributions beyond the thickness of the semiconductor layer 14.

[0040] In this example, the shielded gate trench structure 13 includes an active trench 23 extending inward from the main surface 18 of the semiconductor material region 11 to a depth within the semiconductor layer 14. The shielded gate trench structure 13 also includes a shielding electrode 21, a shielding dielectric layer 264 separating the shielding electrode 21 from the semiconductor layer 14, a gate dielectric 26 located above the upper surface of the active trench 23, a gate electrode 28 disposed adjacent to the gate dielectric 26, and an inter-pad dielectric 27 electrically isolating the shielding electrode 21 from the gate electrode 28. As described later, the shielded gate trench structure 13 may also include additional shielding electrode conductors or additional gate electrode conductors, such as one or more metals or silicides.

[0041] In some examples, the shielding dielectric layer 264 comprises a thermal oxide with a thickness ranging from about 800 angstroms to about 1050 angstroms. The thickness of the shielding dielectric layer 264 may be made thicker or thinner depending on the electrical requirements of the semiconductor device 10. For example, this thickness may be increased for higher voltage devices comprising a thickness of about 4000 angstroms. In other examples, the shielding dielectric layer 264 may comprise more than one dielectric material, such as oxides, nitrides, other dielectric materials known to those skilled in the art, or combinations thereof.

[0042] In some examples, the gate dielectric 26 may comprise oxides, nitrides, tantalum pentoxide, titanium dioxide, barium strontium titanate, high-k dielectric materials, combinations thereof, or other related or equivalent materials known to those skilled in the art. In some examples, the gate dielectric 26 comprises a thermal oxide with a thickness ranging from about 100 angstroms to about 1000 angstroms. In some examples, the shielding electrode 21 and the gate electrode 28 comprise doped polycrystalline semiconductor materials, such as doped polycrystalline silicon. In some examples, the polycrystalline silicon is doped with an N-type conductive dopant, such as phosphorus or arsenic. In other examples, the polycrystalline silicon may be doped with a P-type conductive dopant, such as boron.

[0043] In some examples, the semiconductor device 10 also includes a body region 31, which in this example has P-type conductivity and is disposed adjacent to the shielded gate trench gate structure 13, such as... Figure 1 As generally shown. The body region 31 can be multiple individual doped regions or it can be a continuous interconnect doped region. The body region 31 has a dopant concentration suitable for forming an inversion layer that serves as a conductive channel or channel region of the semiconductor device 10 when an appropriate bias voltage is applied to the gate electrode 28. The body region 31 can extend from the main surface 18 to a depth of, for example, from about 0.7 micrometers to about 1.0 micrometers. Doping techniques such as ion implantation and annealing can be used to form the body region 31. The body region 31 can also be referred to as the base region or PHV region.

[0044] In some examples, the source region 33 may be formed within, in, or covering the body region 31, and in some examples, it may extend from the main surface 18 to a depth of about 0.2 micrometers to about 0.4 micrometers. In some examples, the source region 33 may have N-type conductivity and may be formed using, for example, phosphorus or arsenic doped sources. Doping techniques such as ion implantation and annealing processes may be used to form the source region 33. The source region 33 may also be referred to as a current-conducting region or a current-carrying region.

[0045] In some examples, the interlayer dielectric (ILD) structure 41 may be formed as a cover over the main surface 18. In one embodiment, the ILD structure 41 includes one or more dielectric or insulating layers. In some examples, the ILD structure 41 includes an undoped silicon glass (USG) layer with a thickness ranging from about 800 angstroms to about 1000 angstroms and a phosphorus-doped silicon glass (PSG) layer with a thickness ranging from about 6000 angstroms to about 8000 angstroms. The PSG layer may have a phosphorus weight percentage ranging from about 3% to about 5%. The ILD structure 41 may be formed using chemical vapor deposition (CVD) or similar techniques. In some examples, the ILD structure 41 may be annealed to densify the structure. In some examples, the ILD structure 41 may be planarized using, for example, chemical mechanical planarization (CMP) techniques to provide a more uniform surface morphology, which improves manufacturability.

[0046] According to this specification, the semiconductor device 10 also includes conductive regions 43A and 43B. Conductive region 43A provides electrical connections to source region 33 and body region 31, and conductive region 43B provides electrical connections to shielding electrode 21. As taught in this specification, conductive region 43B provides contact with the shielding electrode within the active region of the semiconductor device 10, thereby reducing the resistance of shielding electrode 21 during device operation. This is an improvement over previous semiconductor devices that only contacted the shielding electrode at the peripheral region of the semiconductor device and relied on long interconnects or feeders from the peripheral region to the active region, which increased resistance and could potentially degrade device performance. In some examples, conductive region 43B may be used instead of the peripheral region shielding electrode contact. In other examples, conductive region 43B may be used in addition to the peripheral region shielding electrode contact.

[0047] In some examples, conductive region 43A may be formed within contact opening 422A or contact via 422A and configured to provide electrical contact with source region 33 and body region 31 via contact region 36. Contact region 36 may also be referred to as body reinforcement region. In some examples, contact region 36 includes P-type conductivity when body region 31 includes P-type conductivity. Doping techniques such as ion implantation and annealing processes can be used to form contact region 36. Conductive region 43B may be formed within contact opening 422B or contact via 422B and configured to provide electrical contact with shielding electrode 21. As described later, conductive region 43A within contact opening 422A may be further formed to provide electrical connection to gate electrode 28 at one or more different locations on semiconductor device 10.

[0048] According to this specification, the conductive region 43B is electrically isolated from the gate electrode 28 by a dielectric 53B, such as a dielectric spacer 53B disposed along the sidewall of the contact opening 422B. In some examples, the dielectric spacer 53B comprises oxides, nitrides, organic dielectrics, other insulating materials known to those skilled in the art, or combinations thereof. This configuration offers advantages over previous methods that use interruptions or breaks in the gate conductor line to completely isolate the gate conductor from the shielding contacts. Compared to previous methods, this configuration makes the gate electrode 28 continuous, thereby increasing the gate resistance.

[0049] Figure 2 A top view of a portion of the semiconductor device 10 is shown to further illustrate this configuration. Figure 2 Two conductive regions 43B are shown, but it should be understood that the semiconductor device 10 may include multiple conductive regions 43B. In some examples, the dielectric spacer 53B completely surrounds or encloses the conductive region 43B. Although the conductive region 43B is shown as a square shape, it should be understood that other shapes, such as circular shapes or shapes with rounded corners, may be used. As mentioned above, in some examples, the gate electrode 28 includes a continuous strip shape, but in the presence of the conductive region 43B, the gate electrode 28 includes a region 28A that is narrower than region 28B, because region 28A accommodates the conductive region 43B. Region 28A is designed to accommodate the critical dimensions of the selected processing flow, such that design rules can take into account both the dielectric spacer 53B and the conductive region 43B, while maintaining a sufficient width for region 28A. In this way, the gate electrode 28 is a continuous structure surrounding the conductive region 43B, so that the gate resistance is not affected in an undesirable manner. More specifically, in some examples, the gate electrode 28 includes a shape surrounding the conductive region 43B in the top view, such that the gate electrode 28 is not interrupted by the conductive region 43B and the dielectric spacer 53B.

[0050] Another advantage of the conductive regions 43B is that these regions can be placed at predetermined locations within the active region of the semiconductor device 10, thereby enabling tuning of the shielding resistor at specific locations to meet specific application requirements. In some examples, the conductive regions 43B can be uniformly distributed within the active region of the semiconductor device 10. In some examples, the conductive regions 43B can be non-uniformly distributed within the active region of the semiconductor device 10.

[0051] In one example, for a 40-volt (V) device, the gate dielectric 26 may have a thickness of approximately 400 angstroms. For reliability reasons, the thickness of the dielectric spacer 53B may be twice the thickness of the gate dielectric 26, or approximately 800 angstroms. For a 4.5 Sigma process, the width of the trench 23 may be approximately 5,250 angstroms, the width of the gate electrode may be approximately 4,500 angstroms, and the width of the conductive region 43B may be approximately 1,200 angstroms.

[0052] In some examples, dielectric spacer 53A may be disposed along the sidewall of opening 422A. Dielectric spacer 53A may comprise the same material as dielectric spacer 53B. In other examples, dielectric spacer 53A may be omitted.

[0053] Re-reference Figure 1 The conductive region 43B extends through the gate electrode 28 and through the IPD 27 to form physical contact with the upper surface 21A of the shielding electrode 21. In some examples, the dielectric spacer 53B extends to the same depth or location as the conductive region 43B within the region of the semiconductor material 11. In other examples, the dielectric spacer 53B may extend only partially into the IPD 27. More specifically, the dielectric spacer 53B extends to a depth sufficient to electrically isolate the conductive region 43B from the gate electrode 28. In some examples, the dielectric spacer 53A may extend to the main surface 18 of the semiconductor material region 11 or may terminate adjacent to the gate dielectric 26.

[0054] In some examples, conductive regions 43A and 43B may be conductive plugs or plug structures. In some examples, conductive regions 43A and 43B may include conductive barrier structures or linings and conductive filler materials. In some examples, the barrier structure may include a metal / metal-nitride configuration, such as titanium / titanium nitride or other related or equivalent materials known to those skilled in the art. In other examples, the barrier structure may also include a metal silicide structure. In some examples, the conductive filler material includes tungsten. In some examples, conductive regions 43A and 43B may be planarized to provide a more uniform surface morphology.

[0055] Conductive layer 44A may be formed covering the main surface 18, and conductive layer 46 may be formed covering the main surface 19. Conductive layers 44A and 46 may be configured to provide electrical connections between individual device components of the semiconductor device 10 and next-level components. In some examples, conductive layer 44A may be titanium / titanium nitride / aluminum copper or other related or equivalent materials known to those skilled in the art. Conductive layer 44A is configured as an external source electrode. Figure 1 An example is shown where the shielding electrode 21 and the source region 33 are electrically connected together via a conductive layer 44A to be at the same potential when the semiconductor device 10 is used. In other examples, the shielding electrode 21 may be configured to be independently biased.

[0056] In some examples, the conductive layer 46 may be a solderable metallic structure, such as titanium nickel silver, chromium nickel gold, or other related or equivalent materials known to those skilled in the art and configured as drain electrodes or terminals. In some examples, an additional passivation layer (not shown) may be formed over the conductive layer 44A. It should also be understood that an additional conductive layer may be included above the conductive layer 44A, separated by an additional ILD layer.

[0057] According to this example, semiconductor device 10 is an improvement over a previous device because the conductive region 43B reduces the shielding resistance. This has been empirically found to improve power conversion efficiency in certain applications, such as buck converter applications and others. As will be described in more detail later, the conductive region 43B can be added by only one additional masking step and between about four (4) and about seven (7) additional process steps, with an estimated cost impact of about $25 per wafer.

[0058] Figure 3 A flowchart of a method 300 for providing an electronic device such as a semiconductor device is shown. In some examples, the semiconductor device of method 300 may be similar to one or more of the semiconductor devices shown herein, including semiconductor device 10 or a variant thereof.

[0059] Block S310 of method 300 includes providing a semiconductor substrate with a shielded gate trench structure. In some examples, the semiconductor substrate may resemble semiconductor material region 11, which includes substrate 12 and semiconductor layer 14, and also includes a shielded gate trench structure 13 adjacent to the main surface 18.

[0060] More specifically, in frame S310, the semiconductor substrate has been processed by several front-end unit processes, such as dielectric formation, photomask, etching, deposition, ion implantation, and annealing unit processes. These unit processes can be used to form the shielded gate structure 13 (including, for example, shielding electrode 21, shielding dielectric 264, IPD 27, gate dielectric 26, and gate electrode 28), the body region 31, and the source region 33, as combined with... Figure 1 As described.

[0061] Block S320 of method 300 includes forming an interlayer dielectric (ILD) on a first main surface of a semiconductor substrate. In some examples, the interlayer dielectric (ILD) may resemble ILD structure 41 or a variation thereof. In some examples, the ILD structure may include an undoped silicon glass (USG) layer with a thickness ranging from about 800 angstroms to about 1000 angstroms and a PSG layer with a thickness ranging from about 6000 angstroms to about 8000 angstroms. The PSG layer may have a phosphorus weight percentage ranging from about 3% to about 5%. The ILD structure may be formed using CVD or similar techniques. In some examples, the ILD structure may be annealed to densify the structure. In some examples, the ILD structure may be planarized using, for example, CMP techniques.

[0062] Block S330 of method 300 includes forming a shielded contact opening by selectively removing a portion of the ILD structure, gate conductor, and inter-pad dielectric (IPD). Figure 4 A cross-sectional view of an electronic device (such as semiconductor device 10) following the steps described in frames S310, S320, and S330 is shown. In some examples, a mask 64 with an opening 64A is provided above the ILD structure 41, in which a conductive region 43B is formed to provide contact with the shielding electrode 21. In some examples, the mask 64 comprises a photomask and can be formed using photoresist deposition, exposure, and development processes. Next, portions of the ILD structure 41, the gate electrode 28, and the IPD 27 can be removed to provide a contact opening 422B, which in some examples can expose the upper surface 21A of the shielding electrode 21. In some examples, dry or wet etching techniques can be used to remove different materials. In some examples, the mask 64 can then be removed after the contact opening 422B has been provided.

[0063] Block S340 of method 300 includes forming a first ILD spacer within the shielded contact opening. In some examples, this may include forming a dielectric spacer 53B within the contact opening 422B, such as... Figure 5The diagram shows a cross-sectional view of the semiconductor device 10 after further processing. In some examples, a dielectric is formed to cover the ILD structure 41 and the contact opening 422B. The thickness of the dielectric is such that the contact opening 422B is not completely filled. In some examples, the thickness of the dielectric is approximately twice the thickness of the gate dielectric 26, as previously described. In some examples, the dielectric may comprise oxides, nitrides, other insulating materials known to those skilled in the art, or combinations thereof. The dielectric can be formed using CVD, plasma-enhanced CVD (PECVD), low-temperature oxide (LTO) processes, or other processes known to those skilled in the art. After the dielectric is formed, anisotropic etching can be used to remove portions of the dielectric along the upper surface of the ILD structure 41 and the upper surface 21A of the shielding electrode 21. The remaining dielectric provides dielectric spacers 53B, such as... Figure 5 As shown.

[0064] Block S350 of method 300 includes forming a first portion of the source / body contact opening by selectively removing a portion of the ILD. In some examples, this includes placing a mask 66 with an opening 66A over the ILD structure 41, such as... Figure 6 The diagram shows a cross-sectional view of the semiconductor device 10 after further processing. In some examples, mask 66 covers contact opening 422B and dielectric spacer 53. Opening 66A corresponds to the location where conductive region 43A will be formed to provide source / body contacts for the semiconductor device 10. In some examples, mask 66 comprises a photomask and can be formed using photoresist deposition, exposure, and development processes. Next, a portion of the ILD structure 41 can be removed to provide contact opening 422A, which can expose the main surface 18 of the semiconductor material region 11. In some examples, this step also removes any portion of the gate dielectric 26 that may exist above the main surface 18, such as... Figure 6 As shown. In some examples, dry or wet etching techniques can be used to remove the ILD structure 41 and the gate dielectric 26. In some examples, the mask 66 can then be removed after providing the contact opening 422A. It should be understood that the frame S350 can also be used to form a gate contact opening at a predetermined location to provide gate contact with the gate electrode 28.

[0065] Block S360 of method 300 includes forming a second ILD spacer within a first portion of the source / body contact opening. In some examples, the second ILD spacer may be similar to the dielectric spacer 53A formed within the contact opening 422A, such as... Figure 7The diagram shows a cross-sectional view of the semiconductor device 10 after further processing. In some examples, a dielectric is formed to cover the ILD structure 41 and the contact opening 422A. The thickness of the dielectric is such that the contact opening 422A is not completely filled. In some examples, the dielectric may comprise oxides, nitrides, other insulating materials known to those skilled in the art, or combinations thereof. The dielectric can be formed using CVD, PECVD, LTO processes, or other processes known to those skilled in the art. After the dielectric is formed, anisotropic etching can be used to remove portions of the dielectric along the exposed portions of the upper surface and main surface 18 of the ILD structure 41. The remaining dielectric provides dielectric spacers 53B, such as... Figure 7 As shown.

[0066] Block S370 of method 300 includes removing a portion of the semiconductor substrate using a second ILD spacer to form a second portion of the source / body contact opening. In some examples, the second portion of the source / body contact may be contact opening 422C, such as... Figure 7 As shown. In some examples, a portion of the semiconductor material region 11 may be removed using a fluorine-based chemical to provide a contact opening 422C extending inward from the main surface 18 aligned with the dielectric spacer 53A. That is, the dielectric spacer 53A is used as a mask to form the contact opening 422C. In some examples, the contact opening 422C extends beyond the source region 33 and terminates in the body region 31 of the semiconductor device 10.

[0067] Block S380 of method 300 includes forming a body enhancement region adjacent to the source / body contact opening within a body region of the semiconductor substrate. In some examples, a contact region 36 may be formed within the body region 31 using ion implantation and annealing processes, such as... Figure 7 As shown. The contact area 36 is configured to enhance the contact characteristics between the main body area 31 and the subsequently formed conductive area 43A.

[0068] Block S390 of method 300 includes forming a shielding contact within a shielding contact opening and forming a source / body contact within a source / body contact region. In some examples, this may include forming a conductive region 43B within contact opening 422B and forming a conductive region 43A within contact openings 422A and 422C, as shown. Figure 8The diagram shows a cross-sectional view of the semiconductor device 10 after further processing. In some examples, conductive regions 43A and 43B may be conductive plugs or plug structures. In some examples, conductive regions 43A and 43B may include conductive barrier structures or linings and conductive filler materials. In some examples, the barrier structure may include a metal / metal-nitride configuration, such as titanium / titanium nitride or other related or equivalent materials known to those skilled in the art. In other examples, the barrier structure may also include a metal silicide structure. Conductive regions 43A and 43B may be formed using vapor deposition, sputtering, CVD, or other processes known to those skilled in the art. In some examples, the conductive filler material includes tungsten. In some examples, conductive regions 43A and 43B may be planarized using a CMP process to provide a more uniform surface morphology.

[0069] Block S395 of method 300 includes a finishing process for the semiconductor substrate. In some examples, this may include forming a conductive layer 44A, using processes such as polishing and etching to reduce the thickness of the semiconductor material region 11, and forming a conductive layer 46 to provide, for example, a finishing process for the semiconductor substrate. Figure 1 The semiconductor device 10 shown. This further includes adding a passivation layer, cutting the semiconductor material region 11 into individual semiconductor devices, and assembling the individual semiconductor devices into a protective package.

[0070] Figure 9 Cross-sectional views of the semiconductor device 10 at different locations within the semiconductor device 10 are shown. More specifically, Figure 9 A portion of a semiconductor device 10 in which a contact with a gate electrode 28 is formed is shown. In some examples, a contact opening 422D is provided via an ILD structure 41, extending to the gate electrode 28. In some examples, a dielectric spacer 53C may be disposed along the sidewall surface of the contact opening 422D. In some examples, the contact opening 422D and the dielectric spacer 53C may be formed simultaneously with the contact opening 422A and the dielectric spacer 53A. In some examples, a conductive region 43C is disposed within the contact opening 422D, may comprise the same material as conductive regions 43A and 43B, and may be formed simultaneously with conductive regions 43A and 43B. In some examples, the contact opening 422D and the conductive region 43C may be positioned adjacent to the peripheral edge portion of the semiconductor device 10. In some examples, a portion of the gate electrode 28 may be etched such that the conductive region 43C is partially embedded within the gate electrode 28, as... Figure 9 As shown. For example, when the contact opening 422C is formed as described above, a portion of the gate electrode 28 can be removed. Figure 9 As shown, in some examples, the dielectric spacer 53C extends only to the upper surface of the gate electrode 28. Additionally, Figure 9Another conductive layer 44B is shown that can be formed simultaneously with conductive layer 44A and provides contact with gate electrode 28 through conductive region 43C. Conductive layer 44B may include the same material as conductive layer 44A and can be patterned using photomask and etching processes.

[0071] Figure 10 An enlarged partial cross-sectional view of an electronic device 20, semiconductor device 20, or shielded gate trench MOSFET 20 having a shielded gate trench structure 13 according to this specification is shown. Semiconductor device 20 is similar to semiconductor device 10, and only the differences will be described below. In semiconductor device 20, dielectric spacers 53B and 53C may be omitted along with the electrical isolation provided by the ILD structure 41. For example, in the previously described method 300, block S360 may be omitted, and blocks S350 and S370 may be combined to provide a contact opening 422A extending all the way to the body region 31 and a contact opening 422D terminating on the gate conductive layer 280 (described below).

[0072] Additionally, the semiconductor device 20 includes a shielding conductive layer 210 located above the shielding electrode 21 and a gate conductive layer 280 located above the gate electrode 28. The shielding conductive layer 210 and the gate conductive layer 280 are provided to reduce the resistance of the shielding electrode 21 and the gate electrode 28. In some examples, the shielding conductive layer 210 and the gate conductive layer 280 may comprise the same material, such as one or more metals, metal nitrides, silicides, or other conductive materials known to those skilled in the art. In this respect, the resistance of the gate electrode 28 and the resistance of the shielding electrode 21 can be more closely matched. In some examples, the shielding conductive layer 210 and the gate conductive layer 280 comprise tungsten (W) silicide, cobalt (Co) silicide, titanium (Ti) silicide, or other silicides known to those skilled in the art. In some examples, the shielding conductive layer 210 and the gate conductive layer 280 comprise titanium nitride (TiN). In other examples, the shielding conductive layer 210 and the gate conductive layer 280 comprise a combination of a polycrystalline semiconductor material (e.g., polycrystalline silicon) and a metal or metal nitride.

[0073] When the contact opening 422B is formed in the semiconductor device 20, a portion of the gate conductive layer 280 can be removed using wet etching before the contact opening 422B is etched through the gate electrode 28. In other examples, a barrier mask can be used so that the gate conductive layer 280 is not formed at the location where the contact opening 422BA will be formed later. It should be understood that the shielding conductive layer 210 and the gate conductive layer 280 can be used in the examples described herein (including variations thereof).

[0074] Semiconductor devices 10 and 20 are examples in which the conductive region 43B extends through the ILD structure 41, the gate electrode 28 and the IPD 27 to a first depth and the dielectric spacer 53B extends to a first depth.

[0075] Figure 11 A flowchart of method 300A for providing an electronic device such as a semiconductor device is shown. In some examples, method 300A may be an alternative to method 300 for manufacturing semiconductor device 10, which will be discussed below. Figures 12 to 16 It is described as a semiconductor device 30.

[0076] The boxes S310 and S320 of method 300A are similar to those of method 300, and the details of the steps will not be repeated here.

[0077] Block S330A of method 300A includes forming a first portion of a shielded contact opening by selectively removing portions of a first portion of the ILD, gate conductor, and inter-pad dielectric (IPD). Figure 12 A cross-sectional view of the semiconductor device 30 is shown after a contact opening 422BA has been formed through the first portion of the ILD structure 41, gate electrode 28, and IPD 27. In some examples, a mask 64 with an opening 64A is disposed above the ILD structure 41, in which a conductive region 43B is formed to provide shielded contact with the shielding electrode 21. In some examples, the mask 64 comprises a photomask and can be formed using photoresist deposition, exposure, and development processes. Next, portions of the first portion of the ILD 41, gate electrode 28, and IPD 27 can be removed to provide the contact opening 422BA. In some examples, the mask 64 can then be removed after the contact opening 422BA has been provided.

[0078] Block S335 of method 300A includes forming a cryogenic dielectric. In some examples, cryogenic oxidation may be used to deposit the dielectric 76 within the contact opening 422BA at least along the exposed portion of the gate electrode 28, such as... Figure 12 As shown. In some examples, the dielectric 76 may have a thickness in the range of about 100 angstroms to about 200 angstroms. It should be understood that it is possible to... Figure 12 Remove the mask 64 before forming the dielectric 76.

[0079] Frame S340A of method 300A includes forming a first ILD spacer within a first portion of the shielded contact opening. In some examples, this may include forming a dielectric spacer 53B within the contact opening 422BA, such as... Figure 13The diagram shows a cross-sectional view of the semiconductor device 30 after further processing. In some examples, the dielectric is formed to cover the ILD structure 41 and the contact opening 422BA. The thickness of the dielectric is such that the contact opening 422BA is not completely filled. In some examples, the thickness of the dielectric is approximately twice the thickness of the gate dielectric 26, as previously described. In some examples, the dielectric may comprise oxides, nitrides, other insulating materials known to those skilled in the art, or combinations thereof. The dielectric can be formed using CVD, PECVD, LTO processes, or other processes known to those skilled in the art. After the dielectric is formed, anisotropic etching can be used to remove portions of the dielectric along the upper surface of the ILD structure 41 and the surface of the IPD 27. The remaining dielectric provides dielectric spacers 53B, as... Figure 13 As shown.

[0080] Block S345 of method 300A includes using a first ILD spacer to form a second portion of the shielded contact opening to expose the upper surface of the shielded electrode within the shielded contact opening. In some examples, this may include removing the second portion of IPD 27 using a dielectric spacer 53B to provide contact opening 422BB and expose the upper surface 21A of the shielded electrode 12, such as... Figure 13 As shown. It should be understood that in this example, the material used for the dielectric spacer 53B is different from that of IPD 27 in order to provide etch selectivity between the materials. In some examples, a second portion of IPD 27 may be removed using a fluorine-based chemical. In this example, the dielectric spacer 53B does not extend the entire shielded contact opening provided by contact openings 422BA and 422BB. Contact openings 422BA and 422BB may be examples of contact opening 422B formed in multiple steps.

[0081] Block S350 of method 300A is similar to block S350 of method 300 previously described, and includes forming a first portion of the source / body contact opening by selectively removing portions of the ILD. In some examples, this includes providing a mask 66 with an opening 66A over the ILD structure 41, such as... Figure 14The diagram shows a cross-sectional view of the semiconductor device 30 after further processing. In some examples, mask 66 covers contact openings 422BA and 422BB and dielectric spacer 53B. Opening 66A corresponds to the location where conductive region 43A will be formed to provide source / body contacts for the semiconductor device 30. In some examples, mask 66 comprises a photomask and can be formed using photoresist deposition, exposure, and development processes. Next, a portion of ILD 41 can be removed to provide contact opening 422A, which can expose the main surface 18 of the semiconductor material region 11. In some examples, this step also removes any portion of the gate dielectric 26 that may exist above the main surface 18, such as... Figure 14 As shown. It should be understood that the frame S350 can also be used to form a gate contact opening at a predetermined location to provide gate contact with the gate electrode 28.

[0082] Block S360 of method 300A is similar to block S360 of method 300 previously described, and includes forming a second ILD spacer within a first portion of the source / body contact opening. In some examples, the second ILD spacer may be similar to the dielectric spacer 53A formed within the contact opening 422A, such as... Figure 15 The diagram shows a cross-sectional view of the semiconductor device 30 after further processing. In some examples, a dielectric is formed to cover the ILD structure 41 and the contact opening 422A. The thickness of the dielectric is such that the contact opening 422A is not completely filled. In some examples, the dielectric may comprise oxides, nitrides, other insulating materials known to those skilled in the art, or combinations thereof. The dielectric can be formed using CVD, PECVD, LTO processes, or other processes known to those skilled in the art. After the dielectric is formed, anisotropic etching can be used to remove portions of the dielectric along the exposed portions of the upper surface and main surface 18 of the ILD structure 41. The remaining dielectric provides dielectric spacers 53B, such as... Figure 15 As shown.

[0083] Block S370 of method 300A is similar to block S370 of method 300, and includes a second portion of the semiconductor substrate removed using a second ILD spacer to form a source / body contact opening. In some examples, the second portion of the source / body contact may be contact opening 422C, such as... Figure 15 As shown. In some examples, a portion of the semiconductor material region 11 may be removed using a fluorine-based chemical to provide a contact opening 422C extending inward from the main surface 18 aligned with the dielectric spacer 53A. That is, the dielectric spacer 53A is used as a mask to form the contact opening 422C. In some examples, the contact opening 422C extends beyond the source region 33 and terminates within the body region 31 of the semiconductor device 30.

[0084] Block S380 of method 300A is similar to block S380 of method 300, and includes forming a body enhancement region adjacent to the second source / body contact opening within the body region of the semiconductor substrate. In some examples, the contact region 36 may be formed within the body region 31 using ion implantation and annealing processes, such as... Figure 15 As shown. When the main body region 31 includes P-type conductivity, the contact region 36 also has P-type conductivity. The contact region 36 is configured to enhance the contact characteristics between the main body region 31 and the subsequently formed conductive region 43A.

[0085] Block S390 of method 300A is similar to block S390 of method 300, and includes forming a shielding contact within the shielding contact opening and forming a source / body contact within the source / body contact region. In some examples, this may include a conductive region 43B within contact openings 422BA and 422BB, and a conductive region 43A within contact openings 422A and 422C, such as Figure 16 The diagram shows a cross-sectional view of the semiconductor device 30 after further processing. In some examples, conductive regions 43A and 43B may be conductive plugs or plug structures. In some examples, conductive regions 43A and 43B may include conductive barrier structures or linings and conductive filler materials. In some examples, the barrier structure may include a metal / metal-nitride configuration, such as titanium / titanium nitride or other related or equivalent materials known to those skilled in the art. In other examples, the barrier structure may also include a metal silicide structure. Conductive regions 43A and 43B may be formed using vapor deposition, sputtering, CVD, or other processes known to those skilled in the art. In some examples, the conductive filler material includes tungsten. In some examples, conductive regions 43A and 43B may be planarized using a CMP process to provide a more uniform surface morphology.

[0086] The box S395 of method 300A is similar to the box S395 of method 300, and details will not be repeated here. It should be understood that additional processing of the box S395 of method 300A can be used to provide, among other things, […]. Figure 1 The conductive layer 44A and conductive layer 46 shown, as well as the conductive layer 44A and conductive layer 46 Figure 9 The conductive layer 44B is shown. According to this specification, the semiconductor device 30 is an example in which the conductive region 43B extends through the ILD structure 41, the gate electrode 28 and the IPD 27 to a first depth, and in which the dielectric spacer 53B extends through the ILD structure 41, the gate electrode 28 and the IPD 27 to a second depth less than the first depth.

[0087] Figure 17A flowchart of method 300B for providing an electronic device such as a semiconductor device is shown. In some examples, method 300B may be an alternative to method 300 for manufacturing a semiconductor device 10, which will be discussed below. Figures 18 to 22 It is described as a semiconductor device 40.

[0088] The boxes S310 and S320 of method 300B are similar to those of method 300, and the details of the steps will not be repeated here.

[0089] Method 300B, frame S330B, includes forming a first portion of the source / body contact opening by selectively removing a portion of the ILD. In some examples, this includes placing a mask 66 with an opening 66A over the ILD structure 41, such as... Figure 18 The diagram shows a cross-sectional view of the semiconductor device 40 after further processing. Opening 66A corresponds to the location where a conductive region 43A will be formed to provide source / body contacts for the semiconductor device 40. In some examples, mask 66 comprises a photomask and can be formed using photoresist deposition, exposure, and development processes. Next, a portion of the ILD structure 41 can be removed to provide contact opening 422A, which can expose the main surface 18 of the semiconductor material region 11. In some examples, this step also removes any portion of the gate dielectric 26 that may exist above the main surface 18, such as... Figure 18 As shown. It should be understood that the frame S330B can also be used to form a gate contact opening at a predetermined location to provide gate contact with the gate electrode 28.

[0090] Block S340B of method 300B includes forming a first portion of a shielding contact opening by selectively removing portions of the ILD, gate conductor, and IPD. In some examples, this includes providing a mask 64 with an opening 64A over the ILD structure 41, in which a conductive region 43B will be formed to provide shielding contact with the shielding electrode 21, such as... Figure 19 The image shows a cross-sectional view of the semiconductor device 40 after further processing. In some examples, mask 64 includes a photomask and can be formed using photoresist deposition, exposure, and development processes. Next, portions of the ILD structure 41, gate electrode 28, and IPD 27 can be removed to provide a contact opening 422B that exposes the upper surface 21A of the shielding electrode 21. In some examples, dry or wet etching techniques can be used to remove different materials. In some examples, mask 64 can then be removed after providing the contact opening 422B.

[0091] Block S350A of method 300B includes forming an ILD spacer within a first portion of the shielded contact opening and the source / body contact opening. In some examples, this may include forming a dielectric spacer 53A within contact opening 422A and forming a dielectric spacer 53B within contact opening 422B, such as... Figure 20 The diagram shows a cross-sectional view of the semiconductor device 40 after further processing. In some examples, a dielectric is formed to cover the ILD structure 41 and the contact openings 422A and 422B. The thickness of the dielectric is such that the contact openings 422A or 422B are not completely filled. In some examples, the dielectric may comprise oxides, nitrides, other insulating materials known to those skilled in the art, or combinations thereof. The dielectric can be formed using CVD, PECVD, LTO processes, or other processes known to those skilled in the art. After the dielectric is formed, anisotropic etching can be used to remove portions of the dielectric along the upper surface 21A of the shielding electrode 21, the upper surface of the ILD structure 41, and the exposed portions of the main surface 18. The remaining dielectric provides dielectric spacers 53A and 53B, such as Figure 20 As shown.

[0092] Block S360A of method 300B includes removing a portion of the semiconductor substrate using an ILD spacer to form a second portion of the source / body contact opening. In some examples, the second portion of the source / body contact may be contact opening 422C, such as... Figure 21 The diagram shows a cross-sectional view of the semiconductor device 40 after further processing. In some examples, a portion of the semiconductor material region 11 may be removed using a fluorine-based chemical to provide a contact opening 422C extending inward from the main surface 18 aligned with the dielectric spacer 53A. That is, the dielectric spacer 53A is used as a mask to form the contact opening 422C. In some examples, the contact opening 422C extends beyond the source region 33 and terminates in the body region 31 of the semiconductor device 40.

[0093] Block S370A of method 300B is similar to block S380 of method 300, and includes forming a body reinforcement region adjacent to the second source / body contact within a body region of the semiconductor substrate. In some examples, contact regions 36 may be formed within the body region 31 using ion implantation and annealing processes, such as... Figure 21 As shown, these contact areas are configured to enhance the contact characteristics between the main body region 31 and the subsequently formed conductive region 43A.

[0094] Block S380A of method 300B is similar to block S390 of method 300, and includes forming a shielding contact within a shielding contact opening and forming a source / body contact within a source / body contact opening. In some examples, this may include a conductive region 43B within contact opening 422B, and a conductive region 43A within contact openings 422A and 422C, such as Figure 22 The diagram shows a cross-sectional view of the semiconductor device 40 after further processing. In some examples, conductive regions 43A and 43B may be conductive plugs or plug structures. In some examples, conductive regions 43A and 43B may include conductive barrier structures or linings and conductive filler materials. In some examples, the barrier structure may include a metal / metal-nitride configuration, such as titanium / titanium nitride or other related or equivalent materials known to those skilled in the art. In other examples, the barrier structure may also include a metal silicide structure. Conductive regions 43A and 43B may be formed using vapor deposition, sputtering, CVD, or other processes known to those skilled in the art. In some examples, the conductive filler material includes tungsten. In some examples, conductive regions 43A and 43B may be planarized using a CMP process to provide a more uniform surface morphology.

[0095] The box S390A of method 300B is similar to the box S395 of method 300, and details will not be repeated here. It should be understood that additional processing of the box S390A of method 300B can be used to provide, among other things, […]. Figure 1 The conductive layer 44A and conductive layer 46 shown, as well as the conductive layer 44A and conductive layer 46 Figure 9 The conductive layer 44B is shown.

[0096] Figure 23 A top view of a portion of the semiconductor device 50 is shown to further illustrate this configuration. Figure 23 The diagram shows a conductive region 43B, but it should be understood that the semiconductor device 50 may include multiple conductive regions 43B. In some examples, the dielectric spacer 53B completely surrounds or encloses the conductive region 43B. Although the conductive region 43B is shown as a square shape, it should be understood that other shapes, such as circular shapes or shapes with rounded corners, may be used.

[0097] Figure 23 Examples are similar to Figure 2The example differs in that, in this example, the shape of the gate dielectric 26 is non-linear. More specifically, the gate dielectric 26 includes an extension 26A extending laterally away from the conductive region 53B. Thus, the regions 28C of the gate electrode 28 located on either side of the conductive region 43B have widths 280A and 280B, such that when combined, the combined width is closer to the width 280C of the gate electrode 28's 28B. This reduces any effect of the conductive region 43B on the gate resistance. The semiconductor device 50 is another example in which the gate electrode 28 includes a shape surrounding the conductive region 43B in the top view, such that the gate electrode 28 is not interrupted by the conductive region 43B and the dielectric spacer 53B.

[0098] From all the foregoing, those skilled in the art can determine, based on one example, that the spacer includes a second dielectric spacer. In another example, a plurality of first conductive regions are uniformly distributed within the active region. In yet another example, a gate conductive layer is interposed between a gate electrode and an ILD structure, wherein the first conductive regions extend through the gate conductive layer; and the gate conductive layer and the gate electrode comprise different materials. In yet another example, the semiconductor device may include a shielding conductive layer interposed between the first conductive regions and a shielding electrode, wherein the shielding conductive layer and the shielding electrode comprise different materials.

[0099] From all the foregoing, a person skilled in the art can determine, by one example, that the semiconductor device may include an active region; and the first conductive region is one of a plurality of first conductive regions within the active region. In another example, the plurality of first conductive regions are non-uniformly distributed within the active region.

[0100] From all the foregoing, those skilled in the art can determine, by one example, a method of forming a semiconductor device, the method comprising: providing a semiconductor material region having a first main surface and a first conductivity type; providing a shielded gate trench structure including an active trench extending from the first main surface into the semiconductor material region and having a first side and a second side opposite to the first side; a shielded dielectric layer adjacent to a lower portion of the active trench; a shielded electrode adjacent to the shielded dielectric layer in the lower portion of the active trench; a gate dielectric adjacent to an upper portion of the active trench; a gate electrode adjacent to the gate dielectric in the upper portion of the active trench; an inter-pad dielectric (IPD) inserted between the gate electrode and the shielded electrode; and providing a body region, the body... The region has a second conductivity type opposite to the first conductivity type, the main region being located in the semiconductor material region, extending from the main surface adjacent to the first and second sides of the active trench; a source region having the first conductivity type is provided, located in the main region adjacent to the first and second sides of the active trench; an interlayer dielectric (ILD) structure is provided above the first main surface; a first conductive region is provided, located within the active trench and extending through the ILD structure, the gate electrode, and the IPD; and a second conductive region is provided, extending through the ILD structure and the source region, wherein the first conductive region is coupled to the shielding electrode; the first conductive region is electrically isolated from the gate electrode by a first dielectric spacer; and the gate electrode includes a shape in the top view surrounding each side of the first conductive region in the top view.

[0101] In another example, providing the first conductive region may include forming a first contact opening extending through at least a portion of the ILD structure, the gate conductor, and the IPD; forming a first dielectric spacer within the first contact opening; and providing a conductive material adjacent to the first dielectric spacer within the first contact opening. In another example, providing the second conductive region may include forming a second contact opening extending through the ILD structure and the source region; forming a second dielectric spacer within the second contact opening; and providing a conductive material adjacent to the second dielectric spacer within the second contact opening.

[0102] In another example, the formation of the first contact opening and the formation of the first dielectric spacer occur before the formation of the second contact opening.

[0103] In yet another example, the method may further include providing a shielding conductive layer interposed between the first conductive region and the shielding electrode. In another example, the method may include providing a gate conductive layer interposed between the gate electrode and the ILD structure, wherein the first conductive region extends through the gate conductive layer.

[0104] In view of all the foregoing, a novel structure and method are clearly disclosed. Among other features, it includes a semiconductor device with a shielded gate trench gate electrode structure, the contact between which and the shielding electrode is formed by forming an electrically isolated contact via a gate conductor. In some examples, recesses are periodically arranged along the gate conductor structure (such as a striped gate conductor) in a manner that does not interrupt the electrical continuity of the gate conductor structure. More specifically, insulating shielding contact regions are arranged at predetermined locations on the gate conductor structure and may include recesses extending through the gate conductor to the shielding electrode. In a cross-sectional view, a portion of the gate conductor remains on at least one side of the recess. Thus, the gate conductor is only partially interrupted by the shielding conductor. In some examples, in a cross-sectional view, a sufficient amount of gate conductor remains on both sides of the recess. Thus, the gate conductor provides channel control on both sides of the trench containing the source region and the body region. The shielding conductor is then disposed within the recess and isolated from the gate conductor by an insulator. These structures and methods use materials and processes compatible with typical semiconductor wafer fabrication facilities and can be manufactured at low cost.

[0105] The shielding resistance can be tuned to suit specific applications and design requirements. That is, the shielding contacts can be arranged in different patterns, either uniformly or non-uniformly, to provide the desired resistive effect. These structures and methods are cost-effective to implement, requiring only a mask layer and etching step in some examples. It has been empirically found that the structures and methods described in this specification have low shielding resistance, which improves power conversion efficiency in power conversion applications such as buck converters.

[0106] Although the subject matter of the invention has been described in conjunction with specific preferred examples, the foregoing figures and description are merely illustrative examples of the subject matter and should not be construed as limiting the scope of the invention. It will be apparent to those skilled in the art that many alternatives and variations will be readily apparent. For example, the materials used for the gate electrode, shield electrode, gate conductive layer, and shield conductive layer may comprise one or more materials. When multiple materials are used, they may be deposited sequentially to provide a laminated structure. In other examples, a first layer (e.g., a first spacer) may be deposited and patterned, and subsequent layers may be deposited and patterned in a similar manner. The conductive materials used for the gate and shield structures may comprise polycrystalline semiconductor materials, silicides, metals, metal nitrides, quasi-metals, and other conductive materials known to those skilled in the art. Various deposition techniques may be used for the materials, including CVD, PECVD, MOCVD, ALD, and other deposition techniques known to those skilled in the art. Additionally, the spacers described herein may comprise other materials that provide characteristics similar to those described herein. For example, spacer 53A may comprise a polycrystalline semiconductor material, a conductive material, an organic dielectric, a printed film, or other materials known to those skilled in the art.

[0107] As reflected in the claims below, various aspects of the invention may have fewer features than all the features of a single example disclosed above. Therefore, the claims set forth below are expressly incorporated into the detailed description, wherein each claim represents an independent example of the invention. Furthermore, although some examples described herein include some features included in other examples but not all of those features, those skilled in the art should understand that combinations of features from different examples are intended to fall within the scope of the invention and to form different examples.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A semiconductor material region having a first main surface and a first conductivity type; Shielded gate trench structure, the shielded gate trench structure comprising: An active trench extends from the first main surface into the semiconductor material region; A shielding dielectric layer, wherein the shielding dielectric layer is adjacent to the lower part of the active trench; A shielding electrode, wherein the shielding electrode is adjacent to the shielding dielectric layer in the lower part of the active trench; A gate dielectric, wherein the gate dielectric is adjacent to the upper portion of the active trench; A gate electrode, wherein the gate electrode is adjacent to the gate dielectric in the upper portion of the active trench; and Inter-pad dielectric IPD, the IPD being inserted between the gate electrode and the shielding electrode; a body region having a second conductivity type opposite to the first conductivity type, the body region being located in the semiconductor material region adjacent to the shielding gate trench structure extending from the first main surface; A source region having the first conductivity type, the source region being located in the body region adjacent to the shielded gate trench structure; An interlayer dielectric (ILD) structure, wherein the ILD structure is located above the first main surface; and A first conductive region is located within the active trench and extends through the ILD structure, the gate electrode, and the IPD, wherein: The first conductive region is coupled to the shielding electrode; The first conductive region is electrically isolated from the gate electrode by a first dielectric spacer; and The gate electrode includes a shape that surrounds the first conductive region in the top view, such that the gate electrode is not interrupted by the first conductive region and the first dielectric spacer.

2. The semiconductor device according to claim 1, wherein: The first conductive region extends through the ILD structure, the gate electrode, and the IPD to a first depth; and The first dielectric spacer extends through the ILD structure, the gate electrode, and the IPD to a second depth, the second depth being less than the first depth.

3. The semiconductor device according to claim 1, wherein: The first conductive region extends through the ILD structure, the gate electrode, and the IPD to a first depth; and The first dielectric spacer extends to the first depth.

4. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: A second conductive region extends through the ILD structure to the main body region; and A spacer is inserted between the second conductive region and the ILD structure.

5. The semiconductor device according to claim 1, wherein, The semiconductor device also includes an active region; The first conductive region is one of a plurality of first conductive regions.

6. The semiconductor device according to claim 5, wherein: The plurality of first conductive regions are non-uniformly distributed within the active region.

7. A semiconductor device, characterized in that, The semiconductor device includes: A semiconductor material region having a first main surface and a first conductivity type; Shielded gate trench structure, the shielded gate trench structure comprising: An active trench extends from the first main surface into the semiconductor material region and has a first side and a second side opposite to the first side; A shielding dielectric layer, wherein the shielding dielectric layer is adjacent to the lower part of the active trench; A shielding electrode, wherein the shielding electrode is adjacent to the shielding dielectric layer in the lower part of the active trench; A gate dielectric, wherein the gate dielectric is adjacent to the upper portion of the active trench; A gate electrode, wherein the gate electrode is adjacent to the gate dielectric in the upper portion of the active trench; and Inter-pad dielectric IPD, the IPD being inserted between the gate electrode and the shield electrode; a body region having a second conductivity type opposite to the first conductivity type, the body region being located in the semiconductor material region, adjacent to the first side and the second side of the active trench, extending from the first main surface; A source region having the first conductivity type, the source region being located in the body region adjacent to the first side and the second side of the active trench; An interlayer dielectric (ILD) structure is located above the first main surface; A first conductive region, located within the active trench and extending through the ILD structure, the gate electrode, and the IPD; and A second conductive region extends through the ILD structure and the source region, wherein: The first conductive region is coupled to the shielding electrode; The first conductive region is electrically isolated from the gate electrode by a first dielectric spacer; and The gate electrode includes a shape that surrounds each side of the first conductive region in the top view.

8. The semiconductor device according to claim 7, wherein, The semiconductor device further includes: A spacer is inserted between the second conductive region and the ILD structure.

9. The semiconductor device according to claim 8, wherein: The spacer includes a second dielectric spacer; and The first dielectric spacer and the second dielectric spacer comprise the same material.

10. The semiconductor device according to claim 7, wherein, The semiconductor device further includes: A shielding conductive layer, the shielding conductive layer being inserted between the first conductive region and the shielding electrode; and A gate conductive layer is interposed between the gate electrode and the ILD structure, wherein: The first conductive region extends through the gate conductive layer.

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