Display panel and display device

Abstract

The present disclosure provides a display panel and a display device, which relate to the field of display technology. The display panel includes a substrate, the substrate including a display area and a peripheral area surrounding the display area, the display area including a first display area and a second display area, the first display area at least partially surrounding the second display area; a plurality of first pixel circuits located in the first display area; a plurality of second pixel circuits located in the second display area; a plurality of first initialization signal lines located at least in the first display area and extending along a first direction, the first initialization signal lines being electrically connected to the first pixel circuits and configured to transmit a first initial voltage signal to the first pixel circuits; a plurality of second initialization signal lines being located at least in the first display area and the second display area and electrically connected to the second pixel circuits and configured to transmit a second initial voltage signal to the second pixel circuits; the first initial voltage signal and the second initial voltage signal being different.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the increasing demand for display screens, especially mobile phone display screens, installing under-screen camera modules has become the current development trend of display panels.

[0003] For the display panel with an under-screen camera module, the corresponding display area of the under-screen camera module on the display panel can present a picture display when in the display state, and the entire display panel presents a full-screen display effect; when not in the display state, the corresponding display area of the under-screen camera module can be transparent to allow external ambient light to pass through for image capture by the camera module.

[0004] In the prior art, there is a display difference between the corresponding display area of the under-screen camera module and the normal display area, resulting in uneven brightness. Summary of the Invention

[0005] The purpose of the technical solution disclosed in the present invention is to provide a display panel and a display device for solving the problem of display difference between the display area of the under-screen camera module and the normal display area in the display panel of the prior art.

[0006] One embodiment of the present disclosure provides a display panel, including a base substrate, wherein the base substrate includes a display area and a peripheral area at least partially surrounding the display area, the display area includes a first display area and a second display area, and the first display area at least partially surrounds the second display area;

[0007] a plurality of first pixel circuits, located in the first display area;

[0008] a plurality of second pixel circuits, located in the second display area;

[0009] a plurality of first initialization signal lines, located at least in the first display area and extending along a first direction, the first initialization signal lines being electrically connected to the first pixel circuits and configured to transmit first initialization voltage signals to the first pixel circuits;

[0010] Multiple second initialization signal lines are located at least in the first display area and the second display area, and are electrically connected to the second pixel circuit, and are configured to transmit a second initial voltage signal to the second pixel circuit; the first initial voltage signal and the second initial voltage signal are different.

[0011] Optionally, in the display panel, the voltage of the first initial voltage signal is higher than the voltage of the second initial voltage signal.

[0012] Optionally, in the display panel, the second initialization signal line includes a first portion located in the first display area and a second portion located in the second display area, and the second portion is connected to the second pixel circuit.

[0013] Optionally, the display panel further comprises a third initialization signal line; wherein the third initialization signal line at least partially surrounds the second pixel circuit, and the plurality of first initialization signal lines are connected to the third initialization signal line.

[0014] Optionally, the display panel, wherein the third initialization signal is on the same layer as the first part of the second initialization signal located in the first display area, the multiple first initialization signal lines are on the same layer as the second part of the second initialization signal located in the second display area, and the first part and the second part are electrically connected and are on different layers.

[0015] Optionally, in the display panel, the third initialization signal line is located in the first display area or the second display area, and the third initialization signal line is in a closed ring shape.

[0016] Optionally, the display panel further comprises a first initialization bus and a second initialization bus located in the peripheral area, the plurality of first initialization signal lines are connected to the first initialization bus, and the plurality of second initialization signal lines are connected to the second initialization bus.

[0017] Optionally, in the display panel, the first initialization bus is located on a side of the second initialization bus away from the base substrate.

[0018] Optionally, in the display panel, the first initialization bus includes a first sub-line and a second sub-line; the first sub-line and the second sub-line are located on both sides of the display area;

[0019] The second initialization bus includes a third sub-line and a fourth sub-line, and the third sub-line and the fourth sub-line are located at two sides of the display area.

[0020] Optionally, in the display panel, the plurality of first pixel circuits include a plurality of first pixel groups, and the plurality of second pixel circuits include a plurality of second pixel groups;

[0021] In the first display area, different first pixel groups are connected to different first initialization signal lines; and in the second display area, different second pixel groups are connected to different second initialization signal lines.

[0022] Optionally, in the display panel, a plurality of first pixel circuits located in the same first pixel group are arranged in a straight line in sequence along a first direction; and a plurality of second pixel circuits located in the same second pixel group are arranged in a staggered manner along a second direction.

[0023] Optionally, in the display panel, in the first display area, at least part of the plurality of first initialization signal lines and at least part of the plurality of second initialization signal lines are alternately arranged along a second direction; the second direction intersects with the first direction.

[0024] Optionally, in the display panel, the plurality of first pixel circuits and the plurality of second pixel circuits respectively include thin film transistors disposed on the base substrate, and the thin film transistors include an active layer, a gate, and a source / drain electrode sequentially disposed in a direction away from the base substrate;

[0025] The display panel further includes a light shielding layer located between the base substrate and the active layer;

[0026] Wherein, the plurality of first initialization signal lines, the second portion and the gate are made of the same layer and the same material;

[0027] The third initialization signal line, the first part and the active layer are made of the same layer and the same material; or, the third initialization signal line, the first part and the light shielding layer are made of the same layer and the same material; or, the third initialization signal line, the first part and the source / drain layer are made of the same layer and the same material.

[0028] Optionally, in the display panel, the first portion and the second portion are electrically connected via a first connection layer, and the plurality of first initialization signal lines and the third initialization signal line are electrically connected via a second connection layer;

[0029] The first connecting layer and the second connecting layer are made of the same layer and the same material.

[0030] Optionally, in the display panel, the first connection layer, the second connection layer and the source / drain are made of the same layer and the same material.

[0031] Optionally, in the display panel, the plurality of first initialization signal lines and the plurality of second initialization signal lines are electrically connected to the source / drain of the thin film transistor, respectively.

[0032] Optionally, in the display panel, the second display area is a light-transmitting display area, and the density of the plurality of second pixel circuits provided in the second display area is less than or equal to the density of the plurality of first pixel circuits provided in the first display area.

[0033] Optionally, in the display panel, the display area further comprises a plurality of auxiliary signal lines located in the first display area and extending along the first direction;

[0034] The plurality of auxiliary signal lines are not connected to any first pixel circuit and any second pixel circuit.

[0035] Optionally, in the display panel, the auxiliary signal line and a portion of the second initialization signal line are made of the same layer and the same material.

[0036] An embodiment of the present disclosure further provides a display device, comprising a display panel as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 Schematic diagram of the planar structure of the display panel according to the embodiment of the present disclosure;

[0039] Figure 2 This is one of the schematic diagrams of the arrangement structure of the first initialization signal line and the second initialization signal line in the display panel according to the embodiment of the present disclosure;

[0040] Figure 3 This is a second schematic diagram of the configuration structure of the first initialization signal line and the second initialization signal line in the display panel according to the embodiment of the present disclosure;

[0041] Figure 4 1 is a schematic structural diagram of a pixel circuit according to one embodiment of the present disclosure;

[0042] Figure 5 Schematic diagram of the structure of a pixel circuit in another embodiment of the present disclosure;

[0043] Figure 6 Schematic diagram of the structure of a pixel circuit in another embodiment of the present disclosure;

[0044] Figure 7 This is a schematic diagram of an enlarged structure of a display panel in an embodiment of the present disclosure;

[0045] Figure 8 Schematic diagram of the cross-sectional structure of a pixel circuit of a display panel in an embodiment of the present disclosure;

[0046] Figure 9is a schematic plan view of a portion of the structure of the peripheral area of a display panel;

[0047] Figures 10A to 10H FIG. 1 is a plan view schematically showing the process of the second pixel circuit in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] In order to make the technical problems, technical solutions and advantages to be solved by the present disclosure clearer, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0049] In order to solve the problem that in the display panel with an under-screen camera module in the prior art, the display area corresponding to the under-screen camera module is displayed differently from the normal display area due to the compression of the pixel circuit, the embodiment of the present disclosure provides a display panel, by connecting the pixel circuit set in the normal display area and the pixel circuit set in the display area corresponding to the under-screen camera module to different initialization signal lines, respectively. In this way, different initialization signal lines can be used to reset the pixel circuit to ensure the consistency of the switching degree of the driving units of different pixel circuits, thereby avoiding the display difference problem in different areas.

[0050] The display panel of the embodiment of the present disclosure includes a base substrate, such as Figure 1 As shown, the base substrate 1 includes a display area 10 and a peripheral area 20 at least partially surrounding the display area 10. The display area 10 includes a first display area 11 and a second display area 12 adjacent to each other. The arrangement structure of the first display area 11 and the second display area 12 can be as follows: Figure 1 shown.

[0051] Optionally, the second display area 12 is formed as a translucent display area. When the display panel is installed on an electronic device, a photosensitive element such as a camera or a sensor can be installed inside the electronic device at a position corresponding to the second display area 12, which is used to capture images through the second display area 12, forming an under-screen camera display structure.

[0052] Optionally, the first display area 11 is the normal display area of the display panel for displaying images. The first display area 11 is at least partially arranged around the second display area 12. The first display area 11 and the second display area 12 are combined to form the entire display area of the display panel. In one embodiment, the entire display area of the display panel can be a light-transmitting display area, or only the second display area 12 is a light-transmitting display area of the display panel for image acquisition by the under-screen camera. Optionally, the display panel is an OLED display panel.

[0053] The display panel of the embodiment of the present disclosure is provided with a plurality of pixel circuits on the base substrate 1. Figure 2 and Figure 3As shown, the first display area 11 is provided with a plurality of first pixel circuits 111, and the second display area 12 is provided with a plurality of second pixel circuits 121. The density of the plurality of second pixel circuits 121 in the second display area 12 is the same as or different from the density of the plurality of first pixel circuits 111 in the first display area 11. For example, the density of the plurality of second pixel circuits 121 in the second display area 12 is less than or equal to the density of the plurality of first pixel circuits 111 in the first display area 11. Of course, the density of the plurality of second pixel circuits 121 in the second display area 12 may also be greater than the density of the plurality of first pixel circuits 111 in the first display area 11.

[0054] Optionally, when the density of the plurality of second pixel circuits 121 in the second display area 12 is less than the density of the plurality of first pixel circuits 111 in the first display area 11, by reducing the pixel distribution density in the second display area 12, the transmittance of the second display area 12 can be improved to meet the image acquisition requirements of the under-screen camera. Figure 2 and Figure 3 As shown, in the embodiment of the present disclosure, on the base substrate 1, a plurality of first pixel circuits 111 provided in the first display area 11 and a plurality of second pixel circuits 121 provided in the second display area 12 are respectively distributed in an array. Optionally, the plurality of first pixel circuits 111 and the plurality of second pixel circuits 121 respectively include a driving unit and a light-emitting unit sequentially provided on the base substrate 1. Among them, in the direction perpendicular to the base substrate 1, one driving unit corresponds to one light-emitting unit. In the embodiment of the present disclosure, the driving unit refers to a structural unit including a thin film transistor, a capacitor and other auxiliary transistors that can drive the corresponding light-emitting unit to emit light. The circuit principle structure of the driving unit can be as follows Figure 4 As shown, it is formed into a 2T1C pixel driving circuit, and can also be formed as Figure 5 The 7T1C circuit shown can of course also be a circuit of other structures, such as an 8T1C circuit, etc. The specific implementation structure of the driving unit is not limited here.

[0055] See Figure 6 As shown, combined with Figures 2 to 5In the first display area 11 and the second display area 12, a plurality of gate lines 2 and a plurality of data lines 3 are further provided on the substrate 1. The plurality of gate lines 2 and the plurality of data lines 3 are insulated and cross-linked to define a plurality of array areas. Each array area corresponds to a first pixel circuit or a second pixel circuit, and each array area is provided with a driving unit. The plurality of driving units located in the same pixel row are each connected to a gate line 2, and the plurality of driving units located in the same pixel column are each connected to a data line 3. Each gate line 2 is also connected to a scan driving circuit. A scan signal Scan is input to each gate line 2 via the scan driving circuit, and a data signal Data is input to each data line 3 via the data driving circuit.

[0056] Combine Figure 4 and Figure 6 As shown, taking the driving unit formed as a 2T1C pixel driving circuit as an example, the gate line 2 and the data line 3 are connected to the first transistor T1 of the driving unit, the first transistor T1 is connected to the second transistor T2, and the second transistor T2 is connected to the light emitting unit L1.

[0057] Specifically, each gate line 2 is connected to a scan driver circuit, which outputs a scan signal Scan to the control terminal of the first transistor T1 via the gate line 2. Each data line 3 is connected to the data driver circuit, which outputs a data signal Data to the first terminal of the first transistor T1 via the data line 3. The second terminal of the first transistor T1 is connected to the control terminal of the second transistor T2 and the first terminal of the first capacitor Cs, respectively. The second terminal of the first capacitor Cs is connected to the first terminal of the second transistor T2 and is connected to the first power signal VDD. The second terminal of the second transistor T2 is connected to the anode of the light-emitting unit L1, and the cathode of the light-emitting unit L1 is connected to the second power signal VSS. In this embodiment, the scan signal Scan is output by the scan driver circuit via the gate line 2 to the control terminal of the first transistor T1 in a time-sharing manner. The data signal Data output by the data driver circuit via the data line 3 is input to the control terminal of the second transistor T2, thereby controlling the light-emitting unit L1 to emit light according to a preset timing.

[0058] Combine Figure 4As shown, in the driving unit, the first end of the driving transistor (second transistor T2) that drives the light-emitting unit L1 to emit light is connected to the first power signal VDD, and the cathode of the light-emitting unit L1 is connected to the second power signal VSS. The first power signal VDD and the second power signal VSS are respectively used to provide constant voltage signals, and the voltage of the first power signal VDD is greater than the voltage of the second voltage signal. In this way, the light-emitting unit L1 can emit light by utilizing the voltage difference between the first power signal VDD and the second power signal VSS. Optionally, on the entire display panel, in multiple driving units located in the same pixel row, the first power signal VDD is connected through one signal line, and the second power signal VSS is connected through another signal line. In this way, the first power signal VDD and the second power signal VSS can be input simultaneously to the multiple driving units located in the same pixel row. Combined Figure 2 and Figure 3 As shown, in the embodiment of the present disclosure, a plurality of initialization signal lines are further provided on the base substrate 1 , and the initialization signal lines are connected to the driving units of the display area and are used to input initial voltage signals to the connected driving units.

[0059] Combine Figure 5 and Figure 6 As shown, when the driving unit is formed as a 7T1C pixel driving circuit, the pixel driving circuit includes a first transistor T1 to a seventh transistor T7 and a first capacitor Cs; wherein, the pixel driving circuit is connected to the scan line GL, the data line DL, the first power signal VDD, the second power signal VSS, the light emitting control line EML, the reset control line RST and the initial signal line INIT respectively. The scan line GL also corresponds to Figure 6 The gate line 2 is used to provide a scan signal SCAN to the pixel circuit; the data line DL also corresponds to Figure 6 The data line 3 is used to provide a data signal DATA to the pixel circuit, and the light-emitting control line EML is used to provide a reset control signal RESET to the pixel circuit; the first power signal VDD and the second power signal VSS are respectively used to provide constant voltage signals, and the voltage of the first power signal VDD is greater than the voltage of the second voltage signal.

[0060] In the pixel circuit of this embodiment, the third transistor T3 is formed as a driving transistor of the light-emitting unit EL, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are respectively formed as switching transistors. Different signal inputs from the scan line GL, the data line DL, the emission control line EML, the reset control line RST, and the initial signal line INIT are used to control the light-emitting unit EL to emit light according to a preset timing to achieve image display.

[0061] Combine Figure 1 、 Figure 2 and Figure 3 As shown, in the embodiment of the present disclosure, when the base substrate 1 includes a first display area 11 and a second display area 12, and the density of the plurality of second pixel circuits 121 provided in the second display area 12 is less than or equal to the density of the plurality of first pixel circuits 111 provided in the first display area 11, in order to adapt to the density setting requirements of the plurality of second pixel circuits 121 on the second display area 12 and meet the transmittance requirements of the second display area 12, the distribution area of a second pixel circuit 121 on the second display area 12 is less than or equal to the distribution area of a first pixel circuit 111 on the first display area 11. Therefore, compared with the first display area 11, the pixel circuits in the second display area 12 are compressed. Figure 4 and Figure 5 As shown, the compression of the pixel circuit on the second display area 12 will cause the first capacitor Cs (also known as the storage capacitor Cst) to decrease, making the stability of the pixel circuit worse and the switching degree of the thin film transistor reduced, thereby causing differences in the display effects between the first display area 11 and the second display area 12.

[0062] To solve this technical problem, the display panel described in the embodiment of the present disclosure is as follows: Figure 2 、 Figure 3 and Figure 7 As shown, the base substrate 1 is also provided with:

[0063] The plurality of first initialization signal lines 200 are at least located in the first display area 11 and extend along a first direction (eg Figure 2 wherein the first initialization signal line 200 is connected to the first pixel circuit 111 and is configured to transmit a first initialization voltage signal to the first pixel circuit 111;

[0064] a plurality of second initialization signal lines 300 , located at least in the first display area 11 and the second display area 12 , and electrically connected to the second pixel circuit 121 , and configured to transmit a second initialization voltage signal to the second pixel circuit 121 ;

[0065] The first initial voltage signal and the second initial voltage signal are different.

[0066] In the embodiment of the present disclosure, a first initialization signal line 200 for inputting an initial voltage signal for a plurality of first pixel circuits 111 of the first display area 11 and a second initialization signal line 300 for inputting an initial voltage signal for a plurality of second pixel circuits 121 of the second display area 12 are arranged independently and input different initial voltage signals to provide different initial voltage signals to the first pixel circuits 111 of the first display area 11 and the second pixel circuits 121 of the second display area 12. Optionally, the voltage of the first initial voltage signal input to the first initialization signal line is higher than the voltage of the second initial voltage signal input to the second initialization signal line, so as to correct the difference in display effects between the first display area 11 and the second display area 12.

[0067] In the disclosed embodiment, first initialization signal line 200 and second initialization signal line 300 can optionally be signal lines capable of inputting a stable voltage signal to the connected pixel circuits. First initialization signal line 200 and second initialization signal line 300 are connected to different pixel circuits. Alternatively, they can be signal lines that input an initialization voltage; in another embodiment, they can each be a signal line that inputs a constant voltage.

[0068] In the embodiment of the present disclosure, optionally, as Figure 3 and Figure 7 As shown, the display panel further includes a third initialization signal line 400 , wherein the third initialization signal line 400 at least partially surrounds the second pixel circuit 121 , and the plurality of first initialization signal lines 200 are connected to the third initialization signal line 400 .

[0069] Combine Figure 3 As shown, multiple first initialization signal lines 200 extend from a first edge of the substrate 1 to a second edge of the substrate 1 along a first direction X, with the second edge being opposite the first edge. In the disclosed embodiment, by providing a third initialization signal line 400 around the second pixel circuit 121, when the first initialization signal line 200 extends along the first direction X to the edge of the second display area 12, the first initialization signal line 200 can continue to extend toward the second edge of the substrate 1 by connecting to the third initialization signal line 400. This allows the first initialization signal line 200 to connect to a greater number of first pixel circuits 111 between the first and second edges, thereby simplifying the wiring and manufacturing process.

[0070] Optionally, in the embodiment of the present disclosure, if Figure 3 As shown, among the plurality of first initialization signal lines 200 provided on the first display area 11 , the plurality of first initialization signal lines 200 extending along the first direction X to the edge of the second display area 12 are respectively connected to the third initialization signal lines 400 .

[0071] Optionally, the third initialization signal line 400 is located in the first display area 11 or the second display area 12, and the third initialization signal line 400 located in the first display area 11 or the second display area 12 is arranged around all the second pixel circuits 121. In one embodiment, Figure 2 and Figure 3 As shown, when the first display area 11 is arranged around the second display area 12 , the third initial signal line 400 goes around the edge of the second display area 12 and surrounds all the second pixel circuits 121 inside to form a closed ring.

[0072] In this embodiment, optionally, a plurality of first initialization signal lines 200 are respectively provided on two opposite sides of the third initialization signal line 400 .

[0073] Based on the set third initialization signal line 400, refer to Figure 2 、 Figure 3 and Figure 7 As shown, multiple second initialization signal lines 300 extend along the first direction X on the base substrate 1, from a first edge of the base substrate 1 toward the opposite second edge, and are divided into at least two parts by the third initialization signal line 400, including a first part 310 located in the first display area 11 and a second part 320 located in the second display area 12; wherein the second part 320 is connected to the second pixel circuit 121.

[0074] Alternatively, as Figure 3 and Figure 7 As shown, the first display area 11 is arranged around the second display area 12, and the third initial signal line 400 surrounds the edge of the second display area 12 to form a closed ring structure. Each second initialization signal line 300 includes a second part 320 and a first part 310 located on both sides of the second part 320, and is connected to the second pixel circuit 121 through the second part 320.

[0075] In the embodiment of the present disclosure, optionally, as Figure 2 As shown, the plurality of first pixel circuits 111 include a plurality of first pixel groups 1111 , and the plurality of second pixel circuits 121 include a plurality of second pixel groups 1211 ;

[0076] In the first display area 11 , different first pixel groups 1111 are connected to different first initialization signal lines 200 ; and in the second display area 12 , different second pixel groups 1211 are connected to different second initialization signal lines 300 .

[0077] In the embodiment of the present disclosure, a plurality of first pixel circuits 111 located in the first display area 11 and connected to the same first initialization signal line 200 can form a first pixel group 1111. Figure 2As shown, the multiple first pixel circuits 111 of a first pixel group 1111 can be formed into a structure arranged along the first direction X, but is not limited to a straight line arrangement. Adjacent first pixel circuits 111 can also be staggered. Similarly, the multiple second pixel circuits 121 located in the second display area 12 and connected to the same second initialization signal line 300 can form a second pixel group 1211. The multiple second pixel circuits 121 of a second pixel group 1211 can also be formed into a structure arranged along the first direction X, but is not limited to a straight line arrangement. Adjacent second pixel circuits 121 can be staggered.

[0078] The display panel of the embodiment of the present disclosure may optionally be as follows: Figure 2 、 Figure 3 and Figure 7 As shown, in the first display area 11 , at least part of the plurality of first initialization signal lines 200 and at least part of the plurality of second initialization signal lines 300 are alternately arranged along the second direction Y; the second direction Y intersects the first direction X.

[0079] Optionally, the second direction Y is perpendicular to the first direction X.

[0080] like Figure 2 and Figure 3 As shown, optionally, in a portion of the first display area 11, an auxiliary signal line 500 is further provided between two adjacent first initialization signal lines 200. The auxiliary signal line 500 is located between two adjacent first pixel groups in the first display area 11 and is not connected to any first pixel circuit 111 or any second pixel circuit 121. In this embodiment, on the base substrate 1, a plurality of second initialization signal lines 300 are provided for a first portion of the first display area 11 located on both sides of the second display area 12, for connecting to the second pixel circuit 121 of the second display area 12. A plurality of auxiliary signal lines 500 are provided for a second portion of the first display area 11 other than the first portion. The auxiliary signal lines 500 are not connected to any first pixel circuit 111 or any second pixel circuit 121, extend in a direction parallel to the first initialization signal lines 200, and are manufactured using the same patterning process as the second initialization signal lines 300, thereby simplifying the manufacturing process.

[0081] In the embodiment of the present disclosure, optionally, the third initialization signal 400 is on the same layer as the first part 310 of the second initialization signal line 300 located in the first display area 11, the multiple first initialization signal lines 200 are on the same layer as the second part 320 of the second initialization signal line 300 located in the second display area 12, and the first part 310 and the second part 320 are electrically connected and are on different layers.

[0082] The following combination Figure 7 and Figure 8 , an example is given of the connection structure between the first initialization signal line 200 and the second initialization signal line 300 and the pixel circuit on the display panel in the embodiment of the present disclosure.

[0083] Take the display panel as a top-emitting OLED display panel as an example. Figure 8 As shown in Figure 10, combined with Figure 2 、 Figure 3 and Figure 4 In the first display area 11 and the second display area 12, the first pixel circuit 111 and the second pixel circuit 121 respectively include a thin film transistor, a light-emitting element, and a capacitor. The thin film transistor has a gate G, a source S, and a drain D. The first capacitor Cs includes a first electrode ED1 and a second electrode ED2. The active layer P-Si of the thin film transistor is located between the buffer layer 510 and the first gate insulating layer 520 and is connected to the source S and drain D. The interlayer insulating layer 540 is located between the gate G and the source S and drain D. The first gate insulating layer 520 is located on the side of the interlayer insulating layer 540 facing the base substrate 110. The second gate insulating layer 530 is located between the interlayer insulating layer 540 and the first gate insulating layer 520. The first electrode ED1 of the capacitor is provided on the same layer as the gate G of the thin film transistor, and the second electrode ED2 of the capacitor is provided between the interlayer insulating layer 540 and the second gate insulating layer 530.

[0084] Optionally, the first pixel circuit 111 and the second pixel circuit 121 further include a passivation layer 1901, a first planar layer 1902, a switching electrode 1903, and a second planar layer 1904, respectively. The passivation layer 1901 is located on the side of the interlayer dielectric layer 540 away from the base substrate 1. The first planar layer 1902 is located on the side of the passivation layer 1901 away from the base substrate 1. The switching electrode 1903 is located on the side of the first planar layer 1902 away from the base substrate 1 and is connected to the source electrode S of the thin film transistor through vias provided in the first planar layer 1902 and the passivation layer 1901. The second planar layer 1904 is provided on the side of the switching electrode 1903 away from the base substrate 1 and at least partially covers the switching electrode 1903.

[0085] The light-emitting element includes an anode 1906, a light-emitting layer 1907, and a cathode 1908. A pixel-defining layer 1905 is located on the side of the second planar layer 1904 away from the substrate 1. Anode 1906 is located on the side of the transition electrode 1903 away from the substrate 1 and is connected to the transition electrode 1903. A light-emitting layer 1907 is located on the side of the anode 1906 away from the substrate 1 and partially covers the anode 1906. A cathode 1908 is located on the side of the light-emitting layer 1907 away from the substrate 1.

[0086] Optionally, the first pixel circuit 111 and the second pixel circuit 121 may further include an encapsulation layer 1909, respectively, located on the side of the cathode 1908 away from the substrate 1. In some embodiments, the encapsulation layer 1909 may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked in sequence.

[0087] In one embodiment, optionally, the first pixel circuit 111 and the second pixel circuit 121 may further include a light-shielding layer 1910, respectively, located between the base substrate 1 and the active layer P-Si. The light-shielding layer 1910 is projected onto the plane where the light-emitting layer 1907 is located, and can cover the light-emitting layer to prevent light from passing through one side of the base substrate 1.

[0088] In the embodiment of the present disclosure, optionally, the third initialization signal line 400 and the first part 310 of the second initialization signal line 300 are made of the same layer and material as the active layer P-Si, the light shielding layer 1910 or the source S / drain D, and the first initialization signal line 200 and the second part 320 of the second initialization signal line 300 are made of the same layer and material as the gate G.

[0089] The third initialization signal line 400 and the first portion 310 of the second initialization signal line 300 are made of the same layer and material as the light shielding layer 1910 , so that the light shielding layer 1910 can be used as a signal line.

[0090] Optionally, the first part 310 and the second part 320 of the second initialization signal line 300 are electrically connected through the first connection layer 330, and the first initialization signal line 200 and the third initialization signal line 400 are electrically connected through the second connection layer 340; wherein, the first connection layer 330 and the second connection layer 340 are made of the same layer and the same material; optionally, the first connection layer 330 and the second connection layer 340 are respectively made of the same layer and the same material as the source S / drain D.

[0091] Combine Figure 8As shown, the third initialization signal line 400 and the first portion 310 of the second initialization signal line 300 are made of the same layer and material as the light shielding layer 1910, and the first initialization signal line 200 and the second portion 320 of the second initialization signal line 300 are made of the same layer and material as the gate G. Optionally, via holes can be made on the interlayer insulating layer 540, the second gate insulating layer 530 and the first gate insulating layer 520, respectively, to expose the third initialization signal line 400 made of the same layer as the light shielding layer 1910P-Si and the first initialization signal line 200 made of the same layer and material as the gate G, respectively, to expose the third initialization signal line 400 made of the same layer as the light shielding layer 1910P-Si and the first initialization signal line 200 made of the same layer and material as the gate G, and to expose the third initialization signal line 400 made of the same layer as the light shielding layer 1910P-Si and the first initialization signal line 200 made of the same layer and material as the gate G. The first connection layer made of the same material can connect the first initialization signal line 200 and the third initialization signal line 400; and by making vias on the interlayer dielectric layer 540, the second gate insulation layer 530 and the first gate insulation layer 520, the first part 310 of the second initialization signal line 300 made of the same layer and material as the light-shielding layer 1910 and the second part 320 of the second initialization signal line 300 made of the same layer and material as the gate G are exposed respectively, and the second connection layer made of the same layer and material as the source S / drain D can connect the first part 310 and the second part 320 of the second initialization signal line 300.

[0092] Similarly, when the third initialization signal line 400 and the first part 310 of the second initialization signal line 300 are made of the same layer and material as the light-shielding layer 1910 or the source S / drain D, and the first initialization signal line 200 and the second part 320 of the second initialization signal line 300 are made of the same layer and material as the gate G, by making vias, the first initialization signal line 200 and the third initialization signal line 400 can also be connected through the first connecting layer, and the first part 310 and the second part 320 of the second initialization signal line 300 can be connected through the second connecting layer. Each implementation method will not be described in detail here.

[0093] In one embodiment of the present disclosure, Figure 5As shown, optionally, the first initialization signal line 200 is used to input an initialization signal to the thin-film transistor of the connected first pixel circuit 111, and the second initialization signal line 300 is used to input an initialization signal to the thin-film transistor of the connected second pixel circuit 121. The first initialization signal line 200 is connected to the source / drain layer of the thin-film transistor of the first pixel circuit 111, and the second portion 320 of the second initialization signal line 300 is connected to the source / drain layer of the thin-film transistor of the second pixel circuit 121. Using the display panel described in this embodiment, the first pixel circuit 111 provided in the first display area 11 and the second pixel circuit 121 provided in the second display area 12 are connected to different initialization signal lines. This allows different initialization signal lines to be used to reset the pixel circuits in different areas. Optionally, multiple first initialization signal lines 200 are connected to one voltage source, and multiple second initialization signal lines 300 are connected to another voltage source. Different voltage sources provide the input initial voltages to the first initialization signal lines 200 and the second initialization signal lines 300, respectively.

[0094] It should be noted that in the embodiments of the present disclosure, the first initialization signal line 200 and the second initialization signal line 300 are not limited to being signal lines used only to provide an initialization voltage. Any signal line on the display panel that provides a stable voltage and is connected to a row of pixel circuits can employ the arrangement of the initialization signal lines of this embodiment. For example, the first initialization signal line 200 and the second initialization signal line 300 can also be signal lines used to input the first power supply signal VDD.

[0095] Combine Figure 4 As shown, for example, when the first initialization signal line 200 and the second initialization signal line 300 are respectively signal lines for inputting the first power signal VDD to the driving transistor of the connected driving unit, each first initialization signal line 200 is respectively connected to the first ends of multiple driving transistors on one pixel row in the first display area 11, and is used to input the first power signal VDD, such as the first voltage value, to the first end of the connected driving transistor; each second initialization signal line 300 is respectively connected to the first ends of multiple driving transistors on one pixel row in the second display area 12, and is used to input the first power signal VDD, such as the second voltage value, to the first end of the connected driving transistor; optionally, the first voltage value is different from the second voltage value.

[0096] The display panel described in the embodiment of the present disclosure connects the pixel circuit set in the normal display area and the pixel circuit set in the display area corresponding to the under-screen camera module to different initialization signal lines, respectively. In this way, different initialization signal lines can be used to reset the voltage of the pixel circuit to ensure the consistency of the switching degree of the driving units of the pixel circuits in different display areas, thereby avoiding the display difference problem in different areas.

[0097] The display panel of the embodiment of the present disclosure is combined with Figure 1 、 Figure 3 and Figure 9 As shown, the display panel also includes a first initialization bus 600 and a second initialization bus 700 located in the peripheral area 20, wherein a plurality of first initialization signal lines 200 are connected to the first initialization bus 600, and a plurality of second initialization signal lines 300 are connected to the second initialization bus 700, for inputting different initial voltage signals to the first initialization signal lines 200 and the second initialization signal lines 300 respectively through the first initialization bus 600 and the second initialization bus 700.

[0098] In the embodiment of the present disclosure, Figure 3 and Figure 9 As shown, optionally, the first initialization bus 600 is located on a side of the second initialization bus 700 away from the substrate.

[0099] Optionally, in the display panel, the first initialization bus 600 includes a first sub-line 610 and a second sub-line 620; the first sub-line 610 and the second sub-line 620 are respectively located on both sides of the display area;

[0100] The second initialization bus 700 includes a third sub-line 710 and a fourth sub-line 720 , and the third sub-line 710 and the fourth sub-line 720 are located at two sides of the display area.

[0101] In the embodiments of the present disclosure, optionally, one implementation method, such as Figure 9 As shown, in the peripheral area 200, the first initialization bus 600 includes multiple connection terminals, some of which are connected to the first initialization signal line 200 for inputting voltage signals to the first initialization signal line 200, and some of which are connected to the gate line 2 for inputting voltage signals to the gate line.

[0102] In this embodiment, the first initialization bus 600 and the second initialization bus 700 are respectively provided on both sides of the display area, for connecting to the first initialization signal line 200 or the second initialization signal line 300 on both sides of the display area.

[0103] Alternatively, as Figure 9 As shown, a plurality of switching blocks 800 are provided inside the first initialization bus 600 and the second initialization bus 700 , respectively, for switching the gate lines or the light emitting control lines EML of the pixel circuit.

[0104] The display panel described in the embodiment of the present disclosure can ensure that the resolution (PPI) of different display areas of the display panel is consistent by setting multiple second pixel circuits 121 on the second display area 12, and can improve the light transmittance of the translucent display area.

[0105] In order to clearly explain the structure of the plurality of second pixel circuits 121 on the second display area 12 and the setting method of the initialization signal line on the second display area, the following is combined with FIG. 10A to FIG. 1 0I describes the structure of the second pixel circuit 121.

[0106] In some exemplary embodiments, the second pixel circuit 121 includes at least one first-type transistor, at least one second-type transistor, and at least one storage capacitor. For example, the second pixel circuit 121 may have an 8T1C (eight transistors and one capacitor) structure. In a direction perpendicular to the substrate, the multiple second pixel circuits 121 on the second display area 12 may include a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer disposed on the substrate. The first semiconductor layer includes at least an active layer of the first-type transistor of the second pixel circuit 121. The first conductive layer includes at least a control electrode of the first-type transistor of the second pixel circuit 121 and a first electrode of the storage capacitor. The second conductive layer includes at least a second electrode of the storage capacitor of the second pixel circuit 121. The second semiconductor layer includes at least an active layer of the second-type transistor of the second pixel circuit 121. The third conductive layer includes at least a control electrode of the second-type transistor of the second pixel circuit 121. The fourth conductive layer includes at least a plurality of connecting electrodes.

[0107] In some exemplary embodiments, the second pixel circuit 121 includes: multiple transistors and at least one storage capacitor. For example, the second pixel circuit 121 can be a 7T1C or 5T1C structure. In a direction perpendicular to the substrate, the second pixel circuit 121 includes: a first semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer arranged on the substrate. The first semiconductor layer includes at least: an active layer of multiple transistors of the second pixel circuit 121. The first conductive layer includes at least: control electrodes of the multiple transistors of the second pixel circuit 121 and a first electrode of the storage capacitor. The second conductive layer includes at least: a second electrode of the storage capacitor of the second pixel circuit 121. The third conductive layer includes at least: multiple connecting electrodes.

[0108] Figure 10A FIG. 1 is a partial plan view of the first display area after forming the first semiconductor layer according to at least one embodiment of the present disclosure. In some exemplary embodiments, Figure 10AAs shown, the first semiconductor layer of the second display area may include: active layers of multiple first-type transistors of the second pixel circuit, for example, active layer T10 of the first transistor T1, active layer T20 of the second transistor T2, active layer T30 of the third transistor T3, active layer T40 of the fourth transistor T4, active layer T50 of the fifth transistor T5, active layer T60 of the sixth transistor T6, and active layer T70 of the seventh transistor T7. The active layers T10 of the first transistor T1 to T70 of the seventh transistor T7 of the second pixel circuit may be interconnected and integrated.

[0109] In some exemplary embodiments, the material of the first semiconductor layer may include, for example, polysilicon. The active layer may include at least one channel region and multiple doped regions. The channel region may not be doped with impurities and have semiconductor properties. Multiple doped regions may be on both sides of the channel region and are doped with impurities, thereby having conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. Portions of the active layer between transistors may be interpreted as impurity-doped wiring that can be used to electrically connect the transistors.

[0110] Figure 10B FIG. 1 is a partial plan view of the second display area after forming the first conductive layer according to at least one embodiment of the present disclosure. Figure 10B As shown, the first conductive layer of the second display area may include: control electrodes of multiple first-type transistors of the second pixel circuit (for example, the control electrode T13 of the first transistor T1, the control electrode T23 of the second transistor T2, the control electrode T33 of the third transistor T3, the control electrode T43 of the fourth transistor T4, the control electrode T53 of the fifth transistor T5, the control electrode T63 of the sixth transistor T6, and the control electrode T73 of the seventh transistor T7), a first electrode C1-1 of the first storage capacitor C1 of the second pixel circuit, a reset connection line 201, a first scan connection line 202, and a light-emitting connection line 203. The reset connection line 201, the first scan connection line 202, and the light-emitting connection line 203 all extend along the first direction X and are arranged sequentially along the second direction Y.

[0111] In some exemplary embodiments, Figure 10BAs shown, the first electrode C1-1 of the first storage capacitor C1 and the control electrode T33 of the third transistor T3 can be an integrated structure, for example, a rectangular shape. The control electrode T23 of the second transistor T2, the control electrode T43 of the fourth transistor T4, the control electrode T73 of the seventh transistor T7, and the first scan connection line 202 can be an integrated structure. The control electrode T53 of the fifth transistor T5, the control electrode T63 of the sixth transistor T6, and the light-emitting connection line 203 can be an integrated structure. The control electrode T13 of the first transistor T1 and the reset connection line 201 can be an integrated structure. However, this embodiment is not limited to this.

[0112] Figure 10C FIG. 1 is a partial plan view of the second display area after forming the second conductive layer according to at least one embodiment of the present disclosure. In some exemplary embodiments, as Figure 10C As shown, the second conductive layer of the second display area may include: an initial connection line 302, a second scan connection line 301, and the second electrode C1-2 of the first storage capacitor C1. The second scan connection line 301 and the initial connection line 302 both extend along the first direction X. The orthogonal projection of the initial connection line 302 on the substrate is located on a side of the orthogonal projection of the control electrode T13 of the first transistor T1 on the substrate, away from the orthogonal projection of the control electrode T23 of the second transistor T2 on the substrate, in the second direction Y. The orthogonal projection of the second scan connection line 301 on the substrate is located between the orthogonal projection of the control electrode T23 of the second transistor T2 on the substrate and the orthogonal projection of the second electrode C1-2 of the first storage capacitor C1 on the substrate. The orthogonal projection of the second electrode C1-2 of the first storage capacitor C1 on the substrate partially overlaps with the orthogonal projection of the first electrode C1-1 on the substrate. For example, the orthogonal projection of the second electrode C1-2 of the first storage capacitor C1 on the substrate may be L-shaped. However, this embodiment is not limited to this.

[0113] Figure 10D FIG. 1 is a partial plan view of the second display region after forming the second semiconductor layer according to at least one embodiment of the present disclosure. In some exemplary embodiments, as Figure 10D As shown, the second semiconductor layer of the second display area may include: an active layer of the second type transistor of the second pixel circuit, for example, the active layer T80 of the eighth transistor T8. The active layer T80 of the eighth transistor T8 extends along the second direction Y. The orthographic projection of the active layer T80 of the eighth transistor T8 on the substrate overlaps the orthographic projection of the second scan connection line 301 on the substrate. In this exemplary embodiment, the material of the second semiconductor layer may include a metal oxide, such as indium gallium zinc oxide (IGZO).

[0114] Figure 10EFIG. 1 is a partial plan view of the second display area after forming the third conductive layer according to at least one embodiment of the present disclosure. Figure 10E As shown, the third conductive layer of the second display area may include: a control electrode of the second type transistor of the second pixel circuit, for example, the control electrode T83 of the eighth transistor T8. The control electrode T83 of the eighth transistor T8 extends along the first direction X. The orthographic projection of the control electrode T83 of the eighth transistor T8 on the substrate overlaps with the orthographic projection of the active layer T80 of the eighth transistor T8 on the substrate. The second scan connection line 301, the active layer T80 of the eighth transistor T8, and the control electrode T83 of the eighth transistor T8 on the substrate have an overlapping area. In this example, the second scan connection line 301 can serve as the bottom gate of the eighth transistor T8, thereby forming an eighth transistor T8 with a dual-gate structure. However, this embodiment is not limited to this.

[0115] Figure 10F FIG. 1 is a partial plan view of the second display area after forming the fifth insulating layer according to at least one embodiment of the present disclosure. Figure 10F As shown, a plurality of via holes are formed on the fifth insulating layer of the second display area. The plurality of via holes may include at least: first via hole K1 to twenty-second via hole K22. The fifth insulating layer, fourth insulating layer, third insulating layer, second insulating layer, and first insulating layer within the first through holes K1 to sixth through holes K6 are etched away, exposing the surface of the first semiconductor layer. The fifth insulating layer, fourth insulating layer, third insulating layer, and second insulating layer within the seventh through holes K7 to thirteenth through holes K13 are etched away, exposing the surface of the first conductive layer. The fifth insulating layer, fourth insulating layer, and third insulating layer within the fourteenth through holes K14 to eighteenth through holes K18 are etched away, exposing the surface of the second conductive layer. The fifth insulating layer and fourth insulating layer within the nineteenth through holes K19 and twentieth through holes K20 are etched away, exposing the surface of the second semiconductor layer. The fifth insulating layer within the twenty-first through holes K21 and twenty-second through holes K22 is etched away, exposing the surface of the third conductive layer.

[0116] Figure 10G FIG. 1 is a partial plan view of the second display area after forming the fourth conductive layer according to at least one embodiment of the present disclosure. Figure 10GAs shown, the fourth conductive layer of the second display area may include: first electrodes and second electrodes of multiple transistors of the second pixel circuit (for example, the first electrode T11 of the first transistor T1, the first electrode T21 of the second transistor T2, the first electrode T41 of the fourth transistor T4, the first electrode T51 of the fifth transistor T5, the second electrode T62 of the sixth transistor T6, the second electrode T72 of the seventh transistor T7, the first electrode T81 of the eighth transistor T8, and the second electrode T82 of the eighth transistor T8), and multiple connecting electrodes (for example, the first connecting electrode 401, the second connecting electrode 402, the third connecting electrode 403, the fourth connecting electrode 404, the fifth connecting electrode 405, the sixth connecting electrode 406, the seventh connecting electrode 407, the eighth connecting electrode 408, the ninth connecting electrode 409, the tenth connecting electrode 410, the eleventh connecting electrode 411, and the twelfth connecting electrode 412).

[0117] In some exemplary embodiments, Figure 10G As shown, the second electrode T62 of the sixth transistor T6 and the second electrode T72 of the seventh transistor T7 can be an integrated structure. The first electrode T21 of the second transistor T2 and the first electrode T81 of the eighth transistor T8 can be an integrated structure. However, this embodiment is not limited to this.

[0118] In some exemplary embodiments, Figure 10G As shown, the first electrode T11 of the first transistor T1 is electrically connected to the initial connection line 302 through the fifteenth via K15, and is also electrically connected to the first doped region of the active layer T10 of the first transistor T1 through the first via K1. The first electrode T41 of the fourth transistor T4 is electrically connected to the first doped region of the active layer T40 of the fourth transistor T4 through the fourth via K4. The first electrode T51 of the fifth transistor T5 is electrically connected to the first doped region of the active layer T50 of the fifth transistor T5 through the fifth via K5, and is also electrically connected to the second electrode C1-2 of the first storage capacitor C1 through the eighteenth via K18. The second electrode T62 of the sixth transistor T6 is electrically connected to the second doped region of the active layer T60 of the sixth transistor T6 through the sixth via K6. The second electrode T72 of the seventh transistor T7 is electrically connected to the second doped region of the active layer T70 of the seventh transistor T7 through the second via K2. The first electrode T21 of the second transistor T2 is electrically connected to the first doped region of the active layer T20 of the second transistor T2 through the third via K3. The first electrode T81 of the eighth transistor T8 is electrically connected to the first doped region of the active layer T80 of the eighth transistor T8 through the nineteenth via K19. The second electrode T82 of the eighth transistor T8 is electrically connected to the second doped region of the active layer T80 of the eighth transistor T8 through the twentieth via K20, and is also electrically connected to the first electrode C1-1 of the first storage capacitor C1 through the seventh via K7.

[0119] In some exemplary embodiments, Figure 10G As shown, the first connection electrode 401 is electrically connected to one end of the reset connection line 201 through the eighth via hole K8, and the second connection electrode 402 is electrically connected to the other end of the reset connection line 201 through the ninth via hole K9. The third connection electrode 403 is electrically connected to one end of the first scan connection line 202 through the tenth via hole K10, and the fourth connection electrode 404 is electrically connected to the other end of the first scan connection line 202 through the eleventh via hole K11. The fifth connection electrode 405 is electrically connected to one end of the light-emitting connection line 203 through the twelfth via hole K12, and the sixth connection electrode 406 is electrically connected to the other end of the light-emitting connection line 203 through the thirteenth via hole K13. The seventh connection electrode 407 is electrically connected to one end of the second scan connection line 301 through the sixteenth via hole K16, and the eighth connection electrode 408 is electrically connected to the other end of the second scan connection line 301 through the seventeenth via hole K17. The ninth connecting electrode 409 is electrically connected to one end of the control electrode T83 of the eighth transistor T8 via the twenty-first via K21. The tenth connecting electrode 410 is electrically connected to the other end of the control electrode T83 of the eighth transistor T8 via the twenty-second via K22. The seventh connecting electrode 407 is adjacent to the ninth connecting electrode 409, and the eighth connecting electrode 408 is adjacent to the tenth connecting electrode 410. The eleventh connecting electrode 411 is electrically connected to one end of the initial connecting line 302 via the fourteenth via K14. The orthographic projection of the twelfth connecting electrode 412 on the base substrate overlaps with the orthographic projections of the initial connecting line 302 and the reset connecting line 201 on the base substrate, and does not overlap with the orthographic projection of the first semiconductor layer on the base substrate. However, this embodiment is not limited to this.

[0120] Figure 10H FIG. 1 is a partial plan view of the second display area after forming the sixth insulating layer according to at least one embodiment of the present disclosure. Figure 10H As shown, a plurality of via holes are formed on the sixth insulating layer of the second display area, and the plurality of via holes may include at least: the twenty-third via hole K23 to the thirty-eighth via hole K38. The sixth insulating layer within the twenty-third via hole K23 to the thirty-eighth via hole K38 is etched away, exposing the surface of the fourth conductive layer.

[0121] The 23rd through hole K23 to the 38th through hole K38 are used to connect the plurality of sub-signal lines of the second display area 12 and the electrodes of the second pixel circuit. Optionally, the plurality of sub-signal lines include: a sub-initialization signal line, a sub-reset control line, a sub-scan line, a sub-light emitting control line and a sub-power supply line. Figure 7 In the embodiment of the present disclosure, the second portion 320 of the second initialization signal line 320 corresponds to the sub-initialization signal line provided for the second display area 12. Figure 10HThe thirty-third via K33 is connected to one of the sub-initialization signal lines, through Figure 10H The thirty-fourth via K34 is connected to another sub-initialization signal line, and the two sub-initialization signal lines are connected through the initial connection line 302 to form the second part 320 of the second initialization signal line 320 .

[0122] In the display panel described in the embodiment of the present disclosure, the multiple second pixel circuits set in the second display area adopt the above-mentioned implementation structure, and the second initialization signal line on the display panel is connected to the second pixel circuit of the second display area, and the first initialization signal line is connected to the first pixel circuit of the first display area, ensuring that the pixel circuit set in the normal display area and the pixel circuit set in the display area corresponding to the under-screen camera module are respectively connected to different initialization signal lines. Different initialization signal lines can be used to reset the pixel circuits, which can ensure the display uniformity of different areas and ensure the high-resolution display effect of the entire display area of the display panel.

[0123] Another aspect of the present disclosure further provides a display device, which includes a display panel with any of the above implementation structures.

[0124] It should be noted that according to Figures 1 to 10H Those skilled in the art can understand the specific implementation structure of the display device using the display panel described in the embodiment of the present disclosure, which will not be described in detail here.

[0125] In addition, in an embodiment of the present disclosure, optionally, the display device further includes a first voltage source and a second voltage source, wherein each of the first initialization signal lines is connected to the first voltage source, and the first voltage source provides a first initial voltage to each of the first initialization signal lines, and each of the second initialization signal lines is connected to the second voltage source, and the second voltage source provides a second initial voltage to each of the second initialization signal lines; the second initial voltage is different from the first initial voltage.

[0126] Another aspect of the present disclosure further provides a display driving method for the display device as described above, wherein the method includes:

[0127] When the display panel displays an image, a first initialization voltage signal is input to the plurality of first initialization signal lines, and a second initialization voltage signal is input to the plurality of second initialization signal lines, so that the plurality of first pixel circuits and the plurality of second pixel circuits can emit light;

[0128] The first initial voltage is different from the second initial voltage.

[0129] Optionally, the second initial voltage is lower than the first initial voltage.

[0130] By adopting this embodiment, by making the initial voltage input to the second pixel circuit of the second display area lower than the initial voltage input to the first pixel circuit of the first display area, the opening degree of the driving transistor on the pixel circuit of the second display area is increased to increase the display brightness of the second display area and reduce the display difference between the second display area and the first display area.

[0131] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary personnel in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A display panel comprising a base substrate, wherein: The base substrate includes a display area and a peripheral area at least partially surrounding the display area, the display area includes a first display area and a second display area, and the first display area at least partially surrounds the second display area; a plurality of first pixel circuits, located in the first display area; a plurality of second pixel circuits, located in the second display area; a plurality of first initialization signal lines, located at least in the first display area and extending along a first direction, the first initialization signal lines being electrically connected to the first pixel circuits and configured to transmit first initialization voltage signals to the first pixel circuits; a plurality of second initialization signal lines, located at least in the first display area and the second display area, electrically connected to the second pixel circuit, and configured to transmit a second initialization voltage signal to the second pixel circuit; the first initialization voltage signal and the second initialization voltage signal are different; The display panel further includes a third initialization signal line; wherein the third initialization signal line at least partially surrounds the second pixel circuit, and the plurality of first initialization signal lines are connected to the third initialization signal line; The third initialization signal line is located in the same layer as a first portion of the second initialization signal line located in the first display area, the multiple first initialization signal lines are located in the same layer as a second portion of the second initialization signal line located in the second display area, and the first portion and the second portion are electrically connected and are in different layers.

2. The display panel according to claim 1, wherein The voltage of the first initial voltage signal is higher than the voltage of the second initial voltage signal.

3. The display panel according to claim 1, wherein: The second initialization signal line includes a first portion located in the first display area and a second portion located in the second display area, and the second portion is connected to the second pixel circuit.

4. The display panel according to claim 1, wherein: The third initialization signal line is located in the first display area or the second display area, and the third initialization signal line is in a closed ring shape.

5. The display panel according to claim 1, wherein: The display panel further includes a first initialization bus and a second initialization bus located in the peripheral area. The plurality of first initialization signal lines are connected to the first initialization bus, and the plurality of second initialization signal lines are connected to the second initialization bus. The display panel according to claim 5 , wherein: The first initialization bus is located on a side of the second initialization bus away from the base substrate.

7. The display panel according to claim 5, wherein: The first initialization bus includes a first sub-line and a second sub-line; the first sub-line and the second sub-line are located on both sides of the display area; The second initialization bus includes a third sub-line and a fourth sub-line, and the third sub-line and the fourth sub-line are located at two sides of the display area.

8. The display panel according to claim 1, wherein: The plurality of first pixel circuits include a plurality of first pixel groups, and the plurality of second pixel circuits include a plurality of second pixel groups; In the first display area, different first pixel groups are connected to different first initialization signal lines; and in the second display area, different second pixel groups are connected to different second initialization signal lines.

9. The display panel according to claim 8, wherein: A plurality of first pixel circuits located in the same first pixel group are sequentially arranged in a straight line along a first direction; a plurality of second pixel circuits located in the same second pixel group are staggered along a second direction.

10. The display panel according to claim 1, wherein In the first display area, at least part of the plurality of first initialization signal lines and at least part of the plurality of second initialization signal lines are alternately arranged along a second direction; the second direction intersects the first direction.

11. The display panel according to claim 1, wherein: The plurality of first pixel circuits and the plurality of second pixel circuits respectively include a thin film transistor disposed on the base substrate, wherein the thin film transistor includes an active layer, a gate, and a source / drain electrode sequentially disposed in a direction away from the base substrate; The display panel further includes a light shielding layer located between the base substrate and the active layer; Wherein, the plurality of first initialization signal lines, the second portion and the gate are made of the same layer and the same material; The third initialization signal line, the first part and the active layer are made of the same layer and the same material; or, the third initialization signal line, the first part and the light shielding layer are made of the same layer and the same material; or, the third initialization signal line, the first part and the source / drain layer are made of the same layer and the same material.

12. The display panel according to claim 11, wherein: The first portion is electrically connected to the second portion via a first connection layer, and the plurality of first initialization signal lines are electrically connected to the third initialization signal line via a second connection layer; The first connecting layer and the second connecting layer are made of the same layer and the same material.

13. The display panel according to claim 12, wherein: The first connection layer, the second connection layer and the source / drain are made of the same layer and the same material.

14. The display panel according to claim 11, wherein: The plurality of first initialization signal lines and the plurality of second initialization signal lines are electrically connected to source / drain electrodes of the thin film transistors, respectively.

15. The display panel according to claim 1, wherein The second display area is a light-transmitting display area, and a density of a plurality of second pixel circuits arranged in the second display area is less than or equal to a density of a plurality of first pixel circuits arranged in the first display area.

16. The display panel according to claim 1, wherein The display area further includes a plurality of auxiliary signal lines, which are located in the first display area and extend along a first direction; The plurality of auxiliary signal lines are not connected to any first pixel circuit and any second pixel circuit.

17. The display panel according to claim 16, wherein: The auxiliary signal line and a portion of the second initialization signal line are made of the same layer and the same material.

18. A display device, wherein: The display panel comprises the display panel according to any one of claims 1 to 17.

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