Display substrate, liquid crystal display panel and manufacturing method of display substrate

Abstract

The present disclosure provides a display substrate, a manufacturing method of the display substrate and a liquid crystal display panel, and belongs to the technical field of display, comprising: a substrate, the substrate comprises a display area and a non-display area adjacent to the display area; a common electrode area is located on one side of the non-display area and is used to introduce a common voltage for the liquid crystal display panel; wherein, in the target area of the common electrode area, there is no intersection point between metal lines, or the number of intersection points between metal lines in the target area is less than a preset number; wherein, the target area is part or all of the common electrode area.

Description

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate, a liquid crystal display panel, and a method for manufacturing the display substrate. Background Technology

[0002] Liquid crystal displays (LCDs) control the amount of light passing through the liquid crystal layer by controlling the rotation direction and angle of liquid crystal molecules, thereby displaying images of various grayscale levels. They offer advantages such as high image quality, small size, and light weight, and are widely used in products such as mobile phones, laptops, televisions, and monitors. Typically, alignment films are formed on the thin-film transistor (TFT) substrate and color filter substrate within an LCD, and the liquid crystal molecules are arranged on these alignment films.

[0003] In related technologies, when forming an alignment film, a polyimide (PI) solution is typically coated onto the non-display area and diffuses from the non-display area to the display area. During the diffusion process, the organic solvent in the PI solution evaporates, thus forming an alignment film of a certain thickness.

[0004] However, PI solution has poor diffusion in the surrounding area. In actual manufacturing process, PI solution will accumulate in areas with wiring in non-display areas, affecting the uniform diffusion of PI solution. Summary of the Invention

[0005] This disclosure provides a display substrate, including:

[0006] A substrate, the substrate including a display area and a non-display area adjacent to the display area;

[0007] A common electrode area, located on one side of the non-display area, is used to introduce a common voltage to the liquid crystal display panel;

[0008] Wherein, there are no intersections between metal lines in the target area of ​​the common electrode area, or the number of intersections between metal lines in the target area is less than a preset number;

[0009] The target area is part or all of the common electrode area.

[0010] In some optional examples, the target area is a portion of the common electrode area, and multiple spacer areas are also spaced apart on the non-display area. The spacer areas are used to set spacer pillars, and the spacer pillars are used to support the display substrate.

[0011] Specifically, all the septum areas located in the common electrode area fall into the target area.

[0012] In some alternative examples, the target area is a portion of the common electrode area, and the area of ​​the common electrode area other than the target area includes multiple intersecting metal lines, or multiple non-intersecting metal lines.

[0013] In some alternative examples, the target area is the edge region of the common electrode area that is far from the display area.

[0014] In some alternative examples, the intersecting plurality of metal lines includes a plurality of first metal lines extending along a first direction and a plurality of second metal lines extending along a second direction;

[0015] The metal wire in the target area is connected to the first metal wire or the second metal wire, and the connection point is located outside the target area.

[0016] In some alternative examples, the target area comprises multiple non-intersecting metal lines.

[0017] In some alternative examples, in the target region, the linewidth of some or all of the metal wires is less than or equal to 2 μm.

[0018] In some alternative examples, the target region is a portion of the common electrode region, the edge of the target region is provided with metal lines extending along the edge, and the interior region of the target region other than the edge does not have a metal layer.

[0019] In some alternative examples, the linewidth of the metal wire extending along the edge is greater than or equal to 10 μm.

[0020] In some alternative examples, the target area is a portion of the common electrode area, and a full-surface metal layer is disposed in the target area.

[0021] In some alternative examples, the display substrate is an array substrate in an ADS panel or an IPS panel.

[0022] In some alternative examples, the display substrate is a color filter substrate in a TN panel or a VA panel.

[0023] In some optional examples, a fan-out area is also provided on one side of the non-display area, and the multiple metal lines provided in the target area are the same in line width and / or trace type as the multiple metal lines in the fan-out area.

[0024] A second aspect of the present disclosure is to provide a liquid crystal display panel, including an opposing substrate and any of the display substrates described in the first aspect;

[0025] The display substrate and the opposing substrate are fitted together, and a liquid crystal layer is filled between the display substrate and the opposing substrate.

[0026] In some optional examples, a plurality of spacer pillars are also included, which are disposed between the display substrate and the opposing substrate and serve to support the display substrate and the opposing substrate;

[0027] Among them, the plurality of spacer pillars include a first spacer pillar corresponding to a common electrode area, and the orthographic projection of the first spacer pillar on the display substrate is located within the target area of ​​the common electrode area.

[0028] In some alternative examples, the target area is a portion of the common electrode area, and no metal wire is provided within the inner area of ​​the target area; among the plurality of septum pillars, the height of the first septum pillar is greater than the height of the second septum pillar excluding the first septum pillar;

[0029] The second septum post has its orthogonal projection on the display substrate located outside the common electrode area.

[0030] In some alternative examples, the height difference between the first septum post and the second septum post is equal to the thickness of the metal layer on the display substrate that contacts the second septum post.

[0031] In some alternative examples, the contact surface between the first spacer post and the display substrate is smaller than the contact surface between the second spacer post and the display substrate.

[0032] Alternatively, the contact surface between the first septum column near the edge of the target area and the target area is smaller than the contact surface between the first septum column away from the edge and the target area.

[0033] In some alternative examples, the display substrate is an array substrate and the opposing substrate is a color filter substrate; or, the display substrate is a color filter substrate and the opposing substrate is an array substrate.

[0034] A third aspect of this disclosure provides a method for preparing a display substrate, the method comprising:

[0035] A substrate is provided, the substrate including a display area and a non-display area adjacent to the display area;

[0036] A common electrode area is defined in the display area;

[0037] Multiple metal lines without intersections are formed in the target area of ​​the common electrode region;

[0038] The target area is part or all of the common electrode area.

[0039] The display substrate using the present disclosure includes a substrate, on which a display area and a non-display area adjacent to the display area are disposed; a common electrode area is disposed on one side of the non-display area, the common electrode area being used to introduce a common voltage to the liquid crystal display panel; and a target area in the common electrode area does not have intersections between metal lines, or the number of intersections between metal lines is less than a preset number; wherein, the target area is part or all of the area of ​​the common electrode area.

[0040] As can be seen, the display substrate provided in this disclosure improves the wiring structure of the common electrode area, so that the metal lines in some or all areas of the common electrode area do not cross each other. Since there are no metal line crossing points, or the number of metal line crossing points is small, when PI diffuses in this common electrode area, there are no crossing points to block the PI solution, thereby avoiding the accumulation of PI solution in the common electrode area, so that the PI solution can diffuse evenly around the display substrate, thereby improving the display quality of the liquid crystal display panel.

[0041] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the dimensions and shapes of the figures in the drawings do not reflect actual proportions and are only intended to illustrate the content of the present invention. The same or similar reference numerals in the drawings represent the same or similar elements or elements having the same or similar functions.

[0043] Figure 1 A schematic top view of the formation of an alignment film on an array substrate is shown.

[0044] Figure 2 An electron micrograph schematically illustrates the diffusion of PI solution in the non-display area of ​​the array substrate;

[0045] Figure 3 The diffusion of PI solution in the common electrode region in related technologies is schematically illustrated, compared with the diffusion change diagram of the common electrode region provided in this disclosure;

[0046] Figures 3a-3g A top view schematically illustrates the arrangement of the common electrode area;

[0047] Figures 4a-4b A top view schematically illustrates the arrangement of the common electrode area on the array substrate;

[0048] Figure 5 An enlarged schematic diagram of the array substrate at the location of the common electrode region is shown.

[0049] Figure 6 schematically shown Figure 1 The dashed box in the figure is a cross-sectional view of the structure along the BB direction;

[0050] Figure 7 A schematic diagram of the cross-sectional structure of a liquid crystal display panel is shown.

[0051] Figure 8 A schematic diagram of the cross-sectional structure of a liquid crystal display panel with spacer columns is shown.

[0052] Figure 9 A schematic top view of the arrangement of the spacer pillars on one side of the array substrate is shown.

[0053] Figure 10a The diagram schematically illustrates the specific cross-sectional structure of a liquid crystal display panel when the liquid crystal display panel is an ADS panel or an IPS panel.

[0054] Figure 10b The diagram schematically illustrates the specific cross-sectional structure of a liquid crystal display panel when the panel is a TN panel or a VA panel.

[0055] Figure 11 A flowchart illustrating the steps of the method for manufacturing a display substrate according to the present disclosure is shown schematically.

[0056] Explanation of reference numerals in the attached figures:

[0057] 100 Display substrate; 200 Opposing substrate; 300 Spacer pillar; 400 PI solution; 500 Frame; 600 Liquid crystal layer; 700 Color filter substrate; 800 Array substrate; 101 Display area; 102 Non-display area; 103 Common electrode area; 1030 Target area; 1031 Near-display area; 1032 Boundary area; 1033 Spacer pillar projection area; 1034 Common electrode; 104 Fan-out 105. Device area; 106. Wiring area; 11. Glass substrate; 12. Gate insulating layer; 13. First passivation layer; 14. Second passivation layer; 15. Pixel electrode; 16. Thin film transistor; 17. Gate line; 401. Alignment film; 201. Color filter layer; 202. Encapsulation layer; 203. Black matrix; 301. Spacer pillar area; 302. First spacer pillar; 303. Second spacer pillar; 31. Internal region; 32. Edge metal line. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0059] In related technologies, liquid crystal display panels generally include a color filter substrate and an array substrate. An alignment film needs to be formed on the color filter substrate and the array substrate. After the color filter substrate and the array substrate are aligned, liquid crystal molecules are filled into the space formed therein. The function of the alignment film is to provide interface conditions for the liquid crystal molecules to be uniformly aligned, so that the liquid crystals are arranged in a predetermined order.

[0060] For ADS or IPS panels, pixel electrodes and common electrodes are disposed on the array substrate, meaning that the pixel electrodes and common electrodes are located on the same side of the liquid crystal layer. (Refer to...) Figure 1 The diagram shows a top view schematic of an alignment film formed on an array substrate; as shown... Figure 1 As shown, a display area and a non-display area are set on the array substrate. Multiple pixel units are arranged in the display area. Each pixel unit can be a sub-pixel, and each sub-pixel has a corresponding common electrode. Generally speaking, the common electrodes of multiple sub-pixels are interconnected, that is, the same common voltage is introduced on the common electrode line.

[0061] In the array substrate, a common electrode area is set in the non-display area to introduce a common voltage to the common electrode of different pixel units. In practice, in order to keep the common voltage of pixel units in different areas as balanced as possible, the common electrode area is set as a grid routing method of metal lines, that is, multiple metal lines are intersected on the common electrode area so that the voltage introduced to the common electrode can be more uniform.

[0062] The alignment film is formed on the array substrate. Generally, the alignment film is formed after the common electrode area and the pixel units of the array substrate are formed, and it needs to cover the display area and part of the non-display area. In related technologies, as the bezels of liquid crystal display panels become narrower, the edge portion of the alignment film has poor diffusion at the edge due to factors such as flow or surface tension. This can lead to problems such as uneven brightness (mura) or light leakage, and yellowing at the periphery of the display panel.

[0063] To avoid uneven brightness and yellowing at the edges, the alignment film needs to be evenly diffused at the edges. This is generally improved by increasing the coating area of ​​the alignment film, such as... Figure 1 As shown, by extending the coating area to a position closer to the outer edge of the non-display area, the PI solution generally diffuses towards the display area. Figure 1 As shown by the dashed arrow, its diffusion in the periphery (edge ​​of the display panel) is poor. In practice, it is necessary to coat the edge area of ​​the PI solution injection point close to the non-display area and far away from the display area to improve the periphery uniformity of the display area.

[0064] However, in the actual alignment film formation process, it was found that the PI solution aggregated in the common electrode area, resulting in the PI height at the aggregation point being abnormally higher than the surrounding area, ultimately manifesting as yellowing defects in the display panel.

[0065] Furthermore, when the common electrode is located on the color filter substrate, i.e., the liquid crystal display panel is a TN panel or a VA panel, the common electrode is generally located on one side of the color filter substrate. In this case, the common electrodes on the color filter substrate can be arranged in an array. Additionally, in some cases, a common electrode region is also provided to introduce a common voltage to each common electrode. The shape of this common electrode region can be similar to... Figure 1 The shapes on the array substrates are different. However, to ensure the uniformity of the introduced common voltage, the traces in the common electrode region are grid traces.

[0066] Similarly, an alignment film still needs to be formed on the color filter substrate. In practice, the problem of PI solution accumulating around the common electrode region also exists.

[0067] To improve the above problems, the inventors used an array substrate with a lot of metal wire wiring as the experimental substrate and conducted multiple comparative experiments. They found that because the common electrode area has a cross-wiring method, there are cross points, which leads to step differences. The PI solution has poor diffusion at the edge. When forming the alignment film, the cross points will block the diffusion of the PI solution, causing the PI solution to accumulate at the edge of the common electrode area. This makes the PI height at the accumulation point abnormally higher than the surrounding area, and ultimately exhibits yellowing defects.

[0068] Reference Figure 2 As shown, an electron microscope image of the diffusion of PI solution in the non-display area of ​​the array substrate, obtained during the inventor's experiment, is presented. Figure 2 As shown, the array substrate includes a fan-out region, which is typically used to introduce the necessary data lines, scan lines, etc., to the pixel units in the display area. In practice, the data lines and scan lines in the fan-out region are routed without crossing each other. Figure 2 It is evident that the PI solution diffuses very evenly in this area, but aggregates appear in the common electrode area where there are intersections. Therefore, the inventors concluded that the cross-wiring pattern in the common electrode area caused the aggregation of the PI solution.

[0069] In view of this, the present disclosure proposes a display substrate in which, in part or all of the common electrode region, there are no intersections between metal lines, or the number of intersections between metal lines is less than a predetermined number. Thus, by reducing the number of intersections between metal lines in the common electrode region, the step difference can be reduced, and the accumulation of PI solution in the common electrode region can be reduced, thus improving diffusion uniformity, given the poor diffusion properties of the PI solution in the surrounding area.

[0070] Reference Figure 3 , 3a - Figure 3f , Figure 4a and Figure 4b As shown, a top plan view of the display substrate 100 of this application is illustrated. Figures 3a-3f As shown, it includes:

[0071] The substrate includes a display area 101 and a non-display area 102 adjacent to the display area 101.

[0072] The common electrode area 103, located on one side of the non-display area 102, is used to introduce a common voltage to the liquid crystal display panel;

[0073] Among them, the target area 1030 in the common electrode area 103 has no intersections between metal lines, or the number of intersections between metal lines in the target area is less than a preset number;

[0074] The target area 1030 is part or all of the common electrode area 103.

[0075] The display substrate 100 can be an array substrate or a color filter substrate, wherein the display area 101 and the non-display area 102 can be continuous, non-spaced regions. Of course, in some embodiments, an auxiliary display area 101 is also provided between the display area 101 and the non-display area 102, wherein the display area 101, the auxiliary display area 101 and the non-display area 102 can be continuous, non-spaced regions.

[0076] Taking an ADS panel or an IPS panel as an example, in this type of panel, the pixel electrode 15 and the common electrode 1034 are disposed on the same side of the liquid crystal layer 600, that is, both are disposed on the array substrate. Therefore, in this example, the display substrate 100 can be an array substrate. The substrate can be provided with multiple pixel units, which can be disposed in the display area 101. In the case of an auxiliary display area 101, pixel units are also disposed in the auxiliary display area 101. The substrate is provided with: gate lines 17, data lines, scan lines, and common electrode lines. The pixel electrode 15, the common electrode 1034, and the thin film transistor 16 are disposed in the area defined by the intersection of the gate lines 17 and the data lines, thereby forming a pixel unit. For each pixel unit, its data line is connected to the pixel electrode 15 of the pixel unit, and the common electrode line is connected to the common electrode 1034 of the pixel unit. The pixel electrode 15 is introduced with pixel voltage by the data line, and the common electrode line introduces common voltage to the common electrode 1034. A horizontal electric field is formed between the pixel electrode 15 and the common electrode 1034 to control the deflection of liquid crystal molecules, thereby realizing the display.

[0077] Taking a TN or VA liquid crystal display panel as an example, in this type of panel, the pixel electrode 15 and the common electrode 1034 are disposed on different sides of the liquid crystal layer 600. Therefore, in this example, the display substrate 100 can be a color filter substrate. The substrate of the color filter substrate can include a color filter layer 201, a black matrix 203, and a common electrode 1034. The black matrix 203 is used to block the metal lines in the pixel units on the array substrate, the color filter layer 201 is used for light filtering, and the common electrode 1034 can be multiple common electrode lines, which introduce a common voltage. The pixel electrode 15 and the thin film transistor 16 are disposed in the area defined by the intersection of the gate line 17 and the data line on the array substrate. Multiple common electrode lines and the common electrode 1034 connected to the common electrode lines are disposed on the color filter substrate. After the color filter substrate and the array substrate are aligned, the orthogonal projection of the common electrode 1034 on the array substrate is located in the area defined by the intersection of the gate line 17 and the data line.

[0078] For TN or VA liquid crystal display panels, the data lines on the array substrate provide pixel voltage to the pixel electrode 15 in the array substrate, and the common electrode lines on the color filter substrate provide common voltage to the common electrode 1034 on the color filter substrate. A vertical electric field is formed between the pixel electrode 15 and the common electrode 1034 to control the deflection of liquid crystal molecules, thereby realizing the display.

[0079] Regardless of whether it's an ADS or IPS LCD panel, or a TN or VA LCD panel, a common voltage needs to be introduced into the common electrode 1034. This is generally achieved by setting a common electrode area 103 in the non-display area 102. There can be one or more common electrode areas 103 in the non-display area 102; there is no restriction on this. Generally, to improve the uniformity of regional display on the panel, common electrode areas 103 are provided in different areas to ensure the uniformity of pixel emission in different display areas 101.

[0080] In this design, a common electrode region 103 can introduce a common voltage to a common electrode 1034 within a region. Taking the display substrate 100 as an array substrate (an ADS panel or an IPS panel liquid crystal display panel) as an example, the specific introduction process can be as follows: the common electrode region 103 introduces the common voltage from the control chip to the common electrode line connected to it, and the common electrode line introduces the common electrode 1034 located in the pixel unit 1011. Therefore, the common electrode region 103 can also be called the VCom introduction region.

[0081] Taking the display substrate 100 as a color filter substrate as an example (a liquid crystal display panel of TN panel or VA panel), the specific introduction process can be referred to the array substrate.

[0082] The common electrode region 103 is located on one side of the non-display region 102. This means that the orthographic projection of the common electrode region 103 onto the substrate is located in the non-display region 102. The shape of the orthographic projection of the common electrode region 103 onto the substrate can be referred to... Figure 1 As shown, its shape can be formed such that the size near the display area 101 is smaller than the size near the edge of the display panel. In this way, a narrow bezel design of the liquid crystal display panel can be achieved, that is, the common electrode area 103 presents a fan-shaped shape, with the smaller end facing the display area 101.

[0083] In this embodiment, some or all of the common electrode region 103 may not have intersections between metal lines. In one example, the entire common electrode region 103 may not have intersections between metal lines. Specifically, the entire common electrode region 103 may include multiple non-intersecting metal lines, or it may include multiple parallel metal lines.

[0084] In another example, the number of metal wire intersections in the entire area of ​​the common electrode area 103 may be less than a preset number. In this case, the edge area of ​​the common electrode area 103 away from the display area 101 may not have any metal wire intersections, while the area near the display area 101 may have metal wire intersections, and the number of intersections may be less than a preset number. The preset number can be determined according to the wiring requirements and the diffusion requirements of the PI solution, for example, less than 10, 20 or 5, which is not limited here. In this way, when the PI solution 400 is injected into the area of ​​the common electrode area 103 near the display area 101, since there are no metal wire intersections in the edge area, even if the diffusion of the PI solution 400 is poor at the periphery, it will not accumulate in the edge area because there are no intersections in the edge area of ​​the common electrode area 103 away from the display area 101. This avoids the problem of abnormally high edge height and improves the problem of yellowing at the periphery of the panel.

[0085] Reference Figure 3 The diagram illustrates the diffusion of PI solution 400 in the common electrode region 103 in related technologies, and compares it with the diffusion variation of the common electrode region 103 provided in this disclosure. Figure 3 The upper image shows the diffusion of the PI solution 400 in the common electrode region 103 in related technologies. The PI solution 400 is injected near the edge of the non-display region 102 to increase the coating area of ​​the alignment film 401 and address the issue of uneven diffusion at the edge of the display region 101. However, due to its poor peripheral diffusion and encountering the grid lines of the common electrode region 103, multiple aggregation points are formed at the edge of the common electrode region 103; for example... Figure 3 As shown in the lower image, since there are no metal wire intersections in part or all of the common electrode region 103, even if the PI solution 400 has poor diffusion around its periphery, it will not be blocked by the lack of intersections in the common electrode region 103, thus allowing it to diffuse evenly in the common electrode region 103 without forming aggregation points.

[0086] For example Figure 3As shown in the lower image, since the common electrode region 103 has few or no intersections between metal lines, the PI solution 400 can be injected closer to the display region 101. This is because the common electrode region 103 does not obstruct the diffusion of the PI solution 400 in the periphery. Therefore, even if the PI solution 400 is injected close to the display region 101, when it diffuses away from the display region 101 (i.e., towards the edge of the display panel in the non-display region 102), it will not accumulate in the common electrode region 103. Thus, the PI solution 400 can be injected close to the display region 101, and even when injected close to the display region 101, no accumulation points will form in the periphery of the non-display region 102, resulting in better diffusion of the alignment film in the periphery. Figure 2 The PI solution 400 injection point, indicated by the dashed line, is closer to the display area 101 than the injection point (solid dot) in related technologies. In other words, using the display substrate 100 of this disclosure, in a narrow-bezel display panel, the PI solution 400 can be coated closer to the edge of the display area 101. In this case, there will be no problems such as uneven brightness or yellowing caused by uneven peripheral diffusion.

[0087] In some embodiments, when the target area 1030 is a portion of the common electrode area 103, the target area 1030 may be an edge region of the common electrode area 103 that is far from the display area 101.

[0088] Therefore, as Figure 3g As shown in the upper-middle image, there are no intersections in the edge region of the common electrode area 103, which can improve the aggregation phenomenon caused by poor diffusion of the PI solution 400 when it is injected near the edge of the display panel.

[0089] In one specific implementation of this embodiment, such as Figures 3b-3f ,as well as Figure 4b As shown, the common electrode area includes a near display area 1031 close to the display area, a target area 1030, and a boundary area 1032. The target area 1030 is located between the near display area 1031 and the boundary area 1032. In this case, the target area 1030 is the edge area of ​​the common electrode area 103 that is far away from the display area 101, but it is not the boundary area 1032.

[0090] In this configuration, the near-display area 1031, the edge area (target area 1030), and the boundary area 1032 are continuous, uninterrupted regions. The near-display area 1031 is adjacent to the edge area, and the edge area is adjacent to the boundary area 1032. In this implementation, the PI solution 400 can be injected into the edge area near the near-display area 1031. This not only improves the accumulation of PI solution 400 around the periphery but also maximizes the coverage area of ​​the PI solution 400, reducing uneven brightness and yellowing issues around the display area 101 of the display panel. The routing of the boundary area 1032 can be the same as or different from that of the near-display area 1031; however, intersections between metal lines are permissible in the boundary area 1032. Figure 3b , Figure 3c and Figure 3d As shown.

[0091] In another specific implementation of this embodiment, the common electrode area 103 includes a near-display area 1031 close to the display area 101 and an edge area, such as... Figure 3g As shown in the upper image, in this case, the common electrode region 103 is divided into two parts: a near-display region 1031 including the display region 101, and an edge region 1033 excluding the near-display region 101. The near-display region 1031 and the edge region 1033 are continuous and uninterrupted regions. In this case, there are no intersections between metal lines in the target region 1030 (edge ​​region), which ensures that even if the PI solution 400 has poor peripheral diffusion when injected near the edge of the display panel, it will not accumulate due to the intersections of the common electrode region 103, thus meeting the requirement of large-area coverage of the alignment film 401.

[0092] The liquid crystal display panel is generally obtained by filling the space between an array substrate and a color filter substrate. In related technologies, spacer pillars 300 are provided on the array substrate and the color filter substrate to support the array substrate and the color filter substrate. Generally, multiple spacer pillars 300 are provided at intervals.

[0093] Reference Figure 5 and Figure 6 As shown, Figure 5 Taking the common electrode region 103 located on the array substrate as an example, an enlarged schematic diagram of the array substrate at the location of the common electrode region 103 is shown. Figure 6 It shows Figure 1 The dashed box in the diagram is a cross-sectional view along the BB direction. Among them, Figure 5In the diagram, region 301 is the orthogonal projection area of ​​the spacer pillar 300 on the array substrate, and is called spacer pillar region 301. Specifically, the part of region 301 in the common electrode region 103 is called spacer pillar projection region 1033, which is the area in the common electrode region 103 projected by the spacer pillar 300.

[0094] like Figure 5 and Figure 6 As shown, the PI solution 400 is injected from the non-display area 102. When it diffuses in the common electrode area 103, if the aggregation point of the PI solution 400 happens to be located at the position of the septum pillar 300, it will lift the septum pillar 300, thereby lifting the opposite substrate (color filter substrate), resulting in a higher gap (cell thickness) at this point, ultimately exhibiting a more severe yellowing defect.

[0095] Therefore, in some embodiments, reference is made to Figure 5 As shown, the target area 1030 can be the area where the spacer pillars 300 are located in the common electrode area 103, i.e., the spacer pillar projection area 1033, or an area including the spacer pillar projection area 1033. In this embodiment, the target area 1030 is a part of the common electrode area 103, and a plurality of spacer areas are also provided at intervals on the non-display area 102. The spacer areas are used to set the spacer pillars 300, and the spacer pillars 300 are used to support the display substrate 100.

[0096] Among them, all the septum areas located in the common electrode area 103 fall into the target area 1030.

[0097] In this embodiment, a septum area can be understood as the orthographic projection of the septum pillar 300 on the display substrate 100, and the target area 1030 can refer to the area where multiple septum areas fall into the common electrode area 103, which is a continuous and uninterrupted area.

[0098] In this embodiment, there are no intersections of metal lines in the target area 1030. Specifically, for example... Figure 3a As shown, the septum column projection area 1033 may include multiple parallel metal lines; or, the septum column projection area 1033 may include multiple non-parallel but non-intersecting metal lines; or, as... Figure 3e and 3c As shown, the target area 1030 (including the projection area 1033 of the diaphragm column) may not require multiple metal lines; or, as... Figure 3d and 3f As shown, the target area 1030 (including the septum column projection area 1033) can be provided with a full-surface metal layer.

[0099] With this common electrode area 103 configuration, when the PI solution 400 is injected into the non-display area 102, since there are no metal wire intersections in the septum pillar projection area 1033 of the common electrode area 103, the PI solution 400 diffuses evenly in this area and does not form aggregates. The septum pillars 300 configured in this area will not cause the opposing substrate to be pushed up due to aggregation, further improving the problem of yellowing defects around the panel.

[0100] In some embodiments, the entire area of ​​the common electrode 1034 may be free of intersections between metal lines, such as... Figure 3a and Figure 4a As shown, this means that the entire area of ​​the common electrode region 103 does not have any metal line intersections. In this case, it can be... Figure 3a and Figure 4a As shown, the multiple metal lines in the common electrode region 103 are arranged in a parallel manner. In some other embodiments, the multiple metal lines in the common electrode region 103 may not be parallel to each other, but they do not cross each other.

[0101] In some specific implementations of this embodiment, there may be no intersections between metal lines in the entire area. It may be that some areas have parallel lines and other areas have non-parallel lines, but they do not intersect. Among them, the areas with parallel lines may be closer to the edge area of ​​the common electrode area 103 away from the display area 101, and the areas with non-parallel lines may be closer to the area of ​​the common electrode area 103 near the display area 101.

[0102] In this context, "mutually parallel" can refer to the fact that the metal wires are parallel to each other, without specifying whether the spacing between any two metal wires is equal.

[0103] In some specific implementations of this embodiment, the entire area may not have any intersections between metal lines. It may be a first area with parallel lines and another part of the second area with parallel lines. The first area may be the edge area of ​​the common electrode area 103 that is further away from the display area 101, and the second area may be the area of ​​the common electrode area 103 that is closer to the display area 101. The first area and the second area are continuous and uninterrupted areas, and the first area and the second area constitute the common electrode area 103. The spacing between metal lines in the first area is greater than the spacing between metal lines in the second area.

[0104] Of course, in practice, the common electrode area 103 can be divided into two areas or multiple areas. The metal lines in different areas do not intersect, but the spacing between the metal lines in different areas can be different. Specifically, it is sufficient to ensure that the spacing between the edge areas far from the non-display area 102 is large, that is, the spacing between the metal lines in the target area 1030 is large.

[0105] In this implementation, the spacing between the metal lines in the edge region is relatively large, which can further improve the diffusion uniformity of the PI solution 400 in the common electrode region 103 without any intersection points. Meanwhile, the spacing between the metal lines near the display region 101 is relatively small, which can ensure the uniformity of the voltage introduced into the common electrode region 103.

[0106] By employing a common electrode region 103 where there are no intersections between metal lines in the entire area, the injection position of the PI solution 400 can be made closer to the display area 101, thereby improving the diffusion uniformity of the PI solution 400 around the display area 101.

[0107] In some other embodiments, the target region 1030 may be a portion of the common electrode region 103, in which there are no intersections between metal lines, while the common electrode region 103, excluding the target region 1030, includes multiple intersecting metal lines or multiple non-intersecting metal lines.

[0108] In some specific examples of this embodiment, such as Figures 3b-3d as well as Figure 4b The image shows a region excluding the target area 1030 that includes multiple intersecting metal lines. Here, "intersecting" can refer to grid intersections, such as... Figures 3b-3d as well as Figure 4b The illustration shows a grid-like intersection. Of course, in some other embodiments, the intersection may not be a grid; it may be a diamond-shaped intersection.

[0109] In this case, the metal lines in the target area 1030 may not have intersections. In one specific implementation, the target area 1030 may include multiple parallel metal lines, or multiple non-parallel but non-intersecting metal lines.

[0110] In one implementation of this specific example, the extension directions of the multiple metal lines included in the common electrode region 103 may be inconsistent. The metal lines with inconsistent extension directions do not form an intersection point in the target region 1030, but form an intersection point in the region of the common electrode region 103 other than the target region 1030. Thus, there is no intersection point between the metal lines in the target region 1030, but multiple intersecting metal lines are formed in the region of the common electrode region 103 other than the target region 1030.

[0111] In another implementation of this specific example, the wiring in the target region 1030 and the common electrode region 103, excluding the target region 1030 (referred to as the non-target region), can be separate wiring. That is, multiple non-intersecting metal lines are laid in the target region 1030, while multiple intersecting metal lines are laid in the non-target region. Of course, in this case, the metal lines in the target region 1030 and the metal lines in the non-target region need to maintain an electrical connection. That is, the metal lines in the target region 1030 need to be connected to the metal lines in the non-target region to ensure the introduction of their common voltage.

[0112] In some specific examples of this embodiment, such as Figure 3e-3f as well as Figure 4a As shown, the non-target area includes multiple non-intersecting metal lines. Here, "non-intersecting" can mean that the metal lines run parallel to each other, or it can mean that the lines are not parallel to each other but do not intersect.

[0113] In parallel traces, the direction of the metal line extension can be the diagonal of the substrate, or the direction of the long or short side of the substrate, without limitation.

[0114] In this example, the routing of the multiple non-intersecting metal lines included in the target area 1030 can differ from the routing of non-intersecting metal lines in non-target areas. Specifically, the differences can be reflected in:

[0115] The target area 1030 includes multiple parallel metal lines, while the non-target area includes multiple non-parallel but also non-intersecting metal lines.

[0116] The target area 1030 includes multiple parallel metal lines, and the non-target area also includes multiple parallel metal lines. The spacing between the multiple metal lines in the two areas can be the same or different. When they are different, the spacing between the multiple metal lines in the target area 1030 can be greater than the spacing between the metal lines in the non-target area.

[0117] The target area 1030 includes multiple metal lines that are not parallel to each other but do not intersect each other, and the non-target area also includes multiple metal lines that are not parallel to each other but do not intersect each other.

[0118] The target area 1030 includes multiple metal lines that are not parallel to each other but do not intersect, while the non-target area includes multiple metal lines that are parallel to each other.

[0119] In some specific examples of this embodiment, when multiple intersecting metal lines are included in the area other than the target area 1030 (non-target area), the multiple intersecting metal lines include multiple first metal lines extending in a first direction and multiple second metal lines extending in a second direction.

[0120] The metal wire in target area 1030 is connected to either the first metal wire or the second metal wire.

[0121] The connection point is located outside the target area 1030.

[0122] In this example, as Figure 3b As shown, the metal lines in the target region 1030 can be understood as extensions of the first metal lines in the non-target region, with no intersections between these extensions; the metal lines in the target region 1030 are extensions of the second metal lines, with no intersections between these extensions. This reduces the difficulty of patterning and fabricating the common electrode region 103.

[0123] Among them, such as Figure 3b As shown, the connection points between the metal lines in the target region 1030 and the first or second metal lines connected to them in the non-target region are not located within the target region 1030. This reduces the number of inflection points in the metal lines generated within the target region 1030, ensuring that the PI solution 400 does not diffuse unevenly due to inflection points.

[0124] The first direction may be perpendicular to the second direction, or it may not be perpendicular to it. When they are perpendicular, the first direction may be the long side direction of the display substrate 100, and the second direction may be the short side direction of the display substrate 100.

[0125] The setting of the target area in the common electrode area 103 is explained below:

[0126] In some embodiments, regardless of whether the target area is the entire area or a part of the common electrode area 103, the target area may include multiple non-intersecting metal lines, which may be parallel to each other or not parallel to each other.

[0127] In a routing scheme where multiple metal lines run parallel to each other, the spacing between adjacent metal lines can be smaller, thereby improving the uniformity of the common voltage introduced by the common electrode region 103. In some examples, the spacing between metal lines can be between 6μm and 20μm, and optionally, it can be 10μm, to ensure a small spacing while avoiding problems such as short circuits caused by excessively small spacing.

[0128] Furthermore, in the case where the multiple metal lines in the target area do not intersect, the linewidth of some or all of the metal lines can be less than or equal to 2 μm. This allows for fine wiring in the target area; preferably, the linewidth can be selected as 1.5 μm or 1.8 μm. This fine wiring method can further reduce the step difference in the common electrode region 103, thereby preventing the accumulation of PI solution 400 in this area and improving its diffusion uniformity.

[0129] In some embodiments, when the target region is a portion of the common electrode region 103, the edge of the target region is provided with metal lines extending along the edge, and the inner region of the target region other than the edge does not have a metal layer.

[0130] In this embodiment, as Figures 3a-3f ,as well as Figures 4a-4b As shown, a metal line extending along the edge of the common electrode region 103 is provided, hereinafter referred to as edge metal line 32. The edge metal line 32 can provide electrical conduction for the common electrode region 103. It can be understood that a metal line extending along the edge is provided at the edge of the target region 1030 to ensure electrical conduction between the target region 1030 and non-target regions, such as... Figure 3e and 3c As shown, no metal layer is provided in the inner region 31 of the target region except for the edge. That is, the target region is hollowed out to expose the film layer in the substrate near the common electrode region 103.

[0131] In this case, the PI solution 400 can diffuse unimpeded in the target area, thus forming an alignment film 401 that is uniformly diffused across the entire surface of the target area.

[0132] In a further example of this embodiment, multiple intersecting metal wires may be included in the non-target area, such as... Figure 3c As shown, this ensures the stability and uniformity of the common voltage introduced by the common electrode region 103 even without a metal layer in the target region.

[0133] In a further example of this embodiment, the target area can be the area into which the septum area falls, i.e., the septum column projection area 1033 described above. It can be the area located between the boundary area 1032 of the target area and the near-display area 1031, such as... Figure 3g The lower image is shown.

[0134] In a further example of this embodiment, the target area may be the edge area of ​​the common electrode area 103 away from the display area 101, which may include the aforementioned septum pillar projection area 1033. In this example, such as... Figure 3g The image above is shown.

[0135] In a further example of this embodiment, the line width of the metal line 32 extending along the edge can be greater than or equal to 10 μm, thereby thickening the line width to compensate for the problem of uneven common voltage introduced when no metal layer is provided in the target area.

[0136] Of course, in this case, if no metal layer is provided in the target region 1030, the width of the edge line of the common electrode region 103 can also be greater than or equal to 10 μm, such as... Figure 3c and 3e As shown.

[0137] In some other embodiments, the target region 1030 is a portion of the common electrode region 103, and a full-surface metal layer may be provided in the target region 1030.

[0138] In this case, the target area 1030 can be covered with a metal layer. In practice, it can be understood that the target area 1030 is filled with metal material. In this case, since there are no intersections in the metal layer, it will not cause the PI solution 400 to accumulate in this area.

[0139] Because the entire surface of metal has high electrical conductivity, in this case, multiple non-intersecting metal lines can be set in the non-target area (including the near display area 1031 and the boundary area 1032), such as... Figure 3f As shown; alternatively, non-target areas can also include multiple intersecting metal lines, such as... Figure 3d As shown.

[0140] The thickness of the entire metal layer can be the same as the thickness of the metal lines in the non-target area, and there is no restriction on this.

[0141] In one example of this embodiment, the target area 1030 can still be the edge area of ​​the common electrode area 103 that is far from the display area 101, such as... Figure 3g The area shown may include the aforementioned septum column projection area 1033; or it may be the area located between the boundary area of ​​the target area 1030 and the near display area 1031, i.e., the septum column projection area 1033.

[0142] In some embodiments, the display substrate 100 is a color filter substrate in a TN panel or a VA panel; or, it can be an array substrate in an ADS panel or an IPS panel.

[0143] When the display substrate 100 is an array substrate, the common electrode region 103 is located on the array substrate. As described above, the array substrate may further include a fan-out region 104, a wiring region 106, and a device region 105. The wiring region 106 is used to lead metal lines from the pixel unit wirings to the device region 105. The device region 105 may include a driver chip, and the metal lines led out by the driver chip are located in the fan-out region 104. Figure 5 As shown, the fan-out area 104 includes multiple fine, non-intersecting metal traces;

[0144] In this case, the routing of the multiple metal lines in the target area 1030 can be similar to that in the fan-out area 104. Specifically, the multiple metal lines in the target area 1030 are the same as the multiple metal lines in the fan-out area 104 in terms of line width and / or routing profile.

[0145] Specifically, the target area 1030 can be the septum pillar projection area 1033, or include the septum pillar projection area 1033; specifically, it can be the edge area of ​​the common electrode area 103 that is away from the display area 101 and includes the septum pillar projection area 1033, such as... Figure 3g As shown in the upper image, it could also be the entire area of ​​the common electrode area 103; of course, it could also be located in the septum projection area 1033, which is located between the near display area 101 and the boundary area 1032 of the target area 1030.

[0146] In this embodiment, the routing pattern of the metal lines in the target area 1030 can be consistent with the routing pattern of the multiple metal lines in the fan-out area 104. The routing pattern can refer to the arrangement direction of the metal lines or the extension direction of the metal lines.

[0147] In this embodiment, the linewidth of the metal line in the target area 1030 can be consistent with the linewidth of the multiple metal lines in the fan-out area 104. For example, if the multiple metal lines in the fan-out area 104 are fine metal traces with a linewidth generally below 2μm, then the linewidth of the metal line in the target area 1030 can also be below 2μm.

[0148] Of course, in some other embodiments, the line width of the metal line in the target area 1030 can be the same as the line width of the multiple metal lines in the fan-out area 104, and the routing pattern can be the same as the multiple metal lines in the fan-out area 104. In other words, the target area 1030 is also a dense network of non-intersecting metal lines.

[0149] In this embodiment, since the PI solution 400 diffuses uniformly in the fan-out region 104 during the experiment, a similar routing pattern and linewidth as the fan-out region 104 can be used to achieve a similar diffusion effect, thereby improving the aggregation of PI solution 400 in the common electrode region 103.

[0150] Below are several specific configuration structures of the display substrate 100:

[0151] Structure A: such as Figure 3a and Figure 4a As shown, the target area 1030 is the entire area of ​​the common electrode area 103. The entire area of ​​the common electrode area 103 uses a non-intersecting metal line routing method, that is, the entire area of ​​the common electrode area 103 includes multiple non-intersecting metal lines, among which the multiple metal lines can be parallel to each other. Figure 3a This is a top view of the common electrode region 103 located on the color filter substrate. Figure 4a This is a top view of the common electrode region 103 located on the array substrate; as shown. Figure 4a As shown, the common electrode area 103 adopts a metal routing method similar to that of the fan-out area 104, namely a dense, non-intersecting routing method.

[0152] Structure B: such as Figure 3b and 4b As shown, the target area 1030 is a part of the common electrode area 103, and multiple septum areas located in the common electrode area 103 fall into the target area 1030. The target area 1030 is located between the near display area 1031 and the boundary area 1032. The target area 1030 includes multiple non-intersecting metal lines, while the non-target areas all include multiple intersecting metal lines.

[0153] Structure C: such as Figure 3c As shown, the target area 1030 is a part of the common electrode area 103, and multiple septum areas located in the common electrode area 103 fall into the target area 1030. The target area 1030 is located between the near display area 103 and the boundary area 1032. The edge of the target area 1030 is provided with a metal line 32 extending along the edge. The inner area 31 of the target area 1030 does not have a metal layer. The width of the metal line extending along the edge of the target area 1030 is 10μm. In the non-target area, multiple intersecting metal lines are included.

[0154] Structure D: such as Figure 3d As shown, the target area 1030 is a part of the common electrode area 103, and multiple septum areas located in the common electrode area 103 fall into the target area 1030. The target area 1030 is located between the near display area 103 and the boundary area 1032. The target area 1030 is provided with a full-surface metal layer, and the non-target area includes multiple intersecting metal lines.

[0155] Structure E: such as Figure 3eAs shown, the target area 1030 is a portion of the common electrode area 103, and multiple septum areas located in the common electrode area 103 fall within the target area 1030. The target area 1030 is located between the near display area 103 and the boundary area 1032. A metal line 32 extending along the edge of the target area 1030 is provided, while no metal line is present in the interior region of the target area 1030. The width of the metal line extending along the edge of the target area 1030 is 10 μm, and multiple parallel metal lines are included in the non-target area.

[0156] Structure F: such as Figure 3f As shown, the target area 1030 is a part of the common electrode area 103, and multiple septum areas located in the common electrode area 103 fall into the target area 1030. The target area 1030 is located between the near display area 103 and the boundary area 1032. The target area 1030 is provided with a full surface of metal, and the non-target area includes multiple parallel metal lines.

[0157] Structure G: such as Figure 3g The upper image shown shows that the target area 1030 is a part of the common electrode area 103 and is located at the edge of the common electrode area 103. The edge area includes the septum pillar projection area 1033. The edge of the target area 1030 is provided with metal lines extending along the edge. There are no metal lines in the inner area of ​​the target area 1030. The non-target area (near the display area 1031) includes multiple parallel metal lines.

[0158] Structure H: such as Figure 4a As shown, the entire target area 1030 is similar to the routing of multiple metal lines in the fan-out area 104 on the array substrate, including multiple parallel metal lines with a linewidth of less than 2μm.

[0159] Structure I: such as Figure 4b As shown, the target region 1030 is a portion of the common electrode region 103, and multiple spacer regions located in the common electrode region 103 fall within this target region 1030. The target region 1030 is located between the near display region 103 and the boundary region 1032. The routing of the target region 1030 is similar to that of the multiple metal lines in the fan-out region 104 on the array substrate, including multiple parallel metal lines with a linewidth of less than 2 μm. The non-target regions (near display region 1031 and boundary region 1032) include multiple intersecting metal lines.

[0160] A display substrate using an embodiment of this disclosure, such as Figure 5As shown, since there are no metal wire intersections in part or all of the common electrode area, the PI solution injected into the common electrode area can be prevented from accumulating in the common electrode area when it diffuses around the periphery, thereby improving the uniformity of the peripheral diffusion of the PI solution.

[0161] In the case where the target area 1030 is a partial area and includes the septum column projection area 1033, since there are no intersections of metal lines, a uniform alignment film can be formed. When the septum column comes into contact with this area, there will be no abnormally high concentration due to the accumulation of PI solution, thus preventing the surrounding area from turning yellow.

[0162] In this design (where the target area 1030 is a partial area and includes the septum pillar projection area 1033), the non-target area includes multiple intersecting metal lines. This ensures that the voltage introduced into the common electrode area is more uniform. In related technologies, when the common electrode area is entirely composed of mesh-like metal lines, the resistance of the common electrode area is 0.4 ohms. In this design (where the target area 1030 is a partial area and includes the septum pillar projection area, and the non-target area includes multiple intersecting metal lines), the resistance of the common electrode area in this embodiment is 0.5 ohms, which is not significantly different. In other words, it ensures that the introduced common voltage is more uniform.

[0163] In the case where the target area 1030 is a partial area and includes the septum column projection area 1033, since it is located in the edge region of the common electrode area far from the display area, the PI solution can be injected closer to the display area. Figure 5 As shown, compared to related technologies, this allows the PI solution to be injected closer to the display area. Figure 5 (As shown in the top row of the PI solution diagram), this does not affect its diffusion in the edge region, as there are no intersections in the edge region, so it will not accumulate. The placement of the septum pillars here does not affect their height. Injecting the PI solution close to the display area shortens the time it takes for the PI solution to diffuse throughout the entire display area, allowing sufficient time for the organic solvent in the PI solution to evaporate before proceeding to the next process step, thereby further improving the quality of the alignment film.

[0164] Based on the same inventive concept, this disclosure also provides a liquid crystal display panel, see reference. Figure 7 As shown, a cross-sectional structural diagram of the liquid crystal display panel is illustrated. Figure 7 As shown, it includes a counter substrate 200 and a display substrate 100 as described in the above embodiment;

[0165] The display substrate 100 and the opposing substrate 200 are paired, and a liquid crystal layer 600 is filled between the display substrate 100 and the opposing substrate 200.

[0166] A frame 500 is used to encapsulate the display substrate 100 and the opposing substrate 200.

[0167] In some embodiments, the liquid crystal display panel may be an ADS panel or an IPS panel, then the display substrate 100 is an array substrate and the opposing substrate 200 is a color filter substrate.

[0168] In some other embodiments, the liquid crystal display panel may be a TN panel or a VA panel, in which case the display substrate 100 is a color filter substrate and the opposing substrate 200 is an array substrate.

[0169] In some embodiments, in order to support the display substrate 100 and the opposing substrate 200, a plurality of spacer pillars 300 may be provided at intervals between the display substrate 100 and the opposing substrate 200. One end of each spacer pillar 300 contacts the display substrate 100 and the other end contacts the opposing substrate 200. It is used to support the display substrate 100 and the opposing substrate 200 to form the filling space of the liquid crystal layer 600.

[0170] Among them, the plurality of spacer pillars 300 include a first spacer pillar 302 corresponding to the common electrode region 103, and the orthographic projection of the first spacer pillar 302 on the display substrate 100 is located within the target region 1030 of the common electrode region 103.

[0171] In this embodiment, the plurality of spacer pillars 300 may be cylindrical and / or inverted conical, wherein, when they are inverted conical, the side facing the array substrate has a smaller dimension.

[0172] The orthographic projections of the plurality of first spacer pillars 302 on the display substrate 100 are all located within the target area 1030 of the common electrode area 103. It should be noted that the plurality of first spacer pillars 302 may be a portion of all spacer pillars 300 in the liquid crystal display panel.

[0173] As described above, the target region 1030 can be a portion of the common electrode region 103.

[0174] In one specific implementation of this embodiment, as described in the above embodiment, in a target area 1030 that is a part of a common electrode area 103, and no metal wire is provided in the internal area of ​​the target area 1030, among the plurality of spacer pillars 300, the height of the first spacer pillar 302 is greater than the height of the second spacer pillar 303 excluding the first spacer pillar 302.

[0175] Specifically, the orthographic projection of the second spacer pillar 303 on the display substrate 100 is located outside the target area 1030. In particular, the orthographic projection of the second spacer pillar 303 on the display substrate 100 is located outside the common electrode area 103.

[0176] Since no metal lines are provided within the target area 1030, the overall thickness of the target area 1030 is less than the overall thickness of the non-target area. Since the spacer pillar 300 is located within the target area 1030, the first spacer pillar 302 within the target area 1030 is closer to the substrate of the display substrate 100 than the second spacer pillar 303 in other areas. Thus, on the side of the opposing substrate 200, the distance between the first spacer pillar 302 and the opposing substrate 200 is larger, which causes the opposing substrate 200 to be recessed at this location.

[0177] In this specific implementation, the height of the first spacer post 302 can be increased to make it greater than the height of the second spacer post 303 excluding the first spacer post 302, so as to compensate for the gap caused by the lack of metal and improve the display quality of the display panel.

[0178] Among them, such as Figure 8 As shown, the height of the first septum post 302 is slightly greater than the height of the second septum post 303. The first septum post 302 is the septum post 300 whose orthographic projection is located in the target area 1030, and the second septum post 303 is the septum post 300 whose orthographic projection is located outside the common electrode area 103.

[0179] Furthermore, in one specific example of this implementation, the height difference between the first spacer post 300 and the second spacer post 303 is equal to the thickness of the metal layer on the display substrate 100 that contacts the second spacer post 303.

[0180] The metal layer on the display substrate 100 that is in contact with the second spacer pillar 303 can be a gate metal layer.

[0181] The height mentioned in this disclosure refers to the direction perpendicular to the plane of the display substrate 100, that is, the direction in which the display substrate 100 is opposite to the opposing substrate 200.

[0182] In this case, since the target area 1030 is hollowed out inside except for the metal line extending along the edge, if the first spacer post 302 happens to cross the boundary of the target area 1030 and contact the inner area, the contact between the first spacer post 302 and the target area 1030 will be unstable due to the hollowed-out interior and the metal line at the boundary, resulting in uneven gaps at the boundary.

[0183] In another specific implementation of this embodiment, the width of the side of the first spacer post 302 that contacts the display substrate 100 can be appropriately reduced to improve the uniformity of the boundary gap.

[0184] Specifically, one design is that the contact surface between the first spacer post 302 and the display substrate 100 can be smaller than the contact surface between the second spacer post 303 and the display substrate 100.

[0185] Another design approach is that the contact surface between the septum post 300 near the edge of the target area 1030 and the target area 1030 is smaller than the contact surface between the septum post 300 away from the edge of the target area 1030 and the target area 1030.

[0186] The smaller the contact surface, the smaller the size of the side of the first spacer pillar 302 that contacts the display substrate 100, the more it can avoid the edge line of the target area 1030, thereby reducing the gap unevenness caused by the first spacer pillar 302 spanning the boundary and inner area of ​​the target area 1030.

[0187] In some embodiments, the area ratio of the contact surfaces of the first septum post 302 and the second septum post 303 may be less than or equal to 0.9.

[0188] In some embodiments, the shape of the side of the spacer post 300 that contacts the display substrate 100 can be circular, rectangular, triangular, elliptical, etc. In some specific implementations, in order to allow the first spacer post 302 to avoid the edge line of the target area 1030, the shape of the side of the first spacer post 302 that contacts the display substrate 100 can be triangular to adapt to the approximately fan-shaped shape of the target area 1030. Thus, the position of the spacer post 300 can be adjusted to avoid the edge line of the target area 1030.

[0189] Reference Figure 9 As shown, an exemplary top view of the arrangement of spacer pillars 300 on one side of the array substrate is illustrated. Taking a cylindrical spacer pillar 300 as an example, the contact surface of the second spacer pillar 303 with the display substrate 100 (non-common electrode area 103) is larger than the contact surface of the first spacer pillar 302 with the display substrate 100 (common electrode area 103). Specifically, the radius of the side of the first spacer pillar 302 with the display substrate 100 may be smaller than the radius of the side of the second spacer pillar 303 with the display substrate 100, so that it contacts the edge metal line of the target area 1030 when no metal layer is provided inside the target area 1030.

[0190] Of course, in some specific designs, when laying the spacer posts 300, the edge of the target area can be avoided as much as possible, so that the first spacer posts 302 are all located inside the target area. The process can also avoid setting the first spacer posts 302 across the edge metal line of the target area.

[0191] In some embodiments, such as Figure 10aThe diagram shows a cross-sectional view of a liquid crystal display panel, specifically an ADS panel or an IPS panel. The display substrate 100 serves as an array substrate 800, and the opposing substrate 200 serves as a color filter substrate 700. On one side of the array substrate 800, the following components are included:

[0192] Glass substrate 11;

[0193] The grid line 17 is disposed on the glass substrate 11;

[0194] The common electrode line (the lead below the common electrode 1034) is disposed on the glass substrate 11;

[0195] The data line is disposed on the glass substrate 11 and intersects with the gate line 17;

[0196] A gate insulating layer 12 is disposed on the side of the gate line 17 facing away from the glass substrate 11;

[0197] Thin film transistor 16 is disposed on the side of gate insulating layer 12 away from glass substrate 11. The first electrode of thin film transistor 16 is connected to data line, the second electrode is connected to gate line 17, and the third electrode is connected to pixel electrode 1.

[0198] The first passivation layer 13 is disposed on the side of the thin film transistor 16 away from the substrate, and an opening is formed thereon for the common electrode 1034 and the pixel electrode 15 to pass through.

[0199] The pixel electrode 15 is disposed on the side of the thin film transistor 16 away from the substrate and is connected to the third electrode of the thin film transistor 16.

[0200] The second passivation layer 14 is disposed on the side of the pixel electrode 15 away from the substrate.

[0201] The common electrode 1034 is disposed on the side of the second passivation layer 14 away from the substrate, and directly overlaps with the common electrode line through openings formed in the second passivation layer 14 and the first passivation layer 13; in some embodiments, the orthographic projections of the common electrodes 1034 of different pixel units on the substrate 101 do not overlap.

[0202] Alignment film 401 is disposed on the side of common electrode 1034 away from the substrate and is used for aligning liquid crystal molecules.

[0203] For the color filter substrate 700, it includes:

[0204] Encapsulation layer 202;

[0205] The color filter layer 201 located on the side of the encapsulation layer 202 close to the array substrate 800 has a black matrix 203 disposed in the color filter layer 201 at intervals. The black matrix 203 is used to block the metal lines in the array substrate. Of course, it can also be used to block the spacer pillars 300. In this case, the spacer pillars 300 are generally disposed on the metal lines so that the black matrix 203 blocks both the metal lines and the spacer pillars 300 at the same time.

[0206] Alignment film 401 is disposed on the side of color filter layer 201 near the array substrate.

[0207] In this structure, the common electrode and the pixel electrode are located on the same side of the liquid crystal layer.

[0208] In some embodiments, such as Figure 10b The diagram shows a cross-sectional structure of a liquid crystal display panel when the panel is a TN or VA panel. The display substrate 100 is a color filter substrate 700, and the opposing substrate is an array substrate 800. On one side of the array substrate 800, the following components are included:

[0209] Glass substrate 11, with grid lines 17 disposed on glass substrate 11;

[0210] The data line is disposed on the glass substrate 11 and intersects with the gate line 17;

[0211] A gate insulating layer 12 is disposed on the side of the gate line 17 facing away from the glass substrate 11;

[0212] A thin-film transistor 16 is disposed on the side of the gate insulating layer 12 away from the glass substrate 11. The first electrode of the thin-film transistor 16 is connected to the data line, the second electrode is connected to the gate line 17, and the third electrode is connected to the pixel electrode 15.

[0213] The first passivation layer 13 is disposed on the side of the thin film transistor 16 away from the substrate, and an opening is formed thereon for the pixel electrode 15 to pass through.

[0214] The pixel electrode 15 is disposed on the side of the thin film transistor 16 away from the substrate, and is connected to the third electrode of the thin film transistor 16 through a via formed in the first passivation layer 13.

[0215] The second passivation layer 14 is disposed on the side of the pixel electrode 15 away from the substrate, and the orthographic projection of the second passivation layer 14 on the substrate does not overlap with the orthographic projection of the pixel electrode 15 on the substrate.

[0216] Alignment film 401 is disposed on the side of the second passivation layer 14 away from the substrate and is used for aligning liquid crystal molecules.

[0217] For one side of the color filter substrate 700, including:

[0218] Encapsulation layer 202;

[0219] The color filter layer 201 is located on the side of the encapsulation layer 202 close to the array substrate 800. A black matrix 203 is disposed in the color filter layer 201 at intervals. The black matrix 203 is used to block the metal lines in the array substrate 800. Of course, it can also be used to block the spacer pillars 300. In this case, the spacer pillars 300 are generally disposed on the metal lines so that the black matrix 203 blocks both the metal lines and the spacer pillars 300 at the same time.

[0220] The common electrode 1034 is located on the side of the color filter layer 201 near the array substrate. The common electrode 1034 can cover the entire color filter layer 201 or it can be linear, which will not be described in detail here. The common electrode 1034 is made of transparent metal material.

[0221] Alignment film 401 is disposed on the side of common electrode 1034 near array substrate 800.

[0222] In this structure, the common electrode and the pixel electrode are located on different sides of the liquid crystal layer.

[0223] The setting of this common electrode area 103 is applicable to both types of display panels mentioned above.

[0224] Based on the same inventive concept, this disclosure also provides a method for preparing a display substrate 100, referring to... Figure 11 The diagram shows a step-by-step flowchart of the preparation method, which may include the following steps:

[0225] Step S1101: Provide a substrate, the substrate including a display area and a non-display area adjacent to the display area;

[0226] Step S1102: Define a common electrode area in the display area;

[0227] Step S1103: Form multiple metal lines without intersections in the target area of ​​the common electrode region; wherein, the target area is part or all of the common electrode region.

[0228] The substrate can be either the substrate in the array substrate 800 or the substrate in the color filter substrate 700.

[0229] In this process, after defining the common electrode region 103, a metal mask can be used to cover the common electrode region 103. The metal mask has a pattern of metal lines for the common electrode region 103. Specifically, the areas where metal lines need to be set are hollowed out, while the areas where metal lines do not need to be set are not hollowed out. In practice, this can be determined according to... Figures 3a-3g as well as Figure 4a and Figure 4b The layout shown is a schematic diagram drawn on a metal mask.

[0230] Next, the metal mask is aligned with the defined common electrode region 103, and metal deposition begins, thereby obtaining a common electrode region 103 in which multiple metal lines without intersections are formed in the target area. The entire area of ​​the common electrode region 103 may include multiple parallel metal lines, or a portion of the common electrode region 103 may include multiple parallel metal lines.

[0231] The plan view of the common electrode region 103 in the obtained display substrate 100 can be seen in detail. Figures 3a-3g as well as Figure 4a and Figure 4b Specifically, based on the requirements, nine display substrates 100 of the above-mentioned structures A to I can be obtained.

[0232] Finally, it should be noted that, unless otherwise defined, the terms "first," "second," and similar terms used herein do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0233] The above provides a detailed description of a display substrate, a liquid crystal display panel, and a method for manufacturing the display substrate. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this disclosure. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

[0234] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0235] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

[0236] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0237] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0238] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This disclosure can be implemented by means of hardware comprising a plurality of different elements and by means of a suitably programmed computer. In a unit claim enumerating a plurality of means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0239] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A display substrate, characterized in that, Applications in LCD panels include: A substrate, the substrate including a display area and a non-display area adjacent to the display area; A common electrode area, located on one side of the non-display area, is used to introduce a common voltage to the liquid crystal display panel; Wherein, there are no intersections between metal lines in the target area of ​​the common electrode area, or the number of intersections between metal lines in the target area is less than a preset number; The target area is part or all of the common electrode area; The target area includes a septum column projection area, which is the area in the common electrode area projected by the septum column, and the septum column is used to support the display substrate; Wherein, the projection area of ​​the diaphragm column does not have multiple metal lines, or the projection area of ​​the diaphragm column is provided with a full metal layer.

2. The display substrate according to claim 1, characterized in that, The target area is a portion of the common electrode area. Multiple spacer areas are also spaced apart on the non-display area. The spacer areas are used to set spacer pillars, and the spacer pillars are used to support the display substrate. Specifically, all the septum areas located in the common electrode area fall into the target area.

3. The display substrate according to claim 1 or 2, characterized in that, The target area is a portion of the common electrode area. The common electrode area, excluding the target area, includes multiple intersecting metal lines or multiple non-intersecting metal lines.

4. The display substrate according to claim 1 or 2, characterized in that, The target area is the edge region of the common electrode area that is far from the display area.

5. The display substrate according to claim 3, characterized in that, The intersecting multiple metal lines include multiple first metal lines extending along a first direction and multiple second metal lines extending along a second direction; The metal wire in the target area is connected to the first metal wire or the second metal wire, and the connection point is located outside the target area.

6. The display substrate according to claim 1 or 2, characterized in that, The target area includes multiple non-intersecting metal lines.

7. The display substrate according to claim 6, characterized in that, In the target area, the linewidth of some or all of the metal wires is less than or equal to 2 μm.

8. The display substrate according to claim 1 or 2, characterized in that, The target area is a portion of the common electrode area. The edge of the target area is provided with metal lines extending along the edge, and the interior area of ​​the target area, excluding the edge, does not have a metal layer.

9. The display substrate according to claim 8, characterized in that, The linewidth of the metal line extending along the edge is greater than or equal to 10 μm.

10. The display substrate according to claim 1 or 2, characterized in that, The target area is a portion of the common electrode area, and a full-surface metal layer is disposed in the target area.

11. The display substrate according to claim 1 or 2, characterized in that, The display substrate is an array substrate in an ADS panel or an IPS panel.

12. The display substrate according to claim 1 or 2, characterized in that, The display substrate is a color filter substrate in a TN panel or a VA panel.

13. The display substrate according to claim 11, characterized in that, A fan-out area is also provided on one side of the non-display area. The multiple metal lines provided in the target area are the same as the multiple metal lines in the fan-out area in terms of line width and / or routing pattern.

14. A liquid crystal display panel, characterized in that, It includes a display substrate as described in any one of claims 1-13, and a counter substrate that is opposite to the display substrate; a liquid crystal layer is filled between the display substrate and the counter substrate.

15. The liquid crystal display panel according to claim 14, characterized in that, It also includes a plurality of spacer pillars, which are disposed between the display substrate and the opposing substrate and are used to support the display substrate and the opposing substrate; Among them, the plurality of spacer pillars include a first spacer pillar corresponding to a common electrode area, and the orthographic projection of the first spacer pillar on the display substrate is located within the target area of ​​the common electrode area.

16. The liquid crystal display panel according to claim 15, characterized in that, The target area is a portion of the common electrode area, and no metal is disposed within the inner area of ​​the target area; among the plurality of septum pillars, the height of the first septum pillar is greater than the height of the second septum pillar excluding the first septum pillar; The second septum post has its orthogonal projection on the display substrate located outside the common electrode area.

17. The liquid crystal display panel according to claim 16, characterized in that, The height difference between the first spacer post and the second spacer post is equal to the thickness of the metal layer on the display substrate that contacts the second spacer post.

18. The liquid crystal display panel according to claim 16, characterized in that, The contact surface between the first spacer post and the display substrate is smaller than the contact surface between the second spacer post and the display substrate. Alternatively, the contact surface between the first septum column near the edge of the target area and the target area is smaller than the contact surface between the first septum column away from the edge and the target area.

19. The liquid crystal display panel according to claim 14, characterized in that, The display substrate is an array substrate, and the opposing substrate is a color filter substrate; or, the display substrate is a color filter substrate, and the opposing substrate is an array substrate.

20. A method for preparing a display substrate, characterized in that, The preparation method includes: A substrate is provided, the substrate including a display area and a non-display area adjacent to the display area; A common electrode area is defined in the display area; Multiple metal lines without intersections are formed in the target area of ​​the common electrode region; The target area is part or all of the common electrode area; The target area includes a septum column projection area, which is the area in the common electrode area projected by the septum column, and the septum column is used to support the display substrate; The projection area of ​​the diaphragm column may have either no multiple metal lines or a full metal layer.

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