Gate driver

Abstract

A gate driver has a plurality of stages for outputting a gate signal for imaging at display driving and outputting a gate signal for sensing at sensing driving after the display driving. Each stage of the plurality of stages includes a pixel row selection unit and an output unit, the pixel row selection unit charging a first node with a first preceding stage carry signal according to a pixel row selection signal of a gate-on voltage during the display driving and charging a second node with a first high potential power voltage according to a sensing start signal of the gate-on voltage and a charged voltage of the first node during the sensing driving, the output unit outputting a scan clock of the gate-on voltage as the gate signal for sensing while the second node remains in a charged state at the sensing driving, wherein the first high potential power voltage is higher at the sensing driving than at the display driving.

Description

[0001] This application is a divisional application of the original invention patent application No. 201911037736.5 (filed on October 29, 2019, invention title: gate driver, organic light-emitting display device including the same and method of operation thereof). Technical Field

[0002] This article relates to a gate driver, an organic light-emitting display device including the gate driver, and a method for operating the gate driver. Background Technology

[0003] Active matrix organic light-emitting display devices include organic light-emitting diodes (OLEDs), which emit light themselves and have high response speed, high luminous efficiency, high brightness and wide viewing angle.

[0004] Organic light-emitting display devices include gate drivers for driving switching elements disposed in pixels. The gates of the switching elements are connected to the gate driver via gate lines. The gate driver generates gate signals (scan signals) and sequentially provides the gate signals (scan signals) to the gate lines. Summary of the Invention

[0005] Organic light-emitting displays (OLEDs) employ external compensation techniques to enhance image quality. This technique senses pixel voltage or current based on the pixel's driving characteristics (or electrical characteristics) and modulates the input image data based on the sensing results, thereby compensating for variations in driving characteristics between pixels. To sense the pixel's driving characteristics during a predetermined time period when no input image is written, a gate driver operates a specific stage during this period to output a gate signal for sensing drive. In the case of sensing drive, the Q-nodes of the specific stage must be sufficiently charged with a gate on-state voltage to output the desired gate signal. Because the Q-node charging path is longer in the case of sensing drive, and the time spent on sensing drive is very short compared to the case of display drive, the charge level of the Q-nodes is insufficient in the case of sensing drive. If the desired gate signal is not applied in the case of sensing drive, the pixel's driving characteristics may not be accurately sensed, leading to a degraded compensation performance.

[0006] This disclosure provides a gate driver that can ensure desired gate output characteristics by enhancing the charge level of the Q node in the case of sensing drive, an organic light-emitting display device including the gate driver, and a method for operating the gate driver.

[0007] In one aspect, the gate driver has multiple stages for outputting a gate signal for imaging during display driving and a gate signal for sensing during sensing driving following the display driving. Each stage includes a pixel row selection unit and an output unit. The pixel row selection unit is configured to charge a first node with a first pre-stage carry signal based on a pixel row selection signal of the gate on-state voltage during the display driving, and is configured to charge a second node with a first high-potential power supply voltage based on a sensing start signal of the gate on-state voltage and the charging voltage of the first node during the sensing driving. The output unit outputs a scan clock of the gate on-state voltage as the gate signal for sensing while the second node remains charged during the sensing driving, wherein the first high-potential power supply voltage is higher during the sensing driving than during the display driving.

[0008] The first high-potential power supply voltage during the sensing drive can be higher than the first high-potential power supply voltage during the display drive, and lower than the breakdown voltage of the transistor connected to the input terminal of the first high-potential power supply voltage.

[0009] Each stage in the stage may further include an inverter unit that disconnects the electrical connection between the input terminal of the second high-potential power supply voltage and the third node while the second node maintains the charging state during the sensing drive, wherein the first high-potential power supply voltage is higher than the second high-potential power supply voltage during the sensing drive.

[0010] The second high-potential power supply voltage can be the same in both the display driving and the sensing driving.

[0011] The gate on-voltage interval of the first front-stage carry signal and the gate on-voltage interval of the pixel row selection signal can be the same.

[0012] In these stages, the number of active stages in which the first node can be charged with the first front-stage carry signal during the display drive according to the pixel row selection signal of the gate on-voltage is one, and the position of the active stage can change at each predetermined time.

[0013] The position of the active stage can be randomly changed in each frame based on the gate on-voltage interval of the first front-stage carry signal and the pixel row selection signal.

[0014] The sensing start signal can be input to the stage as a gate on-state voltage before the gate signal for sensing is output, and the sensing end signal can be input to the stage as a gate on-state voltage after the gate signal for sensing is terminated.

[0015] The display driver can be executed during the vertical activation period when image data is written, and the sensing driver can be executed during the vertical blanking period when the image data is not written.

[0016] The pixel row selection unit may include: a first transistor and a second transistor, the first transistor and the second transistor being connected in series between the input terminal of the first pre-stage carry signal and the first node, and configured to be simultaneously turned on according to the pixel row selection signal of the gate turn-on voltage; a third transistor having a first electrode and a second electrode, the first electrode being connected to the input terminal of the first high-potential power supply voltage, the second electrode being connected between the first transistor and the second transistor, and the third transistor being turned on according to the charging voltage of the first node; a fourth transistor having a first electrode connected to the input terminal of the first high-potential power supply voltage and being turned on according to the charging voltage of the first node; and a fifth transistor having a first electrode connected to the second electrode of the fourth transistor and a second electrode connected to the second node, and being turned on according to the sensing start signal of the gate turn-on voltage.

[0017] The pixel row selection unit may further include a sixth transistor having a first electrode connected to the second node and a second electrode connected to an input terminal of a low-potential power supply voltage, and being turned on according to the sensing end signal of the gate turn-on voltage.

[0018] The pixel row selection unit may further include a capacitor connected between the input terminal of the first high-potential power supply voltage and the first node.

[0019] The inverter unit can be configured to: first, during the display drive, discharge the third node to a low-potential power supply voltage according to a second front-stage carry signal having a phase leading the first front-stage carry signal; second, during the display drive, discharge the third node to the low-potential power supply voltage according to the charging voltage of the second node, and charge the third node with a second high-potential power supply voltage according to the discharge voltage of the second node during the display drive; third, during the sensing drive, discharge the third node to the low-potential power supply voltage according to the sensing start signal of the gate on-stage voltage and the charging voltage of the first node; and fourth, during the sensing drive, discharge the third node to the low-potential power supply voltage according to the charging voltage of the second node.

[0020] The inverter unit may include: a first transistor having a first electrode connected to the input terminal of the second high-potential power supply voltage and a second electrode connected to the input terminal of the low-potential power supply voltage; a second transistor having a first electrode and a gate connected to the input terminal of the second high-potential power supply voltage, and a second electrode connected to the gate of the first transistor; a third transistor having a first electrode connected to the gate of the first transistor and a second electrode connected to the input terminal of the low-potential power supply voltage, and configured to be turned on according to the charging voltage of the second node; and a fourth transistor having a first electrode connected to the third node and a second electrode connected to the low-potential power supply voltage. The third transistor has a second electrode at the input terminal of the low potential power supply voltage and is turned on according to the charging voltage of the second node; a fifth transistor has a first electrode connected to the third node and a second electrode connected to the input terminal of the low potential power supply voltage and is turned on according to the second front-stage carry signal of the gate on voltage; a sixth transistor has a first electrode connected to the third node and is turned on according to the sensing start signal of the gate on voltage; and a seventh transistor has a first electrode connected to the second electrode of the sixth transistor and a second electrode connected to the input terminal of the low potential power supply voltage and is configured to be turned on according to the charging voltage of the first node.

[0021] The inverter unit may include: a first transistor having a first electrode connected to the input terminal of the second high-potential power supply voltage and a second electrode connected to the third node; a second transistor having a first electrode connected to the input terminal of the second high-potential power supply voltage and a gate, and a second electrode connected to the gate of the first transistor; a third transistor having a first electrode connected to the gate of the first transistor, a second electrode connected to the input terminal of the low-potential power supply voltage, and a gate connected to the second node; a fourth transistor having a first electrode connected to the third node, a second electrode connected to the input terminal of the low-potential power supply voltage, and a gate connected to the second node; a fifth transistor having a first electrode connected to the third node, a second electrode connected to the input terminal of the low-potential power supply voltage, and a gate for a second front-stage carry signal to which the gate conduction voltage is applied; a sixth transistor having a first electrode connected to the third node and a gate for a sense start signal to which the gate conduction voltage is applied; and a seventh transistor having a first electrode connected to the second electrode of the sixth transistor, a second electrode connected to the input terminal of the low-potential power supply voltage, and a gate connected to the first node.

[0022] An organic light-emitting display device may include a gate driver according to one aspect of the invention, and a plurality of pixels connected to the gate driver via gate lines and driven according to a gate signal for imaging and a gate signal for sensing.

[0023] In another aspect, a method for operating a gate driver according to one aspect of the present invention includes: operating the pixel row selection unit to charge a first node with a first pre-stage carry signal based on a pixel row selection signal of a gate on-voltage during the display drive, and charging a second node with a first high-potential power supply voltage based on a sensing start signal of a gate on-voltage and a charging voltage of the first node during the sensing drive; and operating the output unit to output a scan clock of the gate on-voltage as a gate signal for sensing while the second node remains in a charging state during the sensing drive, wherein the first high-potential power supply voltage is higher during the sensing drive than during the display drive.

[0024] The first high-potential power supply voltage during sensing can be lower than the breakdown voltage of the transistor connected to the input terminal of the first high-potential power supply voltage.

[0025] Each stage in the stage may further include an inverter unit configured to disconnect the electrical connection between the input of the second high-potential power supply voltage and the third node while the second node maintains the charging state during the sensing drive, and the first high-potential power supply voltage may be higher than the second high-potential power supply voltage during the sensing drive.

[0026] The second high-potential power supply voltage can be the same in both the display driving and the sensing driving.

[0027] The gate on-voltage interval of the first front-stage carry signal and the gate on-voltage interval of the pixel row selection signal can be the same.

[0028] The inverter unit can: first, during the display drive, discharge the third node to a low-potential power supply voltage according to a second front-stage carry signal having a phase leading the first front-stage carry signal; second, during the display drive, discharge the third node to the low-potential power supply voltage (GVSS) according to the charging voltage of the second node, and charge the third node with the second high-potential power supply voltage according to the discharge voltage of the second node during the display drive; third, during the sensing drive, discharge the third node to the low-potential power supply voltage according to the sensing start signal of the gate on-stage voltage and the charging voltage of the first node; and fourth, during the sensing drive, discharge the third node to the low-potential power supply voltage according to the charging voltage of the second node. Attached Figure Description

[0029] Figure 1 An organic light-emitting display according to an embodiment of the present disclosure is shown.

[0030] Figure 2 The composition is shown Figure 1 The connection structure between stages of the gate shift register.

[0031] Figure 3 This is a circuit diagram illustrating a stage according to an embodiment of the present disclosure.

[0032] Figure 4 It shows that based on from Figure 2 and Figure 3 The diagram shows the timing of the gate signal output from the stage for executing the display drive and the sensing drive.

[0033] Figure 5 This is a view showing that the first high-potential power supply voltage applied to each stage during sensing drive is higher than the first high-potential power supply voltage applied to each stage during display drive.

[0034] Figure 6 It is a graph showing that during display driving, the first high-potential power supply voltage and the second high-potential power supply voltage applied to each stage are equal, and during sensing driving, the first high-potential power supply voltage is higher than the second high-potential power supply voltage.

[0035] Figure 7 This shows the process during display driving and sensor driving according to... Figure 5 and Figure 6 A view showing the change in Q-node voltage of the first high-potential power supply voltage in the system.

[0036] Figure 8 Is showing the connection to Figure 3 The view of the pixel level and the data driver connected to that pixel.

[0037] Figure 9 This is a view showing the gate signal and data signal used for sensing drive.

[0038] Figure 10A Is with Figure 9 The equivalent circuit diagram of the pixels corresponding to the set time period.

[0039] Figure 10B Is with Figure 9 The equivalent circuit diagram of the pixel corresponding to the sensing period.

[0040] Figure 10C Is with Figure 9 The equivalent circuit diagram of the pixels corresponding to the reset period. Detailed Implementation

[0041] The advantages and features of this disclosure and its implementation methods will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the exemplary embodiments described. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0042] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings for describing embodiments of the present disclosure are illustrative and are not limited to those shapes, dimensions, ratios, angles, quantities, etc. shown in the present disclosure. The same reference numerals denote the same elements throughout the specification. Furthermore, in the description of the present disclosure, detailed descriptions of known related technologies will be omitted if it is determined that key points of the present disclosure may be unnecessarily obscured.

[0043] When interpreting components, even without an explicit description, the components are interpreted as including a range of error.

[0044] In describing positional relationships, for example, when describing two parts as "on," "above," "below," or "on the side," one or more other parts may be located between the two parts unless "immediately following" or "directly" is used.

[0045] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0046] In this disclosure, the pixel circuit and gate driver formed on the substrate of the display panel can be implemented as a thin-film transistor (TFT) with an n-type metal-oxide-semiconductor field-effect transistor (MOSFET) structure, but are not limited thereto; the pixel circuit and gate driver can also be implemented as a TFT with a p-type MOSFET structure. A TFT is a three-electrode element comprising a gate, a source, and a drain. The source is the electrode that provides charge carriers to the transistor. In a TFT, charge carriers begin to flow from the source. The drain is the electrode through which charge carriers leave the TFT. That is, in a MOSFET, charge carriers flow from the source to the drain. In the case of an n-type TFT, the charge carriers are electrons; therefore, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-type TFT, electrons flow from the source to the drain; therefore, current flows from the drain to the source. Conversely, in the case of a p-type TFT (PMOS), since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-type TFT, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can change depending on the applied voltage. Therefore, in the description of the implementation, one of the source and drain is referred to as the first electrode, and the other as the second electrode.

[0047] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, an organic light-emitting display device comprising organic light-emitting materials will be mainly described as a display device. However, it should be noted that the technical concept of this disclosure is not limited to organic light-emitting display devices, but can be applied to any other display device such as a liquid crystal display.

[0048] In describing this disclosure, if a detailed description of a relevant known function or construction is deemed unnecessary to divert the essence of this disclosure, such description has been omitted, but this will be understood by those skilled in the art.

[0049] In the following description, "preceding stage" refers to a stage located above a reference stage that generates a gate signal that leads the gate signal output from the reference stage in phase. Furthermore, "subsequent stage" refers to a stage located below a reference stage that generates a gate signal that lags the gate signal output from the reference stage in phase. In the following description, the switching element constituting the gate driver of this disclosure can be implemented as at least any one of oxide elements, amorphous silicon elements, and polycrystalline silicon elements. Activating a specific stage means charging the Q node of that stage with a gate on-state voltage, while deactivating a specific stage means discharging the Q node of said stage to a gate off-state voltage.

[0050] Figure 1 An organic light-emitting display device according to an embodiment of the present disclosure is shown.

[0051] Reference Figure 1 The organic light-emitting display device disclosed herein includes a display panel 100, a data driver, a gate driver, and a timing controller 110.

[0052] In the display panel 100, multiple data lines and multiple gate lines intersect each other, and pixels are arranged in a matrix at the intersection points to form a pixel array. The pixel array may also include reference lines connected to each pixel.

[0053] Each pixel may include an organic light-emitting diode (OLED), a driving thin-film transistor (TFT), a storage capacitor, and at least one switching TFT. The TFT may be implemented as P-type, N-type, or a hybrid type of P-type and N-type. In addition, the semiconductor layer of each TFT may include amorphous silicon, polycrystalline silicon, or oxide.

[0054] The timing controller 110 receives image data RGB from an external host system through various known interface schemes. The timing controller 110 can correct the image data RGB based on the sensing results of real-time sensing to compensate for changes in the driving characteristics of pixels, and then send the corrected image data to the source driver IC 120.

[0055] The timing controller 110 receives timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE from the host system. Based on the timing signals from the host system and the gate timing control signal used to control the operation timing of the gate driver, the timing controller 110 generates source timing control signals for controlling the operation timing of the data driver. The source timing control signals include the source sampling clock (SSC) and the source output enable signal (SOE). The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source driver IC 120 based on the rising or falling edge. The source output enable signal SOE is a signal used to control the output timing of the data voltage.

[0056] The timing controller 110 controls the display drive timing and sensing drive timing of the pixel rows of the display panel 100 based on the source timing control signal and the gate timing control signal, so that the driving characteristics of the pixels can be sensed in real time during image display.

[0057] Here, a pixel row refers to a set of pixels in which pixels are adjacent in the horizontal direction. Sensing drive refers to driving the sensor to write sensing data to pixels arranged in a specific pixel row to sense the driving characteristics of the corresponding pixel, and driving the sensor to update the compensation value used to compensate for changes in the driving characteristics of the corresponding pixel based on the sensing results. In the following text, the operation of writing sensing data to pixels arranged in a specific pixel row during sensing drive will be referred to as sensing data writing (SDW) drive.

[0058] Display driving refers to writing input image data (RGB) to the pixel rows within a frame to reproduce the input image on the display panel 100. In the following text, display driving will be referred to as image data writing (IDW) driving.

[0059] The timing controller 110 can implement IDW driving during the vertical active period of a frame, and can implement SDW driving during the vertical blanking period when IDW driving is not performed.

[0060] The data driver includes multiple source driver ICs 120. The source driver ICs 120 receive image data RGB from the timing controller 110. In response to a source timing control signal from the timing controller 110, the source driver ICs 120 convert the image data RGB into a gamma-compensated voltage to generate a data voltage and synchronize it with the gate signal, and provide the gate-synchronized data voltage to the data lines of the panel 100. The source driver ICs can be connected to the data lines of the display panel 100 via a chip-on-glass (COG) process or a tape-on-bond (TAB) process.

[0061] The gate driver includes a gate shift register 130 connected to the gate line and a level shifter 150 that boosts the voltage level of the signal output from the timing controller 110 and provides the boosted voltage level to the gate shift register 130.

[0062] Level shifter 150 boosts the transistor-transistor-logic (TTL) level voltage of the gate timing control signal input from timing controller 110 to a voltage level capable of switching the gate on-state and gate off-state voltages of the TFTs formed on display panel 100. Level shifter 150 provides the level-shifted gate timing control signal to gate shift register 130. The gate timing control signal includes gate start signal VSP, gate shift clock CLK, pixel row select signal LSP, sense start signal SRT, and sense end signal SND. The gate shift clock CLK is implemented as an N-phase clock (N is a natural number) with different phases.

[0063] The gate shift register 130 includes multiple stages that output a gate signal for imaging in the case of IDW driving and a gate signal for sensing in the case of SDW driving, based on a gate timing control signal input from a level shifter 150 and a drive power (high-level supply voltage, low-level supply voltage) input from a power supply circuit (not shown). In addition to the input unit for IDW driving, each stage also includes a pixel row selection unit for SDW driving. To output the desired gate signal for imaging and the gate signal for sensing, the Q-nodes (second nodes) of the corresponding stages must be fully charged for both IDW and SDW driving. However, since the Q-node charge path of the pixel row selection unit is longer than that of the input unit, and the SDW driving time is very short, the Q-node charge voltage used to output the gate signal for sensing can be less than the target value.

[0064] To ensure sufficient Q-node charge voltage for SDW driving, the power supply circuit binaryes the high-potential power supply voltages applied to each stage into a first high-potential power supply voltage GVDD1 applied to the pixel row selection unit and a second high-potential power supply voltage GVDD2 applied to the inverter unit, and periodically changes the voltage level of the first high-potential power supply voltage GVDD1. That is, the power supply circuit sets the first high-potential power supply voltage GVDD1 to be higher during SDW driving than during IDW driving. However, the power supply circuit can set the second high-potential power supply voltage GVDD2 to be equal to the first high-potential power supply voltage GVDD1 during IDW driving to ensure operational stability at each stage. The second high-potential power supply voltage GVDD2 remains constant and does not change periodically.

[0065] The gate shift register 130 can be formed directly on the substrate of the display panel 100 as a gate-in-board (GIP) configuration. The gate shift register 130 can be formed in an area of ​​the display panel 100 where no image is displayed (i.e., the border (BZ) area), but is not limited thereto. To minimize distortion of the gate signal due to RC delay, the gate shift register 130 can be formed in a double-row configuration at the first side border area BZ and the second side border area BZ of the display panel 100, but is not limited thereto.

[0066] Figure 2 The signal lines and included are shown. Figure 1 The connection structure between stages 132 in the gate shift register 130.

[0067] Reference Figure 2 The gate shift register 130 according to an embodiment of the present disclosure includes a plurality of stages 132 cascaded together. Stages 132 may be GIP elements formed in a GIP (gate in panel) manner. At least one upper dummy stage may be provided at the stage preceding the uppermost stage, and at least one lower dummy stage may be provided at the stage following the lowermost stage. However, the present disclosure is not limited thereto.

[0068] Level 132 is connected to the gate line of display panel 100.

[0069] Stage 132 generates a gate signal based on high-potential power supply voltages GVDD1 and GVDD2, low-potential power supply voltage GVSS, gate start signal VSP, carry signals C(n) to C(n+3), gate shift clock CLK, pixel row selection signal LSP, sensing start signal SRT, and sensing end signal SND. The gate signal may include scan signals SCT(n) to SCT(n+3) and carry signals C(n) to C(n+3), and may further include sensing signals (not shown).

[0070] Figure 3 The diagram shows the stage configuration for generating the scan signal SCT(n) and the carry signal C(n) as gate signals. Figure 3 Stage 132 generates a scan signal SCT(n) and provides the generated scan signal SCT(n) to the gate line GLn of the display panel 100, and generates a carry signal C(n) and provides the generated carry signal C(n) to the front stage and the rear stage.

[0071] Stage 132 independently generates carry signals C(n) to C(n+3), thereby preventing the carry signals from being distorted due to gate load. Stage 132 generates carry signals C(n) to C(n+3) and provides them as start signals to one of the subsequent stages, and as reset signals to any of the preceding stages.

[0072] Each stage in stage 132 activates the Q-node based on the gate start signal VSP applied to the start terminal in each frame or the carry signal from the previous stage. The previous stage signal is a carry signal applied from any of the preceding stages. Each stage in stage 132 deactivates the Q-node based on the subsequent stage carry signal applied to the reset terminal in each frame. The subsequent stage carry signal is a carry signal applied from the stage following the previous stage.

[0073] The gate start signal VSP, gate shift clock CLK, pixel row selection signal LSP, sense start signal SRT, and sense end signal SND are jointly provided to stage 132. The gate shift clock CLK, implemented as an N-phase clock (N is a natural number) with different phases, may include an N-phase carry clock and an N-phase scan clock.

[0074] The scan clock is the clock signal used to generate scan signals SCT(n) to SCT(n+3) for imaging or sensing, and the carry clock is the clock signal used to generate carry signals C(n) to C(n+3) for the preceding or following stage. The scan clock oscillates between the gate on-state voltage and the gate off-state voltage to synchronize with the scan signals SCT(n) to SCT(n+3). The carry clock oscillates between the gate on-state voltage and the gate off-state voltage to synchronize with the carry signals C(n) to C(n+3).

[0075] In IDW-driven mode, all stages 132 are activated in a frame to sequentially output scan signals SCT(n) to SCT(n+3) for imaging, and carry signals C(n) to C(n+3) for imaging are output sequentially. Meanwhile, in SDW-driven mode, only one specific stage 132 is activated in a frame to output a scan signal for sensing.

[0076] The pixel row select signal LSP is input to a specific stage 132 as the gate turn-on voltage during IDW driving. The gate turn-on voltage interval is set such that the pixel row select signal LSP is synchronized with the first pre-stage carry signal input to the specific stage 132 during IDW driving. Therefore, the first pre-stage carry signal of the gate turn-on voltage is charged to the M node (first node) of the specific stage 132 according to the pixel row select signal LSP of the gate turn-on voltage.

[0077] Meanwhile, during IDW driving, the pixel row selection signal LSP is input as a gate turn-on voltage to the remaining stages 132 other than the specific stage 132. However, since the carry signal of the previous stage input to the other remaining stages 132 does not overlap with the pixel row selection signal LSP during the gate turn-on voltage interval, the M nodes of the other remaining stages 132 are not charged by the gate turn-on voltage during IDW driving.

[0078] As described above, the number of active levels (referring to a specific level in which M nodes are charged with gate-on voltage by a first pre-stage carry signal overlapping with the pixel row select signal LSP in the gate-on voltage interval) is 1 per predetermined time interval (e.g., one frame). The position of the active level changes at each predetermined time interval. For example, the position of the active level can change randomly in each frame depending on the setting of the gate-on voltage interval of the first pre-stage carry signal and the pixel row select signal LSP.

[0079] During SDW driving, a sensing start signal SRT is input to specific stage 132 as a gate turn-on voltage. Therefore, based on the sensing start signal SRT and the gate turn-on voltage of the M node of specific stage 132, the Q node of specific stage 132 is charged with a first high-potential power supply voltage GVDD1. Here, since the first high-potential power supply voltage GVDD1 is set to be higher in the case of IDW driving than in the case of SDW driving, the Q node can be quickly charged to the gate turn-on voltage during SDW driving.

[0080] Meanwhile, during SDW driving, the sensing start signal SRT is input as a gate turn-on voltage to the remaining stages 132 other than the specific stage 132. However, since the M nodes of the other remaining stages 132 are not charged, the Q nodes of the other remaining stages 132 may not be charged with a gate turn-on voltage during SDW driving.

[0081] The sensing end signal SND is input to specific stage 132 as a gate turn-on voltage during SDW driving to discharge the Q node of specific stage 132 to the gate turn-off voltage. The sensing end signal SND is input to specific stage 132 after the scan signal used for sensing is output from specific stage 132.

[0082] Meanwhile, during SDW driving, the sensing end signal SND can be used as a gate turn-on voltage input to the remaining stages 132 other than the specific stage 132.

[0083] Figure 3 This is a circuit diagram illustrating a stage according to an embodiment of the present disclosure. Figure 4 It shows that based on from Figure 2 and Figure 3 The diagram shows the timing of the gate signal output from the stage for executing the IDW drive and SDW drive.

[0084] Figure 3 Level 132 in the middle is the nth level STGn used to output the nth scan signal SCT(n) for imaging and sensing, and the nth carry signal C(n) for imaging. Figure 3 In this process, the second high-potential power supply voltage GVDD2 can be substantially equal to the gate turn-on voltage, and the low-potential power supply voltage GVSS can be substantially equal to the gate turn-off voltage. Figure 3 Stage 132 can be connected via gate line GLn to, for example Figure 8 The pixel PIX shown.

[0085] Reference Figure 3 and Figure 4 Level 132 includes a pixel row selection unit BLK1, an input unit BLK2, an inverter unit BLK3, an output unit BLK4, and a stabilization unit BLK5.

[0086] When IDW driving is performed during the vertical active period (VWP) of a frame, the pixel row selection unit BLK1 charges the M node with the first pre-stage carry signal C(n-2) based on the pixel row selection signal LSP of the gate on-state voltage to prepare for SDW driving. Subsequently, during the vertical blanking period (VBP) of a frame, the pixel row selection unit BLK1 charges the Q node with the first high-potential power supply voltage GVDD1 based on the sensing start signal SRT of the gate on-state voltage and the charging voltage of the M node to initiate SDW driving.

[0087] The pixel row selection unit BLK1 may include a first transistor T11 to a fifth transistor T15. The first transistor T11 and the second transistor T12 are turned on during the vertical activation period VWP according to the pixel row selection signal LSP of the gate on-state voltage. The third transistor T13 and the fourth transistor T14 are turned on while the M node is in a charged state. The fifth transistor T15 is turned on during the vertical blanking period VBP according to the sensing start signal SRT of the gate on-state voltage.

[0088] The first transistor T11 and the second transistor T12 are connected in series between the input of the first pre-stage carry signal C(n-2) and the M node, and are simultaneously turned on according to the pixel row selection signal LSP to apply the first pre-stage carry signal C(n-2) to the M node. When the gate on-state voltage interval of the first pre-stage carry signal C(n-2) is synchronized with the pixel row selection signal LSP, the M node is charged with the gate on-state voltage through the first pre-stage carry signal C(n-2).

[0089] The first electrode of the third transistor T13 is connected to the input terminal of the first high-potential power supply voltage GVDD1, and the second electrode of the third transistor T13 is connected between the first transistor T11 and the second transistor T12. The gate of the third transistor T13 is connected to the M node. The third transistor T13 is turned on according to the charging voltage of the M node to apply the first high-potential power supply voltage GVDD1 between the first transistor T11 and the second transistor T12, thereby reducing the cutoff current of the first transistor T11 and the second transistor T12 and stably maintaining the charging voltage of the M node until the vertical blanking period VBP of the SDW drive is executed.

[0090] The first electrode of the fourth transistor T14 is connected to the input terminal of the first high-potential power supply voltage GVDD1, the second electrode of the fourth transistor T14 is connected to one electrode of the fifth transistor T15, and the gate of the fourth transistor T14 is connected to node M. The fourth transistor T14 is turned on according to the charging voltage of node M to apply the first high-potential power supply voltage GVDD1 to the first electrode of the fifth transistor T15.

[0091] The first electrode of the fifth transistor T15 is connected to the second electrode of the fourth transistor T14, the second electrode of the fifth transistor T15 is connected to the Q node, and the gate of the fifth transistor T15 is connected to the input terminal of the sensing start signal SRT. The fifth transistor T15 is turned on according to the sensing start signal SRT of the gate turn-on voltage to apply the first high-potential power supply voltage GVDD1 to the Q node.

[0092] In addition, the pixel row selection unit BLK1 may also include a sixth transistor T16 and a capacitor Cx.

[0093] Capacitor Cx is connected between the input of the first high-potential power supply voltage GVDD1 and the M node to stably maintain the charging voltage of the M node until the vertical blanking period VBP of the SDW drive is executed.

[0094] The sixth transistor T16 turns on in response to the sensing end signal SND of the gate on-state voltage during the vertical blanking period VBP, thereby discharging node Q to the low-potential supply voltage GVSS. After outputting the nth scan signal SCT(n) for sensing, the sensing end signal SND is input as the gate on-state voltage during the vertical blanking period VBP. The gate of the sixth transistor T16 is connected to the input terminal of the sensing end signal SND, the first electrode of the sixth transistor T16 is connected to the Q node, and the second electrode of the sixth transistor T16 is connected to the input terminal of the low-potential supply voltage GVSS.

[0095] Input unit BLK2 charges and discharges the Q-nodes used for IDW driving. Input unit BLK2 does not operate during SDW driving.

[0096] During IDW driving, input unit BLK2 charges the Q node with the gate-on voltage of the second pre-stage carry signal C(n-3) input through the start terminal. The gate-on voltage of the second pre-stage carry signal C(n-3) is before the gate-on voltage of the first pre-stage carry signal C(n-1). Input unit BLK2 discharges the Q node to the low-level supply voltage GVSS in response to the post-stage carry signal C(n+3) input through the reset terminal.

[0097] For this purpose, the input unit BLK2 includes multiple transistors T21 and T22. The first transistor T21 includes a gate and a first electrode connected to the input (start) terminal of the second pre-stage carry signal C(n-3), and a second electrode connected to the Q node, and applies the conduction voltage of the second pre-stage carry signal C(n-3) to the Q node. The second transistor T22 includes a gate connected to the input (reset) terminal of the subsequent stage carry signal C(n+3), a first electrode connected to the Q node, and a second electrode connected to the input terminal of the low-potential power supply voltage. When the subsequent stage carry signal C(n+3) is input, the second transistor T22 connects the Q node and the low-potential power supply voltage GVSS to discharge the Q node.

[0098] During IDW and SDW operation, inverter unit BLK3 charges and discharges the QB node (third node) and Q node in opposite directions. During IDW operation, inverter unit BLK3: First, discharges the QB node to a low-potential supply voltage GVSS based on a second pre-stage carry signal C(n-3) with a gate turn-on voltage preceding the phase of the first pre-stage carry signal C(n-2); second, discharges the QB node to a low-potential supply voltage GVSS based on the charging voltage of the Q node, and then charges the QB node with a second high-potential supply voltage GVDD2 based on the discharge voltage of the Q node. Subsequently, during SDW operation, inverter unit BLK3: Third, discharges the QB node to a low-potential supply voltage GVSS based on a sensing start signal SRT of the gate turn-on voltage and the charging voltage of the M node; then, fourth, discharges the QB node to a low-potential supply voltage GVSS based on the charging voltage of the Q node.

[0099] During IDW and SDW operation, inverter unit BLK3 interrupts the electrical connection between the input of the second high-potential power supply voltage GVDD2 and the QB node, while the Q node remains charged. Inverter unit BLK3 can charge the QB node by applying the second high-potential power supply voltage GVDD2 to the QB node based on the voltage of the N1 node. The voltage of the N1 node is controlled to be opposite to that of the Q node. While the Q node remains charged, the N1 node is discharged to the low-potential power supply voltage GVSS, and while the Q node remains discharged, the N1 node is charged with the second high-potential power supply voltage GVDD2. In other words, while the low-potential power supply voltage GVSS is applied to the Q node, the potential of the QB node is charged with the second high-potential power supply voltage GVDD2.

[0100] Therefore, the inverter unit BLK3 includes multiple transistors T31 to T33. The first transistor T31 includes a gate connected to the N1 node, a first electrode connected to the input of the second high-potential power supply voltage GVDD2, and a second electrode connected to the QB node. The second transistor T32 includes a gate and a first electrode connected to the input of the second high-potential power supply voltage GVDD2, and a second electrode connected to the N1 node. The third transistor T33 includes a gate connected to the Q node, a first electrode connected to the N1 node, and a second electrode connected to the input of the low-potential power supply voltage GVSS.

[0101] During IDW and SDW operation, inverter unit BLK3 discharges QB node to the low-potential supply voltage GVSS while Q node is being charged. Furthermore, inverter unit BLK3 can also discharge QB node to the low-potential supply voltage GVSS according to the second front-end carry signal C(n-3) to increase operational reliability.

[0102] To this end, the inverter unit BLK3 also includes multiple transistors T34 and T35. The fourth transistor T34 includes a gate connected to the Q node, a first electrode connected to the QB node, and a second electrode to which a low-potential supply voltage GVSS is applied. The fifth transistor T35 includes a gate to which a second front-stage carry signal C(n-3) is applied, a first electrode connected to the QB node, and a second electrode to which a low-potential supply voltage GVSS is applied.

[0103] To further improve operational reliability, during SDW driving, inverter unit BLK3 discharges the QB node to the low-potential supply voltage GVSS based on the sensing start signal SRT of the gate turn-on voltage and the charging voltage of the M node.

[0104] To this end, the inverter unit BLK3 also includes multiple transistors T36 and T37. The sixth transistor T36 includes a gate to which the sensing start signal SRT is applied, a first electrode connected to the QB node, and a second electrode connected to one electrode of the seventh transistor T37. The seventh transistor T37 includes a gate connected to the M node, a first electrode connected to the second electrode of the sixth transistor T36, and a second electrode to which a low-potential supply voltage GVSS is applied.

[0105] During IDW driving, the output unit BLK4 outputs the scan clock SCCLK(n) of the gate on-state voltage as the scan signal SCT(n) for imaging, and the carry clock CRCLK(n) of the gate on-state voltage as the carry signal C(n) for imaging, while the Q nodes remain in a charging state. Furthermore, during SDW driving, the output unit BLK4 outputs the scan clock SCCLK(n) of the gate on-state voltage as the scan signal SCT(n) for sensing, while the Q nodes remain in a charging state.

[0106] For this purpose, the output unit BLK4 includes a first pull-up transistor T41, a second pull-up transistor T42, and a boost capacitor CB. The first pull-up transistor T41 includes a gate connected to the Q node, a first electrode connected to the input of the carry clock signal CRCLK(n), and a second electrode connected to the first output node NO1. The second pull-up transistor T42 includes a gate connected to the Q node, a first electrode connected to the input of the scan clock SCCLK(n), and a second electrode connected to the second output node NO2. Since the gates of the first pull-up transistor T41 and the second pull-up transistor T42 are connected to the same Q node, the configuration and mounting area of ​​stage 132 are reduced, and the bezel area is advantageously reduced. The boost capacitor CB is connected between the Q node and the second output node NO2, so that the voltage of the Q node is bootstrapped synchronously with the scan clock SCCLK(n) of the gate on-state voltage. When the voltage of the Q node is bootstrapped, the scan clock SCCLK(n) of the gate on-state voltage can be output quickly and without distortion to the scan signal SCT(n) used for imaging.

[0107] The stabilization unit BLK5 stabilizes the voltage state of the Q node and output nodes NO1 and NO2 by applying a low-potential supply voltage GVSS to the Q node and output nodes NO1 and NO2 while the QB node is being charged.

[0108] Therefore, the stabilizing unit BLK5 includes multiple transistors T51 to T53. The first transistor T51 includes a gate connected to the QB node, a first electrode connected to the first output node NO1, and a second electrode to which a low-potential power supply voltage GVSS is applied. The second transistor T52 includes a gate connected to the QB node, a first electrode connected to the second output node NO2, and a second electrode to which a low-potential power supply voltage GVSS is applied. The third transistor T53 includes a gate connected to the QB node, a first electrode connected to the Q node, and a second electrode to which a low-potential power supply voltage GVSS is applied.

[0109] Reference Figure 4The number of active levels that charge the M node with the gate on-state voltage during IDW driving can be one per frame. The position of this active level can be randomly changed in each frame. When the position of the active level is randomly changed each frame for SDW driving, the pixel rows driven by SDW are randomly changed. For example, after the M node connected to the first active level of pixel row A is charged (ready for SDW) during the vertical active period VWP of frame K, pixel row A can be sensed based on the gate signal used to sense the output of the first active level within the vertical blanking period VBP of frame K. Similarly, after the M node connected to the second active level of pixel row B is charged (ready for SDW) during the vertical active period VWP of frame (K+1), pixel row B can be sensed based on the gate signal used to sense the output of the second active level within the vertical blanking period VBP of frame (K+1).

[0110] Since pixels stop emitting light when driven by SDW, when pixel rows are sensed sequentially, the sensed pixel rows can be visually perceived as line dims. Here, if pixel rows are sensed in a random order instead of sequentially, the line dims may not be visible due to visual dispersion effects.

[0111] Figure 5 It shows that it is applied to Figure 3 The first high-potential supply voltage of the stage is higher when driven by SDW than when driven by IDW. Figure 6 It shows that it is applied to Figure 3 The first high-potential power supply voltage and the second high-potential power supply voltage of the stage are the same when the IDW is driven, and the first high-potential power supply voltage is higher than the second high-potential power supply voltage when the SDW is driven. Figure 7 This shows the relationship between display driving and sensor driving based on Figure 5 and Figure 6 A view showing the change in Q-node voltage of the first high-potential power supply voltage in the system.

[0112] Reference Figure 5 and Figure 6 Apply to Figure 3 The high-potential power supply voltage of stage 132 is binary divided into a first high-potential power supply voltage GVDD1 applied to pixel row selection unit BLK1 and a second high-potential power supply voltage GVDD2 applied to inverter unit BLK3.

[0113] To ensure sufficient Q-node charge voltage during SDW driving, the first high-potential supply voltage GVDD1 is set to be higher during SDW driving than during IDW driving. Specifically, the first high-potential supply voltage GVDD1 during SDW driving can be set to be higher than "VX" (the first high-potential supply voltage GVDD1 used for IDW driving) and lower than "VX+" (the breakdown voltage of transistors T13 and T14 connected to the input of the first high-potential supply voltage GVDD1). ".like Figure 7 As shown, in the case of SDW driving, the higher the first high-potential supply voltage GVDD1, the higher the Q-node charging rate and charging time. Figure 7 In the diagram, (A) is the Q node voltage when the first high-potential power supply voltage GVDD1 for the SDW driver is set to "VX", and (B) is the voltage when the first high-potential power supply voltage GVDD1 for the SDW driver is set to "VX+". The Q node voltage.

[0114] However, in the case of SDW driving, the load applied to transistors T13 and T14 increases as the first high-potential power supply voltage GVDD1 increases. Therefore, the first high-potential power supply voltage GVDD1 for SDW driving is preferably increased within a voltage range below the breakdown voltage of transistors T13 and T14.

[0115] However, to ensure operational stability at this stage, the second high-potential power supply voltage GVDD2 can be set to be equal for both IDW and SDW drivers. For example, as... Figure 6 As shown, the second high-potential power supply voltage GVDD2 can be set to "VX" equal to the first high-potential power supply voltage GVDD1 used for IDW driving.

[0116] Figure 8 Is showing the connection to Figure 3 The view of the pixel level and the data driver connected to that pixel. Figure 9 This is a view showing the gate signal and data signal used for sensing drive. Figure 10A Is with Figure 9 The equivalent circuit diagram of the pixels corresponding to the set time period. Figure 10B Is with Figure 9 The equivalent circuit diagram of the pixel corresponding to the sensing period. Figure 10C Is with Figure 9 The equivalent circuit diagram of the pixels corresponding to the reset period.

[0117] from Figure 3 The scan signal SCT(n) output from stage 132 for imaging or sensing is transmitted through... Figure 8 The gate line GLn in the PIX is provided to the pixel. Figure 8The pixels in the image can perform sensing operations for external compensation. Sensing for external compensation is a technique used to sense the driving characteristics of the pixels and correct the RGB values ​​of the image data based on the sensing results.

[0118] Figure 8 The pixels in the image are driven by IDW during the vertical activation period and by SDW during the vertical blanking period. The source driver IC 120 includes a digital-to-analog converter (DAC). The DAC converts image data RGB to a data voltage VIDW for imaging during IDW driving, generates a data voltage for sensing to be written to the pixel during SDW driving, and also generates a reference voltage Vref to be written to the pixel. The source driver IC 120 also includes a sensing circuit SU and an analog-to-digital converter (ADC) required for SDW driving. The sensing circuit SU can be implemented as a current sensing type or a voltage sensing type. The ADC converts the analog signal sampled in the sensing circuit SU into digital data S-DATA. A reference line RL connected to each pixel can be selectively connected to the DAC and the sensing circuit SU via a switching circuit (not shown).

[0119] Reference Figure 8 A pixel PIX may include an OLED, a driver TFT DT, a first switch TFT ST1, a second switch TFT ST2, and a storage capacitor Cst.

[0120] First, the operation of the pixel PIX for IDW driving will be described. IDW driving can be implemented using programming periods and emission periods.

[0121] During the programming period, the first switch TFT ST1 is turned on according to the scanning signal SCT(n) for imaging from the gate line GLn, so as to provide the data voltage VIDW for imaging on the data line DL to the gate Ng of the driving TFT DT. During the programming period, the second switch TFT ST2 is turned on according to the scanning signal SCT(n) for imaging from the gate line GLn, so as to provide the reference voltage Vref on the reference line RL to the source Ns of the driving TFT DT. Therefore, during the programming period, the gate-source voltage of the driving TFT DT is set to "Vdata-Vref".

[0122] Subsequently, during the emission period, the first switch TFT ST1 and the second switch TFT ST2 are turned off. During the emission period, the gate-source voltage of the driving TFT DT is maintained by the storage capacitor Cst. During the emission period, a drive current proportional to the square root of "Vdata-Vref" flows through the driving TFT DT, and the OLED emits by the drive current.

[0123] Next, we will refer to Figures 9 to 10C Describes the operation of a pixel PIX for SDW driving. The vertical blanking period (VBP) for SDW driving includes a setup period ① for setting the gate-source voltage of the driving TFT DT to suit sensing conditions, a sensing period ② for sampling the pixel current, and a reset period ③ for resetting the gate-source voltage of the driving TFT DT to the emitter period of IDW driving.

[0124] Reference Figure 9 and Figure 10A During the setup period ①, the first switch TFT ST1 of the pixel PIX is turned on according to the scan signal SCT(n) for sensing, so as to apply the data voltage VSDW to the gate Ng of the driving TFT DT. During the setup period ①, the second switch TFT ST2 of the pixel PIX is turned on according to the scan signal SCT(n) for sensing, so as to apply the reference voltage Vref to the source Ns of the driving TFT DT. Therefore, during the setup period ①, the gate-source voltage of the driving TFT DT is set to suit the sensing conditions.

[0125] Reference Figure 9 and Figure 10B During sensing period ②, the first switch TFT ST1 and the second switch TFT ST2 of the pixel PIX remain on. During sensing period ②, the sensing circuit SU samples the pixel current input through the second switch TFT ST2 and the reference line RL.

[0126] Reference Figure 9 and Figure 10C During reset period ③, the first switch TFT ST1 and the second switch TFT ST2 of the pixel PIX remain in the on state. During reset period ③, a data voltage VREC for reset is applied to the gate Ng of the driving TFT DT, and a reference voltage Vref is applied to the source Ns of the driving TFT DT. The data voltage VREC for reset can be the data voltage VIDW used for imaging. During reset period ③, the gate-source voltage of the driving TFT DT is reset to the emission period state driven by IDW.

[0127] As described above, according to this disclosure, by further increasing the high-level power supply voltage applied to the pixel row selection unit to be higher during sensing drive than during display drive, the charge level of the Q node can be enhanced during sensing drive, thereby ensuring the desired gate output characteristics. In this disclosure, compensation performance can be improved because the driving characteristics of the pixel are accurately sensed by ensuring the desired gate output characteristics for sensing drive.

Claims

1. A gate driver having a plurality of stages, each of the plurality of stages comprising: A pixel row selection circuit, the pixel row selection circuit being configured to include a first input terminal, the first input terminal being configured to receive a first high-potential power supply voltage; An output circuit configured to output a plurality of gate signals; The pixel row selection circuit includes: First transistor; The second transistor, the first transistor and the second transistor are connected in series between the second input terminal that receives the carry signal from the previous stage and the first node, and the first transistor and the second transistor are configured to be turned on simultaneously based on the pixel row selection signal based on the gate turn-on voltage; A third transistor having a first electrode connected to the first input terminal and a second electrode connected between the first transistor and the second transistor, the third transistor being configured to be turned on based on the charging voltage of the first node; A fourth transistor having a first electrode connected to the first input terminal, the fourth transistor being configured to be turned on based on the charging voltage of the first node; A fifth transistor having a first electrode connected to the second electrode of the fourth transistor and a second electrode connected to the second node, the fifth transistor being configured to be turned on based on a sensed start signal of the gate turn-on voltage; A sixth transistor having a first electrode connected to the second node and a second electrode connected to a third input terminal receiving a low-potential power supply voltage, the sixth transistor being configured to be turned on based on a sensing end signal of the gate on-voltage; and A first capacitor is connected to the first input terminal and the first node, which receive the first high-potential power supply voltage. Each of the plurality of levels further includes: An inverter circuit is configured to include a fourth input terminal and to disconnect the electrical connection between the fourth input terminal, which receives a second high-potential power supply voltage, and a third node while the second node maintains a charging state during sensing drive for sensing pixels.

2. The gate driver according to claim 1, wherein, The first high-potential power supply voltage has a first voltage level and a second voltage level.

3. The gate driver according to claim 1, wherein, During display driving for displaying an image, the pixel row selection circuit charges the first node with the previous stage carry signal based on the pixel row selection signal according to the gate on-voltage.

4. The gate driver according to claim 2, wherein, The first voltage level is higher than the second voltage level.

5. The gate driver according to claim 2, wherein, During the sensing drive for sensing pixels, the pixel row selection circuit charges the second node with the first voltage level of the first high-potential power supply voltage based on the sensing start signal of the gate on-state voltage and the charging voltage of the first node.

6. The gate driver according to claim 2, wherein, At least a portion of the first high-potential power supply voltage is different from at least a portion of the second high-potential power supply voltage.

7. The gate driver according to claim 2, wherein, The first voltage level of the first high-potential power supply voltage is higher than that of the second high-potential power supply voltage, and Wherein, the second voltage level of the first high-potential power supply voltage is equal to the second high-potential power supply voltage.

8. The gate driver according to claim 2, wherein, The second high-potential power supply voltage is the same during both the display drive and the sensing drive that follows the display drive.

9. The gate driver according to claim 1, wherein, The output circuit includes: A first output node is configured to output a current stage carry signal having a phase of the gate on-voltage following the phase of the previous stage carry signal. A first output transistor having a first electrode and a second electrode, the first electrode of the first output transistor being connected to a first clock input terminal receiving a carry clock as the gate on-state voltage of the current stage carry signal, and the second electrode of the first output transistor being connected to the first output node. A second output node, configured to output one of the plurality of gate signals; The second output transistor has a first electrode and a second electrode. The first electrode of the second output transistor is connected to a second clock input terminal that receives a scan clock for the gate on-state voltage, which is one of the plurality of gate signals. The second electrode of the second output transistor is connected to the second output node. The gates of the first output transistor and the second output transistor are connected to the second node.

10. The gate driver according to claim 9, wherein, The output circuit also includes a second capacitor connected to the second node and the second output node.

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