A display panel and display device

Abstract

Embodiments of the present application disclose a display panel and a display device. The display panel comprises a display area, a shift register area and a compensation area. The display area comprises a plurality of display pixel groups, each display pixel group comprising a plurality of first pixel units arranged in a first direction; the shift register area comprises a first shift register unit and a second shift register unit; the first shift register unit is electrically connected with m display pixel groups; the second shift register unit is electrically connected with n display pixel groups, wherein m and n are positive integers, and m > n; the compensation area comprises a load compensation unit, which is electrically connected with the second shift register unit. The embodiments of the present application solve the problem that the number of pixel rows driven by the partial shift register in the display panel is relatively small and the load is small, so that the display panel can make the pixels have substantially the same luminous brightness, achieve the purpose of balancing the luminous brightness of each pixel row, and improve the display uniformity of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the development of display technology, display devices with high screen-to-body ratio and narrow bezels are becoming increasingly popular due to their superior user experience.

[0003] As is well known, display panels require a gate drive circuit to scan the gate lines, and this gate drive circuit uses multiple shift registers to provide scan signals. However, to achieve a narrow bezel design, current display panels use the same shift register to drive multiple pixel rows, thus reducing the number of shift registers. However, this setup results in noticeable overexposure in the bottom few rows of pixels, affecting display uniformity. Summary of the Invention

[0004] The present invention provides a display panel and a display device for load compensation of a portion of the shift register, balancing the luminous brightness of each pixel row, and improving the display uniformity of the display panel.

[0005] In a first aspect, embodiments of the present invention provide a display panel, including a display area and a border area surrounding the display area, the border area including a shift register area and a compensation area, the shift register area being located on at least one side of the display area in a first direction;

[0006] The display area includes multiple display pixel groups, each display pixel group including multiple first pixel units arranged sequentially along the first direction, and the multiple display pixel groups arranged sequentially along the second direction, wherein the first direction intersects the second direction;

[0007] The shift register area includes a first shift register unit and a second shift register unit. The first shift register unit is electrically connected to m of the display pixel groups, and the second shift register unit is electrically connected to n of the display pixel groups, where m and n are positive integers, and m > n.

[0008] The compensation area includes a load compensation unit, which is electrically connected to the second shift register unit.

[0009] In a second aspect, embodiments of the present invention also provide a display device, including a display panel as described in any of the first aspects.

[0010] In this embodiment of the invention, the display panel includes a display area and a border area surrounding the display area. The border area includes a shift register area and a compensation area. The shift register area is located on at least one side of the display area in a first direction. The display area includes a plurality of display pixel groups, each display pixel group including a plurality of first pixel units arranged sequentially along the first direction. The plurality of display pixel groups are arranged sequentially along a second direction, and the first direction intersects the second direction. The shift register area includes a first shift register unit and a second shift register unit. The first shift register unit is electrically connected to m display pixel groups, and the second shift register unit is electrically connected to n display pixel groups, where m and n are positive integers, and m > n. The compensation area includes a load compensation unit, which is electrically connected to the second shift register unit. In this embodiment of the invention, a load compensation unit is electrically connected to the second shift register unit. This can compensate the load of the second shift register unit that is connected to a smaller number of display pixel groups, solving the problem that the number of pixel rows driven by some shift registers in the display panel is relatively small and the load is small. This can make the light emission brightness of the pixel units in the display pixel groups connected to each shift register unit more consistent, thereby improving the display uniformity of the display panel. Attached Figure Description

[0011] Figure 1 and Figure 2 This is a schematic diagram of the gate driving relationship in different areas of a display panel in related technologies;

[0012] Figure 3 This is a schematic diagram of the pixel driving circuit of a display panel in related technologies;

[0013] Figure 4 yes Figure 3 The driving timing diagram of the pixel driving circuit is shown.

[0014] Figure 5 and Figure 6 This is a schematic diagram of the structure of two display panels provided in an embodiment of the present invention;

[0015] Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0016] Figure 8 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0017] Figure 9 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0018] Figure 10 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0019] Figure 11This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0020] Figure 12 and Figure 13 This is a schematic diagram of the layout of the first pixel unit and the second pixel unit in another display panel provided by an embodiment of the present invention;

[0021] Figure 14 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0022] Figure 15 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0023] Figure 16 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0024] Figure 17 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0025] Figure 18 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0026] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0027] The terminology used in the embodiments of this invention is for the purpose of describing specific embodiments only and is not intended to limit the invention. It should be noted that directional terms such as "upper," "lower," "left," and "right" described in the embodiments of this invention are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this invention. Furthermore, in the context, it should be understood that when referring to an element being formed "on" or "below" another element, it can be formed not only directly on or below the other element, but also indirectly on or below it through intermediate elements. The terms "first," "second," etc., are used for descriptive purposes only and do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0028] The term "comprising" and its variations as used in this invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment".

[0029] It should be noted that the concepts of "first" and "second" mentioned in this invention are only used to distinguish the corresponding contents and are not used to limit the order or interdependence.

[0030] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0031] Figure 1 and Figure 2 This is a schematic diagram illustrating the gate driving relationship in different areas of a display panel, based on related technologies. Figure 3 This is a schematic diagram of the pixel driving circuit of a display panel in related technologies. Figure 4 yes Figure 3 The driving timing diagram of the pixel driving circuit shown is for reference. Figures 1-4 As described in the background section, in some display panels, the shift register VSR located in the bezel area synchronously drives adjacent multi-row pixel rows H, that is, it provides the same scan signal to the same scan signal lines of adjacent multi-row pixel rows H. Figure 1 In the example, the first shift register VSR_1 simultaneously provides the same scan signal to the second scan signal line S2 of both pixel row 1H and pixel row 2H. (See reference) Figure 3 As those skilled in the art will know, at this time, pixel row 1H and pixel row 2H are driven by the same scan signal on the first scan signal line S2, and will be in the same stage of a refresh cycle, namely the data writing stage. Therefore, multiple adjacent pixel rows H can be driven synchronously through the same shift register VSR_1, that is, a one-to-many driving method is adopted, which can reduce the number of shift registers VSR.

[0032] In addition, continue to refer to Figure 1 In some display panels, a shift register (VSR) in the border area is configured to simultaneously provide the same scan signal to one scan signal line of one pixel row H and another scan signal line of another pixel row H. The pixels in these two pixel rows H are driven by the scan signals on different scan signal lines and will be in different driving stages. For example, as... Figure 1The first shift register VSR_1 shown provides the same scan signal to both the second scan signal line S2 of the first row of pixels (1H) and the first scan signal line S1 of the fifth row of pixels (15H). At this time, the pixels in row 1H are driven by the scan signal transmitted on the second scan signal line S2 and are in the data writing phase t2 of a refresh cycle; the pixels in row 15H are driven by the scan signal transmitted on the first scan signal line S1 and are in the initialization phase t1 of a refresh cycle. Therefore, the same shift register VSR can simultaneously drive different phases of two rows of pixels spaced a certain number of rows apart, i.e., using a one-to-two method with a certain number of rows between rows, which also reduces the number of shift registers VSR.

[0033] In summary, the same shift register VSR, such as the first shift register VSR_1, simultaneously drives the first row of pixels 1H, the second row of pixels 2H, the 15th row of pixels 15H, and the 16th row of pixels 16H, thus achieving a one-to-four driving mode. This can greatly reduce the number of shift registers VSR, which helps to reduce the area occupied by the gate driving circuit in the bezel region, thereby helping to shrink the bezel region.

[0034] Based on the above shift register driving design, for all pixel rows in the display panel, a corresponding number of shift registers VSR can provide scan signals to the second scan signal lines S2 of all pixel rows H in a one-to-many manner. Simultaneously, a one-to-two manner is used to provide scan signals to the first scan signal lines S1 of all pixel rows H at intervals of a certain number of rows. However, taking the last shift register VSR_1200 as an example, it only provides scan signals to the second scan signal lines S2 of the last two pixel rows, 2399H and 2400H. Since the display panel does not have any pixel rows for which the last shift register VSR_1200 can synchronously provide scan signals to the first scan signal lines S1 of that pixel row, the last shift register VSR_1200 only exhibits a one-to-two driving relationship. Compared to the first shift register VSR_1 or a general shift register VSR with a one-to-four driving relationship, the shift register VSRs at the end positions only have a one-to-two driving relationship. The load connected to them is less than that of a general shift register VSR, and the brightness of the corresponding pixel row H will be greater, resulting in the brightness of the last few pixel rows of the display panel being too bright and the display panel display uniformity being poor.

[0035] In view of the above technical problems, the present invention provides a display panel, which includes a display area and a border area surrounding the display area. The border area includes a shift register area and a compensation area. The shift register area is located on at least one side of the display area in a first direction.

[0036] The display area includes multiple display pixel groups, each display pixel group including multiple first pixel units arranged sequentially along a first direction, and the multiple display pixel groups arranged sequentially along a second direction, the first direction intersecting the second direction;

[0037] The shift register area includes a first shift register unit and a second shift register unit. The first shift register unit is electrically connected to m display pixel groups, and the second shift register unit is electrically connected to n display pixel groups, where m and n are positive integers, and m > n.

[0038] The compensation area includes a load compensation unit, which is electrically connected to the second shift register unit.

[0039] In this invention, the first direction and the second direction can be understood as the row direction and column direction of the display panel, respectively. Thus, a display pixel group represents the concept of a pixel row. The first shift register unit can be understood as a typical shift register using a one-to-many driving method, with a driving quantity of m. The second shift register unit is electrically connected to n display pixel groups, and m > n, indicating that the second shift register unit is essentially a shift register with a specific driving quantity relationship, i.e., a relatively small driving quantity relationship. Based on this, in this embodiment of the invention, a load compensation unit is electrically connected to the second shift register unit. This can compensate for the load of the second shift register unit connected to a smaller number of display pixel groups, solving the problem that some shift registers in the display panel drive a relatively small number of pixel rows and have a small load. This ensures that the load of each shift register unit is basically the same, so that the pixels in the display pixel groups connected to each shift register unit have basically the same luminous brightness. This avoids excessive differences in the luminous brightness of the first pixel units in the display pixel groups connected to the two types of shift register units, thereby improving the display uniformity of the display panel.

[0040] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0041] Figure 5 and Figure 6 This is a schematic diagram of the structure of two display panels provided in embodiments of the present invention, for reference. Figure 5 and Figure 6 The display panel includes a display area 100 and a border area 200 surrounding the display area 100. The border area 200 includes a shift register area 210 and a compensation area 220. The shift register area 210 is located on at least one side of the display area 100 in the first direction X.

[0042] The display area 100 includes a plurality of display pixel groups 10, each display pixel group 10 including a plurality of first pixel units 101 arranged sequentially along a first direction X, and the plurality of display pixel groups 10 arranged sequentially along a second direction Y, wherein the first direction X and the second direction Y intersect.

[0043] The shift register area 210 includes a first shift register unit 211 and a second shift register unit 212. The first shift register unit 211 is electrically connected to m display pixel groups 10, and the second shift register unit 212 is electrically connected to n display pixel groups 10, where m and n are positive integers, and m > n.

[0044] The compensation area 220 includes a load compensation unit 221, which is electrically connected to the second shift register unit 212.

[0045] First, the display area 100 is provided with pixel units arranged in a row and column array, namely first pixel units 101. For example, if the first direction X is the row direction, then multiple first pixel units 101 arranged sequentially along the first direction X form a display pixel group 10, i.e., a pixel row. The first pixel unit 101 can be understood as a sub-pixel, such as a red sub-pixel, a green sub-pixel, or a blue sub-pixel. Each first pixel unit 101 includes a light-emitting element of the corresponding color and a pixel driving circuit that drives the light-emitting element to emit light. Full-color display can be achieved in the display panel through the color coordination of each sub-pixel. For the pixel units in the display area 100, a gate driving circuit needs to be provided in the shift register area 210 of the border area 200 to provide a scanning signal to the pixel driving circuit in each pixel unit to drive the pixel unit. The shift register area 210 is generally located on one or both sides of the display area 100 in the first direction X, i.e., the row direction, and contains multiple cascaded shift register units for sequentially driving the pixel units of multiple pixel rows.

[0046] Furthermore, the shift register area 210 is provided with a first shift register unit 211 and a second shift register unit 212, and the first shift register unit 211 is electrically connected to the m display pixel groups 10. Figure 5 In the example m=4), the second shift register unit 212 is electrically connected to the n display pixel groups 10. Figure 5In the example n=2), and m is greater than n, it indicates that the number of display pixel groups 10 electrically connected to some shift register units, i.e., the second shift register units, is relatively smaller than that of the first shift register units 211. Therefore, the load connected to this part of the second shift register units 212 will be relatively smaller. In this embodiment of the invention, a compensation area 220 is set in the border area 200, and a load compensation unit 221 is set in the compensation area 220, which is connected to this part of the second shift register units 212. It can take on part of the load to compensate for the load connected to the second shift register units 212, so that the load connected to the first shift register units 211 and the second shift register units 212 is relatively more balanced or even completely consistent. This ensures that the load of each shift register unit is basically the same, so that the pixels in the display pixel groups connected to each shift register unit have basically the same luminous brightness. This avoids that there is too much difference in the luminous brightness of the first pixel unit 101 in the display pixel groups 10 connected to the two types of shift register units, thereby improving the display uniformity of the display panel.

[0047] It should be added that, such as Figure 3 As shown, those skilled in the art will know that the pixel unit in the display pixel group includes an OLED light-emitting element and a pixel driving circuit that drives the OLED to emit light. Here, the electrical connection between the shift register unit and the display pixel group refers to the electrical connection with the corresponding pixel driving circuit in the display pixel group, and not the direct electrical connection with the OLED light-emitting element in the display pixel group.

[0048] Furthermore, the compensation area 220 in this embodiment of the invention can be exemplaryly disposed on one or both sides of the display area 100 in the second direction Y, i.e., the column direction. More specifically, in the display panel of this embodiment of the invention, the bezel area 200 further includes a fan-out area 230, such as... Figure 5 As shown, the compensation area 220 can be located between the fan-out area 230 and the display area 100, or, as... Figure 6 As shown, the compensation area 220 can be located on the side of the display area 100 away from the fan-out area 230. Of course, as... Figure 5 and Figure 6 The location and arrangement of the compensation area 220 shown can also be configured by those skilled in the art according to the actual design requirements of the border area; this embodiment of the invention is not limited in this respect. Furthermore, as... Figure 6 The connection relationship and arrangement of the shift register unit and each row of display pixels shown are for illustrative purposes only and are not intended to be limiting.

[0049] Continue to refer to Figure 5More specifically, the display panel includes multiple gate control signal lines G_Ctrl extending along a first direction X. Each gate control signal line G_Ctrl includes a first scan signal line S1 and a second scan signal line S2. A first shift register unit 211 is connected to R adjacent display pixel groups 10 via R first scan signal lines S1, and to another R adjacent display pixel groups 10 via R second scan signal lines S2, where R = m / 2. A second shift register unit 212 is connected to n adjacent display pixel groups 10 via n second scan signal lines S2. The display pixel groups 10 connected to the first shift register unit 211 and the second shift register unit 212 are different.

[0050] For the first shift register unit 211, as Figure 5 In the example, R=2, meaning that each first shift register unit 211 is connected to two first scan signal lines S1 in two display pixel groups 10, and simultaneously connected to two second scan signal lines S2 in the other two display pixel groups 10. As can be seen in the background section, each first shift register unit 211 here adopts a one-to-four driving relationship, and m is actually equal to 4. (Reference) Figure 3 and Figure 5 It can be seen that the two display pixel groups 10 connected by the first scan signal line S1 are synchronously driven under the control of the scan signal of the first shift register unit 211, and the two display pixel groups 10 connected by the second scan signal line S2 are synchronously driven under the control of the scan signal of the first shift register unit 211, that is, they are in the same stage of the same refresh cycle; while the display pixel groups 10 connected by the first scan signal S1 and the second scan signal S2 respectively are driven separately under the control of the scan signal of the first shift register unit 211, and are in different stages of the same refresh cycle. The display pixel group 10 connected by the first scan signal S1 is in the initialization stage, and the display pixel group 10 connected by the second scan signal S2 is in the data writing stage.

[0051] For the second shift register unit 212, the number of display pixel groups 10 it connects to is relatively small, n (n=2 in the example in the figure), and all n display pixel groups 10 it connects to are connected through n second scan signal lines S2, not through the first scan signal line S1. This comparison also shows that the second shift register unit 212 connects to a relatively small number of display pixel groups 10 because the display area 100 does not have enough display pixel groups 10 for the second shift register unit 212 to connect to through the first scan signal line S1.

[0052] Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, for reference. Figure 7Optionally, the display pixel group 10 where the second scan signal line S2, which is electrically connected to the first shift register unit 211, is located is the first display pixel group 11, and the display pixel group 10 where the first scan signal line S1, which is electrically connected to the first shift register unit 211, is located is the second display pixel group 12. There is a gap of S display pixel groups 10 between adjacent first display pixel groups 11 and second display pixel groups 12; where R and S are both positive integers, and S is an integer multiple of R; the compensation area 220 includes T load compensation units 221, wherein each R adjacent load compensation units 221 is electrically connected to a second shift register unit 212, and T = R + S.

[0053] Based on the connection method and relationship between the first shift register unit 211 and the second shift register unit 212 and the display pixel group 10, it can be deduced that the number of load compensation units 221 provided in the compensation area 220 essentially depends on the number of display pixel groups 10 spaced apart between the display pixel groups 10 electrically connected to the first shift register unit 211 through the second scan signal line S2 and the first scan signal line S1, that is, it depends on the number S of display pixel groups 10 between adjacent first display pixel groups 11 and second display pixel groups 12, and also depends on the number R of display pixel groups 10 electrically connected to each first shift register unit 211 through the same scan signal line. Figure 1 and Figure 2 Given the driving relationship, for example R=2, S=12, there are (R+S) / R=7 second shift register units 212. For these 7 second shift register units 212, the derivation formula for the number T of load compensation units 221 that need to be set in the compensation area 220 is as follows: T=(R+S) / R×R=R+S, that is, T=14.

[0054] Considering that the above-mentioned one-to-four connection method between the shift register unit and the display pixel group is a special example, the embodiments of the present invention also provide a way to set the compensation unit for general situations. Figure 8 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, for reference. Figure 8 Optionally, the load compensation unit 221 includes a compensation pixel group 20, which includes a plurality of second pixel units 201 arranged sequentially along the first direction X. The second shift register unit 212 is electrically connected to x compensation pixel groups 20, where x is a positive integer and m = n + x.

[0055] In this embodiment, except that no light-emitting element is provided or the light-emitting element has no anode and cannot be driven to emit light, the compensation pixel group 20 can be configured to be completely identical to the internal structure of the display pixel group 10 of the display area 100. The second pixel unit 201 can be configured to be completely identical to the internal structure, i.e., the pixel circuit, of the first pixel unit 101 of the display area 100. The difference is that the second pixel unit 201 is located in the compensation area 220 of the border area 200 and is connected to the second shift register unit 212. Therefore, the number of pixel rows connected to the second shift register unit 212 is the same as the number of pixel rows connected to the first shift register unit 211, both being m. This ensures that the second shift register unit 212 and the first shift register unit 211 have the same load, and the corresponding pixel rows in the driven display area 100 have the same luminous brightness. It should be noted that since the compensation pixel group 20 and its second pixel unit 201 cannot be driven to emit light because no light-emitting element is provided or the light-emitting element has no anode, these pixel units in the compensation area will not emit light and will not affect the display of the normal display area.

[0056] In other embodiments of the present invention, the second pixel unit may be specially designed to distinguish it from the first pixel unit in the display area, which needs to have display function.

[0057] Figure 9 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, for reference. Figure 9 In one specific embodiment, the length of the optional second pixel unit 201 in the second direction Y is less than the length of the first pixel unit 101 in the second direction Y. In this case, the second pixel unit 201 located in the border area 200 has essentially compressed its length in the second direction Y, thereby reducing the area occupied by the compensation pixel group 20 in the border area 200, which helps to achieve a narrow border design.

[0058] Figure 10 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, for reference. Figure 10In another embodiment of the present invention, the first pixel unit 101 and the second pixel unit 201 may both include a data signal line Data extending along the second direction Y and a gate control signal line G_Ctrl extending along the first direction X; the gate control signal line G_Ctrl intersects with the data signal line Data; wherein, the number of gate control signal lines G_Ctrl in the second pixel unit 201 is less than the number of gate control signal lines G_Ctrl in the first pixel unit 101. More specifically, the gate control signal line G_Ctrl includes a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, and a light emission control signal line Emit. Optionally, the first pixel unit 101 includes the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, and the light emission control signal line Emit; the second pixel unit 201 includes the first scan signal line S1.

[0059] In this embodiment of the invention, by retaining the first scan signal line S1 in the second pixel unit 201, the load on the first scan signal line S1 connected to the second shift register unit 212 can be kept consistent with the load on the first scan signal line S1 connected to the first shift register unit 211, thus solving the problem of bright lines at the bottom of the panel. Furthermore, removing part or all of the gate control signal lines G_Ctrl other than the first scan signal line S1 in the second pixel unit 201 helps to reduce the length of the second pixel unit 201 in the column direction, which is beneficial for reducing the bezel of the display panel. On the other hand, it also avoids excessive overlap between the gate control signal lines G_Ctrl and the data signal lines Data in the additionally set second pixel unit 201, preventing the addition of capacitance on the data signal lines Data and thus avoiding excessive influence on the data signal. For example, in the second pixel unit 201, except for the first scan signal line S1 used to connect to the second shift register unit 212, all other gate control signal lines extending along the first direction X, i.e., the row direction, can be removed. That is, the second scan signal line S2, the third scan signal line S3, and the light emission control signal line Emit are not provided in the second pixel unit 201. In this way, while reducing the bezel of the display panel, it is possible to avoid the second scan signal line S2, the third scan signal line S3, and the light emission control signal line Emit overlapping with the data signal line Data in the second pixel unit 201 to form capacitance and affect the data signal. In addition, one or two of the second scan signal line S2, the third scan signal line S3, and the light emission control signal line Emit can be retained in the second pixel unit 201 according to actual needs. For example, the gate control signal line G_Ctrl, which has a smaller impact on the data signal line Data, can be retained, while the gate control signal line G_Ctrl, which has a larger impact on the data signal line Data, can be removed. This embodiment of the invention does not limit this.

[0060] Figure 11 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, for reference. Figure 11 In another embodiment of the present invention, the first pixel unit 101 and the second pixel unit 201 may each include at least one first reference signal line Vref1; wherein the first reference signal line Vref1 extends along a first direction X and is located on one side of the first scan signal line S1 in a second direction Y. Further, the distance D1 between the first reference signal line Vref1 and the first scan signal line S1 in the first pixel unit 101 may be equal to the distance D2 between the first reference signal line Vref1 and the first scan signal line S1 in the second pixel unit 201. It is understood that there may be some special designs in the pixel driving circuit, so the first reference signal line Vref1 and the first scan signal line S1 may not be straight lines, for example, there may be some protrusions or depressions at the edge positions. Therefore, when the first reference signal line Vref1 and the first scan signal line S1 are not straight lines, the distance between the first reference signal line Vref1 and the first scan signal line S1 is the distance between two straight lines after approximating them as straight lines.

[0061] In this design, the first pixel unit 101 contains a signal line that extends in parallel and is close to the first scan signal line S1. In practical applications, this is typically the first reference signal line Vref1. It is understood that since there is lateral capacitance when two adjacent signal lines extend in parallel, the load of the first scan signal line S1 connected to the first shift register unit 211 will also include this lateral capacitance. Considering that the load of the second pixel unit 201 in the compensation pixel group needs to be as consistent as possible with that of the first pixel unit 101, when setting the second pixel unit 201, the first scan signal line S1 can also extend in parallel with the first reference signal line Vref1, ensuring that it has the same lateral capacitance. This makes the load of the second shift register unit 212 consistent with the load of the first shift register unit 211, which helps to better solve the problem of bright lines at the bottom of the display panel.

[0062] Figure 12 and Figure 13 This is a schematic diagram of the layout of the first pixel unit and the second pixel unit in another display panel provided in an embodiment of the present invention, with reference to... Figure 3 , Figure 12 and Figure 13 In another embodiment of the present invention, the number of transistors in a second pixel unit 201 may be less than the number of transistors in a first pixel unit 101. Specifically, the transistors in the first pixel unit 101 may include:

[0063] Drive transistor T0;

[0064] The first transistor T1 has its control terminal electrically connected to the third scan signal line S3, its first terminal electrically connected to the first terminal of the drive transistor T0, and its second terminal electrically connected to the data signal line Data.

[0065] The second transistor T2 has its control terminal electrically connected to the second scan signal line S2, its first terminal electrically connected to the gate (N1 node) of the driving transistor T0, and its second terminal electrically connected to the second terminal of the driving transistor.

[0066] The third transistor T3 has its control terminal electrically connected to the first scan signal line S1, its first terminal electrically connected to the gate (N1 node) of the driving transistor T0, and its second terminal electrically connected to the first reference signal line Vref1 (in the example shown in the figure, the first sub-reference signal line Vref1_1 in the first reference signal line).

[0067] The fourth transistor T4 has its control terminal electrically connected to the third scan signal line S3, its first electrode electrically connected to the first electrode of the light-emitting element OLED, and its second electrode electrically connected to the first reference signal line Vref1 (in the example in the figure, the second sub-reference signal line Vref1_2 in the first reference signal line).

[0068] The fifth transistor T5 has its control terminal electrically connected to the light emission control signal line Emit, its first terminal electrically connected to the first terminal of the driving transistor T0, and its second terminal electrically connected to the first power supply signal line PVDD.

[0069] The sixth transistor T6 is electrically connected to the control terminal of the light-emitting control signal line Emit. The first terminal of the sixth transistor T6 is electrically connected to the second terminal of the driving transistor T0. The second terminal of the sixth transistor T6 is electrically connected to the first terminal of the light-emitting element OLED.

[0070] The transistor in the second pixel unit 201 includes:

[0071] The seventh transistor T7 has its control terminal electrically connected to the first scan signal line S1. The first terminal of the seventh transistor T7 is floating, and the second terminal of the seventh transistor T7 is electrically connected to the first reference signal line Vref1 (in the example in the figure, the first sub-reference signal line Vref1_1 in the first reference signal line).

[0072] In this specific embodiment, with Figure 12 Compared to the layout structure of the first pixel unit 101 shown, Figure 13The second pixel unit 201 shown only contains the first scan line S1, the first reference signal line Vref1, and a portion of the active layer pattern to form the seventh transistor T7. The second electrode of the seventh transistor T7 is electrically connected to the first reference signal line Vref1 via a via and a cross-line. (As above) Figure 12 and Figure 13 As can be seen from the comparison, in practical applications, the solution in the embodiments of the present invention can simplify the structure of the pixel unit by reducing the number of transistors and removing some signal lines in the second pixel unit 201, thereby achieving compression of the pixel unit. This avoids the compensation area occupying too large an area in the border area, which helps to achieve a narrow border design. Furthermore, as... Figure 13 As shown, in this embodiment of the invention, a first scan signal line S1, a seventh transistor T7, and a first reference signal line Vref1 are provided in the second pixel unit 201. The seventh transistor T7 can be used as a load directly electrically connected to the first scan signal line S1, thereby... Figure 12 The first scan signal line S1 of the first pixel unit 101 is directly electrically connected to the load substrate. Simultaneously, the first reference signal line Vref1 adjacent to the first scan signal line S1 is retained, which can provide lateral capacitance to the first scan signal line S1. Figure 12 The lateral capacitance of the first scan signal line S1 of the first pixel unit 101 is kept consistent. This ensures that the first scan signal line S1 is consistent with... Figure 12 The first scan signal line S1 of the first pixel unit 101 implements a considerable load.

[0073] Furthermore, in this embodiment, removing some transistors in the second pixel unit 201 while retaining the seventh transistor T7 not only causes the first scan signal line S1 to form a corresponding load and compresses the area of ​​the second pixel unit 201, but also, as in the aforementioned embodiment, at least partially deleting the light emission control signal line Emit, the second scan signal S2, and the third scan signal line S3 in the second pixel unit 201, causes the transistors connected to the light emission control signal line Emit, the second scan signal S2, and the third scan signal line S3 to remain continuously conducting due to the lack of gates. This would cause some signal lines to be short-circuited together, affecting the normal transmission of signals. For example, if both the light emission control signal line Emit and the third scan signal line S3 are deleted, the first transistor T1 and the fifth transistor T5 lack gates and can be considered as wires. Therefore, the first power signal line PVDD and the data signal line Data would be short-circuited together, potentially affecting the normal transmission of the first power signal, data signal, etc. Therefore, in this embodiment of the invention, the transistors corresponding to the removed gate control signal lines can also be removed after removing some of the gate control signal lines to avoid short circuits of various signal lines, thereby ensuring normal signal transmission and avoiding driving defects caused by compression or simplification of the second pixel unit area. Of course, this invention is not limited to the scheme of only setting the first scan signal line S1, the seventh transistor T7, and the first reference signal line Vref1 in the second pixel unit 201. Based on the purpose of avoiding short circuits of other types of signal lines caused by the removal of the gate control signal lines, reasonable reduction schemes for transistors based on the removed gate control signal lines also fall within the protection scope of this invention.

[0074] It should be noted that in some embodiments, the second scan signal line S2 and the third scan signal line S3 can be the same scan signal line, that is, they can be controlled simultaneously by a single scan signal line. Figure 3 The first transistor T1 and the second transistor T2 are configured to be turned on and off simultaneously, so that data signals are written to the gate of the driving transistor T0 when both are turned on.

[0075] To facilitate wiring and transistor placement, Figure 12 and Figure 13The first reference signal line extending along the first direction X, as illustrated, may include a first sub-reference signal line Vref1_1 and a second sub-reference signal line Vref1_2. The voltages of the signals transmitted on the first sub-reference signal line Vref1_1 and the second sub-reference signal line Vref1_2 may be the same or different, which is not limited here. A third transistor T3 is electrically connected to the first sub-reference signal line Vref1_1 through a via, receiving the reference signal provided by the first sub-reference signal line Vref1_1. A fourth transistor T4 is electrically connected to the second sub-reference signal line Vref1_2 through a via, receiving the reference signal provided by the second sub-reference signal line Vref1_2. These two sub-reference signal lines can be externally electrically connected and simultaneously receive the same reference signal.

[0076] Additionally, to ensure that pixel units in adjacent rows receive the same reference signal, in actual layout design, the first reference signal lines of pixel units in adjacent rows are electrically connected. This requires setting a second reference signal line Vref2 extending along the second direction, i.e., vertically. Figure 12 As shown, the second reference signal line Vref2 is responsible for connecting the two first sub-reference signal lines Vref1_1 through a via.

[0077] Figure 14 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, for reference. Figure 14 Optionally, the distance between two first scanning signal lines S1 in two adjacent second pixel units 201 in the second direction Y at a preset position in the first direction X can be set to D3, and the distance between two first scanning signal lines S1 in two adjacent first pixel units 101 in the second direction Y at a preset position in the first direction X can be set to D4, wherein the preset position is any position in the first direction X, and D3 < D4.

[0078] In this embodiment, since the first scan signal line S1 in the pixel unit is not a completely straight line, its edge may have a certain curve or polygonal design. Based on this, the spacing between two adjacent first scan signal lines S1 may change with the edge line, that is, it is not a fixed value. In this embodiment, for any preset position in the first direction X, the spacing between the two first scan signal lines S1 in two adjacent rows of second pixel units 201 is always less than the spacing between the two first scan signal lines S1 in two adjacent rows of first pixel units 101. In essence, the distance between the two first scan signal lines S1 in two adjacent rows of second pixel units 201 is reduced. This achieves the goal of reducing the length of the second pixel unit 201 in the column direction by only setting the first scan signal line S1 in the second pixel unit 201, and further reducing the spacing between the two rows of second pixel units 201 in the column direction. This is more conducive to reducing the area of ​​the load compensation unit, thereby facilitating the implementation of a narrow bezel design.

[0079] In addition to the above embodiments where only the first pixel unit is provided in the second pixel unit, in this invention, the first scan signal line and the second scan signal line may be provided in the second pixel unit simultaneously. Figure 15 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, for reference. Figure 15 In another embodiment of the present invention, the first pixel unit 101 and the second pixel unit 201 may both include a first scan signal line S1 and a second scan signal line S2; the first scan signal line S1 and the second scan signal line S2 both extend along a first direction X, and the distance D5 between the first scan signal line S1 and the second scan signal line S2 in the second pixel unit 201 is less than the distance D6 between the first scan signal line S1 and the second scan signal line S2 in the first pixel unit 101, and / or, the line width L2 of the first scan signal line S1 and the second scan signal line S2 in the second pixel unit 201 is less than the line width L1 of the first scan signal line S1 and the second scan signal line S2 in the first pixel unit 101.

[0080] Therefore, compared to the first pixel unit 101, the line width and / or spacing of the two scanning signal lines in the second pixel unit 201 are set to be relatively smaller. The purpose is also to compress the second pixel unit 201 in the second direction Y, i.e. the column direction, so as to minimize the area of ​​the load compensation unit and thus achieve a narrow bezel design.

[0081] It should be added that, due to the special design of the line width and spacing of the first scan signal line S1 and the second scan signal line S2 in the second pixel unit 201, this special design may affect the load of the second pixel unit 201, causing it to differ from the load of the first pixel unit 101. Therefore, in this embodiment, it is also possible that the lateral capacitance of the first scan signal line S1 and the second scan signal line S2 in the second pixel unit 201 is equal to the lateral capacitance of the first scan signal line S1 and the second scan signal line S2 in the first pixel unit 101. In this case, even if the line width and spacing of the first scan signal line S1 and the second scan signal line S2 in the second pixel unit 201 are changed, the lateral capacitance of the two scan signal lines can be adjusted by other means, such as using different conductive materials or adding dielectric materials, to avoid excessive load changes.

[0082] Furthermore, the above-described embodiments are essentially simplifications based on existing pixel circuits. In addition to improvements based on existing pixel circuits, the embodiments of the present invention also provide other forms of load compensation units.

[0083] Figure 16 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, for reference. Figure 16 The load compensation unit 221 includes redundant signal lines S_dummy, which extend along the first direction X. The second shift register unit 212 is electrically connected to y redundant signal lines S_dummy, where y is a positive integer and m = n + y.

[0084] In this embodiment, the load compensation structure is essentially achieved by using signal lines as a simple load compensation method for the second shift register unit 212. The number of redundant signal lines S_dummy connected to the second shift register unit 212 is equal to the number of additional display pixel groups 10 (i.e., pixel rows) connected to the first shift register unit 211 compared to the second shift register unit 211. By replacing the pixel rows with redundant signal lines S_dummy, the number of pixel rows connected to the second shift register unit 212 is the same as the number of pixel rows connected to the first shift register unit 211, both being m. This ensures that the loads of the second shift register unit 212 and the first shift register unit 211 are consistent, and the luminous brightness of the pixel rows in the corresponding driven display area 100 is the same.

[0085] Furthermore, the display area 100 includes multiple first signal lines 110, which extend along the second direction Y and to the compensation area 220; redundant signal lines S_dummy overlap with and are insulated from the first signal lines 110. Considering that the load of the pixel unit connected to the shift register unit is mainly reflected in the capacitance inside the pixel unit, when the pixel row is replaced by the redundant signal line S_dummy, the sum of the overlapping capacitance of the redundant signal line S_dummy and the multiple first signal lines 110 can be equal to the capacitance of the display pixel group 10.

[0086] Here, the first signal line 110 can be a power signal line or a reference signal line, and the signals transmitted on it are all fixed potential signals, so they are less affected by the capacitance overlapping with the redundant signal line S_dummy. Optionally, the spacing D7 between two adjacent redundant signal lines S_dummy is greater than or equal to 10μm. In this case, not only can the problem of high fabrication difficulty of redundant signal lines due to insufficient etching precision be avoided, and the fabrication of two redundant signal lines S_dummy is facilitated, but also a small lateral capacitance between the redundant signal lines S_dummy can be ensured, avoiding additional load between the redundant signal lines.

[0087] Furthermore, the first pixel unit 101 includes a first scan signal line S1 and a second scan signal line S2, both of which extend along a first direction X; the display area 100 includes multiple first signal lines 110, which extend along a second direction Y and to the compensation area 220; the redundant signal line S_dummy overlaps with and is insulated from the first signal lines 110. Based on this, the line width L3 of the redundant signal line S_dummy in the area overlapping with the first signal line 110 can be set to be greater than the line width L1 of the first scan signal line S1 and the second scan signal line S2, and / or, the line width L4 of the first signal line 110 in the area overlapping with the redundant signal line S_dummy can be greater than the line width L5 of the first signal line 110 in the display area 100.

[0088] In this embodiment, the redundant signal line S_dummy overlaps with the signal line extending longitudinally to the compensation region 220 to form a capacitor, which serves as a load compensation to the second shift register unit 212. Increasing the linewidth of the overlapping area between the redundant signal line S_dummy and the first signal line 110 essentially increases the overlapping area, i.e., increases the size of the overlapping capacitor, thereby ensuring that the redundant signal line S_dummy forms a sufficient overlapping capacitor to compensate the second shift register unit 212.

[0089] Based on the above-described method of adjusting the load by improving the linewidth of the overlapping area, in other embodiments of the present invention, the linewidth L6 of the redundant signal line S_dummy in the area not overlapping with the first signal line 110 can be set to be smaller than the linewidth L1 of the first scan signal line S1 and the second scan signal line S2. In this case, for the entire redundant signal line S_dummy, widening the linewidth of a portion of the overlapping area can easily cause a change in the overall resistance of the redundant signal line S_dummy. Correspondingly, appropriately narrowing the linewidth of the non-overlapping area can compensate for the overall resistance, ensuring consistency in the resistive load of the display pixel group connected to the first shift register unit 211.

[0090] Figure 17 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention, for reference. Figure 17 In other embodiments of the present invention, the load compensation unit 221 may optionally include a compensation capacitor 2211, and the second shift register unit 212 may be electrically connected to at least one compensation capacitor 2211; and / or, the load compensation unit 221 may include a compensation resistor 2212, and the second shift register unit 212 may be electrically connected to at least one compensation resistor 2211.

[0091] In this embodiment, the compensation capacitor 2211 and compensation resistor 2212 are actually separate and specially designed capacitor and resistor elements in the bezel area 200 of the display panel. They can achieve certain capacitance and resistance values ​​through material selection, dielectric material, etc., to match the capacitance and resistance values ​​in the reduced load of the second shift register unit 212 relative to the first shift register unit 211. Load compensation is then directly performed using the compensation capacitor 2211 and compensation resistor 2212. It is understood that those skilled in the art can obtain the load difference between the first shift register unit 211 and the second shift register unit 212 through simulation, thereby obtaining the specific values ​​of the compensation capacitor 2211 and compensation resistor 2212, and then fabricating them at appropriate locations in the bezel area of ​​the panel.

[0092] It should be added that the setting of compensation capacitors and compensation resistors should meet the total value and load compensation requirements. There is no restriction on the number of compensation capacitors 2211 and compensation resistors 2212, and their connection method can be series or parallel, which is also not restricted here. Furthermore, as... Figure 17 The placement of the compensation capacitor 2211 and the compensation resistor 2212 between the fan-out area 230 and the display area 100 is merely an example. Those skilled in the art may also place them in other border areas that do not affect the wiring and routing, and there are no restrictions here either.

[0093] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 18This is a schematic diagram of a display device provided in an embodiment of the present invention, with reference to... Figure 18 The display device may include any of the display panels 1 provided in the above embodiments. Furthermore, since the display device is made using the aforementioned display panel, it possesses the same or corresponding technical effects as the aforementioned display panel. It should be noted that the display device also includes other devices for supporting the normal operation of the display device. Specifically, the display device may be a mobile phone, tablet, computer, television, wearable smart device, etc., and the embodiments of the present invention do not impose any limitations.

[0094] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized by, The display panel comprises a display area and a frame area surrounding the display area, the frame area comprises a shift register area and a compensation area, the shift register area is located at least one side of the display area in a first direction; The display area comprises a plurality of display pixel groups, each display pixel group comprises a plurality of first pixel units arranged in sequence along the first direction, and a plurality of display pixel groups are arranged in sequence along a second direction, the first direction intersects the second direction; The shift register area comprises a first shift register unit and a second shift register unit, the first shift register unit is electrically connected with m display pixel groups, and the second shift register unit is electrically connected with n display pixel groups, wherein m and n are positive integers, and m > n; The compensation area comprises a load compensation unit, and the load compensation unit is electrically connected with the second shift register unit; The display panel comprises a plurality of gate control signal lines extending along the first direction, and the gate control signal lines comprise first scan signal lines and second scan signal lines; One first shift register unit is connected with R adjacent display pixel groups through R first scan signal lines and connected with another R adjacent display pixel groups through R second scan signal lines, and R = m / 2; One second shift register unit is connected with n adjacent display pixel groups through n second scan signal lines; The display pixel groups connected by the first shift register unit and the second shift register unit are different; The display pixel group where the second scan signal line electrically connected with the first shift register unit is located is a first display pixel group, the display pixel group where the first scan signal line electrically connected with the first shift register unit is located is a second display pixel group, and the first display pixel group and the second display pixel group are separated by S display pixel groups; R and S are positive integers, and S is an integer multiple of R; The compensation area comprises T load compensation units, and every R adjacent load compensation units are electrically connected with one second shift register unit, and T = R + S.

2. The display panel of claim 1, wherein, The frame area further comprises a fan-out area, and the compensation area is located between the fan-out area and the display area; or the compensation area is located on a side of the display area away from the fan-out area.

3. The display panel of claim 1, wherein, The load compensation unit comprises a compensation pixel group, the compensation pixel group comprises a plurality of second pixel units arranged in sequence along the first direction, and the second shift register unit is electrically connected with x compensation pixel groups, wherein x is a positive integer, and m = n + x.

4. The display panel of claim 3, wherein, The length of the second pixel unit in the second direction is less than the length of the first pixel unit in the second direction.

5. The display panel of claim 3, wherein The first pixel unit and the second pixel unit each comprise a data signal line extending along the second direction and a gate control signal line extending along the first direction; and the gate control signal line intersects the data signal line. The number of the gate control signal lines in the second pixel unit is less than the number of the gate control signal lines in the first pixel unit.

6. The display panel of claim 5, wherein, The gate control signal lines include a first scan signal line, a second scan signal line, a third scan signal line and a light-emitting control signal line. The first pixel unit includes the first scan signal line, the second scan signal line, the third scan signal line and the light-emitting control signal line; and the second pixel unit includes the first scan signal line.

7. The display panel of claim 6, wherein, The first pixel unit and the second pixel unit each include at least one first reference signal line. The first reference signal line extends along the first direction and is located on one side of the first scan signal line in the second direction.

8. The display panel of claim 7, wherein, The spacing between the first reference signal line and the first scan signal line in the first pixel unit is equal to the spacing between the first reference signal line and the first scan signal line in the second pixel unit.

9. The display panel of claim 7, wherein, The number of transistors in one second pixel unit is less than the number of transistors in one first pixel unit.

10. The display panel of claim 9, wherein, The transistors in the first pixel unit include: a driving transistor; a first transistor, a control end of the first transistor being electrically connected with the third scan signal line, a first electrode of the first transistor being electrically connected with a first electrode of the driving transistor, and a second electrode of the first transistor being electrically connected with the data signal line; a second transistor, a control end of the second transistor being electrically connected with the second scan signal line, a first electrode of the second transistor being electrically connected with a gate of the driving transistor, and a second electrode of the second transistor being electrically connected with a second electrode of the driving transistor; a third transistor, a control end of the third transistor being electrically connected with the first scan signal line, a first electrode of the third transistor being electrically connected with the gate of the driving transistor, and a second electrode of the third transistor being electrically connected with the first reference signal line; a fourth transistor, a control end of the fourth transistor being electrically connected with the third scan signal line, a first electrode of the fourth transistor being electrically connected with a first electrode of a light-emitting element, and a second electrode of the fourth transistor being electrically connected with the first reference signal line; a fifth transistor, a control end of the fifth transistor being electrically connected with the light-emitting control signal line, a first electrode of the fifth transistor being electrically connected with the first electrode of the driving transistor, and a second electrode of the fifth transistor being electrically connected with a first power signal line; a sixth transistor, a control end of the sixth transistor being electrically connected with the light-emitting control signal line, a first electrode of the sixth transistor being electrically connected with the second electrode of the driving transistor, and a second electrode of the sixth transistor being electrically connected with the first electrode of the light-emitting element; The transistors in the second pixel unit include: a seventh transistor, a control end of the seventh transistor being electrically connected with the first scan signal line, a first electrode of the seventh transistor being floating, and a second electrode of the seventh transistor being electrically connected with the first reference signal line.

11. The display panel of claim 1, wherein, The load compensation unit comprises a redundant signal line extending along the first direction, and the second shift register unit is electrically connected with y redundant signal lines, wherein y is a positive integer, and m = n + y.

12. The display panel of claim 11, wherein, The display area comprises a plurality of first signal lines extending along the second direction and extending to the compensation area. The redundant signal lines and the first signal lines are mutually overlapped and insulated, and the sum of the overlapping capacitances of the redundant signal lines and the plurality of first signal lines is equal to the capacitance of the display pixel group.

13. The display panel of claim 11, wherein, The first pixel unit comprises a first scan signal line and a second scan signal line, and the first scan signal line and the second scan signal line both extend along the first direction. The display area comprises a plurality of first signal lines extending along the second direction and extending to the compensation area. The line width of the redundant signal line in the region overlapping with the first signal line is greater than the line width of the first scan signal line and the second scan signal line, and / or the line width of the first signal line in the region overlapping with the redundant signal line is greater than the line width of the first signal line in the display area.

14. The display panel of claim 13, wherein, The first signal line comprises a power signal line and a reference signal line.

15. The display panel of claim 13, wherein, The spacing between two adjacent redundant signal lines is greater than or equal to 10 μm.

16. The display panel of claim 13, wherein, The line width of the redundant signal line in the region not overlapping with the first signal line is less than the line width of the first scan signal line and the second scan signal line.

17. The display panel of claim 1, wherein, The load compensation unit comprises a compensation capacitor, and the second shift register unit is electrically connected with at least one compensation capacitor. And / or, the load compensation unit comprises a compensation resistor, and the second shift register unit is electrically connected with at least one compensation resistor.

18. A display device comprising: The display panel comprises the display panel as claimed in any one of claims 1-17.

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