Clock division circuit

Abstract

The present invention discloses a clock frequency division circuit, belonging to the clock frequency division technology. The circuit includes an enable module that obtains a switching signal based on a first input clock signal and a fifth signal; a division ratio configuration word adjustment module that samples an input division ratio configuration word with a second clock signal to obtain a first division ratio configuration word, and samples the first division ratio configuration word with the second clock signal to obtain a second division ratio configuration word; a dynamic frequency divider module that divides or does not divide a second input clock signal under the control of an output signal division ratio configuration word and outputs a first output clock signal; the first output clock signal is inverted to obtain a second output clock signal, the second output clock signal is inverted to obtain a third clock signal, the third clock signal is inverted to obtain the second clock signal, and a final output clock signal is obtained by performing a NOR operation on the second output clock signal and a thirteenth signal. The present invention can achieve dynamic frequency division of an output clock signal, and no glitches will occur in the output clock signal.

Description

Technical Field

[0001] The present invention relates to a frequency division circuit, and more particularly to a clock frequency division circuit. Background Art

[0002] When performing clock dynamic frequency division applications, generally, most of the control signals are used to control the reset state of D flip-flops. When the control signal remains unchanged, the working state of the D flip-flop is stable. However, when the control signal switches states, the working state of the D flip-flop will change, and this jumping signal is fed back to the output clock waveform through the coupling capacitance between MOS transistors. As a result, when the control signal switches states, the frequency of the output clock signal will change with the control signal, causing the waveform of the output clock signal to generate glitches, resulting in an unstable output clock signal. Therefore, a circuit is needed that can still output the output clock signal normally and without generating glitches when the control signal changes. On this basis, the frequency division ratio of the output clock signal can be adjusted. Summary of the Invention

[0003] The purpose of the present invention is to provide a clock frequency division circuit with an adjustable frequency division ratio of the output clock signal and without generating glitches.

[0004] The present invention is achieved by the following technical solutions:

[0005] A clock frequency division circuit includes:

[0006] An enable module for obtaining a switch signal based on a first input clock signal and a fifth signal;

[0007] The frequency division ratio configuration word adjustment module is used to sample the input frequency division ratio configuration word through a third D flip - flop with a second clock signal to obtain a first frequency division ratio configuration word, sample the first frequency division ratio configuration word through a fourth D flip - flop with the second clock signal to obtain a second frequency division ratio configuration word, sample the second frequency division ratio configuration word through a fifth D flip - flop with the second clock signal to obtain a third frequency division ratio configuration word, sample the second frequency division ratio configuration word through a sixth D flip - flop with a switch signal to obtain an output signal frequency division ratio configuration word, and perform an exclusive - OR operation on the second frequency division ratio configuration word and the third frequency division ratio configuration word to obtain a first exclusive - OR output signal; it is used to perform an exclusive - OR operation on a seventh signal and the first exclusive - OR output signal to obtain a second exclusive - OR output signal, sample the second exclusive - OR output signal through a seventh D flip - flop with the second clock signal to obtain a sixth signal, perform an AND operation on the sixth signal and a fifth signal to obtain a seventh signal, obtain an eighth signal after passing the sixth signal through a second buffer, sample a ninth signal through an eighth D flip - flop with a third clock signal to obtain a tenth signal, invert the tenth signal to obtain a ninth signal, sample the fifth signal through a ninth D flip - flop with the ninth signal to obtain an eleventh signal, invert the eleventh signal to obtain a fifth signal, sample the eighth signal through a tenth D flip - flop with the second clock signal to obtain a twelfth signal, and obtain a thirteenth signal after passing the twelfth signal through a third buffer; wherein, the eighth signal is respectively input to the reset terminals of the eighth D flip - flop and the ninth D flip - flop; the input frequency division ratio configuration word is respectively input to the ID terminals of the third D flip - flop, the fourth D flip - flop, the fifth D flip - flop, and the sixth D flip - flop;

[0008] The dynamic frequency divider module divides or does not divide the second input clock signal under the control of the output signal frequency division ratio configuration word, and its output terminal outputs a first output clock signal;

[0009] Wherein, the first input clock signal and the second input clock signal are a pair of differential clock signals, the first output clock signal is inverted to obtain a second output clock signal, the second output clock signal is inverted to obtain a third clock signal, the third clock signal is inverted to obtain a second clock signal, and the second output clock signal and the thirteenth signal are subjected to a NOR operation to obtain a final output clock signal.

[0010] The specific method for the enabling module to obtain the switch signal based on the first input clock signal and the fifth signal is as follows: invert the first input clock signal to obtain a first clock signal, perform an AND operation on the fourth signal and the fifth signal to obtain a first signal, sample the first signal with the first clock signal to obtain a second signal, sample the second signal with the first clock signal to obtain a third signal, and invert the third signal to obtain the switch signal.

[0011] The enabling module is also used to invert the result of the AND - OR operation of the total switch enabling signal and the dynamic frequency division mode switch signal to obtain a fourth signal.

[0012] The reset terminals of the third D flip-flop, the fourth D flip-flop, the fifth D flip-flop, the sixth D flip-flop, the seventh D flip-flop, and the tenth D flip-flop are respectively input with a second reset signal.

[0013] The second reset signal is obtained by performing a NOR operation on the input reset signal and the fourteenth signal.

[0014] Compared with the prior art, the present invention has the following beneficial technical effects:

[0015] The present invention can achieve dynamic frequency division of the output clock signal, and no glitch will occur in the output clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a circuit principle block diagram of the present invention;

[0017] Figure 2 is a circuit schematic diagram of the enable module of the present invention;

[0018] Figure 3 is a partial circuit schematic diagram of the frequency division ratio configuration word adjustment module of the present invention;

[0019] Figure 4 is the remaining circuit schematic diagram of the frequency division ratio configuration word adjustment module of the present invention;

[0020] Figure 5 is the overall timing diagram of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] All features disclosed in this specification, or all steps in any method or process disclosed, except for mutually exclusive features and / or steps, can be combined in any manner, and unless specifically stated, can be replaced by other equivalent or features with similar purposes, that is, unless specifically stated, each feature is only one embodiment in a series of equivalent or similar features.

[0022] See Figure 1 , a clock frequency division circuit of the present invention includes an enable module, a frequency division ratio configuration word adjustment module, a dynamic frequency divider module, a fifth inverter inv5, a second NOR gate nor2, and a fourth buffer buf4.

[0023] The enable module is used to obtain a switch signal CKAXI_PD based on the first input clock signal CKIN_DIV2 and the fifth signal SER2.

[0024] See Figure 2, specifically, the enabling module includes a first inverter inv1, a first NAND gate nand1, a second inverter inv2, a first AND gate and1, a first D flip-flop dff1, a second D flip-flop dff2, a third inverter inv3, and a fourth inverter inv4.

[0025] The first input clock signal CKIN_DIV2 is input to the first inverter inv1, and the first inverter inv1 outputs the first clock signal CKIP_DIV2_BUF, achieving inversion of the first input clock signal CKIN_DIV2 to obtain the first clock signal CKIP_DIV2_BUF. The result of the AND-OR operation of the total switch enabling signal POWER_ON and the dynamic frequency division mode switch signal CHAXI_EN input to the first NAND gate nand1 respectively is input to the second inverter inv2 for inversion, and the second inverter inv2 outputs the fourth signal SER1, that is, achieving inversion of the result of the AND-OR operation of the total switch enabling signal POWER_ON and the dynamic frequency division mode switch signal CHAXI_EN to obtain the fourth signal SER1. The dynamic frequency division mode switch signal CHAXI_EN is the enabling signal for controlling the dynamic switching switch of the frequency division ratio. The function of the fourth signal SER1 is to establish the logical relationship between the total switch enabling signal POWER_ON and the dynamic frequency division mode switch signal CHAXI_EN.

[0026] The fourth signal SER1 and the fifth signal SER2 are input to the first AND gate and1 for AND operation to obtain the first signal D1. The function of the fifth signal SER2 is to establish the connection between the enabling module and the frequency division ratio configuration word adjustment module. The first clock signal CKIP_DIV2_BUF is input to the clock input terminal of the first D flip-flop dff1, and the first signal D1 is input to the data input terminal of the first D flip-flop dff1. The Q terminal of the first D flip-flop dff1 outputs the second signal D2, achieving sampling of the first signal D1 with the first clock signal CKIP_DIV2_BUF to obtain the second signal D2. The first clock signal CKIP_DIV2_BUF is input to the clock input terminal of the first D flip-flop dff1, and the second signal D2 is input to the data input terminal of the second D flip-flop dff2. The Q terminal of the second D flip-flop dff2 outputs the third signal Q1, achieving sampling of the second signal D2 with the first clock signal CKIP_DIV2_BUF to obtain the third signal Q1. The third signal Q1 is input to the fourth inverter inv4, and the fourth inverter inv4 outputs the switch signal CKAXI_PD, achieving inversion of the third signal Q1 to obtain the switch signal CKAXI_PD.

[0027] The main switch enable signal POWER_ON is input to the third inverter inv3. The third inverter inv3 outputs the first reset signal RST1. The first reset signal RST1 is respectively input to the reset terminals of the first D flip-flop dff1 and the second D flip-flop dff2. For example, when the first reset signal RST1 is at a high level, the first D flip-flop dff1 and the second D flip-flop dff2 are in a reset state.

[0028] See Figure 3 , Figure 4 , specifically, the frequency division ratio configuration word adjustment module includes a first buffer buf1, a third D flip-flop dff3, a fourth D flip-flop dff4, a fifth D flip-flop dff5, a sixth D flip-flop dff6, a first exclusive-OR gate xor1, a first NOR gate nor1, a second exclusive-OR gate xor2, a seventh D flip-flop dff7, a second AND gate and2, a second buffer buf2, an eighth D flip-flop dff8, a sixth inverter inv6, a ninth D flip-flop dff9, a seventh inverter inv7, a third buffer buf3, an eighth inverter inv8, and a ninth inverter inv9.

[0029] See Figure 3, the input frequency division ratio configuration word CKAXI_CTL<1:0> is input to the data input terminal of the third D flip-flop dff3 through the first buffer buf1, the second clock signal CLKB_AXI_BUF is input to the clock input terminal of the third D flip-flop dff3, and the Q terminal of the third D flip-flop dff3 outputs the first frequency division ratio configuration word, realizing sampling the input frequency division ratio configuration word CKAXI_CTL<1:0> with the second clock signal CLKB_AXI_BUF through the third D flip-flop dff3 to obtain the first frequency division ratio configuration word. The first frequency division ratio configuration word is input to the data input terminal of the fourth D flip-flop dff4, the second clock signal CLKB_AXI_BUF is input to the clock input terminal of the fourth D flip-flop dff4, and the Q terminal of the fourth D flip-flop dff4 outputs the second frequency division ratio configuration word CKAXI_CTL_BUF1<1:0>, realizing sampling the first frequency division ratio configuration word with the second clock signal CLKB_AXI_BUF through the fourth D flip-flop dff4 to obtain the second frequency division ratio configuration word CKAXI_CTL_BUF1<1:0>. The second frequency division ratio configuration word CKAXI_CTL_BUF1<1:0> is input to the data input terminal of the fifth D flip-flop dff5, the second clock signal CLKB_AXI_BUF is input to the clock input terminal of the fifth D flip-flop dff5, and the Q terminal of the fifth D flip-flop dff5 outputs the third frequency division ratio configuration word CKAXI_CTL_BUF2<1:0>, realizing sampling the second frequency division ratio configuration word CKAXI_CTL_BUF1<1:0> with the second clock signal CLKB_AXI_BUF through the fifth D flip-flop dff5 to obtain the third frequency division ratio configuration word CKAXI_CTL_BUF2<1:0>. The second frequency division ratio configuration word CKAXI_CTL_BUF1<1:0> is input to the data input terminal of the sixth D flip-flop dff6, the switch signal CKAXI_PD is input to the clock input terminal of the sixth D flip-flop dff6, and the Q terminal of the sixth D flip-flop dff6 outputs the output signal frequency division ratio configuration word CKAXI_CTL_LOAD<1:0>, realizing sampling the second frequency division ratio configuration word CKAXI_CTL_BUF1<1:0> with the switch signal CKAXI_PD through the sixth D flip-flop dff6 to obtain the output signal frequency division ratio configuration word CKAXI_CTL_LOAD<1:0>. The second frequency division ratio configuration word CKAXI_CTL_BUF1<1:0> and the third frequency division ratio configuration word CKAXI_CTL_BUF2<1:0> are respectively input to the first exclusive-OR gate xor1, and the first exclusive-OR gate xor1 outputs the first exclusive-OR output signal CKAXI_XOR<1:0>, realizing performing an exclusive-OR operation on the second frequency division ratio configuration word CKAXI_CTL_BUF1<1:0> and the third frequency division ratio configuration word CKAXI_CTL_BUF2<1:0> to obtain the first exclusive-OR output signal CKAXI_XOR<1:0>.The input division ratio configuration words CKAXI_CTL<1:0> are respectively input to the ID terminals of the third D flip-flop dff3, the fourth D flip-flop dff4, the fifth D flip-flop dff5, and the sixth D flip-flop dff6.

[0030] The input reset signal RST and the fourteenth signal BYPS are respectively input to the first NOR gate nor1. The first NOR gate nor1 outputs the second reset signal RSTB, implementing the NOR operation on the input reset signal RST and the fourteenth signal BYPS to obtain the second reset signal RSTB. The second reset signal RSTB is respectively input to the reset terminals of the third D flip-flop dff3, the fourth D flip-flop dff4, the fifth D flip-flop dff5, and the sixth D flip-flop dff6.

[0031] See Figure 4, the seventh signal SER4 and the first exclusive-OR output signal CKAXI_XOR<1:0> are respectively input into the second exclusive-OR gate xor2. The second exclusive-OR gate xor2 outputs the second exclusive-OR output signal RATE_CHANGE_NAND, realizing the exclusive-OR operation of the seventh signal SER4 and the first exclusive-OR output signal CKAXI_XOR<1:0> to obtain the second exclusive-OR output signal RATE_CHANGE_NAND. The second exclusive-OR output signal RATE_CHANGE_NAND is input into the data input terminal of the seventh D flip-flop dff7, and the second clock signal CLKB_AXI_BUF is input into the clock input terminal of the seventh D flip-flop dff7. The Q terminal of the seventh D flip-flop dff7 outputs the sixth signal SER3, realizing sampling the second exclusive-OR output signal RATE_CHANGE_NAND with the second clock signal CLKB_AXI_BUF through the seventh D flip-flop dff7 to obtain the sixth signal SER3. The sixth signal SER3 and the fifth signal SER2 are respectively input into the second AND gate and2. The second AND gate and2 outputs the seventh signal SER4, realizing the AND operation of the sixth signal SER3 and the fifth signal SER2 to obtain the seventh signal SER4. The sixth signal SER3 is input into the second buffer buf2. The second buffer buf2 outputs the eighth signal RATE_CHANGE_PRE, realizing obtaining the eighth signal RATE_CHANGE_PRE after the sixth signal SER3 passes through the second buffer buf2. The ninth signal RST_PRE is input into the data input terminal of the eighth D flip-flop dff8, and the third clock signal CLKB_AXI_INV is input into the clock input terminal of the eighth D flip-flop dff8. The Q terminal of the eighth D flip-flop dff8 outputs the tenth signal, realizing sampling the ninth signal RST_PRE with the third clock signal CLKB_AXI_INV through the eighth D flip-flop dff8 to obtain the tenth signal. The tenth signal is input into the sixth inverter inv6. The sixth inverter inv6 outputs the ninth signal RST_PRE, realizing inverting the tenth signal to obtain the ninth signal RST_PRE. The fifth signal SER2 is input into the data input terminal of the ninth D flip-flop dff9, and the ninth signal RST_PRE is input into the clock input terminal of the ninth D flip-flop dff9. The Q terminal of the ninth D flip-flop dff9 outputs the eleventh signal, realizing sampling the fifth signal SER2 with the ninth signal RST_PRE through the ninth D flip-flop dff9 to obtain the eleventh signal. The eleventh signal is input into the seventh inverter inv7. The seventh inverter inv7 outputs the fifth signal SER2, realizing inverting the eleventh signal to obtain the fifth signal SER2.The eighth signal RATE_CHANGE_PRE is input to the data input terminal of the tenth D flip-flop dff10, and the second clock signal CLKB_AXI_BUF is input to the clock input terminal of the tenth D flip-flop dff10. The Q terminal of the tenth D flip-flop dff10 outputs the twelfth signal, realizing sampling the eighth signal RATE_CHANGE_PRE through the tenth D flip-flop dff10 with the second clock signal CLKB_AXI_BUF to obtain the twelfth signal. The twelfth signal is input to the third buffer buf3, and the third buffer buf3 outputs the thirteenth signal RATE_CHANGE, realizing obtaining the thirteenth signal RATE_CHANGE after passing the twelfth signal through the third buffer buf3.

[0032] The eighth signal RATE_CHANGE_PRE is respectively input to the reset terminals of the eighth D flip-flop dff8 and the ninth D flip-flop dff9. The second reset signal RSTB is respectively input to the reset terminals of the seventh D flip-flop dff7 and the tenth D flip-flop dff10.

[0033] For example, when the second reset signal RSTB is at a low level and the ID terminal is at a high level, the third D flip-flop dff3, the fourth D flip-flop dff4, the fifth D flip-flop dff5, and the sixth D flip-flop dff6 are all in a reset state; when the second reset signal RSTB is at a low level, the seventh D flip-flop dff7 and the tenth D flip-flop dff10 are both in a reset state. The meaning of the fourteenth signal BYPS is that when the fourteenth signal BYPS is at a high level and the input frequency division ratio configuration word CKAXI_CTL<1:0> is at a high level, the frequency division ratio configuration word adjustment module will be in a reset state, which can also be understood as that in the reset state, the frequency division ratio configuration word adjustment function does not work.

[0034] See Figure 1 、 Figure 5 , the dynamic frequency divider module divides or does not divide the second input clock signal CKIP_DIV2 under the control of the output signal frequency division ratio configuration word CKAXI_CTL_LOAD<1:0>, and its output terminal outputs the first output clock signal CLK_AXI_PRE. The first input clock signal CKIN_DIV2 and the second input clock signal CKIP_DIV2 are a group of differential clock signals.

[0035] See Figure 1, the first output clock signal CLK_AXI_PRE is input to the fifth inverter inv5, and the fifth inverter inv5 outputs the second output clock signal CLKB_AXI, realizing that the first output clock signal CLK_AXI_PRE is inverted to obtain the second output clock signal CLKB_AXI. The second output clock signal CLKB_AXI is input to the ninth inverter inv9, and the ninth inverter inv9 outputs the third clock signal CLKB_AXI_INV, realizing that the second output clock signal CLKB_AXI is inverted to obtain the third clock signal CLKB_AXI_INV. The third clock signal CLKB_AXI_INV is input to the eighth inverter inv8, and the eighth inverter inv8 outputs the second clock signal CLKB_AXI_BUF, realizing that the third clock signal CLKB_AXI_INV is inverted to obtain the second clock signal CLKB_AXI_BUF. The second output clock signal CLKB_AXI and the thirteenth signal RATE_CHANGE are respectively input to the second nor gate nor2, and the signal output by the second nor gate nor2 is input to the fourth buffer buf4, and the fourth buffer buf4 outputs the final output clock signal CLK_AXI, realizing that the second output clock signal CLKB_AXI and the thirteenth signal RATE_CHANGE are NOR-operated to obtain the final output clock signal CLK_AXI.

[0036] The switch signal CKAXI_PD is also sent to the input end of the dynamic frequency divider module. When the switch signal CKAXI_PD is at a high level, the dynamic frequency divider module does not work.

[0037] See Figure 5, before the main switch enable signal POWER_ON is at a high level, the present invention is in an off state and there is no clock output. Before the dynamic frequency division mode switch signal CHAXI_EN is at a high level, the dynamic frequency divider module is in an off state. Only after the main switch enable signal POWER_ON and the dynamic frequency division mode switch signal CHAXI_EN are at a high level, and when the fourteenth signal BYPS is 0, the invention enters the dynamic frequency division ratio adjustment mode. At the moment when the input frequency division ratio configuration word CKAXI_CTL<1:0> starts to change, the eighth signal RATE_CHANGE_PRE changes from a low level to a high level at the third rising edge of the second output clock signal CLKB_AXI. After that, the ninth signal RST_PRE changes from a high level to a low level, lasting for one clock cycle of the second output clock signal CLKB_AXI. The fifth signal SER2 changes from a high level to a low level along with the ninth signal RST_PRE, lasting for half a clock cycle of the second output clock signal CLKB_AXI, so that the switch signal CKAXI_PD also changes from a low level to a high level following the fifth signal SER2. When the thirteenth signal RATE_CHANGE changes from a low level to a high level, the final output clock signal CLK_AXI output by the present invention is 0. Only when it is confirmed that the thirteenth signal RATE_CHANGE signal is at a low level, the dynamic frequency divider module will normally output the first output clock signal CLK_AXI_PRE, so that the present invention outputs the final output clock signal CLK_AXI.

[0038] During the above dynamic frequency division process, there are no glitches in the final output clock signal CLK_AXI output by the present invention. At the same time, by confirming the state of the thirteenth signal RATE_CHANGE, normal clock frequency division is completed during the switching process of the input frequency division ratio configuration word CKAXI_CTL<1:0>.

[0039] In the present invention, the frequency division ratio configuration word adjustment module mainly meets the timing requirements during the dynamic switching of the frequency division ratio, and converts the input frequency division ratio configuration word CKAXI_CTL<1:0> into the output signal frequency division ratio configuration word CHAXI_CTL_LOAD<1:0>. CKAXI_CTL_LOAD<1:0> is a 2-bit character used to control the configuration word signal for adjusting the frequency division ratio. The adjustable frequency division ratio means that the second input clock signal CKIP_DIV2 is divided by 1, 2, 4, 8, etc. The dynamic frequency divider module is responsible for dividing the second input clock signal CKIP_DIV2 through identifying the timing relationship between the output signal frequency division ratio configuration word CKAXI_CTL_LOAD<1:0> and the switch signal CKAXI_PD, to obtain an output clock signal without glitches.

[0040] In the present invention, the input frequency division ratio configuration word CKAXI_CTL<1:0> is sampled by a D flip-flop and then delayed and sent to the dynamic frequency division module. If the input frequency division ratio configuration word CKAXI_CTL<1:0> is not processed, it will directly cause glitches in the output clock. However, through the sampling delay of the D flip-flop, the output signal frequency division ratio configuration word CHAXI_CTL_LOAD<1:0> that has a timing relationship with the enable module is obtained. When the input frequency division ratio configuration word CKAXI_CTL<1:0> changes, the output signal frequency division ratio configuration word CHAXI_CTL_LOAD<1:0> also changes. However, the output signal frequency division ratio configuration word CHAXI_CTL_LOAD<1:0> is also controlled by the switch signal CKAXI_PD. Only when the switch signal CKAXI_PD is at a high level can the state of the output signal frequency division ratio configuration word CHAXI_CTL_LOAD<1:0> be received by the dynamic frequency division module. This enables the output clock to maintain its previous state during the change stage of the original input frequency division ratio configuration word CKAXI_CTL<1:0>. After the change of the frequency division ratio configuration word is completed, the state of the output signal frequency division ratio configuration word CHAXI_CTL_LOAD<1:0> after being sampled and delayed by the D flip-flop is judged to determine the frequency division ratio after the change. For example, when it is judged that the output signal frequency division ratio configuration word CHAXI_CTL_LOAD<1:0> is 00, the dynamic frequency division module selects no frequency division; when it is judged that the output signal frequency division ratio configuration word CHAXI_CTL_LOAD<1:0> is 01, it selects a frequency division by 2; when it is judged that the output signal frequency division ratio configuration word CHAXI_CTL_LOAD<1:0> is 10, it selects a frequency division by 4; when it is judged that the output signal frequency division ratio configuration word CHAXI_CTL_LOAD<1:0> is 11, it selects a frequency division by 8, thus realizing that the frequency division ratio of the output clock signal is adjustable and no glitches will be generated.

[0041] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A clock frequency division circuit, characterized in that, Comprising: An enabling module, which is used to obtain a switching signal (CKAXI_PD) based on a first input clock signal (CKIN_DIV2) and a fifth signal (SER2); The frequency division ratio configuration word adjustment module is used to sample the input frequency division ratio configuration word (CKAXI_CTL<1:0>) with the second clock signal (CLKB_AXI_BUF) through the third D flip-flop (dff3) to obtain the first frequency division ratio configuration word, sample the first frequency division ratio configuration word with the second clock signal (CLKB_AXI_BUF) through the fourth D flip-flop (dff4) to obtain the second frequency division ratio configuration word (CKAXI_CTL_BUF1<1:0>), sample the second frequency division ratio configuration word (CKAXI_CTL_BUF1<1:0>) with the second clock signal (CLKB_AXI_BUF) through the fifth D flip-flop (dff5) to obtain the third frequency division ratio configuration word (CKAXI_CTL_BUF2<1:0>), sample the second frequency division ratio configuration word (CKAXI_CTL_BUF1<1:0>) with the switch signal (CKAXI_PD) through the sixth D flip-flop (dff6) to obtain the output signal frequency division ratio configuration word (CKAXI_CTL_LOAD<1:0>), perform an exclusive OR operation on the second frequency division ratio configuration word (CKAXI_CTL_BUF1<1:0>) and the third frequency division ratio configuration word (CKAXI_CTL_BUF2<1:0>) to obtain the first exclusive OR output signal (CKAXI_XOR<1:0>); it is used to perform an exclusive OR operation on the seventh signal (SER4) and the first exclusive OR output signal (CKAXI_XOR<1:0>) to obtain the second exclusive OR output signal (RATE_CHANGE_NAND), sample the second exclusive OR output signal (RATE_CHANGE_NAND) with the second clock signal (CLKB_AXI_BUF) through the seventh D flip-flop (dff7) to obtain the sixth signal (SER3), perform an AND operation on the sixth signal (SER3) and the fifth signal (SER2) to obtain the seventh signal (SER4), obtain the eighth signal (RATE_CHANGE_PRE) after passing the sixth signal (SER3) through the second buffer (buf2), sample the ninth signal (RST_PRE) with the third clock signal (CLKB_AXI_INV) through the eighth D flip-flop (dff8) to obtain the tenth signal, invert the tenth signal to obtain the ninth signal (RST_PRE), sample the fifth signal (SER2) with the ninth signal (RST_PRE) through the ninth D flip-flop (dff9) to obtain the eleventh signal, invert the eleventh signal to obtain the fifth signal (SER2), sample the eighth signal (RATE_CHANGE_PRE) with the second clock signal (CLKB_AXI_BUF) through the tenth D flip-flop (dff10) to obtain the twelfth signal, and obtain the thirteenth signal (RATE_CHANGE) after passing the twelfth signal through the third buffer (buf3);Among them, the eighth signal (RATE_CHANGE_PRE) is respectively input to the reset terminals of the eighth D flip-flop (dff8) and the ninth D flip-flop (dff9); the input frequency division ratio configuration word (CKAXI_CTL<1:0>) is respectively input to the ID terminals of the third D flip-flop (dff3), the fourth D flip-flop (dff4), the fifth D flip-flop (dff5), and the sixth D flip-flop (dff6); A dynamic frequency divider module, which divides or does not divide the second input clock signal (CKIP_DIV2) under the control of an output signal frequency division ratio configuration word (CKAXI_CTL_LOAD<1:0>), and its output terminal outputs a first output clock signal (CLK_AXI_PRE); Wherein, the first input clock signal (CKIN_DIV2) and the second input clock signal (CKIP_DIV2) are a group of differential clock signals, the first output clock signal (CLK_AXI_PRE) is inverted to obtain a second output clock signal (CLKB_AXI), the second output clock signal (CLKB_AXI) is inverted to obtain a third clock signal (CLKB_AXI_INV), the third clock signal (CLKB_AXI_INV) is inverted to obtain a second clock signal (CLKB_AXI_BUF), and the second output clock signal (CLKB_AXI) and a thirteenth signal (RATE_CHANGE) are subjected to a NOR operation to obtain a final output clock signal (CLK_AXI).

2. The clock frequency division circuit according to claim 1, wherein The enabling module obtains the switching signal (CKAXI_PD) based on the first input clock signal (CKIN_DIV2) and the fifth signal (SER2) specifically as follows: the first input clock signal (CKIN_DIV2) is inverted to obtain a first clock signal (CKIP_DIV2_BUF), the fourth signal (SER1) and the fifth signal (SER2) are subjected to an AND operation to obtain a first signal (D1), the first clock signal (CKIP_DIV2_BUF) is used to sample the first signal (D1) to obtain a second signal (D2), the first clock signal (CKIP_DIV2_BUF) is used to sample the second signal (D2) to obtain a third signal (Q1), and the third signal (Q1) is inverted to obtain the switching signal (CKAXI_PD).

3. The clock division circuit according to claim 2, wherein The enabling module is further used to invert the result of the AND-OR operation of the total switch enabling signal (POWER_ON) and the dynamic frequency division mode switch signal (CHAXI_EN) to obtain the fourth signal (SER1).

4. The clock division circuit according to claim 1, wherein The reset terminals of the third D flip-flop (dff3), the fourth D flip-flop (dff4), the fifth D flip-flop (dff5), the sixth D flip-flop (dff6), the seventh D flip-flop (dff7), and the tenth D flip-flop (dff10) are respectively input with a second reset signal (RSTB).

5. The clock division circuit according to claim 4, wherein The second reset signal (RSTB) is obtained by performing a NOR operation on the input reset signal (RST) and a fourteenth signal (BYPS).

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