A high-precision and low-power CDAC circuit

Abstract

The present invention belongs to the technical field of analog-to-digital converters, and particularly relates to a high-precision and low-power CDAC circuit. The present invention mainly includes a segmented capacitor module, a sampling switch module, and a common-mode voltage generator module. The present invention is a capacitive DAC based on charge redistribution. By utilizing the characteristic of capacitors storing charge, when the upper plate of the capacitor is suspended at the end of sampling, the sampling and holding of the input signal can be completed without an additional sampling and holding circuit; the present invention adopts a three-stage capacitor array, which greatly reduces the area of the capacitor while maintaining the linearity of the capacitor, thereby achieving high precision; in the present invention, the CDAC adopts a split capacitor technology, and the switch switching mode is a non-setting monotonic capacitor switching mode, which saves most of the power consumption compared with the traditional setting-type switch switching mode, realizing low power consumption; in the present invention, the CDAC adopts a structure without a common-mode voltage, eliminating the power consumption of the external common-mode voltage and related common-mode driving, reducing the power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog-to-digital converters, and particularly relates to a high-precision and low-power CDAC circuit. Background Art

[0002] Today's world is a digital world. As a bridge between the analog world and the digital world, the analog-to-digital converter is particularly important and is often an important factor restricting system performance. With the enhancement of people's health awareness, medical detection devices will gradually enter thousands of households. At present, in medical devices, such as medical imaging systems like digital X-rays and magnetic resonance imaging, high requirements are put forward for the performance of analog-to-digital converters, and the analog-to-digital converter is required to have high precision (precision greater than 16 bits). In addition, the requirement for power consumption is also as low as possible. In analog-to-digital converters, successive approximation analog-to-digital converters have received extensive attention due to their simple structure, small area, and the ability to achieve high precision and low power consumption.

[0003] In a successive approximation analog-to-digital converter, the CDAC is one of the most important modules. For the CDAC module of a successive approximation analog-to-digital converter, as the resolution of the analog-to-digital converter increases, the number of capacitors increases exponentially. When the resolution of the analog-to-digital converter exceeds 14 bits, due to the too large capacitor area, it is difficult to integrate the capacitors on the chip. At the same time, due to the too large capacitors, in order to ensure that the voltage on the capacitors is established to sufficient precision, the size of the switches also increases, resulting in the aggravation of non-ideal factors such as charge injection and clock feedthrough of the switches. The above problems make it difficult to achieve high precision.

[0004] For the traditional CDAC switch switching method, each time the potential of the lower plate of the capacitor is switched according to the comparison result, it is also necessary to set the potential of the lower plate of the capacitor in the previous bit. For each conversion cycle, the setting operation will generate a large amount of power consumption. When the CDAC samples, the upper plate of the capacitor needs to be connected to the common-mode voltage. For the common-mode voltage provided externally by the circuit, due to the too large capacitors of the high-precision CDAC, a large drive is required for the common-mode voltage, which will also generate a large amount of power consumption. Summary of the Invention

[0005] In view of the above problems, the present invention proposes a high-precision and low-power CDAC circuit.

[0006] The technical solution adopted by the present invention is as follows:

[0007] A high-precision and low-power CDAC circuit includes a segmented capacitor module, a sampling switch module, and a common-mode voltage generator module;

[0008] The segmented capacitor module includes a first capacitor array, a second capacitor array, a third capacitor array, a fourth capacitor array, a fifth capacitor array, a sixth capacitor array, a seventh capacitor array, an eighth capacitor array, a first bridging capacitor, a second bridging capacitor, a third bridging capacitor, and a fourth bridging capacitor;

[0009] The first connection terminal of the first bridging capacitor is connected to the upper plates of the first capacitor array and the second capacitor array, and the second connection terminal is connected to the upper plate of the third capacitor array; the first connection terminal of the second bridging capacitor is connected to the upper plate of the third capacitor array, and the second connection terminal is connected to the upper plate of the fourth capacitor array;

[0010] The first connection terminal of the third bridging capacitor is connected to the upper plates of the fifth capacitor array and the sixth capacitor array, and the second connection terminal of the third bridging capacitor is connected to the upper plate of the seventh capacitor array; the first connection terminal of the fourth bridging capacitor is connected to the upper plate of the seventh capacitor array, and the second connection terminal of the fourth bridging capacitor is connected to the upper plate of the eighth capacitor array;

[0011] The input terminal of the first sampling switch is connected to the VINP signal in the differential input signal, and the output terminal is connected to the lower capacitor plates of the first capacitor array and the second capacitor array. After sampling is completed, the sampled signal is output to the subsequent circuit through the upper plates of the first capacitor array and the second capacitor array; the input terminal of the second sampling switch is connected to the VINN signal in the differential input signal, and the output terminal is connected to the lower capacitor plates of the fifth capacitor array and the sixth capacitor array. After sampling is completed, the sampled signal is output to the subsequent circuit through the upper plates of the fifth capacitor array and the sixth capacitor array;

[0012] The common-mode voltage generator module includes a first common-mode voltage generator and a second common-mode voltage generator. The inputs of the first common-mode voltage generator and the second common-mode voltage generator are both external control signals; the first output terminal of the first common-mode voltage generator is connected to the lower plate of the first capacitor array, and the second output terminal is connected to the lower plate of the second capacitor array; the first output terminal of the second common-mode voltage generator is connected to the upper plate of the fifth capacitor array, and the second output terminal is connected to the upper plate of the sixth capacitor array.

[0013] Furthermore, the first common-mode voltage generator and the second common-mode voltage generator have the same structure, and both include a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a first PMOS transistor, a first NOMS transistor, a second NMOS transistor, a second PMOS transistor, a first switch, a second switch, and a third switch;

[0014] The input terminal of the first inverter is connected to the input terminal of the common-mode voltage generator. The output terminal of the first inverter is connected to the input terminal of the second inverter. The output terminal of the second inverter is connected to the input terminal of the third inverter. The output terminal of the third inverter is connected to the input terminal of the fourth inverter. The output terminal of the fourth inverter is connected to the input terminal of the fifth inverter. The gates of the first PMOS transistor and the first NMOS transistor are connected to the output terminal of the fifth inverter. The drain of the first PMOS transistor is connected to the power supply VDD. The source of the first PMOS transistor is connected to the drain of the first NMOS transistor and the first connection terminal of the first switch. The source of the first NMOS transistor is grounded. The second connection terminal of the first switch is connected to the first output terminal of the common-mode voltage generator and the first connection terminal of the third switch.

[0015] The input terminal of the sixth inverter is connected to the input terminal of the common-mode voltage generator. The output terminal of the sixth inverter is connected to the input terminal of the seventh inverter. The output terminal of the seventh inverter is connected to the input terminal of the eighth inverter. The output terminal of the eighth inverter is connected to the input terminal of the ninth inverter. The gates of the second PMOS transistor and the second NMOS transistor are connected to the output terminal of the ninth inverter. The drain of the second PMOS transistor is connected to the power supply VDD. The source of the second PMOS transistor is connected to the drain of the second NMOS transistor and the first connection terminal of the second switch. The source of the second NMOS transistor is grounded. The second connection terminal of the second switch is connected to the second output terminal of the common-mode voltage generator and the second connection terminal of the third switch.

[0016] It is defined that the first control signal is generated at the output terminal of the third inverter, and the second control signal is generated at the output terminal of the seventh inverter. And the first control signal controls the first switch, the second control signal controls the second switch, and the first control signal and the second control signal jointly control the third switch. The specific control method is as follows: when the CDAC circuit samples, the input signal of the common-mode voltage generator is in the first state, the first control signal and the second control signal are in the first state. When the sampling ends, the input signal of the common-mode voltage generator is inverted, and the first control signal and the second control signal are in the second state. When the first control signal and the second control signal are in the first state, the first switch and the second switch are closed, and the third switch is open. When the first control signal and the second control signal are in the second state, the first switch and the second switch are open, and the third switch is closed.

[0017] The present invention is a capacitive DAC (capacitive DAC, hereinafter referred to as CDAC) based on charge redistribution. Utilizing the characteristic of capacitors to store charge, when the sampling ends, the upper plate of the capacitor is suspended, and thus the sampling and holding of the input signal can be completed without an additional sampling and holding circuit.

[0018] The beneficial effects of the present invention are as follows. The capacitive array of the present invention uses segmented capacitors to reduce the capacitive area, enabling the capacitors to be integrated. At the same time, the reduction of the capacitive area reduces the switch size and the non-ideal factors of the switch. The sampling method of the present invention uses bottom-plate sampling to reduce the charge injection of the sampling switch, achieving high precision. The present invention adopts the split-capacitor technology to divide the high-section capacitor into two, and the capacitive switch switching mode becomes monotonic switching. Each comparison does not require a reset operation, saving most of the power consumption compared with the traditional reset-type switch switching mode, achieving low power consumption. The common-mode voltage generator is used to generate the common-mode voltage from the circuit, eliminating the power consumption of the external common-mode voltage and its common-mode drive circuit, and reducing the power consumption. Brief Description of the Drawings

[0019] Figure 1 It is a schematic diagram of the overall structure of the present invention.

[0020] Figure 2 It is a schematic diagram of the capacitive array structure of the CDAC circuit in the present invention.

[0021] Figure 3 It is a schematic diagram of the common-mode voltage generator structure of the present invention. Detailed Embodiments

[0022] Next, in combination with examples, the technical solutions of the present invention will be described in detail. In the present invention, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. For example, the first connection end and the second connection end of the capacitor and the switch only represent two connection ends of the capacitor and the switch, and the first connection end and the second connection end can be interchanged; for another example, the control clock signal can be high level in the first state and low level in the second state, or low level in the first state and high level in the second state.

[0023] The high-precision and low-power CDAC circuit proposed by the present invention includes a segmented capacitor module, a sampling switch module, and a common-mode voltage generator module. As Figure 2 shown, it is a 16-bit CDAC circuit. Adopting the segmented capacitor structure and the split-capacitor technology, the capacitive array is a differential structure. The segmented capacitor structure connects the capacitive arrays through bridging capacitors, and adjusts the size of the bridging capacitors to achieve the linearity of the weights between different capacitive arrays, ensuring the accuracy of the CDAC circuit while reducing the area.

[0024] As Figure 1As shown, the segmented capacitor module includes a first capacitor array CS1, a second capacitor array CS2, a third capacitor array CS3, a fourth capacitor array CS4, a fifth capacitor array CS5, a sixth capacitor array CS6, a seventh capacitor array CS7, an eighth capacitor array CS8, a first bridging capacitor Ca1, a second bridging capacitor Ca2, a third bridging capacitor Ca3, and a fourth bridging capacitor Ca4. The first connection end of the first bridging capacitor Ca1 is connected to the first capacitor array CS1 and the second capacitor array CS2, and the second connection end is connected to the third capacitor array CS3. The first connection end of the second bridging capacitor Ca2 is connected to the third capacitor array CS3, and the second connection end is connected to the fourth capacitor array CS4. The connection of the first capacitor array CS1, the second capacitor array CS2, the third capacitor array CS3, and the fourth capacitor array CS4 is completed. The first connection end of the third bridging capacitor Ca3 is connected to the fifth capacitor array CS5 and the sixth capacitor array CS6, and the second connection end is connected to the seventh capacitor array CS7. The first connection end of the fourth bridging capacitor is connected to the seventh capacitor array CS7, and the second connection end is connected to the eighth capacitor array CS8. The connection of the fifth capacitor array CS5, the sixth capacitor array CS6, the seventh capacitor array CS7, and the eighth capacitor array CS8 is completed.

[0025] As Figure 1 shown, the segmentation mode of the segmented capacitor module is 8 + 4 + 4, with 8 bits in the high segment, 4 bits in the middle segment, and 4 bits in the low segment. In the high segment, a split-capacitor structure is adopted, splitting the capacitor into two halves. Therefore, the 8 bits in the high segment are composed of the first capacitor array CS1, the second capacitor array CS2, the fifth capacitor array CS5, and the sixth capacitor array CS5; the 4 bits in the middle segment are composed of the third capacitor array CS3 and the seventh capacitor array CS7; the 4 bits in the low segment are composed of the fourth capacitor array CS4 and the eighth capacitor array CS8. The sampling method is high-segment sampling, and the sampling capacitor arrays are the first capacitor array CS1, the second capacitor array CS2, the fifth capacitor array CS5, and the sixth capacitor array CS5.

[0026] The structure diagram of the common-mode voltage generator is as Figure 2As shown in the figure. It includes the first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4, the fifth inverter INV5, the sixth inverter INV6, the seventh inverter INV7, the eighth inverter INV8, the ninth inverter INV9, the first PMOS transistor M1, the first NOMS transistor M2, the second PMOS transistor M3, the second NMOS transistor M4, the first switch S1, the second switch S2 and the third switch S3. The first control signal SIG1 is generated at the output terminal of the third inverter INV3, and the second control signal SIG2 is generated at the output terminal of the seventh inverter INV7. The first control signal SIG1 controls the first switch S1, the second control signal SIG2 controls the second switch S2, and the first control signal SIG1 and the second control signal SIG2 jointly control the third switch.

[0027] When the CDAC is in the sampling state, the input terminal Vin of the common-mode voltage generator is in the first state. The fifth inverter INV5 outputs a low level, the first PMOS transistor M1 is turned on, the first NMOS transistor M2 is turned off, and the drain of the first PMOS transistor is charged to VDD through M1. The third inverter INV3 outputs the first control signal SIG1, which is in the first state, the first switch S1 is turned on, and the first output terminal Vout1 outputs the signal VDD. The ninth inverter INV9 outputs a high level, the second PMOS transistor M3 is turned off, the second NMOS transistor M4 is turned on, and the drain of the second NMOS transistor M4 is discharged to GND through M4. The seventh inverter INV7 outputs the second control signal SIG2, which is in the first state, the second switch S2 is turned on, and the second output terminal Vout2 outputs the signal GND. During sampling, the third switch S3 is turned off. When the CDAC sampling ends, the input terminal Vin of the common-mode voltage generator is in the first state and then in the second state, so that the first control signal SIG1 and the second control signal SIG2 are in the second state, the first switch S1 and the second switch S2 are disconnected, and the third switch S3 is closed to connect the first output terminal Vout1 and the second output terminal Vout2.

[0028] When the CDAC is in the sampling state, the input signal VINN is sampled to the lower plates of the first capacitor array CS1 and the second capacitor array CS2 through the first sampling switch, and the input signal VINP is sampled to the lower plates of the fifth capacitor array CS5 and the sixth capacitor array CS6 through the first sampling switch. The first output terminal VOUT1 of the first common-mode voltage generator provides the VDD signal to the upper plates of the first capacitor array CS1 and the second capacitor array CS2. The second output terminal VOUT2 provides the GND signal to the upper plates of the fifth capacitor array CS5 and the sixth capacitor array CS6. After the sampling is completed, the upper plates of the first capacitor array CS1 and the second capacitor array CS2 are connected together through the common-mode generator, and the upper plates of the fifth capacitor array CS5 and the sixth capacitor array CS6 are connected together. Through the charge redistribution characteristic of the capacitor, the common-mode voltage is generated internally by the circuit:

[0029] V CM =(V DD +GND) / 2

[0030] Through the above structure, the internal generation of the common-mode voltage, the reduction of the capacitor area, and the change of the switch switching mode are realized. While improving the accuracy of the CDAC, the power consumption of the circuit is reduced, and high-precision and low-power applications are achieved.

Claims

1. A high-precision and low-power CDAC circuit, characterized in that It includes a segmented capacitor module, a sampling switch module, and a common-mode voltage generator module; The segmented capacitor module includes a first capacitor array, a second capacitor array, a third capacitor array, a fourth capacitor array, a fifth capacitor array, a sixth capacitor array, a seventh capacitor array, an eighth capacitor array, a first bridging capacitor, a second bridging capacitor, a third bridging capacitor, and a fourth bridging capacitor; The first connection end of the first bridging capacitor is connected to the upper plates of the first capacitor array and the second capacitor array, and the second connection end is connected to the upper plate of the third capacitor array. The first connection end of the second bridging capacitor is connected to the upper plate of the third capacitor array, and the second connection end is connected to the upper plate of the fourth capacitor array; The first connection end of the third bridging capacitor is connected to the upper plates of the fifth capacitor array and the sixth capacitor array, and the second connection end of the third bridging capacitor is connected to the upper plate of the seventh capacitor array. The first connection end of the fourth bridging capacitor is connected to the upper plate of the seventh capacitor array, and the second connection end of the fourth bridging capacitor is connected to the upper plate of the eighth capacitor array; The input end of the first sampling switch is connected to the VINP signal in the differential input signal, and the output end is connected to the lower capacitor plates of the first capacitor array and the second capacitor array. After sampling is completed, the sampled signal is output to the subsequent circuit through the upper plates of the first capacitor array and the second capacitor array. The input end of the second sampling switch is connected to the VINN signal in the differential input signal, and the output end is connected to the lower capacitor plates of the fifth capacitor array and the sixth capacitor array. After sampling is completed, the sampled signal is output to the subsequent circuit through the upper plates of the fifth capacitor array and the sixth capacitor array; The common-mode voltage generator module includes a first common-mode voltage generator and a second common-mode voltage generator. The inputs of the first common-mode voltage generator and the second common-mode voltage generator are both external control signals. The first output end of the first common-mode voltage generator is connected to the lower plate of the first capacitor array, and the second output end is connected to the lower plate of the second capacitor array; The first output end of the second common-mode voltage generator is connected to the upper plate of the fifth capacitor array, and the second output end is connected to the upper plate of the sixth capacitor array.

2. The high-precision and low-power CDAC circuit according to claim 1, wherein The first common-mode voltage generator and the second common-mode voltage generator have the same structure, and both include a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a first PMOS transistor, a first NOMS transistor, a second NMOS transistor, a second PMOS transistor, a first switch, a second switch, and a third switch; The input terminal of the first inverter is connected to the input terminal of the common-mode voltage generator. The output terminal of the first inverter is connected to the input terminal of the second inverter. The output terminal of the second inverter is connected to the input terminal of the third inverter. The output terminal of the third inverter is connected to the input terminal of the fourth inverter. The output terminal of the fourth inverter is connected to the input terminal of the fifth inverter. The gates of the first PMOS transistor and the first NMOS transistor are connected to the output terminal of the fifth inverter. The drain of the first PMOS transistor is connected to the power supply VDD. The source of the first PMOS transistor is connected to the drain of the first NMOS transistor and the first connection terminal of the first switch. The source of the first NMOS transistor is grounded. The second connection terminal of the first switch is connected to the first output terminal of the common-mode voltage generator and the first connection terminal of the third switch. The input terminal of the sixth inverter is connected to the input terminal of the common-mode voltage generator. The output terminal of the sixth inverter is connected to the input terminal of the seventh inverter. The output terminal of the seventh inverter is connected to the input terminal of the eighth inverter. The output terminal of the eighth inverter is connected to the input terminal of the ninth inverter. The gates of the second PMOS transistor and the second NMOS transistor are connected to the output terminal of the ninth inverter. The drain of the second PMOS transistor is connected to the power supply VDD. The source of the second PMOS transistor is connected to the drain of the second NMOS transistor and the first connection terminal of the second switch. The source of the second NMOS transistor is grounded. The second connection terminal of the second switch is connected to the second output terminal of the common-mode voltage generator and the second connection terminal of the third switch. It is defined that the first control signal is generated at the output terminal of the third inverter, and the second control signal is generated at the output terminal of the seventh inverter. The first control signal controls the first switch, the second control signal controls the second switch, and the first control signal and the second control signal jointly control the third switch. The specific control method is as follows: When the CDAC circuit samples, the input signal of the common-mode voltage generator is in the first state, and the first control signal and the second control signal are in the first state. When the sampling ends, the input signal of the common-mode voltage generator is inverted, and the first control signal and the second control signal are in the second state. When the first control signal and the second control signal are in the first state, the first switch and the second switch are closed, and the third switch is open. When the first control signal and the second control signal are in the second state, the first switch and the second switch are open, and the third switch is closed.

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