Multi-time-domain clock processing method, apparatus, device, and storage medium
By receiving clock acquisition requests from the target application, obtaining the current time of the reference time domain and performing hardware synchronization, maintaining feature data, determining and transmitting back the time of the target time domain, the problem of application layer perception of multiple time domains is solved, supporting data fusion in high-level intelligent driving and fully autonomous driving, and achieving low latency and determinism of data.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ECARX (HUBEI) TECHCO LTD
- Filing Date
- 2022-02-28
- Publication Date
- 2026-05-29
Smart Images
Figure CN116707692B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technology, and in particular to a multi-time-domain clock processing method, apparatus, device and storage medium. Background Technology
[0002] With the advent of the era of intelligent and connected vehicles, the bandwidth requirements for in-vehicle communication are increasing, leading to the emergence of automotive Ethernet. Simultaneously, with the further development of intelligent driving technology, more and more mass-produced vehicles are achieving Level 2 and Level 3 autonomous driving. To achieve higher levels of intelligent driving or even fully autonomous driving, large amounts of environmental data are collected and fused. In this scenario, Time-Sensitive Networking (TSN) technology is widely used to ensure low latency and determinism of data.
[0003] In TSN-related standards, IEEE Std 802.1AS defines a high-precision clock synchronization mechanism, under which clock synchronization accuracy can be less than 1 microsecond. Avnu has further clarified how to achieve high-precision clock synchronization in the automotive field. Both the IEEE Std.802.1AS standard and the AutoSAR standard explicitly define the need to support time synchronization across multiple time domains.
[0004] However, how the application layer perceives time across multiple time domains for ease of use has not yet been explained. Summary of the Invention
[0005] This application provides a multi-time-domain clock processing method, apparatus, device, and storage medium, which provides an implementation scheme for how the application layer can perceive time in multiple time domains for easy use.
[0006] In a first aspect, this application provides a multi-time-domain clock processing method, including:
[0007] Receive clock acquisition requests initiated by the target application;
[0008] In response to the clock acquisition request, the current time of the reference time domain is acquired, and the time of the reference time domain is synchronized with the hardware time;
[0009] The time of the target time domain is determined based on the clock acquisition request, the current time of the reference time domain, and the first feature data, and the time of the target time domain is sent back to the target application.
[0010] In one possible design, the method further includes:
[0011] Receive clock synchronization message, the clock synchronization message including the time when the candidate time field entered the Ethernet interface the most recently, the candidate time field including any time field other than the reference time field;
[0012] Obtain the characteristic time recorded by the Ethernet interface, the characteristic time including the timestamps of the two most recent entries of the candidate time field into the Ethernet interface;
[0013] The second feature data corresponding to the candidate time domain is determined based on the clock synchronization message and the feature time, and the first feature data includes the second feature data.
[0014] In one possible design, determining the second feature data corresponding to the candidate time domain based on the clock synchronization message and the feature time includes:
[0015] The time difference and frequency ratio between the candidate time domain and the reference time domain are determined based on the clock synchronization message and the characteristic time, respectively.
[0016] The time difference, the frequency ratio, and the timestamp of the most recent entry of the candidate time domain into the Ethernet interface in the characteristic time are determined as the second characteristic data.
[0017] In one possible design, determining the time of the target time domain based on the clock acquisition request, the current time of the reference time domain, and the first feature data includes:
[0018] The target time domain is determined from the candidate time domains according to the clock acquisition request;
[0019] The time of the target time domain is determined based on the current time of the reference time domain, the second feature data corresponding to the target time domain, and the transmission delay of the target time domain. The first feature data also includes the transmission delay of the target time domain.
[0020] In one possible design, when the target application sets a timer for the target time domain, the method further includes:
[0021] The countdown time of the hardware timer is determined for the target time domain based on the countdown time of the timer and the frequency ratio between the target time domain and the reference time domain.
[0022] In one possible design, the time in the reference time domain is also used to control the QBV queue.
[0023] In one possible design, the timestamp is the time representation of the reference time domain when the alternative time domain enters the Ethernet interface.
[0024] Secondly, this application provides a multi-time-domain clock synchronization device, comprising:
[0025] The receiving module is used to receive clock acquisition requests initiated by the target application;
[0026] The first processing module is used to obtain the current time of the reference time domain in response to the clock acquisition request, wherein the time of the reference time domain is synchronized with the hardware time.
[0027] The second processing module is used to determine the time of the target time domain based on the clock acquisition request, the current time of the reference time domain, and the first feature data, and to send the time of the target time domain back to the target application.
[0028] In one possible design, the multi-time-domain clock synchronization device further includes: a third processing module; the third processing module is used for:
[0029] Receive clock synchronization message, the clock synchronization message including the time when the candidate time field entered the Ethernet interface the most recently, the candidate time field including any time field other than the reference time field;
[0030] Obtain the characteristic time recorded by the Ethernet interface, the characteristic time including the timestamps of the two most recent entries of the candidate time field into the Ethernet interface;
[0031] The second feature data corresponding to the candidate time domain is determined based on the clock synchronization message and the feature time, and the first feature data includes the second feature data.
[0032] In one possible design, the third processing module is further configured to:
[0033] The time difference and frequency ratio between the candidate time domain and the reference time domain are determined based on the clock synchronization message and the characteristic time, respectively.
[0034] The time difference, the frequency ratio, and the timestamp of the most recent entry of the candidate time domain into the Ethernet interface in the characteristic time are determined as the second characteristic data.
[0035] In one possible design, the second processing module is specifically used for:
[0036] The target time domain is determined from the candidate time domains according to the clock acquisition request;
[0037] The time of the target time domain is determined based on the current time of the reference time domain, the second feature data corresponding to the target time domain, and the transmission delay of the target time domain. The first feature data also includes the transmission delay of the target time domain.
[0038] In one possible design, when the target application sets a timer for the target time domain, the multi-time domain clock synchronization device further includes: a fourth processing module; the fourth processing module is used for:
[0039] The countdown time of the hardware timer is determined for the target time domain based on the countdown time of the timer and the frequency ratio between the target time domain and the reference time domain.
[0040] In one possible design, the time in the reference time domain is also used to control the QBV queue.
[0041] In one possible design, the timestamp is the time representation of the reference time domain when the alternative time domain enters the Ethernet interface.
[0042] Thirdly, this application provides an electronic device, including: a processor, and a memory communicatively connected to the processor;
[0043] The memory stores computer-executed instructions;
[0044] The processor executes computer execution instructions stored in the memory to implement any of the possible multi-time-domain clock processing methods provided in the first aspect.
[0045] Fourthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement any of the possible multi-time-domain clock processing methods provided in the first aspect.
[0046] Fifthly, this application provides a computer program product including computer execution instructions, which, when executed by a processor, are used to implement any of the possible multi-time-domain clock processing methods provided in the first aspect.
[0047] This application provides a multi-time-domain clock processing method, apparatus, device, and storage medium. First, it receives a clock acquisition request initiated by a target application. Then, in response to the clock acquisition request, it acquires the current time of a reference time domain, wherein the time of the reference time domain is synchronized with the hardware time. Next, it determines the time of a target time domain based on the clock acquisition request, the current time of the reference time domain, and first feature data. Finally, it sends the time of the target time domain back to the target application, providing the application layer with an interface to acquire the time of any time domain and synchronize it to the time of the desired time domain. This allows the application layer to perceive multiple time domains, facilitating its use. Attached Figure Description
[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0049] Figure 1 This is a schematic diagram of an application scenario provided by an embodiment of this application;
[0050] Figure 2 A flowchart illustrating a multi-time-domain clock processing method provided in an embodiment of this application;
[0051] Figure 3 A flowchart illustrating another multi-time-domain clock processing method provided in an embodiment of this application;
[0052] Figure 4 A flowchart illustrating another multi-time-domain clock processing method provided in an embodiment of this application;
[0053] Figure 5 A flowchart illustrating another multi-time-domain clock processing method provided in an embodiment of this application;
[0054] Figure 6 A schematic diagram of the structure of a multi-time-domain clock processing system provided in an embodiment of this application;
[0055] Figure 7 This is a schematic diagram of the structure of a multi-time-domain clock processing device provided in an embodiment of this application;
[0056] Figure 8 A schematic diagram of another multi-time-domain clock processing device provided in an embodiment of this application;
[0057] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0058] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of methods and apparatus consistent with some aspects of this application as detailed in the appended claims.
[0059] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0060] To achieve higher levels of intelligent driving and even fully autonomous driving, massive amounts of environmental data are collected and fused. In this scenario, Time Synchronization (TSN) technology is widely used to ensure low latency and determinism of data. Among TSN-related standards, IEEE Std. 802.1AS defines a high-precision clock synchronization mechanism, achieving a synchronization accuracy of less than 1 microsecond. Avnu has further clarified how to achieve high-precision clock synchronization in the automotive field. Both the IEEE Std. 802.1AS and AutoSAR standards explicitly define the need to support multi-time domain time synchronization. However, how the application layer perceives time across multiple time domains for ease of use has not yet been elaborated upon.
[0061] To address the aforementioned problems in the existing technology, this application provides a multi-time-domain clock processing method, apparatus, device, and storage medium. The inventive concept of the multi-time-domain clock processing method provided in this application is as follows: using the time of a reference time domain as a base time, synchronizing this time with the hardware time, and maintaining corresponding feature data in the first feature data based on the reference time domain. When a clock acquisition request initiated by a target application is received, the time of the target time domain is determined according to the current time of the reference time domain and the first feature data, and then the time of the target time domain is sent back to the target application, providing an interface for the target application at the application layer to acquire time, enabling the application layer to perceive multiple time domains, thus facilitating its use.
[0062] The following describes exemplary application scenarios of the embodiments of this application.
[0063] Figure 1 This is a schematic diagram of an application scenario provided in an embodiment of this application, such as... Figure 1 As shown, electronic device 100 is configured to execute the multi-time-domain clock processing method provided in the embodiments of this application. It can run software code that implements clock processing functions, such as a clock synchronization protocol stack. By executing the multi-time-domain clock processing method provided in the embodiments of this application, electronic device 100 can maintain the time in multiple time domains, for example, maintaining the time in time domains 1 to n, and enabling the target application 200 configured in the application layer to perceive the time in multiple time domains for use by the application layer.
[0064] The electronic device 100 can be a computer, a TCU (Transmission Control Unit) control unit, etc. This application embodiment does not limit the type of electronic device 100. Figure 1 The electronic device 100 in the example is a computer. The target application 200 configured in the application layer can be any functional module that needs to acquire time in the time domain. This functional module includes, but is not limited to, the fault recording module, task scheduling module, communication scheduling module, and program modules related to autonomous driving in the vehicle 300, such as the vehicle sensor data fusion module. The specific content of the target application 200 is not limited in the embodiments of this application.
[0065] It should be noted that the above application scenarios are merely illustrative, and the multi-time domain clock processing method, apparatus, device, and storage medium provided in the embodiments of this application include, but are not limited to, the above application scenarios.
[0066] Figure 2 This is a flowchart illustrating a multi-time-domain clock processing method provided in an embodiment of this application.
[0067] like Figure 2As shown, the multi-time-domain clock processing method provided in this application includes:
[0068] S101: Receives a clock acquisition request initiated by the target application.
[0069] When the target application needs to obtain the time of the corresponding time domain, the target application will initiate a clock acquisition request.
[0070] For example, the clock synchronization protocol stack provides interfaces for target applications to call in different time domains. Therefore, when the target application needs to obtain the time of the corresponding time domain, it will call the interface of the corresponding time domain to send a clock acquisition request to the clock synchronization protocol stack to obtain the time of the corresponding time domain.
[0071] S102: In response to a clock acquisition request, obtain the current time of the reference time field.
[0072] The reference time domain time is synchronized with the hardware time.
[0073] One of the multiple time domains is defined as the reference time domain, which is synchronized with the hardware time. An operating system has only one hardware time, which is typically implemented and maintained by the chip. Programs running on the chip can read and write the hardware time. The operating system can be various commonly used automotive real-time operating systems, such as AutoSAR, Linux, and Android.
[0074] After receiving a clock acquisition request, the clock synchronization protocol stack retrieves the current time in the reference time field. The current time in the reference time field is the hardware time at the time the clock acquisition request was received.
[0075] S103: Determine the time of the target time domain based on the clock acquisition request, the current time of the reference time domain, and the first feature data, and send the time of the target time domain back to the target application.
[0076] The clock synchronization protocol stack calculates the time of the target time domain based on the clock acquisition request, the current time of the reference time domain, and the first feature data. The first feature data includes corresponding feature data characterizing the relationship between the time of the reference time domain and the time of the target time domain. Based on this feature data, the time of the target time domain can be maintained based on the time of the reference time domain. The target time domain can be obtained from the clock acquisition request, and its time can then be calculated.
[0077] It is important to understand that different time domains have different functions, resulting in each time domain having its own time. In the embodiments of this application, a hardware time is used to represent the time of the reference time domain. For example, this time can be a local time, such as Beijing time. All individuals using Beijing time can be considered to be within the time domain using Beijing time. If a time domain's time is GPS time or World Time, then individuals using GPS time or World Time are considered to be within the time domain using GPS time or World Time. There are time discrepancies between different time domains; for example, Beijing time and World Time have a fixed discrepancy. The time rate can also differ between different time domains. For instance, 1 second may pass in time domain 1, while 2 seconds may have passed in time domain n within the same time period.
[0078] Since different time domains have their own times, this application provides a multi-time domain clock processing method, which synchronizes the time of the reference time domain with the hardware time, maintains the time of the target time domain based on the time of the reference time domain, and enables the target application at the application layer to obtain the time of the target time domain that it wants to obtain, thereby enabling the target application to be aware of multiple time domains.
[0079] After determining the time in the target time domain, the time in the target time domain is sent back to the target application so that the target application can use it.
[0080] The multi-time-domain clock processing method provided in this application first receives a clock acquisition request initiated by the target application, then acquires the current time of the reference time domain in response to the clock acquisition request, wherein the time of the reference time domain is synchronized with the hardware time. Next, the time of the target time domain is determined according to the clock acquisition request, the current time of the reference time domain, and the first feature data. Finally, the time of the target time domain is sent back to the target application, so as to provide the target application at the application layer with an interface to acquire the time of any time domain among multiple time domains, so that the target application can acquire the time of the time domain it wants to acquire, and the application layer can perceive multiple time domains, which is convenient for the application layer to use.
[0081] As described in the foregoing embodiments, the clock synchronization protocol stack maintains corresponding feature data in the first feature data based on the time in the reference time domain. Assuming that the corresponding feature data in the first feature data is defined as the second feature data, the possible implementations of maintaining this second feature data based on the time in the reference time domain are as follows: Figure 3 As shown.
[0082] Figure 3 This is a flowchart illustrating another multi-time-domain clock processing method provided in an embodiment of this application. Figure 3 As shown, the multi-time-domain clock processing method provided in this application includes:
[0083] S201: Receive clock synchronization message.
[0084] The clock synchronization message includes the times when the candidate time field entered the Ethernet interface most recently, and the candidate time field includes any time field other than the reference time field.
[0085] Ethernet interfaces, such as Ethernet network cards, can receive clock synchronization messages via the time synchronization protocol stack. These clock synchronization messages include the times of at least the two most recent entries into the Ethernet interface for a candidate time field. The candidate time field is any one of several time fields other than the reference time field.
[0086] For example, a clock synchronization message includes the time T of the time field n when it last entered the Ethernet interface. n and T n '(T n '>T n The time domain n is the alternative time domain. Assuming time domain 1 is the reference time domain, the value of n can be 2, 3, 4, ... etc., depending on the number of time domains.
[0087] S202: Obtain the characteristic time recorded by the Ethernet interface.
[0088] The characteristic time includes the timestamps of the two most recent entries of the candidate time domain into the Ethernet interface.
[0089] When a candidate time domain enters the Ethernet interface, the Ethernet interface records a timestamp. The timestamps of the two most recent entries of the candidate time domain into the Ethernet interface are defined as the characteristic time. The timestamp uses the time representation of the reference time domain when the candidate time domain enters the Ethernet interface, which is the hardware time representation.
[0090] Assuming time domain 1 is the reference time domain, the timestamps recorded by the Ethernet interface when the candidate time domain entered the Ethernet interface most recently can be represented as T1 and T1' (T1'>T1), respectively. It can be understood that T1 represents the time when the candidate time domain entered the Ethernet interface. n The timestamp for this event is T1', which is the time when the candidate time field enters the Ethernet interface. n 'The timestamp of this instance. The characteristic times corresponding to the two most recent instances include T1 and T1'.
[0091] S203: Determine the second characteristic data corresponding to the candidate time domain based on the clock synchronization message and the characteristic time.
[0092] The first feature data includes the second feature data.
[0093] The clock synchronization protocol stack calculates the second characteristic data corresponding to the candidate time domain based on the corresponding data and characteristic time in the clock synchronization message. The first characteristic data includes the second characteristic data.
[0094] In one possible design, step S203 could be implemented as follows: Figure 4 As shown. Figure 4 This is a flowchart illustrating another multi-time-domain clock processing method provided in an embodiment of this application. Figure 4 As shown, the embodiments of this application include:
[0095] S2031: Determine the time difference and frequency ratio between the candidate time domain and the reference time domain based on the clock synchronization message and the characteristic time, respectively.
[0096] Calculate the time difference and frequency ratio between the candidate time domain and the reference time domain based on the corresponding data and characteristic time in the clock synchronization message.
[0097] For example, the time difference offset_n between the candidate time domain and the reference time domain can be calculated using the following formula (1):
[0098] offset_n = [(T n -T1)+(T n '-T1')] / 2 (1)
[0099] Where offset_n represents the time difference between the candidate time domain (e.g., time domain n) and the reference time domain (e.g., time domain 1), T n and T n 'T1 and T1' are the times when the candidate time domain entered the Ethernet interface most recently, respectively. T1 and T1' are the timestamps when the candidate time domain entered the Ethernet interface most recently, which are also the characteristic times.
[0100] For example, the frequency ratio rate_ratio_n between the candidate time domain and the reference time domain can be calculated using the following formula (2):
[0101] rate_ratio_n=(T n '-T n ) / (T1'-T1) (2)
[0102] Where rate_ratio_n represents the frequency ratio between the candidate time domain (e.g., time domain n) and the reference time domain (e.g., time domain 1), T n and T n 'T1 and T1' are the times when the candidate time domain entered the Ethernet interface most recently, respectively. T1 and T1' are the timestamps when the candidate time domain entered the Ethernet interface most recently, which are also the characteristic times.
[0103] The time difference and frequency ratio between the candidate time domain and the reference time domain can be obtained through the above formulas (1) and (2).
[0104] S2032: The time difference, frequency ratio, and the timestamp of the most recent entry into the Ethernet interface in the candidate time domain of the characteristic time are determined as the second characteristic data.
[0105] After obtaining the time difference and frequency ratio between the candidate time domain and the reference time domain, the time difference, frequency ratio, and the timestamp of the most recent entry of the candidate time domain into the Ethernet interface within the characteristic time are determined as the second characteristic data corresponding to the candidate time domain. For example, the data represented by offset_n, rate_ratio_n, and T1' mentioned above are determined as the second characteristic data corresponding to the candidate time domain (i.e., time domain n).
[0106] It should be noted that each time the clock synchronization protocol stack receives a clock synchronization message, it will execute the embodiment of this application to update the second feature data.
[0107] The multi-time-domain clock processing method provided in this application embodiment allows the clock synchronization protocol stack to maintain second feature data corresponding to candidate time domains based on the time of the reference time domain, thereby enabling an operating system to maintain the time of multiple time domains. Furthermore, based on the maintained second feature data, first feature data including the second feature data can be used to provide the target application at the application layer with the time of the corresponding time domain that the target application wants to obtain.
[0108] Figure 5 This is a flowchart illustrating another multi-time-domain clock processing method provided in an embodiment of this application. Figure 5 As shown, the embodiments of this application include:
[0109] S301: Receives a clock acquisition request initiated by the target application.
[0110] S302: In response to a clock acquisition request, obtain the current time of the reference time field.
[0111] The reference time domain time is synchronized with the hardware time.
[0112] The implementation methods, principles, and technical effects of steps S301 and S302 are similar to those of steps S101 and S102, respectively. For details, please refer to the foregoing embodiments, which will not be repeated here.
[0113] S303: Determine the target time domain from the candidate time domains based on the clock acquisition request.
[0114] A clock acquisition request is initiated when the target application wants to obtain the time of the corresponding time domain. Therefore, the target time domain can be determined from the candidate time domains based on the clock acquisition request. The target time domain is the corresponding time domain for which the target application wants to obtain the time.
[0115] S304: Determine the time of the target time domain based on the current time of the reference time domain, the second feature data corresponding to the target time domain, and the transmission delay of the target time domain.
[0116] The first feature data also includes the transmission delay in the target time domain.
[0117] After determining the target time domain, the time of the target time domain is calculated based on the current time of the reference time domain, the second feature data corresponding to the target time domain, and the transmission delay of the target time domain.
[0118] For example, the time Tm in the target time domain can be calculated using the following formula (3):
[0119] T m =(T0-T1”)*rate_ratio_m+Offset_m+Pdelay_m (3)
[0120] Among them, T m T0 represents the current time in the target time domain, T1 represents the time in the reference time domain when the clock synchronization protocol stack last updated the second feature data corresponding to the target time domain, rate_ratio_m and Offset_m represent the frequency ratio and time difference between the target time domain and the reference time domain, respectively, and Pdelay_m represents the transmission delay in the target time domain.
[0121] Understandably, m is only used to distinguish the target time domain from the alternative time domains. The target time domain can be any alternative time domain, and the value of m is determined by the target application.
[0122] The transmission delay of the target time domain refers to the time it takes for information to be transmitted from the network port of the ECU (Electronic Control Unit) implementing multiple time domains to the network port of an external ECU. Its specific value can be calculated using IEEE std.802.1AS-2020. It is understood that the transmission delay of all alternative time domains can be calculated. Therefore, for any alternative time domain, its transmission delay and its second characteristic data can be determined as the first characteristic data of that alternative time domain. Thus, the first characteristic data also includes the transmission delay of the target time domain.
[0123] S305: Return the time of the target time domain to the target application.
[0124] After obtaining the time from the target application, it is sent back to the target application, enabling the target application to obtain the time in the target time domain.
[0125] The multi-time-domain clock processing method provided in this application first receives a clock acquisition request initiated by the target application, then acquires the current time of the reference time domain in response to the clock acquisition request. The time of the reference time domain is synchronized with the hardware time. Next, the target time domain is determined from the candidate time domains according to the clock acquisition request. Then, the time of the target time domain is determined according to the current time of the reference time domain, the second feature data corresponding to the target time domain, and the transmission delay of the target time domain. The time of the target time domain is then sent back to the target application. This provides the target application at the application layer with an interface to acquire the time of multiple time domains, enabling it to acquire the time of the time domain it wants. This allows the application layer to be aware of multiple time domains, facilitating its use.
[0126] The clock synchronization protocol stack provides interfaces for different time domains to be called by the target application. Therefore, based on the above embodiments, the target application can set a timer for any time domain through the interfaces provided by the clock synchronization protocol stack.
[0127] For example, when a target application sets a timer in the target time domain, the clock synchronization protocol stack can convert the countdown time of the timer set by the target application into the countdown time represented by the time in the reference time domain, that is, the countdown time that can be represented by hardware time.
[0128] Specifically, assuming the countdown time of the timer set by the target application is represented as Timer_m, the countdown time of the hardware timer Timer_1 can be determined for the target time domain based on the countdown time of the timer and the frequency ratio between the target time domain and the reference time domain. For example, the countdown time Timer_1 of the hardware timer can be calculated using the following formula (4):
[0129] Timer_1=Timer_m / rate_ratio_m (4)
[0130] The hardware timer is a timer that uses hardware time for timing. Since the time in the reference time domain is consistent with the hardware time, assuming time domain 1 is the reference time domain, then 1 second of the hardware timer is equal to 1 second of time domain 1. However, 1 second in the target time domain m may not be equal to 1 second of the hardware timer. Therefore, the countdown time of the timer set in the target time domain can be converted into the countdown time of the hardware timer using the above formula (4) so that the hardware timer can be used uniformly for countdown timing to realize the timing function. When the countdown time of the hardware timer is exceeded, corresponding control operations can be performed. For example, the task scheduling module needs to obtain the current time information to determine how long after the specified task will be activated.
[0131] Optionally, in the multi-time-domain clock processing method provided in the above embodiments, the time in the reference time domain can also be used to control the QBV queue.
[0132] Specifically, the QBV Ethernet interface uses hardware timing for QBV queue control, implementing QBV queue control in a multi-time domain system to precisely control data transmission time and achieve deterministic delay and jitter control for time-sensitive data within the vehicle. The implementation process of QBV queue control can be found in IEEE Std802.1Qbv, and will not be elaborated here.
[0133] Figure 6 This is a schematic diagram of the structure of a multi-time-domain clock processing system provided in an embodiment of this application. Figure 6 As shown, the clock synchronization protocol stack can define one of multiple time domains (such as time domain 1 to time domain n) as the reference time domain (e.g., Figure 6 In the first time domain (reference time domain), the time of the reference time domain is synchronized with the hardware time. Multiple time domains are maintained based on the reference time domain, providing an interface for the target application to obtain the time of the corresponding time domain. This allows the target application to be aware of multiple time domains. When the target application sets a timer for a target time domain, the countdown time of the set timer can be converted into the countdown time of the hardware timer, using hardware time to implement the timing function. Additionally, the Ethernet interface can record the timestamps of alternative time domains entering the Ethernet interface and represent these timestamps using hardware time. Furthermore, QBV queue control is performed using the time of the reference time domain, instead of using the time of other time domains. Moreover, in the multi-time domain clock processing method provided in this application embodiment, the clock synchronization protocol stack interacts with the lower-level software and hardware through only one set of interfaces in one time domain. The lower-level software and hardware cannot be aware of multiple time domains, thus preserving the original operating system interface without requiring driver changes.
[0134] It should be noted that the clock synchronization protocol stack described in the embodiments of this application refers to software code that can implement clock processing functions, which can be achieved through... Figure 1 The electronic device 100 shown runs the software code to achieve the corresponding function.
[0135] Figure 7 This is a schematic diagram of the structure of a multi-time-domain clock processing device provided in an embodiment of this application.
[0136] like Figure 7 As shown, the multi-time-domain clock processing device 400 provided in this application embodiment includes:
[0137] The receiving module 401 is used to receive a clock acquisition request initiated by the target application;
[0138] The first processing module 402 is used to obtain the current time of the reference time domain in response to the clock acquisition request, and the time of the reference time domain is synchronized with the hardware time.
[0139] The second processing module 403 is used to determine the time of the target time domain based on the clock acquisition request, the current time of the reference time domain, and the first feature data, and to send the time of the target time domain back to the target application.
[0140] exist Figure 7 On this basis, Figure 8 This is a schematic diagram of another multi-time-domain clock processing device provided in an embodiment of this application. Figure 8 As shown, the multi-time-domain clock processing device 400 provided in this application embodiment further includes: a third processing module 404. The third processing module 404 is used for:
[0141] Receive clock synchronization messages. The clock synchronization messages include the times when the candidate time field entered the Ethernet interface the most recent two times. The candidate time field includes any time field other than the reference time field.
[0142] Obtain the characteristic time recorded by the Ethernet interface. The characteristic time includes the timestamps of the two most recent entries into the Ethernet interface in the candidate time field.
[0143] The second characteristic data corresponding to the candidate time domain is determined based on the clock synchronization message and the characteristic time. The first characteristic data includes the second characteristic data.
[0144] In one possible design, the third processing module 404 is also used for:
[0145] The time difference and frequency ratio between the candidate time domain and the reference time domain are determined based on the clock synchronization message and the characteristic time, respectively.
[0146] The time difference, frequency ratio, and the timestamp of the most recent entry into the Ethernet interface from the candidate time domain in the characteristic time are determined as the second characteristic data.
[0147] In one possible design, the second processing module 403 is specifically used for:
[0148] The target time domain is determined from the candidate time domains based on the clock acquisition request;
[0149] The time of the target time domain is determined based on the current time of the reference time domain, the second feature data corresponding to the target time domain, and the transmission delay of the target time domain. The first feature data also includes the transmission delay of the target time domain.
[0150] In one possible design, when the target application sets a timer for the target time domain, the multi-time domain clock processing device 400 further includes a fourth processing module. This fourth processing module is used for:
[0151] The countdown time of the hardware timer is determined for the target time domain based on the countdown time of the timer and the frequency ratio between the target time domain and the reference time domain.
[0152] In one possible design, the time referenced in the time domain is also used to control the QBV queue.
[0153] In one possible design, the timestamp is a time representation of the reference time domain when it enters the Ethernet interface from the alternative time domain.
[0154] The multi-time-domain clock processing apparatus provided in this application embodiment can execute the corresponding steps of the multi-time-domain clock processing method in the above method embodiment. Its implementation principle and technical effect are similar, and will not be repeated here.
[0155] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 9 As shown, the electronic device 500 may include a processor 501 and a memory 502 communicatively connected to the processor 501.
[0156] Memory 502 is used to store programs. Specifically, the program may include program code, which includes computer-executable instructions.
[0157] The memory 502 may include high-speed RAM memory, and may also include non-volatile memory (MoM-volatile memory), such as at least one disk storage device.
[0158] The processor 501 is used to execute computer execution instructions stored in the memory 502 to implement a multi-time domain clock processing method.
[0159] The processor 501 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.
[0160] Optionally, the memory 502 can be either standalone or integrated with the processor 501. When the memory 502 is a device independent of the processor 501, the electronic device 500 may further include:
[0161] Bus 503 is used to connect processor 501 and memory 502. The bus can be an industry standard architecture (ISA) bus, a peripheral component (PCI) bus, or an extended industry standard architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc., but this does not mean there is only one bus or one type of bus.
[0162] Optionally, in a specific implementation, if the memory 502 and the processor 501 are integrated on a single chip, the memory 502 and the processor 501 can communicate through an internal interface.
[0163] This application also provides a computer-readable storage medium, which may include various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a disk, or an optical disk. Specifically, the computer-readable storage medium stores computer-executable instructions, which are used in the multi-time domain clock processing method described in the above embodiments.
[0164] This application also provides a computer program product, including computer instructions that, when executed by a processor, implement the multi-time-domain clock processing method described above.
[0165] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.
[0166] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A multi-time-domain clock processing method, characterized in that, include: Receive clock acquisition requests initiated by the target application; In response to the clock acquisition request, the current time of the reference time domain is acquired, and the time of the reference time domain is synchronized with the hardware time; The time of the target time domain is determined based on the clock acquisition request, the current time of the reference time domain, and the first feature data, and the time of the target time domain is sent back to the target application. Receive clock synchronization message, the clock synchronization message including the time when the candidate time field entered the Ethernet interface the most recently, the candidate time field including any time field other than the reference time field; Obtain the characteristic time recorded by the Ethernet interface, the characteristic time including the timestamps of the two most recent entries of the candidate time field into the Ethernet interface; The second feature data corresponding to the candidate time domain is determined based on the clock synchronization message and the feature time, and the first feature data includes the second feature data.
2. The multi-time-domain clock processing method according to claim 1, characterized in that, The step of determining the second feature data corresponding to the candidate time domain based on the clock synchronization message and the feature time includes: The time difference and frequency ratio between the candidate time domain and the reference time domain are determined based on the clock synchronization message and the characteristic time, respectively. The time difference, the frequency ratio, and the timestamp of the most recent entry of the candidate time domain into the Ethernet interface in the characteristic time are determined as the second characteristic data.
3. The multi-time-domain clock processing method according to claim 2, characterized in that, Determining the time of the target time domain based on the clock acquisition request, the current time of the reference time domain, and the first feature data includes: The target time domain is determined from the candidate time domains according to the clock acquisition request; The time of the target time domain is determined based on the current time of the reference time domain, the second feature data corresponding to the target time domain, and the transmission delay of the target time domain. The first feature data also includes the transmission delay of the target time domain.
4. The multi-time-domain clock processing method according to claim 2 or 3, characterized in that, When the target application sets a timer for the target time domain, the method further includes: The countdown time of the hardware timer is determined for the target time domain based on the countdown time of the timer and the frequency ratio between the target time domain and the reference time domain.
5. The multi-time-domain clock processing method according to claim 4, characterized in that, The time in the reference time domain is also used to control the QBV queue.
6. The multi-time-domain clock processing method according to claim 2, characterized in that, The timestamp of the most recent entry of the candidate time domain into the Ethernet interface and the timestamps of the two most recent entries of the candidate time domain into the Ethernet interface are both represented by the time of the reference time domain when the candidate time domain enters the Ethernet interface.
7. A multi-time-domain clock processing device, characterized in that, include: The receiving module is used to receive clock acquisition requests initiated by the target application; The first processing module is used to obtain the current time of the reference time domain in response to the clock acquisition request, wherein the time of the reference time domain is synchronized with the hardware time. The second processing module is used to determine the time of the target time domain based on the current time of the requested reference time domain and the first feature data, and to send the time of the target time domain back to the target application. The third processing module is used to receive clock synchronization messages, which include the times of the two most recent entry of the candidate time field into the Ethernet interface, and the candidate time field includes any time field other than the reference time field. Obtain the characteristic time recorded by the Ethernet interface, the characteristic time including the timestamps of the two most recent entries of the candidate time field into the Ethernet interface; The second feature data corresponding to the candidate time domain is determined based on the clock synchronization message and the feature time, and the first feature data includes the second feature data.
8. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the multi-time domain clock processing method as described in any one of claims 1 to 6.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the multi-time-domain clock processing method as described in any one of claims 1 to 6.