Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display. The display panel comprises a display area and a frame area located at the periphery of the display area, the display area comprises a plurality of sub-pixels and a plurality of data lines connected with the sub-pixels, the frame area comprises a test area and a binding area; the test area comprises a plurality of test units arranged periodically along a first direction, the test unit comprises at least one switching transistor, the first electrode of the switching transistor is connected with a test signal lead, and the second electrode is connected with a data line; the binding area comprises a plurality of binding units arranged periodically along the first direction, the binding unit comprises at least one binding pad, and the binding pad is connected with the data line; wherein, in the first direction, the ratio between the number of switching transistors contained in one arrangement period of the test unit and the number of binding pads contained in one arrangement period of the binding unit is greater than 0 and less than 2.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Liquid crystal display (LCD) panels, as a widely used flat panel display, occupy an important position in the display industry. To minimize production costs, defect detection is performed at each stage of display panel production to prevent defective products from flowing into downstream processes and wasting production materials. For example, after the cell assembly process, a liquid crystal cell test (CT) is required. Summary of the Invention

[0003] This disclosure provides a display panel, including a display area and a border area located around the display area. The display area includes a plurality of sub-pixels and a plurality of data lines connected to the sub-pixels. The border area includes a test area and a binding area.

[0004] The test area includes a plurality of test units arranged periodically along a first direction. Each test unit includes at least one switching transistor. The first terminal of the switching transistor is connected to a test signal lead, which is used to transmit a test signal. The second terminal of the switching transistor is connected to the data line.

[0005] The bonding area includes a plurality of bonding units arranged periodically along the first direction, each bonding unit including at least one bonding pad, the bonding pad being connected to the data line;

[0006] In the first direction, the ratio between the number of switching transistors in one arrangement cycle of the test unit and the number of bonding pads in one arrangement cycle of the bonding unit is greater than 0 and less than 2.

[0007] In one alternative implementation, within the test area, both the test signal lead and the data line extend along a second direction, which is perpendicular to the first direction.

[0008] A portion of the test signal lead is multiplexed as the first terminal of the switching transistor, and a portion of the data line is multiplexed as the second terminal of the switching transistor.

[0009] In one optional implementation, the test unit includes a plurality of the switching transistors;

[0010] Within the test unit, the first electrode of each of the switching transistors is located on the same side of the second electrode, and the orthographic projections of each of the switching transistors in the second direction do not overlap with each other. The second direction is perpendicular to the first direction. The plurality of switching transistors include a first transistor and a second transistor, and the orthographic projections of the second electrode of the first transistor and the first electrode of the second transistor in the first direction overlap.

[0011] In one alternative implementation, within the test unit, the plurality of switching transistors further include a third transistor, which is adjacent to the second transistor, and the second electrode of the second transistor and the first electrode of the third transistor overlap in their orthogonal projections in the first direction.

[0012] In one alternative implementation, the test area and the binding area are located on opposite sides of the display area.

[0013] In one alternative implementation, the test area and the binding area are located on the same side of the display area, with the binding area located between the display area and the test area.

[0014] In one alternative implementation, the data line includes a data transmission line and a data input line, with both ends of the data transmission line connected to the second terminal of the switching transistor and the first end of the bonding pad, respectively, and the second end of the bonding pad connected to the data input line.

[0015] In one alternative implementation, the switching transistor includes a channel region having a width-to-length ratio greater than or equal to 13 / 3 and less than or equal to 200 / 4.

[0016] In one alternative implementation, the ratio is 1.

[0017] In one optional implementation, the border area further includes an input area located on the side of the test area away from the display area. The input area includes multiple test signal buses, and the extension direction of the test signal buses intersects with the extension direction of the test signal leads.

[0018] The test signal bus is connected to the test signal lead, and the test signal bus is used to input the test signal to the data line of the sub-pixel of the same color through the test signal lead.

[0019] In one alternative implementation, the plurality of test signal buses includes at least one internal transmission bus located in the first metal layer;

[0020] The test signal lead is located in the second metal layer, and a first insulating layer is provided between the first metal layer and the second metal layer;

[0021] A second insulating layer is provided on the side of the second metal layer away from the first metal layer, and a first electrode layer is provided on the side of the second insulating layer away from the first metal layer, the first electrode layer including a plurality of transition electrodes; or a third insulating layer is provided on the side of the first metal layer away from the second metal layer, and a second electrode layer is provided on the side of the third insulating layer away from the second metal layer, the second electrode layer including a plurality of transition electrodes.

[0022] The test signal lead is connected to the internal transmission bus via the adapter electrode; the first part of the adapter electrode is connected to the test signal lead via a first via, and the second part of the adapter electrode is connected to the internal transmission bus via a second via.

[0023] In one alternative implementation, the orthographic projection of the first via onto the plane containing the test signal lead is located within the range of the test signal lead.

[0024] In one alternative implementation, the at least one internal transmission bus includes a first internal bus and a second internal bus, wherein the first internal bus is located on the side of the second internal bus closer to the display area;

[0025] The arrangement direction of the first via and the second via connecting the test signal lead to the first internal bus is perpendicular to the extension direction of the first internal bus.

[0026] The arrangement direction of the first and second vias connecting the test signal leads to the second internal bus is parallel to the extension direction of the second internal bus.

[0027] In one optional implementation, the plurality of test signal buses further includes an edge transmission bus located on the side of the at least one internal transmission bus away from the display area. The edge transmission bus is located on the second metal layer, and the interconnected edge transmission buses and test signal leads form an integral structure.

[0028] In one optional implementation, the plurality of test signal buses includes a first test signal bus, a second test signal bus, and a third test signal bus;

[0029] The first test signal bus is used to input a first test signal to the data line of the first color sub-pixel, the second test signal bus is used to input a second test signal to the data line of the second color sub-pixel, and the third test signal bus is used to input a third test signal to the data line of the third color sub-pixel.

[0030] The first color sub-pixel, the second color sub-pixel, and the third color sub-pixel emit different colors.

[0031] In one optional implementation, the plurality of test signal buses further includes a fourth test signal bus, which is used to input a fourth test signal to the data line of the fourth color sub-pixel;

[0032] The fourth color sub-pixel emits the same color as the first color sub-pixel, and the data lines connecting the fourth test signal bus and the data lines connecting the first test signal bus are alternately arranged.

[0033] In one optional implementation, the plurality of test signal buses further includes a fifth test signal bus, which is used to input a fifth test signal to the data line of the fifth color sub-pixel;

[0034] The fifth color sub-pixel emits the same color as the second color sub-pixel, and the data lines connecting the fifth test signal bus and the data lines connecting the second test signal bus are alternately arranged.

[0035] In one optional implementation, the plurality of test signal buses further includes a sixth test signal bus, which is used to input a sixth test signal to the data line of the sixth color sub-pixel;

[0036] The sixth color sub-pixel emits the same color as the third color sub-pixel, and the data lines connecting the sixth test signal bus and the data lines connecting the third test signal bus are alternately arranged.

[0037] In one alternative implementation, the input area further includes a first signal input terminal, a second signal input terminal, and a third signal input terminal;

[0038] The fourth test signal bus and the first test signal bus are both connected to the first signal input terminal, the fifth test signal bus and the second test signal bus are both connected to the second signal input terminal, and the sixth test signal bus and the third test signal bus are both connected to the third signal input terminal.

[0039] In one optional implementation, within the input region, multiple test signal leads constitute multiple lead units, and the multiple lead units are periodically arranged in the first direction;

[0040] In the first direction, the ratio between the arrangement period of the lead unit and the arrangement period of the bonding unit is equal to the ratio between the number of test signal leads contained in the lead unit and the number of bonding pads contained in the bonding unit.

[0041] In one optional implementation, the plurality of sub-pixels includes sub-pixels of N colors, where N is greater than or equal to 1;

[0042] If the number of test signal buses is N, and the data lines of all sub-pixels of the same color are connected to the same test signal bus, then the number of test signal leads contained in the lead unit is N.

[0043] If the number of test signal buses is greater than a×N and less than or equal to (a+1)×N, and the number of test signal buses connected to the data lines of all sub-pixels of the same color is greater than or equal to a and less than or equal to a+1, then the number of test signal leads contained in the lead unit is (a+1)×N, where a is a positive integer.

[0044] This disclosure provides a display device, including the display panel described in any one of the claims.

[0045] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the scale in the drawings is for illustration only and does not represent the actual scale.

[0047] Figure 1 A schematic diagram of the structure of a display panel in the related art is shown.

[0048] Figure 2 A schematic diagram of the planar structure of a display panel provided in this disclosure is shown.

[0049] Figure 3 A schematic diagram of the structure of the display panel bezel area provided in this disclosure is shown.

[0050] Figure 4 A schematic diagram of the structure of the test area of ​​the first type of display panel provided in this disclosure is shown.

[0051] Figure 5 A schematic diagram of the structure of the first type of driver chip provided in this disclosure is shown.

[0052] Figure 6 A schematic diagram of the structure of the test area of ​​the second type of display panel provided in this disclosure is shown.

[0053] Figure 7 A schematic diagram of the structure of the second type of driver chip provided in this disclosure is shown.

[0054] Figure 8 A schematic cross-sectional view of the input region AA' provided in this disclosure is shown.

[0055] Figure 9 This schematically illustrates another cross-sectional structure at the location of the input region AA' provided in this disclosure;

[0056] Figure 10 A schematic diagram of the structure of the first type of input area provided in this disclosure is shown.

[0057] Figure 11 A schematic diagram of the structure of the second type of input area provided in this disclosure is shown.

[0058] Figure 12 A schematic diagram of the structure of the third type of input area provided in this disclosure is shown.

[0059] Figure 13 A schematic diagram of the structure of the fourth type of input area provided in this disclosure is shown.

[0060] Figure 14 A schematic image of the second type of input region structure provided in this disclosure is shown. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0062] Switch testing is a type of CT inspection. After the liquid crystal cell manufacturing process is complete, an electrical signal is applied to the liquid crystal cell to illuminate it, allowing for manual defect detection and grading. This prevents defective products from flowing into subsequent processes and causing waste. Because switch testing can save a laser cutting process, which is beneficial for increasing production capacity, it is widely used.

[0063] Reference Figure 1 The diagram illustrates a structural schematic of a display panel in the related art. In the related art, the Switch Test structure 10 typically includes a plurality of first units 11 located in a bezel region and periodically arranged in the horizontal direction, each first unit 11 including a number of thin-film transistors 12. The bezel region typically also includes a plurality of second units 13 periodically arranged in the horizontal direction, each second unit 13 including a number of bonding pads 14. In the related art, the number of thin-film transistors 12 included in the first unit 11 is typically twice the number of bonding pads 14 included in the second unit 13.

[0064] When the second unit 13 includes three binding pads 14 arranged vertically, as Figure 1 As shown, each first unit 11 includes six thin-film transistors 12 arranged vertically. Since the six thin-film transistors 12 arranged vertically occupy a large space, they are not suitable for products with narrow bezels.

[0065] To address the aforementioned problems, one embodiment of this disclosure provides a display panel, referring to... Figure 2 A schematic diagram illustrating a planar structure of a display panel provided in this disclosure is shown, such as... Figure 2 As shown, the display panel includes a display area A and a border area B located around the display area A. The display area A includes multiple sub-pixels 21 and multiple data lines 22 connected to the sub-pixels 21. The border area B includes a test area B1 and a binding area B2.

[0066] Reference Figure 3 A schematic diagram illustrating the structure of the bezel area of ​​a display panel provided in this disclosure is shown. (Refer to...) Figure 4 It shows Figure 3 A schematic diagram of the local structure of test region B1. (See attached diagram.) Figure 4 As shown, the test area B1 includes a plurality of test units 31 arranged periodically along a first direction. Each test unit 31 includes at least one switching transistor 32. The first terminal of the switching transistor 32 is connected to a test signal lead 33, which is used to transmit test signals. The second terminal of the switching transistor 32 is connected to a data line 22.

[0067] like Figure 3As shown, the binding area B2 includes a plurality of binding units 34 arranged periodically along a first direction. Each binding unit 34 includes at least one binding pad 35, which is connected to the data line 22.

[0068] In the first direction, the ratio between the number of switching transistors 32 included in one arrangement period T1 of the test unit 31 and the number of bonding pads 35 included in one arrangement period T2 of the bonding unit 34 is greater than 0 and less than 2.

[0069] In a specific implementation, the ratio between the arrangement period T1 of the test unit 31 and the arrangement period T2 of the bonding unit 34 can be equal to the ratio between the number of switching transistors 32 contained in the test unit 31 and the number of bonding pads 35 contained in the bonding unit 34.

[0070] In this embodiment, the test area B1 includes a plurality of switching transistors 32, which constitute a plurality of test units 31 arranged periodically along the first direction.

[0071] The binding region B2 includes a plurality of binding pads 35, which constitute a plurality of binding units 34 arranged periodically along a first direction.

[0072] The switching transistor 32 can be, for example, a thin-film transistor, and this disclosure does not limit it. The switching transistor 32 is used to control the conduction and cutoff between the test signal lead 33 and the data line 22.

[0073] When the switching transistor 32 is a thin-film transistor, its first terminal can be the source and its second terminal can be the drain. The gates of all switching transistors 32 within the test region B1 can be connected together and controlled by the same signal; this disclosure does not limit this.

[0074] During CT detection, a test signal can be input to the test signal lead 33, and the control switch transistor 32 can be used to turn on the test signal lead 33 and the data line 22, thereby inputting the test signal into the sub-pixel of the display area.

[0075] Optionally, after the CT scan is completed, a shutdown signal can be connected to the gate of the switching transistor 32 in the test area B1 to ensure that the switching transistor 32 is in the off state; the first terminal of the switching transistor 32 can also be connected to the ground potential signal to avoid interference signals being input to the data line 22 in the display area A during normal display, which could lead to display abnormalities.

[0076] In this embodiment, the bonding pad 35 in the bonding area B2 is used to bond the driver chip, which is used to provide display signals to each sub-pixel 21 through the data line 22 during the display process of the display panel.

[0077] In this embodiment, when the number of bonding pads 35 included in the bonding unit 34 is 3, the number of switching transistors 32 included in the test unit 31 is less than 6. Specifically, the number of switching transistors 32 included in the test unit 31 can be, for example, 3, 4, or 5. Figure 1 Compared to the display panel shown, the display panel provided in this embodiment can reduce the space occupied by each test unit 31 in the vertical direction by setting a smaller number of switching transistors 32 in the test unit 31, which is beneficial to reducing the bezel size and is suitable for products with narrow bezel size.

[0078] Furthermore, since the ratio between the arrangement period T1 of the test unit 31 and the arrangement period T2 of the bonding unit 34 is equal to the ratio between the number of switching transistors 32 included in the test unit 31 and the number of bonding pads 35 included in the bonding unit 34, the number of switching transistors 32 and the number of bonding pads 35 are equal within a certain width range in the first direction, and they are connected in a one-to-one correspondence. Through proper design, the uniformity of the length of the data lines disposed between the switching transistors 32 and the bonding pads 35 can be improved.

[0079] With a fixed test area size perpendicular to the first direction, and since the number of switching transistors 32 within each test unit 31 is relatively small, a channel region with a larger aspect ratio can be designed when the switching transistors 32 have a channel region. A channel region with a larger aspect ratio allows for the passage of larger current test signals, meeting the testing requirements of larger display panels. Figure 3 and Figure 4 In the middle, the width direction of the channel region is the second direction, and the length direction of the channel region is the first direction.

[0080] In this embodiment, the second direction is perpendicular to the first direction.

[0081] In a specific implementation, the structure of the bonding pads 35 within the bonding region B2 is the same as the structure of the output pins on the driver chip. The structure of the bonding pads 35 may include, for example, the arrangement period of the bonding pads 35 and the number of bonding pads 35 within each period.

[0082] like Figure 5 It shows the relationship with Figure 3 The diagram shows the structure of the driver chip corresponding to the binding area B2. Figure 5 As shown, the driver chip includes a plurality of first pin units 51 arranged periodically along a first direction. Each first pin unit 51 includes three first pins 52. The three first pins 52 are arranged sequentially in a second direction, and two adjacent first pins 52 partially overlap in the first direction. Figure 5The arrangement period T3 of the first pin unit 51 shown in the first direction is 33um.

[0083] Accordingly, such as Figure 3 As shown, each binding unit 34 within the binding region B2 includes three binding pads 35, which are arranged sequentially in the second direction, with adjacent binding pads 35 partially overlapping in the first direction. The arrangement period T2 of the binding units 34 in the first direction is 33 μm.

[0084] like Figure 3 and Figure 4 As shown, each test unit 31 within test area B1 includes three switching transistors 32, which are arranged sequentially in the second direction, with adjacent switching transistors 32 partially overlapping in the first direction. The arrangement period T1 of the test units 31 in the first direction is 33µm.

[0085] Figure 3 In the display panel shown, in the first direction, the ratio between the arrangement period T1 of the test unit 31 and the arrangement period T2 of the bonding unit 34 is 1, and the ratio between the number of switching transistors 32 included in the test unit 31 and the number of bonding pads 35 included in the bonding unit 34 is 1.

[0086] like Figure 4 As shown, within the arrangement period T1 of a test unit 31, four traces need to be spaced out. Therefore, when the arrangement period T1 of the test unit 31 is 33µm, the period of each trace is 33µm / 4 = 8.25µm. Specifically, the trace width is 4.25µm, and the trace spacing is 4µm. This trace width and trace spacing are the process limits of ordinary photomasks. Figure 3 and Figure 4 The structure of the test area shown can minimize the space occupied by the test area in the first direction.

[0087] It should be noted that, for Figure 3 The binding area B2 and test area B1 shown are not limited to... Figure 3The structure is shown. The ratio between the arrangement period T1 of the test unit 31 and the arrangement period T2 of the bonding unit 34, and the ratio between the number of switching transistors 32 included in the test unit 31 and the number of bonding pads 35 included in the bonding unit 34, can also be other values. For example, when the number of bonding pads 35 included in the bonding unit 34 is 3, the number of switching transistors 32 included in the test unit 31 can also be 4 or 5, that is, the above ratios can be 4 / 3, 5 / 3, etc. When the above ratio is 4 / 3 and the arrangement period T2 of the bonding unit 34 is 33μm, the arrangement period T1 of the test unit 31 is 44μm; when the above ratio is 5 / 3 and the arrangement period T2 of the bonding unit 34 is 33μm, the arrangement period T1 of the test unit 31 is 55μm.

[0088] like Figure 3 and Figure 4 As shown, by setting the ratio between the arrangement period T1 of the test unit 31 and the arrangement period T2 of the bonding unit 34, and the ratio between the number of switching transistors 32 contained in the test unit 31 and the number of bonding pads 35 contained in the bonding unit 34 to 1, the space occupied by the test unit 31 in the first direction and the second direction can be minimized to the greatest extent without exceeding the limits of ordinary mask process, and the bezel size of the display panel can be minimized to the greatest extent.

[0089] When the number of binding pads 35 included in the binding unit 34 is 2, refer to Figure 6 A schematic diagram of the corresponding test area is shown for reference. Figure 7 A schematic diagram of the corresponding driver chip is shown. For example... Figure 7 As shown, the driver chip includes a plurality of second pin units 71 arranged periodically along a first direction. Each second pin unit 71 includes two second pins 72. The two second pins 72 are arranged sequentially perpendicular to the first direction, and two adjacent second pins 72 partially overlap in the first direction. Figure 7 The arrangement period T3 of the second pin unit 71 shown in the first direction is 28um.

[0090] Accordingly, in the context of binding Figure 7 Within the bonding region B2 of the driver chip shown, each bonding unit 34 includes two bonding pads 35, which are arranged sequentially in a direction perpendicular to the first direction, with adjacent bonding pads 35 partially overlapping in the first direction. The arrangement period T2 of the bonding units 34 in the first direction is 28 μm.

[0091] like Figure 6As shown, each test unit 31 within test area B1 includes two switching transistors 32, which are arranged sequentially in the second direction, with adjacent switching transistors 32 partially overlapping in the first direction. The arrangement period T1 of the test units 31 in the first direction is 28µm.

[0092] Figure 6 In the test area shown, in the first direction, the ratio between the arrangement period T1 of the test unit 31 and the arrangement period T2 of the bonding unit 34 is 1, that is, the ratio between the number of switching transistors 32 included in the test unit 31 and the number of bonding pads 35 included in the bonding unit 34 is 1. In other words, the number of bonding pads 35 included in the bonding unit 34 is 2, and the number of switching transistors 32 included in the test unit 31 is 2.

[0093] It should be noted that when the number of bonding pads 35 included in the bonding unit 34 is 2, the number of switching transistors 32 included in the test unit 31 can also be 1 or 3, that is, the above ratio can be 1 / 2, 3 / 2, etc. When the above ratio is 1 / 2 and the arrangement period T2 of the bonding unit 34 is 28μm, the arrangement period T1 of the test unit 31 is 14μm; when the above ratio is 3 / 2 and the arrangement period T2 of the bonding unit 34 is 28μm, the arrangement period T1 of the test unit 31 is 42μm.

[0094] like Figure 6 As shown, within the arrangement period T1 of a test unit 31, two traces need to be set at intervals. When the arrangement period T1 of the test unit 31 is 14μm, the trace period is 14um / 2=7um, that is, the sum of the trace width and the trace spacing is 7μm. This value is lower than the process limit of 8.25μm for ordinary photomasks.

[0095] like Figure 6 As shown, by setting the ratio between the arrangement period T1 of the test unit 31 and the arrangement period T2 of the bonding unit 34, and the ratio between the number of switching transistors 32 contained in the test unit 31 and the number of bonding pads 35 contained in the bonding unit 34 to 1, the space occupied by the test unit 31 in the first direction and the second direction can be minimized to the greatest extent without exceeding the limits of ordinary mask process, and the bezel size of the display panel can be minimized to the greatest extent.

[0096] Therefore, in one optional implementation, the ratio between the arrangement period T1 of the test unit 31 and the arrangement period T2 of the bonding unit 34 is equal to the ratio between the number of switching transistors 32 included in the test unit 31 and the number of bonding pads 35 included in the bonding unit 34, and this ratio is 1. In this way, without exceeding the limits of ordinary photomask processes, the space occupied by the test unit 31 in the first and second directions can be minimized to the greatest extent possible, thereby maximizing the reduction of the bezel size of the display panel.

[0097] In practice, there are several ways to set the test area B1 and the binding area B2 within the border area B.

[0098] In the first implementation, the test area B1 and the binding area B2 are located on opposite sides of the display area A, as shown below. Figure 2 As shown in the diagram, in this implementation, one end of each data line 22 is connected to the second electrode of the switching transistor 32, and the other end is connected to the bonding pad 35.

[0099] In the second implementation, such as Figure 3 As shown, test area B1 and binding area B2 are located on the same side of display area A, with binding area B2 located between display area A and test area B1. By placing test area B1 and binding area B2 on the same side of display area A, the structure of border area B can be made more compact, which helps to further reduce the border size.

[0100] like Figure 3 As shown, the data line 22 may include a data transmission line 221 and a data input line 222. The two ends of the data transmission line 221 are respectively connected to the second pole of the switching transistor 32 and the first end of the bonding pad 35, and the second end of the bonding pad 35 is connected to the data input line 222.

[0101] The bonding pad 35 is located between the data transmission line 221 and the data input line 222, which are connected by the bonding pad 35. The second terminal of the switching transistor 32 in the test area B1 is connected to the data transmission line 221, and the first terminal is connected to the test signal lead 33. When the first and second terminals of the switching transistor 32 are switched on, the test signal on the test signal lead 33 can be transmitted to the data transmission line 221 and the data input line 222.

[0102] In this implementation, by setting the binding area B2 between the display area A and the test area B1, during CT detection, the test signal is transmitted sequentially from the test signal lead 33 to the data transmission line 221, the binding pad 35 and the data input line 222. Therefore, CT detection can simultaneously detect defects in the binding area B2 and the display area A, resulting in a more comprehensive detection range.

[0103] In a specific implementation, the switching transistor 32 may include a channel region. The aspect ratio of the channel region may be greater than or equal to 13 / 3 and less than or equal to 200 / 4. For example, the aspect ratio of the channel region may be 42 / 4, 50 / 4, etc. In a specific implementation, the aspect ratio of the channel region may be determined based on factors such as available space and process conditions, and this disclosure does not impose any limitations on it.

[0104] Since the switching transistor 32, with its channel area having a large aspect ratio, can allow a large current test signal to pass through, it can meet the testing requirements of large-size display panels.

[0105] Optionally, within test area B1, such as Figure 4 and Figure 6 As shown, both the test signal lead 33 and the data line 22 extend along the second direction, which is perpendicular to the first direction.

[0106] Optionally, such as Figure 4 and Figure 6 As shown, a portion of the test signal lead 33 is multiplexed as the first terminal of the switching transistor 32, and a portion of the data line 22 is multiplexed as the second terminal of the switching transistor 32.

[0107] By using a portion of the test signal lead 33 as the first electrode of the switching transistor 32 and a portion of the data line 22 as the second electrode of the switching transistor 32, it is not necessary to separately set the individual film layer structures of the switching transistor 32, thereby reducing the difficulty of the fabrication process and saving the fabrication cost.

[0108] In one alternative implementation, such as Figure 4 and Figure 6 As shown, the test unit 31 includes a plurality of switching transistors 32. That is, each test unit 31 includes at least two switching transistors 32.

[0109] like Figure 4 and Figure 6 As shown, within the test unit 31, the first pole of each switching transistor 32 is located on the same side of the second pole, and the orthographic projections of each switching transistor 32 in the second direction do not overlap with each other, wherein the second direction is perpendicular to the first direction.

[0110] The fact that the first electrode of each switching transistor 32 is located on the same side of the second electrode means that the first electrode of each switching transistor 32 is located close to the same edge of the test area B1. For example... Figure 4 and Figure 6 As shown, the first electrode of each switching transistor 32 in the test unit 31 is located to the left of the second electrode, that is, the first electrode of each switching transistor 32 is located close to the left edge of the test area B1.

[0111] like Figure 4 and Figure 6 As shown, the multiple switching transistors 32 within the test unit 31 may include a first transistor 321 and a second transistor 322. The second electrode of the first transistor 321 and the first electrode of the second transistor 322 overlap in their orthogonal projections in the first direction. By setting the second electrode of the first transistor 321 and the first electrode of the second transistor 322 to overlap in the first direction, the space in the first direction can be effectively utilized, reducing the space occupied by the test unit 31 in the first direction.

[0112] Optionally, the orthographic projections of the second electrode of the first transistor 321 and the first electrode of the second transistor 322 in the first direction can completely overlap, such as... Figure 4 and Figure 6 As shown, by setting the second electrode of the first transistor 321 and the first electrode of the second transistor 322 to completely overlap in the first direction, the space occupied by the test unit 31 in the first direction can be minimized.

[0113] When the test unit 31 includes at least three switching transistors 32, the multiple switching transistors 32 in the test unit 31 may also include a third transistor 323, such as Figure 4 As shown, the third transistor 323 is adjacent to the second transistor 322, and the second electrode of the second transistor 322 and the first electrode of the third transistor 323 overlap in their orthogonal projections in the first direction. The overlap of the second electrode of the second transistor 322 and the first electrode of the third transistor 323 in the first direction can effectively utilize the space in the first direction and reduce the space occupied by the test unit 31 in the first direction.

[0114] Optionally, the orthographic projections of the second electrode of the second transistor 322 and the first electrode of the third transistor 323 in the first direction can completely overlap, such as... Figure 4 As shown, by setting the second electrode of the second transistor 322 and the first electrode of the third transistor 323 to completely overlap in the first direction, the space occupied by the test unit 31 in the first direction can be minimized.

[0115] In order to input the test signal to the test signal lead 33, in the specific implementation, such as Figure 2 As shown, the border area B may also include an input area B3, which can be located on the side of the test area B1 away from the display area A. By setting the input area B3 on the side of the test area B1 away from the display area A, the distance between the test area B1 and the input area B3 is closer, thus saving the space occupied by the connecting line between them and helping to reduce the size of the border area.

[0116] like Figure 3As shown, the input area B3 may include multiple test signal buses 36, and the extension direction of the test signal buses 36 intersects with the extension direction of the test signal leads 33.

[0117] The test signal bus 36 is connected to the test signal lead 33. The test signal bus 36 is used to input test signals to the data line 22 of the sub-pixels of the same color through the test signal lead 33. That is, the sub-pixels connected to the same test signal bus 36 emit the same color.

[0118] The extension direction of the test signal bus 36 can be, for example, a first direction, such as... Figure 3 As shown, this disclosure does not limit this.

[0119] In practical implementation, there can be multiple ways to connect the test signal bus 36 and the test signal lead 33. (Refer to...) Figures 10 to 13 The schematic diagram illustrates the planar structure of several input areas.

[0120] In one alternative implementation, such as Figures 10 to 13 As shown, the multiple test signal buses 36 include at least one internal transmission bus 101. (Refer to...) Figure 8 and Figure 9 The diagrams show cross-sectional views of the connection points between the test signal leads and the internal transmission bus. Figure 8 and Figure 9 As shown, the internal transmission bus 101 is located on the first metal layer 81, the test signal lead 33 is located on the second metal layer 82, and a first insulating layer 83 is provided between the first metal layer 81 and the second metal layer 82.

[0121] like Figure 8 As shown, a second insulating layer 84 is provided on the side of the second metal layer 82 opposite to the first metal layer 81, and a first electrode layer 85 is provided on the side of the second insulating layer 84 opposite to the first metal layer 81. The first electrode layer 85 includes a plurality of transition electrodes 86; or, as shown... Figure 9 As shown, a third insulating layer 91 is provided on the side of the first metal layer 81 that is away from the second metal layer 82, and a second electrode layer 92 is provided on the side of the third insulating layer 91 that is away from the second metal layer 82. The second electrode layer 92 includes a plurality of transition electrodes 86.

[0122] like Figure 8 and Figure 9 As shown, the test signal lead 33 is connected to the internal transmission bus 101 through the adapter electrode 86; the first part of the adapter electrode 86 is connected to the test signal lead 33 through the first via 87, and the second part of the adapter electrode 86 is connected to the internal transmission bus 101 through the second via 88.

[0123] The first metal layer 81 may be the same layer and made of the same material as the gate line in the display area, the second metal layer 82 may be the same layer and made of the same material as the data line in the display area, and the transition electrode 86 may be the same layer and made of the same material as the pixel electrode in the display area A. This disclosure does not limit this.

[0124] In this implementation, the adapter electrode 86 is connected to the test signal lead 33 and the internal transmission bus 101 via, respectively. Since the first via 87 and the second via 88 can be formed synchronously with the via connecting the pixel electrode and the drain of the thin film transistor in the sub-pixel in the display area, it is not necessary to add a mask separately, which can reduce the difficulty of the fabrication process and save the fabrication cost.

[0125] In a specific implementation, the test signal lead 33 and the internal transmission bus 101 can also be connected through a via provided on the first insulating layer 83. This disclosure does not limit the connection method between the test signal bus 36 and the test signal lead 33.

[0126] Optionally, such as Figure 8 and Figure 9 As shown, the orthographic projection of the first via 87 onto the plane containing the test signal lead 33 lies within the range of the test signal lead 33. By ensuring that the test signal lead 33 completely covers the orthographic projection of the first via 87 onto the plane containing the test signal lead 33, the risk of via failure and excessive resistance at the location of the first via 87 can be reduced.

[0127] Optionally, such as Figures 10 to 13 As shown, at least one internal transmission bus 101 includes a first internal bus 111, and the arrangement direction of the first via 87 and the second via 88 connecting the test signal lead 33 to the first internal bus 111 can be perpendicular to the extension direction of the first internal bus 111.

[0128] like Figures 10 to 13 As shown, the orthographic projection of the first via 87 connecting the test signal lead 33 and the first internal bus 111 on the plane of the first internal bus 111 is located on the side of the first internal bus 111 closer to the display area A, and the orthographic projection of the first via 87 connecting the test signal lead 33 and the first internal bus 111 on the plane of the first internal bus 111 is located within the range of the first internal bus 111.

[0129] Optionally, such as Figures 11 to 13As shown, at least one internal transmission bus 101 may further include a second internal bus 112, which is located on the side of the first internal bus 111 away from the display area A. That is, the first internal bus 111 is located on the side of the second internal bus 112 closer to the display area A. The arrangement direction of the first via 87 and the second via 88 connecting the test signal lead 33 to the second internal bus 112 may be parallel to the extension direction of the second internal bus 112.

[0130] like Figures 11 to 13 As shown, the orthographic projections of the first via 87 and the second via 88 connecting the test signal lead 33 and the second internal bus 112 on the plane of the first internal bus 111 are both within the range of the first internal bus 111.

[0131] Since the first internal bus 111 is close to the display area A, there are a large number of test signal leads 33 that need to be set in the first direction, and the available space for vias is small. Therefore, the two vias (first via 87 and second via 88) connecting any test signal lead 33 to the first internal bus 111 can be arranged perpendicular to the extension direction of the first internal bus 111 to reduce the risk of short circuit.

[0132] Since the second internal bus 112 is far from the display area A, the number of test signal leads 33 that need to be set in the first direction is small, and there is more available space for vias. Therefore, the two vias (first via 87 and second via 88) connecting any test signal lead 33 to the second internal bus 112 can be arranged parallel to the extension direction of the first internal bus 111. This can reduce the space occupied by the input area B3 in the perpendicular direction and help to reduce the bezel size of the display panel.

[0133] exist Figure 10 In this configuration, all test signal buses 36 within input area B3 are internal transmission buses 101, meaning all test signal buses 36 are located on the first metal layer 81. Furthermore, the internal transmission buses 101 can all be first internal buses 111, such as... Figure 10 As shown, this disclosure does not limit it.

[0134] exist Figures 11 to 13 In the input area B3, a portion of the test signal bus 36 serves as the internal transmission bus 101. In specific implementations, the number of the first internal bus 111 and the second internal bus 112 can be designed according to the available space. For example... Figure 11 As shown, the number of first internal buses 111 is 2, and the number of second internal buses 112 is 1; Figure 12 As shown, the number of first internal buses 111 is 2, and the number of second internal buses 112 is 2; as Figure 13As shown, the number of first internal buses 111 is 2, and the number of second internal buses 112 is 3.

[0135] Optionally, such as Figures 11 to 13 As shown, the multiple test signal buses 36 also include an edge transmission bus 102. The edge transmission bus 102 is located on the side of at least one internal transmission bus 101 away from the display area A. The edge transmission bus 102 is located on the second metal layer 82. The interconnected edge transmission buses 102 and test signal leads 33 are integrated into one structure.

[0136] In a specific implementation, all test signal buses 36 in the input area B3, except for the edge transmission bus 102, can be internal transmission buses 101.

[0137] In this implementation, the edge transmission bus 102 and the test signal lead 33 are located on the same layer, namely the second metal layer 82. The edge transmission bus 102 and the test signal lead 33 can be directly connected or form an integral structure without the need for via connections, thus saving the space occupied by vias. Therefore, the space occupied by the input area B3 in the vertical direction can be further reduced, which helps to reduce the bezel size of the display panel.

[0138] In this implementation, by placing the outermost test signal bus 36 (the one furthest from the display area A), i.e., the edge transmission bus 102, on the second metal layer 82, a short circuit between the edge transmission bus 102 and the internal test signal lead 33 can be avoided. The internal test signal lead 33 is the test signal lead 33 connected to the internal transmission bus 101.

[0139] In practice, there are multiple ways to configure the multiple test signal buses 36 within the input area B3.

[0140] In the first implementation, such as Figure 10 As shown, the multiple test signal buses 36 include a first test signal bus DR1, a second test signal bus DG1, and a third test signal bus DB1.

[0141] The first test signal bus DR1 is used to input the first test signal to the data line of the first color sub-pixel, the second test signal bus DG1 is used to input the second test signal to the data line of the second color sub-pixel, and the third test signal bus DB1 is used to input the third test signal to the data line of the third color sub-pixel.

[0142] Among them, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel emit different colors.

[0143] In this embodiment, the first color sub-pixel is red, the second color sub-pixel is green, and the third color sub-pixel is blue, as an example.

[0144] In this implementation, the input area B3 further includes a first signal input terminal 103, a second signal input terminal 104, and a third signal input terminal 105. Specifically, a first test signal bus DR1 is connected to the first signal input terminal 103, a second test signal bus DG1 is connected to the second signal input terminal 104, and a third test signal bus DB1 is connected to the third signal input terminal 105.

[0145] In this implementation, different test signal buses 36 within the input area B3 are used to connect the data lines 22 of different color sub-pixels. When the display area A includes three color sub-pixels, at least three test signal buses 36 are required. When the input area B3 is equipped with only three test signal buses 36, i.e., the minimum number of test signal buses 36, the space occupied by the input area B3 can be reduced, and the bezel size of the display panel can be reduced.

[0146] In the second implementation, such as Figure 11 As shown, the multiple test signal buses 36 also include a fourth test signal bus DR2, which is used to input the fourth test signal to the data line of the fourth color sub-pixel.

[0147] Reference Figure 14 It shows Figure 11 The input area shown is an image of the entity structure.

[0148] The fourth color sub-pixel emits the same color as the first color sub-pixel, and the data line connecting the fourth test signal bus DR2 is alternately set with the data line connecting the first test signal bus DR1.

[0149] Assuming that the sub-pixels in columns 1, 4, 7, 10, and 13 of the display area are red sub-pixels, then the sub-pixels in columns 1, 7, and 13 can be first color sub-pixels, connected to the first test signal bus DR1 via data lines and test signal leads 33; the sub-pixels in columns 4 and 10 can be fourth color sub-pixels, connected to the fourth test signal bus DR2 via data lines and test signal leads 33. This allows for alternating settings between the data lines connected to the fourth test signal bus DR2 and the data lines connected to the first test signal bus DR1.

[0150] Optionally, both the fourth test signal bus DR2 and the first test signal bus DR1 can be connected to the first signal input terminal 103 to ensure that the fourth test signal is the same as the first test signal.

[0151] In this implementation, the first color sub-pixel and the fourth color sub-pixel are the same color sub-pixel, both being red sub-pixels. The first test signal bus DR1 and the fourth test signal bus DR2 are connected in parallel. A portion of the red sub-pixels, such as the first color sub-pixels, are connected to the first test signal bus DR1, and another portion of the red sub-pixels, such as the fourth color sub-pixels, are connected to the fourth test signal bus DR2. Therefore, the number of vias on the first test signal bus DR1 or the fourth test signal bus DR2 can be reduced, ensuring that the first vias 87 corresponding to the first test signal bus DR1 or the fourth test signal bus DR2 have a larger available space. This allows the linewidth of the test signal leads 33 at these first vias 87 to be increased, enabling the test signal leads 33 to cover the orthographic projection of the first vias 87 on the plane where the test signal leads 33 are located, thereby reducing the risk of via failure and excessive resistance.

[0152] In the third implementation, such as Figure 12 As shown, the multiple test signal buses 36 also include a fifth test signal bus DG2, which is used to input the fifth test signal to the data line of the fifth color sub-pixel.

[0153] The fifth color sub-pixel emits the same color as the second color sub-pixel, and the data line connecting the fifth test signal bus DG2 is alternately set with the data line connecting the second test signal bus DG1.

[0154] Assuming that the sub-pixels in columns 2, 5, 8, 11, and 14 of the display area are green sub-pixels, then the sub-pixels in columns 2, 8, and 14 can be second-color sub-pixels, connected to the second test signal bus DG1 via data lines and test signal leads 33; the sub-pixels in columns 5 and 11 can be fifth-color sub-pixels, connected to the fifth test signal bus DG2 via data lines and test signal leads 33. This allows for alternating settings between the data lines connected to the fifth test signal bus DG2 and the data lines connected to the second test signal bus DG1.

[0155] Optionally, both the fifth test signal bus DG2 and the second test signal bus DG1 can be connected to the second signal input terminal 104 to ensure that the fifth test signal is the same as the second test signal.

[0156] In this implementation, the fifth color sub-pixel and the second color sub-pixel are the same color sub-pixel, both being green sub-pixels. The second test signal bus DG1 and the fifth test signal bus DG2 are connected in parallel. A portion of the green sub-pixels, such as the second color sub-pixels, are connected to the second test signal bus DG1, and another portion of the green sub-pixels, such as the fifth color sub-pixels, are connected to the fifth test signal bus DG2. Therefore, the number of vias on the second test signal bus DG1 or the fifth test signal bus DG2 can be reduced, ensuring that the first vias 87 corresponding to the second test signal bus DG1 or the fifth test signal bus DG2 have a larger usable space. This allows the linewidth of the test signal leads 33 at these first vias 87 to be increased, enabling the test signal leads 33 to cover the orthographic projection of the first vias 87 on the plane where the test signal leads 33 are located, thereby reducing the risk of via failure and excessive resistance.

[0157] In the fourth implementation, such as Figure 13 As shown, the multiple test signal buses 36 also include a sixth test signal bus DB2, which is used to input the sixth test signal to the data line 22 of the sixth color sub-pixel.

[0158] The sixth color sub-pixel emits the same color as the third color sub-pixel, and the data line 22 connecting the sixth test signal bus DB2 and the data line 22 connecting the third test signal bus DB1 are alternately set.

[0159] Assuming that the sub-pixels in columns 3, 6, 9, 12, and 15 of the display area are blue sub-pixels, then the sub-pixels in columns 3, 9, and 15 can be third-color sub-pixels, connected to the third test signal bus DB1 via data lines and test signal leads 33; the sub-pixels in columns 6 and 12 can be sixth-color sub-pixels, connected to the sixth test signal bus DB2 via data lines and test signal leads 33. This allows for alternating settings between the data lines connected to the sixth test signal bus DB2 and the data lines connected to the third test signal bus DB1.

[0160] Optionally, both the sixth test signal bus DB2 and the third test signal bus DB1 can be connected to the third signal input terminal 105 to ensure that the sixth test signal is the same as the third test signal.

[0161] In this implementation, the sixth color sub-pixel and the third color sub-pixel are the same color sub-pixel, both being blue sub-pixels. The third test signal bus DB1 and the sixth test signal bus DB2 are connected in parallel. A portion of the blue sub-pixels, such as the third color sub-pixels, are connected to the third test signal bus DB1, and another portion of the blue sub-pixels, such as the sixth color sub-pixels, are connected to the sixth test signal bus DB2. Therefore, the number of vias on the third test signal bus DB1 or the sixth test signal bus DB2 can be reduced, ensuring that the first vias 87 corresponding to the third test signal bus DB1 or the sixth test signal bus DB2 have a larger available space. This allows the linewidth of the test signal leads 33 at these first vias 87 to be increased, enabling the test signal leads 33 to cover the orthographic projection of the first vias 87 on the plane where the test signal leads 33 are located, thereby reducing the risk of via failure and excessive resistance.

[0162] By setting multiple test signal buses 36 connected to the same color sub-pixel in parallel, the available space of the first via 87 connecting these test signal buses 36 can be increased, and the line width of the test signal lead 33 at the location of these first via 87 can be increased. This solves the problem of insufficient width of the test signal lead 33 at the first via 87 due to process limitations, conforms to the design trend of increasingly smaller arrangement period of the bonding unit 34, and helps to make narrow bezel display panels.

[0163] As the arrangement period of the binding unit 34 becomes smaller, multiple test signal buses 36 connecting the first color sub-pixel can be connected in parallel; furthermore, multiple test signal buses 36 connecting the first color sub-pixel and multiple test signal buses 36 connecting the second color sub-pixel can also be connected in parallel; furthermore, multiple test signal buses 36 connecting the first color sub-pixel and multiple test signal buses 36 connecting the second color sub-pixel and multiple test signal buses 36 connecting the third color sub-pixel can also be connected in parallel.

[0164] In addition, to obtain a larger usable space for the first via, a phase-shift mask can be used to fabricate the second metal layer 82 in the specific implementation. Since the minimum trace spacing fabricated by the phase-shift mask is 2.4μm, while the minimum trace spacing fabricated by a regular mask is 4μm, using a phase-shift mask to fabricate the second metal layer 82 can reduce the spacing between the test signal leads 33, thereby increasing the usable space of the first via 87, increasing the linewidth of the test signal lead 33 at the first via 87, ensuring that the test signal lead 33 covers the orthographic projection of the first via 87 on the plane where the test signal lead 33 is located, and reducing the risk of via failure and excessive resistance.

[0165] Given the same size for the binding region B2 Figure 3The total width (dimension perpendicular to the first direction) of the test area B1 and the input area B3 shown is 285 micrometers. Figure 1 The total width of the test area B1 and the input area B3 shown is 320 micrometers. Therefore, it can be seen that using the display panel provided in this application can effectively reduce the bezel size of the display panel.

[0166] In one alternative implementation, such as Figures 10 to 13 As shown, within the input region B3, multiple test signal leads 33 constitute multiple lead units 106, and the multiple lead units 106 are periodically arranged in the first direction.

[0167] In the first direction, the ratio between the arrangement period T4 of the lead unit 106 and the arrangement period T2 of the bonding unit 34 is equal to the ratio between the number of test signal leads 33 included in the lead unit 106 and the number of bonding pads 35 included in the bonding unit 34.

[0168] Since the ratio between the arrangement period T1 of the test unit 31 and the arrangement period T2 of the bonding unit 34 is equal to the ratio between the number of switching transistors 32 contained in the test unit 31 and the number of bonding pads 35 contained in the bonding unit 34, the ratio between the arrangement period T4 of the lead unit 106 and the arrangement period T1 of the test unit 31 is equal to the ratio between the number of test signal leads 33 contained in the lead unit 106 and the number of switching transistors 32 contained in the test unit 31.

[0169] In this implementation, within a certain width range in the first direction, the number of test signal leads 33 is equal to the number of switching transistors 32, and they are connected in a one-to-one correspondence. Through proper design, the uniformity of the length of the test signal leads 33 can be improved.

[0170] In a specific implementation, multiple sub-pixels 21 can include sub-pixels 21 of N colors, where N is greater than or equal to 1.

[0171] If the number of test signal buses 36 is N, and the data lines 22 of all sub-pixels 21 of the same color are connected to the same test signal bus 36, then the number of test signal leads 33 contained in the lead unit 106 can be N.

[0172] If the number of test signal buses 36 is greater than a×N and less than or equal to (a+1)×N, and the number of test signal buses 36 connected to the data lines 22 of all sub-pixels 21 of the same color is greater than or equal to a and less than or equal to a+1, then the number of test signal leads 33 contained in the lead unit 106 can be (a+1)×N, where a is a positive integer.

[0173] like Figure 10As shown, display area A includes three colors of sub-pixels 21 (e.g., red sub-pixels, blue sub-pixels, and green sub-pixels, N=3), and the number of test signal buses 36 is N=3. All data lines of the red sub-pixels are connected to the first test signal bus DR1 via test signal leads 33; all data lines of the green sub-pixels are connected to the second test signal bus DG1 via test signal leads 33; and all data lines of the blue sub-pixels are connected to the third test signal bus DB1 via test signal leads 33. In this case, the number of test signal leads 33 included in lead unit 106 is N=3.

[0174] like Figure 11 As shown, display area A includes three colors of sub-pixels 21 (e.g., red, blue, and green sub-pixels, N=3), and the number of test signal buses 36 is 4. Since 4 is greater than 1×3 and less than 2×3, a=1. The minimum number of test signal buses 36 connecting sub-pixels 21 of the same color is one, and the maximum number is two, such as... Figure 11 As shown, a portion of the red sub-pixels, such as the first color sub-pixel, is connected to the first test signal bus DR1, and another portion of the red sub-pixels, such as the fourth color sub-pixel, is connected to the fourth test signal bus DR2; the data lines of all green sub-pixels are connected to the second test signal bus DG1 via test signal leads 33; and the data lines of all blue sub-pixels are connected to the third test signal bus DB1 via test signal leads 33. In this case, the number of test signal leads 33 included in the lead unit 106 is (a+1)×N=6.

[0175] like Figure 12 As shown, display area A includes three colors of sub-pixels 21 (e.g., red, blue, and green sub-pixels, N=3), and the number of test signal buses 36 is 5. Since 5 is greater than 1×3 and less than 2×3, a=1. The minimum number of test signal buses 36 connecting sub-pixels 21 of the same color is one, and the maximum number is two, such as... Figure 12 As shown, a portion of the red sub-pixels, such as the first color sub-pixel, is connected to the first test signal bus DR1, and another portion of the red sub-pixels, such as the fourth color sub-pixel, is connected to the fourth test signal bus DR2; a portion of the green sub-pixels, such as the second color sub-pixel, is connected to the second test signal bus DG1, and another portion of the green sub-pixels, such as the fifth color sub-pixel, is connected to the fifth test signal bus DG2; the data lines of all blue sub-pixels are connected to the third test signal bus DB1 through test signal leads 33. In this case, the number of test signal leads 33 included in the lead unit 106 is (a+1)×N=6.

[0176] like Figure 13As shown, display area A includes three colors of sub-pixels 21 (e.g., red, blue, and green sub-pixels, N=3), and the number of test signal buses 36 is 6. Since 6 equals 2×3, a=1. The minimum number of test signal buses 36 connecting sub-pixels 21 of the same color is one, and the maximum number is two, such as... Figure 13 As shown, a portion of the red subpixels, such as the first color subpixel, is connected to the first test signal bus DR1, and another portion of the red subpixels, such as the fourth color subpixel, is connected to the fourth test signal bus DR2; a portion of the green subpixels, such as the second color subpixel, is connected to the second test signal bus DG1, and another portion of the green subpixels, such as the fifth color subpixel, is connected to the fifth test signal bus DG2; a portion of the blue subpixels, such as the third color subpixel, is connected to the third test signal bus DB1, and another portion of the blue subpixels, such as the sixth color subpixel, is connected to the sixth test signal bus DB2. In this case, the number of test signal leads 33 included in the lead unit 106 is (a+1)×N=6.

[0177] like Figure 10 As shown, the number of test signal leads 33 included in lead unit 106 is 3, the number of bonding pads 35 included in bonding unit 34 is 3, the arrangement period of bonding unit 34 is 33μm, and the arrangement period of lead unit 106 is 33μm.

[0178] like Figures 11 to 13 As shown, the number of test signal leads 33 included in lead unit 106 is 6, the number of bonding pads 35 included in bonding unit 34 is 3, the arrangement period of bonding unit 34 is 33μm, and the arrangement period of lead unit 106 is 66μm.

[0179] This disclosure also provides a display device, which includes a display panel as provided in any of the above embodiments.

[0180] The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Its implementation principle and beneficial effects are the same as those of the display panel provided above, and will not be repeated here.

[0181] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0182] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0183] The above provides a detailed description of a display panel and display device provided by this disclosure. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

[0184] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0185] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

[0186] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0187] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0188] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This disclosure can be implemented by means of hardware comprising a plurality of different elements and by means of a suitably programmed computer. In a unit claim enumerating a plurality of means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0189] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A display panel, wherein, It includes a display area and a border area located around the display area. The display area includes multiple sub-pixels and multiple data lines connected to the sub-pixels. The border area includes a test area and a binding area. The test area includes a plurality of test units arranged periodically along a first direction. Each test unit includes at least one switching transistor. The first terminal of the switching transistor is connected to a test signal lead, which is used to transmit a test signal. The second terminal of the switching transistor is connected to the data line. The bonding area includes a plurality of bonding units arranged periodically along the first direction, each bonding unit including at least one bonding pad, the bonding pad being connected to the data line; In the first direction, the ratio between the number of switching transistors in one arrangement cycle of the test unit and the number of bonding pads in one arrangement cycle of the bonding unit is greater than 0 and less than 2. The border area further includes an input area, which is located on the side of the test area away from the display area. The input area includes multiple test signal buses, and the extension direction of the test signal buses intersects with the extension direction of the test signal leads. The test signal bus is connected to the test signal lead, and the test signal bus is used to input the test signal to the data line of the sub-pixel of the same color through the test signal lead; The multiple test signal buses include at least one internal transmission bus, which is located in the first metal layer; The test signal lead is located in the second metal layer, and a first insulating layer is provided between the first metal layer and the second metal layer; A second insulating layer is provided on the side of the second metal layer away from the first metal layer, and a first electrode layer is provided on the side of the second insulating layer away from the first metal layer, the first electrode layer including a plurality of transition electrodes; or a third insulating layer is provided on the side of the first metal layer away from the second metal layer, and a second electrode layer is provided on the side of the third insulating layer away from the second metal layer, the second electrode layer including a plurality of transition electrodes. The test signal lead is connected to the internal transmission bus via the adapter electrode; the first part of the adapter electrode is connected to the test signal lead via a first via, and the second part of the adapter electrode is connected to the internal transmission bus via a second via.

2. The display panel according to claim 1, wherein, Within the test area, both the test signal lead and the data line extend along a second direction, which is perpendicular to the first direction. A portion of the test signal lead is multiplexed as the first terminal of the switching transistor, and a portion of the data line is multiplexed as the second terminal of the switching transistor.

3. The display panel according to claim 2, wherein, The test unit includes multiple switching transistors; Within the test unit, the first electrode of each of the switching transistors is located on the same side of the second electrode, and the orthographic projections of each of the switching transistors in the second direction do not overlap with each other. The second direction is perpendicular to the first direction. The plurality of switching transistors include a first transistor and a second transistor, and the orthographic projections of the second electrode of the first transistor and the first electrode of the second transistor in the first direction overlap.

4. The display panel according to claim 3, wherein, Within the test unit, the plurality of switching transistors also include a third transistor, which is adjacent to the second transistor, and the second electrode of the second transistor and the first electrode of the third transistor overlap in the orthographic projection of the second electrode in the first direction.

5. The display panel according to any one of claims 1 to 2, or 4, wherein, The test area and the binding area are located on opposite sides of the display area, respectively.

6. The display panel according to any one of claims 1 to 2, or 4, wherein, The test area and the binding area are located on the same side of the display area, and the binding area is located between the display area and the test area.

7. The display panel according to claim 6, wherein, The data line includes a data transmission line and a data input line. The two ends of the data transmission line are respectively connected to the second terminal of the switching transistor and the first end of the bonding pad. The second end of the bonding pad is connected to the data input line.

8. The display panel according to any one of claims 1 to 2, or 4, wherein, The switching transistor includes a channel region having a width-to-length ratio greater than or equal to 13 / 3 and less than or equal to 200 / 4.

9. The display panel according to any one of claims 1 to 2, or 4, wherein, The ratio is 1.

10. The display panel according to any one of claims 1 to 2, or 4, wherein, The orthographic projection of the first via onto the plane containing the test signal lead is within the range of the test signal lead.

11. The display panel according to any one of claims 1 to 2, or 4, wherein, The at least one internal transmission bus includes a first internal bus and a second internal bus, wherein the first internal bus is located on the side of the second internal bus closer to the display area; The arrangement direction of the first via and the second via connecting the test signal lead to the first internal bus is perpendicular to the extension direction of the first internal bus. The arrangement direction of the first and second vias connecting the test signal leads to the second internal bus is parallel to the extension direction of the second internal bus.

12. The display panel according to any one of claims 1 to 2, or 4, wherein, The multiple test signal buses also include an edge transmission bus, which is located on the side of the at least one internal transmission bus away from the display area. The edge transmission bus is located on the second metal layer, and the interconnected edge transmission buses and test signal leads are integrated into one structure.

13. The display panel according to claim 12, wherein, The multiple test signal buses include a first test signal bus, a second test signal bus, and a third test signal bus; The first test signal bus is used to input a first test signal to the data line of the first color sub-pixel, the second test signal bus is used to input a second test signal to the data line of the second color sub-pixel, and the third test signal bus is used to input a third test signal to the data line of the third color sub-pixel. The first color sub-pixel, the second color sub-pixel, and the third color sub-pixel emit different colors.

14. The display panel according to claim 13, wherein, The multiple test signal buses also include a fourth test signal bus, which is used to input the fourth test signal to the data line of the fourth color sub-pixel; The fourth color sub-pixel emits the same color as the first color sub-pixel, and the data lines connecting the fourth test signal bus and the data lines connecting the first test signal bus are alternately arranged.

15. The display panel according to claim 14, wherein, The multiple test signal buses also include a fifth test signal bus, which is used to input the fifth test signal to the data line of the fifth color sub-pixel; The fifth color sub-pixel emits the same color as the second color sub-pixel, and the data lines connecting the fifth test signal bus and the data lines connecting the second test signal bus are alternately arranged.

16. The display panel according to claim 15, wherein, The multiple test signal buses also include a sixth test signal bus, which is used to input the sixth test signal to the data line of the sixth color sub-pixel; The sixth color sub-pixel emits the same color as the third color sub-pixel, and the data lines connecting the sixth test signal bus and the data lines connecting the third test signal bus are alternately arranged.

17. The display panel according to claim 16, wherein, The input area also includes a first signal input terminal, a second signal input terminal, and a third signal input terminal; The fourth test signal bus and the first test signal bus are both connected to the first signal input terminal, the fifth test signal bus and the second test signal bus are both connected to the second signal input terminal, and the sixth test signal bus and the third test signal bus are both connected to the third signal input terminal.

18. The display panel according to any one of claims 13 to 17, wherein, Within the input area, multiple test signal leads constitute multiple lead units, and the multiple lead units are periodically arranged in the first direction; In the first direction, the ratio between the arrangement period of the lead unit and the arrangement period of the bonding unit is equal to the ratio between the number of test signal leads contained in the lead unit and the number of bonding pads contained in the bonding unit.

19. The display panel according to claim 18, wherein, The plurality of sub-pixels includes sub-pixels of N colors, wherein N is greater than or equal to 1; If the number of test signal buses is N, and the data lines of all sub-pixels of the same color are connected to the same test signal bus, then the number of test signal leads contained in the lead unit is N. If the number of test signal buses is greater than a×N and less than or equal to (a+1)×N, and the number of test signal buses connected to the data lines of all sub-pixels of the same color is greater than or equal to a and less than or equal to a+1, then the number of test signal leads contained in the lead unit is (a+1)×N, where a is a positive integer.

20. A display device, wherein, The display panel includes any one of claims 1 to 2, or 4, or 7, or 13 to 17, or 19.

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