FPGA-based implantable electrode spike signal detection system and method

Abstract

The application relates to an FPGA-based implantable electrode Spike signal detection system and method, which uses FPGA to collect brain electrical data signals transmitted by an implantable electrode chip, carries out filtering processing and automatic threshold feature extraction on the collected brain electrical data, completes the Spike extraction task, and sends the processed brain electrical data and the original data to an upper computer through a PCI-E mode. Compared with the prior art, the application adopts FPGA parallel processing data, integrates the Spike signal detection method on the FPGA, greatly reduces the real-time detection speed of the Spike, adopts a filter to pre-process the brain electrical data, can effectively retain Spike effective signals, adopts an automatic threshold feature extraction method, can adaptively extract Spike signals according to brain electrical signal fluctuations, not only reduces the power consumption of the chip, but also guarantees the accuracy of Spike signal extraction.

Description

Technical Field

[0001] This invention relates to the field of Spike signal detection technology, and in particular to an FPGA-based implantable electrode Spike signal detection system and method. Background Technology

[0002] During physical movement, the brain generates neuronal action potentials (Spike signals), and the detection of Spike signals is of great significance in electroencephalogram (EEG) signal research. Currently, Spike signal detection mainly employs wavelet transform, template comparison, and threshold comparison methods, and is performed using a PC. This is because PCs can use complex algorithms to calculate a large number of Spike signals. However, this method is prone to severe signal lag because the transmission bandwidth from the EEG acquisition electrodes to the PC receiver is high, thus requiring specialized devices to meet the high bandwidth requirements.

[0003] Therefore, integrated methods for detecting spike signals are a current research hotspot. These methods primarily involve integrating detection algorithms into front-end implanted chips to ensure good real-time performance. However, limitations imposed by chip size and power consumption necessitate the use of relatively simple algorithms. This inevitably leads to lower spike signal detection accuracy, failing to meet the requirements of large-scale and high-precision acquisition in experiments. Furthermore, simple algorithms often require manual parameter input, hindering automated processing. Therefore, improving detection accuracy and enhancing automation are pressing issues that need to be addressed in the field of integrated detection. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the existing technology and provide an implantable electrode Spike signal detection system and method based on FPGA (Field-Programmable Gate Array), which can realize automatic data processing on the basis of real-time detection and effectively improve detection accuracy.

[0005] The objective of this invention can be achieved through the following technical solution: an FPGA-based implantable electrode Spike signal detection system, comprising an implantable electrode acquisition chip, an FPGA, and a host computer connected in sequence. The FPGA internally encapsulates an IIC data parsing module, a data splitting module, a data encapsulation module, a first FIFO (First Input First Output) cache module, and a DDR3 (double-data-rate three) cache module connected in sequence. The data encapsulation module is also connected to a filter. The filter is connected to the DDR3 cache module through a threshold extraction module and a second FIFO cache module. The IIC data parsing module is used to acquire valid EEG data from the implantable electrode acquisition chip.

[0006] The data splitting module is used to deserialize valid EEG data from serial data.

[0007] The data encapsulation module is used to encapsulate the deserialized data to obtain the original data;

[0008] The first FIFO cache module is used to temporarily cache the original data;

[0009] The filter is used to preprocess the raw data to obtain processed data;

[0010] The threshold extraction module is used to extract valid Spike data from the processed data;

[0011] The second FIFO cache module is used to temporarily cache valid Spike data;

[0012] The DDR3 cache module is used to cache raw data and valid Spike data, and then sends the cached data to the host computer.

[0013] Furthermore, the implantable electrode acquisition chip is connected to the FPGA via the IIC communication protocol.

[0014] Furthermore, the FPGA communicates with the host computer via the PCI-E communication protocol.

[0015] Furthermore, the filter is specifically a Chebyshev filter with a fixed frequency band.

[0016] A method for detecting Spike signals in implanted electrodes based on FPGA includes the following steps:

[0017] S1. Implantable electrode acquisition chip acquires EEG data in real time and transmits it to FPGA;

[0018] S2. The FPGA receives valid EEG data and performs data deserialization and data encapsulation processing on the valid EEG data in sequence to obtain the original data.

[0019] S3. Parallel processing of the raw data: On the one hand, the raw data is written to the first FIFO cache module and the DDR3 cache module in sequence; on the other hand, the raw data is preprocessed, and then the Spike valid data is extracted from the processed data using an automatic threshold extraction algorithm, and then written to the second FIFO cache module and the DDR3 cache module in sequence.

[0020] S4. According to the preset data transmission rules, the DDR3 cache module transmits the original data and Spike valid data to the host computer.

[0021] Furthermore, step S2 specifically includes the following steps:

[0022] S21. Detect whether the EEG data transmitted to the FPGA is STAT and STOP signals. If so, start receiving valid 8-channel EEG data. Otherwise, consider the currently transmitted EEG data as invalid data and do not receive the data.

[0023] S22. The received 8-channel EEG data are sequentially deserialized and encapsulated to obtain the original data.

[0024] Further, the specific process of step S21 is as follows: a valid IIC data signal is preset. When the transmitted EEG data is detected to be STAT and STOP signals, the valid IIC data signal is pulled high, indicating that the currently transmitted 8-channel EEG data is valid EEG data and each channel of the 8-channel EEG data is 16-bit. Otherwise, it is not considered as valid EEG data.

[0025] When a valid signal is received, the next 16 bits of the STAT signal are used as the first frame data of the first channel. The first frame data of the first channel is temporarily buffered. The second 16 bits of data is the first frame data of the second channel. The first frame data of the second channel is temporarily buffered. This continues until the eighth 16 bits of data. The first frame data of the eighth channel is temporarily buffered. When the first frame data of the eight channels has been received, the IIC data valid signal is pulled low.

[0026] Furthermore, the preprocessing of the raw data in step S3 specifically involves filtering out noise signals and retaining valid EEG signals.

[0027] Furthermore, the specific process of preprocessing the raw data in step S3 is as follows:

[0028] A1. The first frame of data for each channel is input to the zero-point module of the filter. This zero-point module has a 16-bit input and a 26-bit output. Then, the lower 16 bits of the first frame of data are directly output. The specific formula is as follows:

[0029] b1*y(1)=a1*x(1)

[0030] Where y(1) is the output data corresponding to the first frame data, x(1) is the input first frame data, and b1 and a1 are both set coefficients;

[0031] A2. Input y(1) into the pole module, which has 16-bit input and 26-bit output;

[0032] A3. The second frame of data for each channel is input into the zero-point module of the filter, then subtracted from the pole-point module, and the lower 16 bits are output. The specific formula is as follows:

[0033] b1*y(2)=a1*x(2)+a2*x(1)-b2*y(1)

[0034] Where y(2) is the output data corresponding to the second frame data, x(2) is the input second frame data, and b1, a1, b2 and a2 are all set coefficients;

[0035] A4. The third frame of data for each channel is input into the zero-point module of the filter, then subtracted from the pole-point module, and the lower 16 bits are output. The specific formula is as follows:

[0036] b1*y(3)=a1*x(3)+a2*x(2)+a3*x(1)-b2*y(2)-b3*y(1)

[0037] Where y(3) is the output data corresponding to the third frame data, x(3) is the input third frame data, and b1, a1, b2, a2, b3 and a3 are all set coefficients;

[0038] A5. The fourth frame of data from each channel is input to the zero-point module of the filter, then subtracted from the pole-point module, and the lower 16 bits are output. The specific formula is as follows:

[0039] b1*y(4)=a1*x(4)+a2*x(3)+a3*x(2)+a4*x(1)-b2*y(3)-b3*y(2)-b4*y(1)

[0040] Where y(4) is the output data corresponding to the fourth frame data, x(4) is the input fourth frame data, and b1, a1, b2, a2, b3, a3, b4 and a4 are all set coefficients;

[0041] A6. The fifth frame of data for each channel is fed into Chebyshev's zero-point module, then subtracted from the pole-point module, and the lower 16 bits are output. The specific formula is as follows:

[0042] b1*y(5)=a1*x(5)+a2*x(4)+a3*x(3)+a4*x(2)-b2*y(4)-b3*y(3)-b4*y(2)

[0043] Where y(5) is the output data corresponding to the fifth frame data, x(5) is the fifth frame data, b1, a1, b2, a2, b3, a3, b4 and a4 are all set coefficients, and the data after the fifth frame of each channel are calculated according to the above formula.

[0044] Furthermore, the specific process of extracting valid Spike data from the processed data in step S3 is as follows:

[0045] B1. When the first frame of preprocessed data is received, the absolute value of the first frame of preprocessed data is processed, and then subtracted from the first frame of preprocessed data. This subtracted data is then multiplied by a set first threshold coefficient. The resulting data is added to the first frame of preprocessed data and multiplied by a second threshold coefficient to obtain the corresponding threshold. All threshold calculations are performed on the current frame. The specific formula is as follows:

[0046] th=β(y+α(|y|-y))

[0047] Where th is the threshold, α is the first threshold coefficient, β is the second threshold coefficient, and y is the preprocessed data of the current frame;

[0048] B2. After receiving the first 10 frames of preprocessed data, the threshold extraction module is enabled. When the eleventh frame of preprocessed data is detected to be below the corresponding threshold, the first frame of preprocessed data is changed to 0 and output to the second FIFO buffer module.

[0049] When the eleventh frame of preprocessed data reaches the corresponding threshold, the first frame of data is retained and output to the second FIFO buffer module, and then a Spike valid signal is activated to pull it high.

[0050] B3. After the first frame of preprocessed data is output, the subsequent preprocessed data will be shifted forward, that is, the second frame of preprocessed data becomes the first frame of preprocessed data. If the current Spike valid signal is low, return to step B1 for threshold detection. If the current Spike valid signal is high, the first 10 frames of data, the 11th frame of data and the subsequent 33 frames of preprocessed data do not need threshold detection and are directly output to the second FIFO buffer module. After outputting 44 frames of data, pull the Spike valid signal low and return to step B1 to continue threshold detection.

[0051] Compared with the prior art, the present invention has the following advantages:

[0052] I. This invention utilizes an FPGA to encapsulate a sequentially connected IIC data parsing module, a data splitting module, a data encapsulation module, a first FIFO buffer module, and a DDR3 buffer module. The data encapsulation module is also connected to a filter, which is connected to the DDR3 buffer module via a threshold extraction module and a second FIFO buffer module. The IIC data parsing module acquires valid EEG data from an implanted electrode acquisition chip; the data splitting module deserializes the valid EEG data; the data encapsulation module encapsulates the deserialized data to obtain the original data; the first FIFO buffer module temporarily buffers the original data; the filter preprocesses the original data to obtain processed data; the threshold extraction module extracts valid Spike data from the processed data; the second FIFO buffer module temporarily buffers the valid Spike data; and the DDR3 buffer module buffers both the original data and the valid Spike data before sending the buffered data to a host computer. This fully leverages the parallel processing capabilities of the FPGA for EEG data and integrates the Spike signal detection method onto the FPGA, significantly reducing the real-time speed of Spike detection and meeting the high real-time requirements of Spike detection.

[0053] Second, this invention integrates a Chebyshev filter and an automatic threshold feature extraction algorithm onto an FPGA chip. The FPGA is used to extract Spike signals, and the Chebyshev filter preprocesses the EEG data, effectively preserving valid Spike signals. The automatic threshold feature extraction method adapts to EEG signal fluctuations to extract Spike signals. This not only effectively reduces chip power consumption but also ensures the accuracy of Spike signal extraction. Attached Figure Description

[0054] Figure 1 This is a schematic diagram of the system structure of the present invention;

[0055] Figure 2 A schematic diagram illustrating the process of saving the original data during FPGA execution;

[0056] Figure 3 A schematic diagram illustrating the data preprocessing process performed on the FPGA;

[0057] Figure 4 It uses the IIC data protocol format;

[0058] Figure 5 It is in PCI-E data protocol format;

[0059] The markings in the diagram are as follows: 1. Implantable electrode acquisition chip; 2. FPGA; 3. IIC data parsing module; 4. Data splitting module; 5. Data encapsulation module; 6. First FIFO cache module; 7. DDR3 cache module; 8. Filter; 9. Threshold extraction module; 10. Second FIFO cache module; 11. Host computer. Detailed Implementation

[0060] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0061] Example

[0062] like Figure 1 As shown, an FPGA-based implantable electrode Spike signal detection system includes an implantable electrode acquisition chip 1, an FPGA 2, and a host computer 11 connected in sequence. The FPGA 2 internally encapsulates an IIC data parsing module 3, a data splitting module 4, a data encapsulation module 5, a first FIFO buffer module 6, and a DDR3 buffer module 7 connected in sequence. The data encapsulation module 5 is also connected to a filter 8. The filter 8 is connected to the DDR3 buffer module 7 through a threshold extraction module 9 and a second FIFO buffer module 10. The IIC data parsing module 3 is used to acquire valid EEG data from the implantable electrode acquisition chip 1.

[0063] Data splitting module 4 is used to deserialize valid EEG data from serial data.

[0064] Data encapsulation module 5 is used to encapsulate the deserialized data to obtain the original data;

[0065] The first FIFO cache module 6 is used to temporarily cache raw data;

[0066] Filter 8 is used to preprocess the raw data to obtain processed data;

[0067] Threshold extraction module 9 is used to extract valid Spike data from the processed data;

[0068] The second FIFO cache module 10 is used to temporarily cache valid Spike data;

[0069] The DDR3 cache module 7 is used to cache raw data and valid Spike data, and sends the cached data to the host computer 11.

[0070] In practical applications, the implantable electrode acquisition chip 1 communicates with FPGA 2 via the IIC communication protocol, and FPGA 2 communicates with the host computer 11 via the PCI-E communication protocol. That is, the implantable electrode acquisition chip 1 transmits EEG data to FPGA 2 via the IIC communication protocol, and FPGA 2 sends the processed data and the original data to the host computer 11 (e.g., a PC) via the PCI-E interface for subsequent Spike processing.

[0071] In addition, in this embodiment, filter 8 adopts a low-order Chebyshev filter, selects a fixed frequency band, effectively filters noise signals, and retains valid EEG signals.

[0072] Using the above system, a Spike signal detection method for implantable electrodes based on FPGA is implemented, including:

[0073] S1. Implantable electrode acquisition chip acquires EEG data in real time and transmits it to FPGA;

[0074] S2. The FPGA receives valid EEG data and performs data deserialization and data encapsulation processing on the valid EEG data in sequence to obtain the original data.

[0075] S3. Parallel processing of the raw data: On the one hand, the raw data is written to the first FIFO cache module and the DDR3 cache module in sequence; on the other hand, the raw data is preprocessed, and then the Spike valid data is extracted from the processed data using an automatic threshold extraction algorithm, and then written to the second FIFO cache module and the DDR3 cache module in sequence.

[0076] S4. According to the preset data transmission rules, the DDR3 cache module transmits the original data and Spike valid data to the host computer.

[0077] The specific application process of this embodiment is mainly divided into the original data saving process (such as...). Figure 2 (as shown) and EEG data preprocessing workflow (such as...) Figure 3 As shown), the original data saving process is jointly implemented by the IIC data parsing module 3, the data splitting module 4, the data encapsulation module 5, the first FIFO cache module 6, and the DDR3 cache module 7. The IIC data parsing module 3 will receive valid IIC data (such as...) Figure 4 (As shown) The data is sent to the data splitting module 4 for channel data deserialization. The deserialized data is then sent to the data encapsulation module 5 to encapsulate the 8-channel data by channel. The encapsulated data is temporarily cached by channel in the first FIFO cache module 6, and finally cached in the DDR3 cache module 7.

[0078] In specific implementation, FPGA2 receives data from the implanted electrode acquisition chip 1 using the IIC protocol. The IIC data parsing module 3 considers the data valid if it acquires the start and end bits; otherwise, it considers it invalid. When the data is considered valid, the IIC data parsing module 3 sends it to the data deserializing module 4 to deserialize the 8-channel serial data. The deserialized data is then sent to the data encapsulation module 5, which encapsulates the data according to each channel. The data encapsulation module 5 then temporarily buffers the encapsulated data in the first FIFO buffer module 6, and finally in the DDR3 buffer module 7. The data is then transmitted via PCI-E (data format as shown in the image). Figure 5 (As shown) is sent to the host computer 11.

[0079] The EEG data preprocessing process is jointly implemented by filter module 8, threshold extraction module 9, second FIFO cache module 10 and DDR3 cache module 7. Filter module 8 sends the preprocessed data to threshold extraction module 9 to extract the Spike valid signal. The extracted data is sent to second FIFO cache module 10 for temporary caching and finally cached in DDR3 cache module 7. Then it is sent to host computer 11 through PCI-E.

[0080] In practice, the encapsulated data is transmitted to filter module 8 for preprocessing. The input data is 16 bits, and the processed output data is also 16 bits, consistent with the original data bit width. The preprocessed data is then sent to threshold extraction module 9. Threshold extraction module 9 calculates a variable threshold in real time based on an automatic threshold algorithm. When the preprocessed data reaches the threshold, valid data is retained; otherwise, the data is changed to 0. The extracted data is temporarily cached in the second FIFO cache module 10, and finally cached in the DDR3 cache module 7. Then, it is transmitted via PCI-E (data format as shown in the image). Figure 5 (As shown) is sent to the host computer 11.

[0081] This enables a Spike signal detection process:

[0082] (1) Implantable electrode acquisition chip 1 acquires EEG data in real time and sends it to FPGA 2 via IIC communication protocol. When IIC data parsing module 3 detects that the IIC communication data is STAT and STOP signals, it starts to receive 8-channel EEG data, where each channel of the 8-channel EEG data is 16-bit.

[0083] (2) The received 8-channel EEG data needs to be deserialized by the channel data splitting module 4 and the encapsulation module 5, and then encapsulated according to the data of each channel. The specific steps of EEG data splitting and encapsulation are as follows:

[0084] (2-1) When the IIC data parsing module 3 receives data as STAT and STOP signals, it will set an IIC data valid signal. If the signal is pulled high, it proves that the 8-channel data is valid; otherwise, it is not considered valid data.

[0085] (2-2) When the IIC data parsing module 3 receives a valid signal, the next 16-bit data of STAT becomes the first frame data of the first channel. The first frame data of the first channel is temporarily buffered by variables. The second 16-bit data becomes the first frame data of the second channel. The first frame data of the second channel is temporarily buffered by variables. This continues until the eighth 16-bit data, when the first frame data of the eighth channel is temporarily buffered by variables.

[0086] (2-3) When the first frame of data from the 8 channels is received, the IIC valid signal is pulled low;

[0087] (3) The encapsulated EEG data is temporarily cached by the first FIFO cache module 6 with a channel writing depth of 64 bits. While caching, the first FIFO cache module 6 writes the data into the DDR3 cache module 7 to cache the original data. Finally, the original data will be stored in the DDR3 cache module 7.

[0088] (4) After step (2), the raw data of each channel is sent to the filter module 8 for preprocessing of the EEG data. The specific preprocessing process is as follows:

[0089] (4-1) The first frame of data for each channel is fed into Chebyshev's zero-point module. The zero-point module has a 16-bit input and a 26-bit output. Then, the lower 16 bits of the first frame of data are directly taken and output. The specific formula is as follows:

[0090] b1*y(1)=a1*x(1)

[0091] (4-2) Then the output y(1) is fed into the pole module, which has 16-bit input and 26-bit output;

[0092] (4-3) The second frame of data for each channel is fed into Chebyshev's zero-point module, then subtracted from the pole-point module, and the lower 16 bits are output. The specific formula is as follows:

[0093] b1*y(2)=a1*x(2)+a2*x(1)-b2*y(1)

[0094] (4-4) The third frame of data for each channel is fed into Chebyshev's zero-point module, then subtracted from the pole-point module, and the lower 16 bits are output. The specific formula is as follows:

[0095] b1*y(3)=a1*x(3)+a2*x(2)+a3*x(1)-b2*y(2)-b3*y(1)

[0096] (4-5) The fourth frame of data for each channel is fed into Chebyshev's zero-point module, then subtracted from the pole-point module, and the lower 16 bits are output. The specific formula is as follows:

[0097] b1*y(4)=a1*x(4)+a2*x(3)+a3*x(2)+a4*x(1)-b2*y(3)-b3*y(2)-b4*y(1)

[0098] (4-6) The fifth frame of data for each channel is fed into Chebyshev's zero-point module and then subtracted from the pole-point module. The lower 16 bits are then taken as the output. The specific formula is as follows:

[0099] b1*y(5)=a1*x(5)+a2*x(4)+a3*x(3)+a4*x(2)-b2*y(4)-b3*y(3)-b4*y(2)

[0100] (4-7) The data after the fifth frame of each channel are calculated using the formula in step (4-6) above;

[0101] (5) The preprocessed data is directly sent to the Spike threshold extraction module 9, and Spike extraction is performed based on the threshold obtained from the automatic threshold calculation formula. The specific threshold extraction process is as follows:

[0102] (5-1) When the first frame of preprocessed data is received, the absolute value of the first frame data is processed and subtracted from the first frame data, then multiplied by a coefficient. The resulting data is added to the first frame data and multiplied by another coefficient to obtain the threshold. The threshold calculation is based on the current frame. The specific formula is as follows:

[0103] th=β(y+α(|y|-y))

[0104] (5-2) After receiving the first 11 frames of preprocessed data, the Spike threshold extraction module 9 is enabled. When the eleventh frame data is detected to be below the threshold, the first frame data becomes 0 and is output to the second FIFO buffer module 10. When the eleventh frame reaches the threshold, the first frame data is retained and output to the second FIFO buffer module 10, which will enable a Spike valid signal to go high.

[0105] (5-3) After the first frame of data is output, the subsequent data will be shifted forward. The second frame of data becomes the first frame of data. If the Spike valid signal is low, threshold detection is required. If the Spike valid signal is high, the first 10 frames of data, the 11th frame of data, and the subsequent 33 frames of data do not require threshold detection and are directly output. After 44 frames of data are output, the Spike valid signal is pulled low and threshold detection continues.

[0106] (6) The extracted Spike data is written to the second FIFO cache module 10 with a depth of 64 bits to temporarily cache the valid Spike data. While caching, the second FIFO cache module 10 writes the valid Spike data into the DDR3 cache module 7.

[0107] (7) When the raw data of each channel cached in the DDR3 cache module 7 reaches 64 bits, it is sent to the host computer 11 via PCI-E.

[0108] In summary, this technical solution integrates EEG data filtering algorithms and Spike threshold extraction algorithms on an FPGA and transmits the data to a host computer via a PCI-E interface to implement a Spike signal detection scheme. Leveraging the parallel processing capabilities of the FPGA for EEG data, the integration of the Spike signal detection method onto the FPGA significantly reduces the real-time detection speed of Spike signals, ensuring that a single frame of data is processed within 100ms, thus meeting the high real-time requirements of Spike detection. Furthermore, the low-order Chebyshev filter and simplified automatic threshold extraction algorithm used in this system reduce chip power consumption. Through comparison with various filters and Spike signal extraction algorithms, the optimal algorithm was determined, ensuring the accuracy of Spike signal extraction.

Claims

1. A Spike signal detection method for implantable electrodes based on FPGA, applied to an FPGA-based Spike signal detection system for implantable electrodes, characterized in that, The system includes an implantable electrode acquisition chip (1), an FPGA (2), and a host computer (11) connected in sequence. The FPGA (2) is internally encapsulated with an IIC data parsing module (3), a data splitting module (4), a data encapsulation module (5), a first FIFO cache module (6), and a DDR3 cache module (7) connected in sequence. The data encapsulation module (5) is also connected to a filter (8). The filter (8) is connected to the DDR3 cache module (7) through a threshold extraction module (9) and a second FIFO cache module (10). The IIC data parsing module (3) is used to acquire valid EEG data from the implantable electrode acquisition chip (1). The data splitting module (4) is used to deserialize valid EEG data. The data encapsulation module (5) is used to encapsulate the deserialized data to obtain the original data; The first FIFO cache module (6) is used to temporarily cache the original data; The filter (8) is used to preprocess the original data to obtain processed data; The threshold extraction module (9) is used to extract valid Spike data from the processed data; The second FIFO cache module (10) is used to temporarily cache valid Spike data; The DDR3 cache module (7) is used to cache the original data and valid Spike data, and sends the cached data to the host computer (11); The detection method of the above system includes the following steps: S1. Implantable electrode acquisition chip acquires EEG data in real time and transmits it to FPGA; S2. The FPGA receives valid EEG data and performs data deserialization and data encapsulation processing on the valid EEG data in sequence to obtain the original data. S3. Parallel processing of the raw data: On the one hand, the raw data is written to the first FIFO cache module and the DDR3 cache module in sequence; on the other hand, the raw data is preprocessed, and then the Spike valid data is extracted from the processed data using an automatic threshold extraction algorithm, and then written to the second FIFO cache module and the DDR3 cache module in sequence. S4. According to the preset data transmission rules, the DDR3 cache module transmits the original data and Spike valid data to the host computer; Step S2 specifically includes the following steps: S21. Detect whether the EEG data transmitted to the FPGA is STAT and STOP signals. If so, start receiving valid 8-channel EEG data. Otherwise, consider the currently transmitted EEG data as invalid data and do not receive the data. S22. The received 8-channel EEG data are sequentially deserialized and encapsulated to obtain the original data; The specific process of extracting valid Spike data from the processed data in step S3 is as follows: B1. When the first frame of preprocessed data is received, the absolute value of the first frame of preprocessed data is processed, and then subtracted from the first frame of preprocessed data. This subtracted data is then multiplied by a set first threshold coefficient. The resulting data is added to the first frame of preprocessed data and multiplied by a second threshold coefficient to obtain the corresponding threshold. All threshold calculations are performed on the current frame. The specific formula is as follows: th=β(y+α(|y|-y)) Where th is the threshold, α is the first threshold coefficient, β is the second threshold coefficient, and y is the preprocessed data of the current frame; B2. After receiving the first 10 frames of preprocessed data, the threshold extraction module is enabled. When the eleventh frame of preprocessed data is detected to be below the corresponding threshold, the first frame of preprocessed data is changed to 0 and output to the second FIFO buffer module. When the eleventh frame of preprocessed data reaches the corresponding threshold, the first frame of data is retained and output to the second FIFO buffer module, and then a Spike valid signal is activated to pull it high. B3. After the first frame of preprocessed data is output, the subsequent preprocessed data will be shifted forward, that is, the second frame of preprocessed data becomes the first frame of preprocessed data. If the current Spike valid signal is low, return to step B1 for threshold detection. If the current Spike valid signal is high, the first 10 frames of data, the 11th frame of data and the subsequent 33 frames of preprocessed data do not need threshold detection and are directly output to the second FIFO buffer module. After outputting 44 frames of data, pull the Spike valid signal low and return to step B1 to continue threshold detection.

2. The Spike signal detection method for implantable electrodes based on FPGA according to claim 1, characterized in that, The implantable electrode acquisition chip (1) is connected to the FPGA (2) via the IIC communication protocol.

3. The Spike signal detection method for implantable electrodes based on FPGA according to claim 1, characterized in that, The FPGA (2) is connected to the host computer (11) via the PCI-E communication protocol.

4. The Spike signal detection method for implantable electrodes based on FPGA according to claim 1, characterized in that, The filter (8) is specifically a Chebyshev filter with a fixed frequency band.

5. The Spike signal detection method for implantable electrodes based on FPGA according to claim 1, characterized in that, The specific process of step S21 is as follows: a valid IIC data signal is preset. When the transmitted EEG data is detected to be STAT and STOP signals, the valid IIC data signal is pulled high, indicating that the currently transmitted 8-channel EEG data is valid EEG data and each channel of the 8-channel EEG data is 16-bit. Otherwise, it is not considered as valid EEG data. When a valid signal is received, the next 16 bits of the STAT signal are used as the first frame data of the first channel. The first frame data of the first channel is temporarily buffered. The second 16 bits of data is the first frame data of the second channel. The first frame data of the second channel is temporarily buffered. This continues until the eighth 16 bits of data. The first frame data of the eighth channel is temporarily buffered. When the first frame data of the eight channels has been received, the IIC data valid signal is pulled low.

6. The Spike signal detection method for implantable electrodes based on FPGA according to claim 1, characterized in that, The preprocessing of the raw data in step S3 specifically involves filtering out noise signals and retaining valid EEG signals.

7. The method for detecting Spike signals of an implantable electrode based on FPGA according to claim 6, characterized in that, The specific process of preprocessing the raw data in step S3 is as follows: A1. The first frame of data for each channel is input to the zero-point module of the filter. This zero-point module has a 16-bit input and a 26-bit output. Then, the lower 16 bits of the first frame of data are directly output. The specific formula is as follows: b1*y(1)=a1*x(1) Where y(1) is the output data corresponding to the first frame data, x(1) is the input first frame data, and b1 and a1 are both set coefficients; A2. Input y(1) into the pole module, which has 16-bit input and 26-bit output; A3. The second frame of data for each channel is input into the zero-point module of the filter, then subtracted from the pole-point module, and the lower 16 bits are output. The specific formula is as follows: b1*y(2)=a1*x(2)+a2*x(1)-b2*y(1) Where y(2) is the output data corresponding to the second frame data, x(2) is the input second frame data, and b1, a1, b2 and a2 are all set coefficients; A4. The third frame of data for each channel is input into the zero-point module of the filter, then subtracted from the pole-point module, and the lower 16 bits are output. The specific formula is as follows: b1*y(3)=a1*x(3)+a2*x(2)+a3*x(1)-b2*y(2)-b3*y(1) Where y(3) is the output data corresponding to the third frame data, x(3) is the input third frame data, and b1, a1, b2, a2, b3 and a3 are all set coefficients; A5. The fourth frame of data from each channel is input to the zero-point module of the filter, then subtracted from the pole-point module, and the lower 16 bits are output. The specific formula is as follows: b1*y(4)=a1*x(4)+a2*x(3)+a3*x(2)+a4*x(1)-b2*y(3)-b3*y(2)-b4*y(1) Where y(4) is the output data corresponding to the fourth frame data, x(4) is the input fourth frame data, and b1, a1, b2, a2, b3, a3, b4 and a4 are all set coefficients; A6. The fifth frame of data for each channel is fed into Chebyshev's zero-point module, then subtracted from the pole-point module, and the lower 16 bits are output. The specific formula is as follows: b1*y(5)=a1*x(5)+a2*x(4)+a3*x(3)+a4*x(2)-b2*y(4)-b3*y(3)-b4*y(2) Where y(5) is the output data corresponding to the fifth frame data, x(5) is the fifth frame data, b1, a1, b2, a2, b3, a3, b4 and a4 are all set coefficients, and the data after the fifth frame of each channel are calculated according to the above formula.

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