Wafer level system in package test structure and method of operation
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI ARTIFICIAL INTELLIGENCE INNOVATION CENT
- Filing Date
- 2023-04-13
- Publication Date
- 2026-07-24
Smart Images
Figure CN116736060B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a test structure for a wafer-level system and its operation method. Background Technology
[0002] Semiconductor testing spans the entire process of semiconductor design, manufacturing, packaging, and application, and is a crucial step in determining or evaluating the functionality and performance of integrated circuits. From the initial chip design that meets specific functional requirements, through wafer fabrication and packaging, before the final product is formed, it is necessary to test whether the product conforms to various specifications. Semiconductor testing can be divided into three categories according to the production process: verification testing, wafer testing, and packaging testing. Wafer testing, also known as front-end testing, targets the entire undivided wafer and aims to monitor front-end process yield and reduce back-end packaging costs. After wafer testing is completed, KGD (Know-Good Die) dicing and separation are performed.
[0003] In wafer testing, individual dies can be tested, or the entire wafer can be treated as a high-density computing system for wafer-level testing. Wafer-level testing can employ boundary scan JTAG (Joint Test Action Group) technology. JTAG technology tests the device and its peripheral circuitry through BSCs (Boundary Scan Cells) located between the device's input / output pins and the core circuitry. It can be used to determine whether interconnects have open circuits, short circuits, or fixed logic faults. Currently, most large-scale IC devices provide JTAG interfaces, allowing multiple JTAG test ports to be connected serially, with the daisy-chain structure being the most common.
[0004] Daisy-chaining, also known as daisy-chaining, is a one-dimensional extension structure where only adjacent devices can communicate directly; non-adjacent devices must communicate through other devices to avoid loops. However, this also makes it difficult for daisy-chain-based JTAG test structures to account for potential manufacturing defects in the test circuitry itself. This can lead to a loss of control over the die downstream of the defect, resulting in false positives in yield testing. Summary of the Invention
[0005] To address some or all of the problems in the prior art, the first aspect of this invention provides a wafer-level system test structure, which controls the TAPs of dies in a wafer through a TAP controller to form a two-dimensional test network, wherein each die includes:
[0006] The first test access port TAP can be communicatively connected to the third test access port TAP in the previous level die in the Y direction, forming a Y-direction test chain;
[0007] The second test access port (TAP) is communicatively connected in the X-axis to the third test access port (TAP) in the next-level die, forming an X-axis test chain, wherein the X-axis is orthogonal to the Y-axis; and
[0008] The third test access port TAP can be communicatively connected to the first test access port TAP in the Y direction, and can also be communicatively connected to the second test access port TAP in the X direction.
[0009] Furthermore, the TAPs within the grain are connected via a JTAG bus.
[0010] Furthermore, TAPs from different die types are connected via a JTAG bus.
[0011] Furthermore, the third test access port TAP includes:
[0012] The first bus multiplexer has its first input connected to the first test access port TAP in the Y direction of this die, and its second input connected to the second test access port TAP in the previous die in the X direction.
[0013] A first bus demultiplexer is disposed at the output terminal of the first bus multiplexer. Its first output is connected to the first test access port TAP of the next stage die in the Y direction, and its second output is connected to the second test access port TAP in the current die in the X direction.
[0014] The second bus multiplexer has its first input connected in the X-axis direction to the second test access port TAP in this die, and its second input connected in the Y-axis direction to the first test access port TAP in the next stage die; and
[0015] The second bus demultiplexer is located at the output of the second bus multiplexer. Its first output is connected to the second test access port TAP of the previous stage die in the X direction, and its second output is connected to the first test access port TAP in this die in the Y direction.
[0016] Based on the test structure described above, a second aspect of the present invention provides a test method for a wafer-level system, comprising:
[0017] Based on the testing requirements, control the link path of the third test access port TAP to form at least one test chain in a specified direction, with each test chain being independent of the others.
[0018] Furthermore, the testing method includes:
[0019] When Y-axis testing is required, the TAP controller enables the first test access port TAP to communicate with the third test access port TAP within its own die and the first test access port TAP within the next level die, forming a Y-axis test chain.
[0020] Furthermore, the testing method includes:
[0021] When X-axis testing is required, the TAP controller enables the third test access port TAP to communicate with the second test access port TAP within its own die and the third test access port TAP within the next level die, forming an X-axis test chain.
[0022] Furthermore, the testing method also includes:
[0023] Once a defect is detected, the link path of the third test access port (TAP) in the die after the defect is switched, and a test chain in another direction is used for the die after the defect.
[0024] This invention provides a wafer-level system test structure and method that utilizes the internal test access port (TAP) and multiplexing / demultiplexing circuitry to form a two-dimensional grid deployment. On one hand, it provides redundant paths, enabling effective testing of the die's functionality and efficient wafer screening even when manufacturing defects occur in the test structure itself, thus improving yield compared to existing solutions. On the other hand, compared to one-dimensional extended structures, the two-dimensional structure allows for flexible selection of Y-axis or X-axis test chains according to the test objectives, improving test efficiency and reducing test costs. Attached Figure Description
[0025] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.
[0026] Figure 1 This diagram illustrates a test structure of a wafer-level system according to an embodiment of the present invention.
[0027] Figure 2 A schematic diagram of the structure of the third test access port (TAP) according to an embodiment of the present invention is shown; and
[0028] Figures 3a-3c This diagram illustrates a wafer-level testing structure based on an embodiment of the present invention for wafer-level testing. Detailed Implementation
[0029] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or in conjunction with other alternatives and / or additional methods or components. In other instances, well-known structures or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific numbers and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.
[0030] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.
[0031] It should be noted that the embodiments of the present invention are described with specific sequential method steps; however, this is only for illustrating the specific embodiment and not for limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.
[0032] As a one-dimensional extended structure, daisy-chain technology requires non-adjacent devices to be relayed through other devices. This leads to a loss of control over the subsequent path if the test circuit itself has defects, resulting in false negatives in yield. To avoid this situation and effectively improve product yield, this invention proposes a two-dimensional grid deployment. When a manufacturing defect occurs in the test structure itself, the test link can be switched, thus still effectively performing chip functional testing and screening. Compared to existing daisy-chain JTAG systems, this significantly improves product yield.
[0033] The test structure and method of this invention are implemented based on the JTAG protocol. After the test link is formed, the specific test operations and principles are basically the same as those in the prior art, and therefore will not be repeated in this invention. The following terms are mainly involved in the embodiments of this invention:
[0034] TAP, or Test Access Port, is a general-purpose port that allows access to all data registers (DR) and instruction registers (IR) provided by the chip (die), enabling testing and debugging of the die. The entire TAP is controlled by the TAP Controller.
[0035] The signals transmitted in the JTAG bus include:
[0036] TMS: Test mode selection signal, input;
[0037] TCK: Test clock signal, input;
[0038] TDI: Test data input signal, input;
[0039] TDO: Test data output signal, output;
[0040] (n)TRST: Internal TAP controller reset signal, input, optional signal. If not set, the TAPController can be reset via TMS;
[0041] STCK: Clock return signal, optional; and
[0042] DBGRQ: Control signal for the working status on the target board; this is an optional signal.
[0043] Y-direction refers to the longitudinal direction; and
[0044] X-direction refers to the horizontal direction.
[0045] The present invention will be further described below with reference to the accompanying drawings of the embodiments.
[0046] Figure 1 A schematic diagram of a test structure for a wafer-level system according to an embodiment of the present invention is shown. Figure 1 As shown, a wafer-level system test structure is presented, which uses a TAP controller to control the connection direction of the TAPs of the dies in the wafer, forming a two-dimensional test network. Figure 1As shown, each die 100 in the wafer includes three test access ports (TAPs). The first test access port TAP 101 can form a Y-axis test chain with the third test access port TAP 103, where the first test access port TAP acts as the master TAP and the third test access port TAP acts as the slave TAP. The second test access port TAP 102 can form an X-axis test chain with the third test access port TAP 103, where the third test access port TAP acts as the master TAP and the second test access port TAP acts as the slave TAP. The X-axis is orthogonal to the Y-axis, and the slave TAP is controlled by the master TAP and can control the master TAP in the next die. Therefore, in the overall test structure, the first test access port TAP 101 is configured to communicatively connect to the third test access port TAP in the previous die in the Y-axis, forming a Y-axis test chain, while the second test access port TAP 102 is communicatively connected to the third test access port TAP in the next die in the X-axis, forming an X-axis test chain. Meanwhile, to enable test chains in different directions, the third test access port TAP 103 should have a multiplexing function, allowing it to be communicatively connected to the first test access port TAP 101 in the same die in the Y direction, or communicatively connected to the second test access port TAP 102 in the same die in the X direction, as needed. It should be understood that the figures are merely examples; in practical applications, the number of dies in each direction of the wafer can be more or less.
[0047] Since this invention is based on the JTAG protocol, in the embodiments of this invention, the first test access port (TAP) and the third test access port (TAP) within the die, as well as the second test access port (TAP) and the third test access port (TAP), are connected via a JTAG bus, referred to as the on-chip JTAG bus. Furthermore, TAPs from different dies are also connected via a JTAG bus, referred to as the off-chip JTAG bus.
[0048] To achieve the multiplexing function, in one embodiment of the present invention, the third test access port TAP includes a multiplexing / demultiplexing circuit. Figure 2 A schematic diagram of the structure of the third test access port (TAP) according to an embodiment of the present invention is shown. Figure 2 As shown, the multiplexing / demultiplexing circuit includes a bus multiplexer and a corresponding bus demultiplexer. Since the communication between TAPs is bidirectional, in practical applications, the third test access port TAP includes two sets of bus multiplexers and corresponding bus demultiplexers. Figure 2As shown, the first input of the first bus multiplexer 131 is connected to the first test access port TAP in the current die in the Y-direction, and the second input is connected to the second test access port TAP in the previous die in the X-direction. The first bus demultiplexer 132 is located at the output of the first bus multiplexer 131, with its first output connected to the first test access port TAP of the next die in the Y-direction, and its second output connected to the second test access port TAP in the current die in the X-direction. Similarly, the first input of the second bus multiplexer 133 is connected to the second test access port TAP in the current die in the X-direction, and its second input is connected to the first test access port TAP of the next die in the Y-direction. The second bus demultiplexer 134 is located at the output of the second bus multiplexer, with its first output connected to the second test access port TAP of the previous die in the X-direction, and its second output connected to the first test access port TAP in the current die in the Y-direction. As mentioned above, in one embodiment of the present invention, the input of the bus multiplexer mainly includes the TDI, TMS, TCK, TRST signals transmitted in the JTAG bus, and the output is the TDO signal. The bus multiplexer and the corresponding bus demultiplexer select their input and output through the JTAG_vh_mode signal.
[0049] Figures 3a-3c This diagram illustrates a wafer-level testing structure based on an embodiment of the present invention. As shown, wafer-level testing based on the aforementioned test structure includes:
[0050] Based on the testing requirements, control the link path of the third test access port TAP to form at least one test chain in the specified direction, and each test chain is independent of the others.
[0051] like Figure 3a As shown, when X-axis testing is required, the TAP controller controls the first bus multiplexer to select its second input, the second bus multiplexer to select its first input, the first bus demultiplexer to select its second output, and the second bus demultiplexer to select its first output, so that the third test access port TAP can be communicatively connected with the second test access port TAP in its own die and the second test access port TAP in the previous die, forming an X-axis test chain.
[0052] Similarly, when focusing on testing inter-die interconnects in the Y direction, the Y direction can be selected for testing, such as... Figure 3bAs shown, when Y-axis testing is required, the TAP controller controls the first bus multiplexer to select its first input, the second bus multiplexer to select its second input, the first bus demultiplexer to select its first output, and the second bus demultiplexer to select its second output. This allows the third test access port TAP to communicatively connect with the first test access port TAP within its own die and the first test access port TAP within the next level die, forming a Y-axis test chain. Taking a 2x2 die as an example, the test objective can be achieved through two independent JTAG chains. In contrast, traditional methods require two X-axis JTAGs to cooperate, and when testing the Y-axis interconnect in the rightmost column, all dies need to be enabled, resulting in unnecessary test power consumption.
[0053] The two-dimensional mesh test structure provides low-cost redundancy paths. Even with manufacturing defects in the test circuit itself, alternative test paths can still be selected to test the die. As shown in Figure 3, in one embodiment of the invention, when a defect point (marked with a star in the figure) is detected, the link path of the third test access port (TAP) in the die after the defect point can be switched to another direction, thereby using a test chain in another direction for the die after the defect point. Specifically, as shown in the figure, after initially detecting a defect point using an X-direction test chain, the die after the defect point is adjusted to form multiple independent Y-direction test chains, thereby achieving full-die testing.
[0054] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.
Claims
1. A test structure for a wafer-level system, characterized in that, include: The TAP controller is configured to control the Test Access Port (TAP) of the die in the wafer to form a two-dimensional test network. as well as Multiple grains, wherein each grain comprises: The first test access port TAP can be communicatively connected to the third test access port TAP in the previous level die in the Y direction, forming a Y-direction test chain; The second test access port (TAP) is communicatively connected in the X-axis to the third test access port (TAP) in the next-level die, forming an X-axis test chain, wherein the X-axis is orthogonal to the Y-axis; and The third test access port (TAP) can be configured as needed to be communicatively connected to the first test access port (TAP) in the Y-axis direction, or to be communicatively connected to the second test access port (TAP) in the X-axis direction. The third test access port (TAP) includes a first bus multiplexer, a first bus demultiplexer, a second bus multiplexer, and a second bus demultiplexer. The first input of the first bus multiplexer is connected in the Y-axis direction to the first test access port (TAP) in this die, and the second input is connected in the X-axis direction to the second test access port (TAP) in the next higher-level die. The first bus demultiplexer is located within the first bus multiplexer. At the output end, its first output is connected to the first test access port TAP of the next-level die in the Y direction, and its second output is connected to the second test access port TAP of the die in the X direction. The first input of the second bus multiplexer is connected to the second test access port TAP of the die in the X direction, and its second input is connected to the first test access port TAP of the next-level die in the Y direction. The second bus demultiplexer is set at the output end of the second bus multiplexer, its first output is connected to the second test access port TAP of the previous-level die in the X direction, and its second output is connected to the first test access port TAP of the die in the Y direction.
2. The test structure as described in claim 1, characterized in that, The test access ports (TAPs) inside the die are connected via a JTAG bus.
3. The test structure as described in claim 1, characterized in that, The test access ports (TAPs) of different chips are connected via a JTAG bus.
4. A method for operating a test structure according to any one of claims 1 to 3, characterized in that, Including the following steps: Based on the testing requirements, control the link path of the third test access port TAP to form at least one test chain in the specified direction, with each test chain being independent of the others.
5. The test method as described in claim 4, characterized in that, Including the following steps: When Y-axis testing is required, the TAP controller enables the first test access port TAP to communicate with the third test access port TAP within its own die and the first test access port TAP within the next level die, forming a Y-axis test chain.
6. The test method as described in claim 4, characterized in that, Including the following steps: When X-axis testing is required, the TAP controller enables the third test access port TAP to communicate with the second test access port TAP within its own die and the third test access port TAP within the next level die, forming an X-axis test chain.
7. The test method as described in claim 4, characterized in that, Also includes: Once a defect is detected, the link path of the third test access port (TAP) in the die after the defect is switched, and the die after the defect is tested using a test chain in another direction.
8. A wafer testing machine, characterized in that, Includes the test structure according to any one of claims 1 to 3.