A detection circuit for parasitic capacitance discharge loss of a GaN HEMT device

Abstract

The application provides a detection circuit for parasitic capacitance discharge loss of a GaN HEMT device, characterized by comprising a power supply, a series of capacitor groups with a capacitance value of 0.5 pf-100 pf in parallel, a voltage detection unit composed of a voltage division circuit formed by a series of resistors and an operational amplifier LM324PW, a current detection circuit, and a single-chip microcomputer control unit for controlling the parallel connection of the capacitors into the circuit and the disconnection of the capacitors from the circuit; when the parasitic capacitance of the GaN HEMT changes with voltage, the voltage detection unit measures the voltage across the parasitic capacitance, the capacitance value of Cds at this voltage level is obtained according to a C-V curve, the MCU unit controls the parallel connection of the capacitors equal to the capacitance value into the circuit, the current measurement circuit obtains the discharge current Ioss, and the MCU calculates the loss Eoss by the discharge current Ioss and the drain-source voltage Vds through serial communication and transmission from the RXD and TXD pins to the upper computer.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more particularly to a detection circuit for the parasitic capacitance discharge loss of a GaN HEMT device. Background Technology

[0002] Gallium nitride high electron mobility transistors (GaN HEMTs) are a new type of wide-bandgap semiconductor device following SiC transistors in the third generation of semiconductor devices. Their direct bandgap wurtzite crystal structure gives them a bandgap of 3.39 eV and electron mobility far exceeding that of silicon, germanium, and gallium arsenide. Therefore, GaN HEMT devices can be fabricated to produce transistors with superior performance, including high voltage withstand, high current, high temperature resistance, high frequency, and strong anti-interference capabilities. GaN HEMT devices are currently a new field with promising application prospects, market opportunities, and enormous development potential.

[0003] GaN HEMTs, based on heterojunctions formed with AlGaN, possess a high-concentration two-dimensional electron gas (2DEG) with a bulk density on the order of 10¹⁹ in their spontaneous polarization and the potential well formed by their lattice constant, resulting in extremely low on-resistance. Furthermore, GaN HEMT devices have wide interlayer material band gaps and high dielectric constants, allowing for very low junction capacitance. For example, the input capacitance (Ciss), output capacitance (Coss), and Miller capacitance (Crss) of GaN Systems' GS66502B GaN HEMT are typically 60 pF, 17 pF, and 0.5 pF, respectively, at a gate-source voltage Vgs = 0 V, a drain-source voltage Vds = 400 V, and a frequency of 100 kHz—far lower than the thousands of pF levels of silicon-based MOSFETs.

[0004] GaN HEMTs, with their extremely high electron mobility and switching speed, can be applied to various high-frequency applications. However, this also makes loss analysis crucial in their practical applications. In the hard-switching process of GaN HEMTs based on a dual-pulse test circuit, the capacitor discharge loss (Eoss) generated when Cds releases the charge accumulated during turn-off is called Eoss. VI loss, Eqoss loss, and ESD loss can be obtained from the drain-source current Id, charging current Iqoss, reverse conduction current, and drain-source voltage Vds at various stages, respectively. However, since the capacitor discharge current Ioss, which causes Eoss, cannot be measured, its loss cannot be directly obtained from voltage and current. Furthermore, the Eoss loss calculated directly from Coss obtained from the datasheet has a large error in practical analyses of capacitance variations with Vds. Therefore, there is currently no suitable solution for the parasitic capacitor discharge loss problem in practical research. Summary of the Invention

[0005] To address the above technical problems, this invention provides a detection circuit for the parasitic capacitance discharge loss of a GaN HEMT device. This circuit measures the voltage across the parasitic capacitance using a voltage detection unit, obtains the capacitance value (Cds) at this voltage level based on the CV curve, and then uses an MCU unit to control an equal capacitor to be connected in parallel with the circuit. Finally, a current measurement circuit obtains the discharge current (Ioss) of this capacitor.

[0006] This invention provides a detection circuit for the parasitic capacitance discharge loss of a GaN HEMT device. The circuit comprises a power supply, a series of parallel capacitor banks with capacitance values ​​ranging from 0.5pF to 100pF, a voltage detection unit consisting of a voltage divider circuit composed of a series resistor and an operational amplifier LM324PW, a current detection circuit, and a microcontroller control unit that controls the parallel input and output circuits of the capacitors. The power supply powers the operational amplifier and the microcontroller control unit. The capacitor banks are adapted to the parasitic capacitance value of the GaN HEMT. The voltage detection unit, composed of a voltage divider circuit composed of a series resistor and an operational amplifier LM324PW, measures the voltage across the target parasitic capacitance of the GaN HEMT. The current measurement circuit detects the current in the parallel capacitor branch to obtain the magnitude of the discharge current on the parasitic capacitance. The microcontroller control unit controls the parallel input and output circuits of the corresponding capacitor banks and samples the voltage and current values, uploading the data to a host computer via serial communication for reading.

[0007] The operational amplifier described is a quad op-amp integrated circuit, model LM324PW, packaged in an SOP-14 package. It has 14 pins: pins 1, 7, 8, and 14 are the output pins of the four operational amplifiers; pins 2, 3, 5, 6, 9, 10, 12, and 13 are the positive and inverting inputs of the four operational amplifiers; pin 4 is the VCC+ pin, connected to a 5V power supply; and pin 11 is the VCC- pin, grounded. Internally, it contains four identical operational amplifiers that are independent of each other except for sharing a power supply. Each operational amplifier has five signal pins: "+" and "-" are the two signal inputs; "V+" and "V-" are the positive and negative power supply terminals; and "Vo" is the output. Of the two signal inputs, Vi(-) is the inverting input, meaning the signal at the op-amp output Vo is out of phase with this input; Vi(+) is the non-inverting input, meaning the signal at the op-amp output Vo is in phase with this input.

[0008] R1, R2, R3, etc., are a series of high-precision resistors of the same type. In this circuit, R1 = 40kΩ, R2 = 40kΩ, and R3 = 0.8kΩ.

[0009] C1, C2, C3, etc., are a series of capacitor groups with the same model and capacitance values ​​ranging from 0.5pF to 100pF.

[0010] The current detection circuit used is a Hall effect-based current sensor, model ACS712, which has a total of 8 pins. Pins 1 and 2 are the input pins IP+ for the current to be measured, pins 3 and 4 are the output pins IP- for the current to flow out, pins 5 and 8 are the ground pin and the module power supply voltage pin, respectively, pin 6 is the filter pin, which connects to the external capacitor of the terminal and is used to set the bandwidth, and pin 7 VIOUT is the module output voltage value. The ACS712 converts the analog current to be measured into an analog voltage output, so VIOUT can be connected to the AD converter and measured by the AD converter. Since VIOUT has a linear relationship with the current to be measured, the current to be measured can be deduced in reverse.

[0011] The microcontroller control unit is an STM32 microcontroller, model STM32F103C8T6. Its minimum system board has 40 pins. Pins 9, 11, 17, and 19 are AD1, AD2, AD3, and AD4 pins, which are used to detect the voltage value across R2 and the analog voltage value output by the current detection unit in the current branch of a series of parallel capacitors controlled by the microcontroller unit. Pins 1 and 2 are VCC and GND pins, which are connected to the power supply and ground, respectively. Pins 28 and 30 are TXD and RXD pins, respectively, used for data transmission with the host computer.

[0012] Furthermore, the specific steps of the parasitic capacitance discharge loss detection method based on GaN HEMT devices are as follows:

[0013] A. Connect the electrical detection circuit to the drain-source capacitor Cds (ports A and B are connected to measurement ports 1 and 2 respectively), and send the double pulse signal sent by the drive unit Vgate to the gate of the lower transistor Q2, so that the double pulse circuit runs and the lower transistor Q2 is turned on twice.

[0014] B. When the lower transistor Q2 is turned on, the voltage monitoring unit detects the voltage value of the voltage divider resistor in the voltage divider circuit, thereby obtaining the drain-source voltage Vds of the GaN HEMT and converting it into an analog signal for acquisition by the AD1 pin of the MCU.

[0015] C. The MCU unit obtains the capacitance value corresponding to Vds based on the CV (capacitance as a function of voltage) curve in the datasheet, and connects the capacitor with the corresponding capacitance value into the parallel circuit. The current of the circuit is measured by the current measurement unit to obtain the capacitor discharge current Ioss, and it is converted into an analog signal for the MCU's AD2 and other pins to acquire.

[0016] D. The microcontroller control unit sends the measured current and voltage values ​​to the host computer via serial communication, and calculates the drain-source capacitance Cds and discharge loss Eoss of the GaN HEMT device during the conduction process based on the obtained drain-source voltage Vds and discharge current Ioss.

[0017] E. Connect the capacitance detection circuit to the gate-source capacitor Cgs and the gate-drain capacitor Cgd respectively (connect ports A and B to measurement ports 1 and 4, 2 and 3 respectively), and repeat the above process A to D to obtain the discharge loss Eoss of the gate-source capacitor and the gate-drain capacitor.

[0018] The beneficial effects of this invention are as follows: This invention provides a detection circuit for the discharge loss of parasitic capacitance in GaN HEMT devices. When the parasitic capacitance of the GaN HEMT changes with voltage, this invention measures the voltage across the parasitic capacitance using a voltage detection unit and obtains the capacitance value Cds at this voltage level based on the CV (capacitance versus voltage) curve. An MCU unit then controls an equal capacitor to be connected in parallel with the capacitor, and a current measurement circuit obtains the discharge current Ioss. The MCU then uses the discharge current Ioss and drain-source voltage Vds transmitted to the host computer via serial communication through the RXD and TXD pins to calculate the loss Eoss. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the circuit structure of the present invention;

[0020] Figure 2 This is a schematic diagram of the internal voltage follower of the operational amplifier used in this invention;

[0021] Figure 3 This is a schematic diagram of the wiring method of the operational amplifier LM324PW in the voltage detection unit used in this invention;

[0022] Figure 4 This is a schematic diagram of the wiring method of ACS712 in the current detection circuit used in this invention. Detailed Implementation

[0023] Example 1

[0024] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings.

[0025] This invention provides a detection circuit for the parasitic capacitance discharge loss of a GaN HEMT device. It is characterized by comprising a power supply, a series of capacitors connected in parallel with capacitance values ​​ranging from 0.5pF to 100pF, a voltage detection unit consisting of a voltage divider circuit composed of a series resistor and an operational amplifier LM324PW, a current detection circuit, and a control capacitor connected in parallel to the circuit and disconnected from the circuit by a microcontroller control unit. An independent power supply is connected to power pin 1 (VCC3V3) of the MCU unit and pin 4 (VCC+) of the operational amplifier. Taking the detection of discharge loss of drain-source parasitic capacitance (Cds) as an example, the voltage detection unit is connected in parallel between the drain and source of the GaN HEMT to detect the voltage value across the parasitic capacitance between the drain and source. Pins 2 and 3 of the operational amplifier are respectively connected to one of the resistors in the series voltage divider circuit of the voltage detection unit, and pin 1 is connected to pin 9 (AD1) of the STM32F103C8T6 to output the obtained voltage value to the MCU control unit. The MCU unit receives the Vds voltage signal output from the operational amplifier, determines the corresponding capacitance value through the CV curve, and controls the switch of the corresponding capacitance branch to connect it to the detection circuit. The current value Ic is measured by the current detection circuit connected in series on this capacitor branch, where Ic = 1 / 2Ioss. In the current detection circuit, pin 4 of each ACS712 chip is connected to pins 11, 17, and 19 (AD2, AD3, AD4) of the STM32F103C8T6 to transmit the obtained current magnitude as an analog voltage value to the MCU unit. The microcontroller then transmits the obtained drain-source voltage value and capacitor discharge current value to the host computer via serial communication. The discharge loss Eoss can be calculated using Ioss and Vds.

[0026] Additionally, when a capacitor bank is connected in parallel across the parasitic capacitor to detect losses, the addition of the capacitor bank will generate additional losses. However, since this loss is an independent loss generated by the measurement circuit rather than an additional loss caused by the measurement circuit to the device itself, and the time the capacitor bank is connected in parallel across the parasitic capacitor is short, resulting in minimal losses, this loss will not affect the capacitor discharge loss (Eoss) of the GaN HEMT device detected by this patent.

[0027] To make the technical solution and advantages of this patent clearer, the patent will be further described below with reference to the accompanying drawings. The specific embodiments described herein are merely illustrative of this patent and are not intended to limit the scope of this patent.

[0028] Figure 1 This patent provides a schematic diagram of the circuit structure for detecting the parasitic capacitance discharge loss of a GaN HEMT device. Figure 1As shown, this patent includes a power supply, a series of parallel capacitor banks with capacitance values ​​of 0.5pF-100pF, a voltage detection unit composed of a voltage divider circuit consisting of a series resistor and an operational amplifier LM324PW, a current detection circuit, and a microcontroller control unit with control capacitors connected in parallel into and out of the circuit.

[0029] Figure 2 This is a circuit diagram of a voltage follower. R1 is an anti-reflection resistor. The voltages at pins 5 and 6 of this op-amp are the same, and its input impedance is infinite. The input signal current mainly flows to ground through R4, and the input voltage is formed at INPUT. Theoretically, no current flows through R1. If the anti-reflection resistor R1 is not present, the signal will be completely reflected to INPUT. If the signal source's internal resistance is too high, i.e., its load-carrying capacity is low, the reflected signal will form a strong emitted oscillation near the input point of R4. Such noise, after amplification, will result in very poor output signal quality.

[0030] Figure 3 This patent provides a schematic diagram of the wiring structure of the operational amplifier LM328PW in a parasitic capacitance discharge loss detection circuit for a GaN HEMT device. (See diagram for details.) Figure 3 As shown, the LM324PW is powered by a 5V DC power supply. Its input pins Input+ and Input- are connected to both ends of the voltage divider resistor to measure its voltage value, and the output pin Out1 is connected to the AD1 pin of the STM32F103C8T6 to transmit the voltage to the MCU unit.

[0031] Figure 4 This patent provides a schematic diagram of the wiring of the ACS712 current detection circuit in a parasitic capacitance discharge loss detection circuit for a GaN HEMT device. The ACS712 is a Hall effect-based current sensor that operates in series; therefore, it is connected in series within the detection capacitor circuit. Figure 4 As shown, the ACS712 is powered by a 5V DC power supply. Its input pin IP+ is connected to the circuit of each sensing capacitor to detect its current value. Its output pin IP- is connected to the AD2, AD3, and AD4 pins of the STM32F107C8T6 to convert the measured current value into a voltage signal and transmit it to the MCU unit. Finally, the MCU unit transmits the signal to the host computer via serial communication.

[0032] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. The various components mentioned in this invention are common technologies in the existing field. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A detection circuit for the parasitic capacitance discharge loss of a GaN HEMT device, characterized in that... The system includes a power supply, a series of parallel capacitor banks, a voltage detection unit consisting of a voltage divider circuit composed of a set of series resistors and an operational amplifier, a current detection circuit, and a microcontroller control unit that controls the parallel input and output of the capacitors. The power supply powers the operational amplifier and the microcontroller control unit. The capacitor banks are used to adapt to the parasitic capacitance value of the GaN HEMT. The voltage detection unit, consisting of a voltage divider circuit composed of a set of series resistors and an LM324PW operational amplifier, measures the voltage across the target parasitic capacitance of the GaN HEMT. The current detection circuit detects the current in the parallel capacitor branch to obtain the magnitude of the capacitor discharge current on the parasitic capacitance. The microcontroller control unit controls the parallel input and output of the corresponding capacitor banks and samples the voltage and current values, uploading the data to a host computer via serial communication for reading.

2. The detection circuit for parasitic capacitance discharge loss of a GaN HEMT device according to claim 1, characterized in that... The operational amplifier is a quad operational amplifier integrated circuit, specifically the LM324PW chip, packaged in an SOP (Surface Mount Technology) package. It has 14 pins: four output pins (pins 1, 7, 8, and 14), and four inverting input pins (pins 2, 3, 5, 6, 9, 10, 12, and 13). Pins 2, 5, 10, and 13 are inverting inputs, while pins 3, 6, 9, and 12 are inverting inputs. Pin 4 is the VCC+ pin, connected to a 5V power supply, and pin 11 is the VCC- pin, grounded. There are four operational amplifiers, all of which are identical in form and independent of each other except for sharing a power supply. Each operational amplifier has five signal pins: "+" and "-" are two signal input terminals, "V+" and "V-" are positive and negative power supply terminals, and "Vo" is the output terminal. Of the two signal input terminals, Vi- is the inverting input terminal, indicating that the signal at the op-amp output terminal Vo is out of phase with the signal at this input terminal; Vi+ is the non-inverting input terminal, indicating that the signal at the op-amp output terminal Vo is in phase with the signal at this input terminal.

3. The detection circuit for parasitic capacitance discharge loss of a GaN HEMT device according to claim 2, characterized in that... In the circuit of the internal voltage follower of the operational amplifier of the quad operational amplifier integrated circuit, R1 is an anti-reflection resistor.

4. The detection circuit for parasitic capacitance discharge loss of a GaN HEMT device according to claim 1, characterized in that... The series resistors in this group are of the same type.

5. The detection circuit for parasitic capacitance discharge loss of a GaN HEMT device according to claim 1, characterized in that... The series of parallel capacitor banks have capacitance values ​​ranging from 0.5pF to 100pF and are of the same model.

6. The detection circuit for parasitic capacitance discharge loss of a GaN HEMT device according to claim 1, characterized in that... The current detection circuit used is a Hall effect-based current sensor, model ACS712, which has 8 pins. Pins 1 and 2 are the input pins IP+ for the current to be measured, pins 3 and 4 are the output pins IP- for the current to flow out, pins 5 and 8 are the ground pin and the module power supply voltage pin, respectively, pin 6 is the filter pin, which connects to the external capacitor of the terminal and is used to set the bandwidth, and pin 7 is the module output voltage pin VIOUT. The ACS712 converts the analog current to be measured into an analog voltage output, so VIOUT is connected to the AD converter and measured by the AD converter.

7. The detection circuit for parasitic capacitance discharge loss of a GaN HEMT device according to claim 1, characterized in that... The microcontroller control unit is an STM32 microcontroller, model STM32F103C8T6. Its minimum system board has a total of 40 pins. Pins 9, 11, 17, and 19 are AD1, AD2, AD3, and AD4 pins, which are used to detect the voltage value across R2 and the analog voltage value output by the current detection circuit in the current branch of a series of parallel capacitors controlled by the microcontroller unit. Pins 1 and 2 are VCC and GND pins, which are connected to the power supply and ground, respectively.

8. The detection circuit for parasitic capacitance discharge loss of a GaN HEMT device according to claim 7, characterized in that... The specific steps of the detection method using this detection circuit are as follows: A. Connect the current detection circuit across the drain-source capacitor Cds. Ports A and B are connected to measurement ports 1 and 2 respectively. The double pulse signal sent by the drive unit Vgate is sent to the gate of the lower transistor Q2, causing the double pulse circuit to run and the lower transistor Q2 to be turned on twice. B. When the lower transistor Q2 is turned on, the voltage detection unit detects the voltage value of the voltage divider resistor in the voltage divider circuit, thereby obtaining the drain-source voltage Vds of GaNHEMT, and converting it into an analog signal for acquisition by the AD1 pin of the MCU. C. The MCU unit obtains the capacitance value corresponding to Vds based on the CV curve in the datasheet, and connects the capacitor with the corresponding capacitance value into the parallel circuit. The current in the circuit is measured by the current detection circuit to obtain the capacitor discharge current Ioss, and it is converted into an analog signal for the MCU's AD2 pin to acquire. D. The microcontroller control unit sends the measured current and voltage values ​​to the host computer via serial communication, and calculates the drain-source capacitance Cds and discharge loss Eoss of the GaN HEMT device during the conduction process based on the obtained drain-source voltage Vds and discharge current Ioss. E. Connect the capacitance detection circuit to the gate-source capacitor Cgs and the gate-drain capacitor Cgd respectively, with ports A and B connected to measurement ports 1 and 4, and 2 and 3 respectively, and repeat the above process A to D to obtain the discharge loss Eoss of the gate-source capacitor and the gate-drain capacitor.

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