An integrated system for accelerator low-level control and power monitoring

Abstract

The present invention discloses an integrated system for low-level control and power monitoring of an accelerator, comprising a CPCI chassis, an FPGA board, a CompactPCI blade, and a directional coupler. The FPGA board has the functions of low-level control, power detection, and standing wave ratio protection. No detector is required for power detection, and the inlet and outlet power can be accurately detected. By making the accelerator low-level control system and the power detection and standing wave ratio protection system share the same FPGA board, two orthogonal signals output by a DDS of the low-level control system can be directly sent to a power detection module for I,Q demodulation, thereby achieving the functions of low-level control, power detection, and standing wave ratio protection simultaneously. No analog devices such as up- and down-conversion and local oscillators are required for low-level control. No detector is required for radio frequency power detection within a wide frequency range. The power value of each spectral component contained in the signal is detected, and the power in the accelerator cavity can be accurately detected.

Description

Technical Field

[0001] The present invention relates to the technical field of particle accelerators, in particular to an integrated system for low-level control and power monitoring of accelerators. Background Art

[0002] A particle accelerator is a special electromagnetic, high-vacuum device that controls charged particles in a high-vacuum field by magnetic field forces and accelerates them by electric field forces to reach high energy. It is a modern equipment that artificially provides various high-energy particle beams or radiation lines. Common particle accelerators in daily life include cathode ray tubes and X-ray tubes used in televisions. Some low-energy accelerators are used in nuclear science and nuclear engineering, while others are widely used in basic research in chemistry, physics and biology, as well as in various fields of the national economy such as radiation chemistry, radiography, activation analysis, ion implantation, radiation therapy, isotope production, disinfection and sterilization, welding and smelting, radiation treatment of seeds and food, and national defense.

[0003] Cancer is one of the greatest threats to human health. With the advancement of accelerator technology, accelerator-based boron neutron capture tumor therapy devices have been extensively researched both domestically and internationally in recent years due to their advantages, including precise targeting, low side effects, broad indications, a one-time solution, and ease of use in hospitals in densely populated areas. The boron neutron capture therapy (BNCT) device, developed by the Spallation Neutron Source Science Center, utilizes a radio frequency quadrupole accelerator (RFQ) to provide a high-intensity proton beam. The proton beam travels through a beam transfer line and impacts a lithium target, generating a high flux of neutrons. The accelerator is designed for high-repetition-rate pulsed operation, with an RFQ cavity high-frequency frequency of 180 MHz, a beam duty cycle of 80%, a beam pulse length of 4 ms, a repetition rate of 200 Hz, and a pulse intensity of 25 mA.

[0004] Traditional accelerator low-level control systems and cavity power monitoring systems are often divided into two systems with complex system structures. The accelerator low-level control system is mainly composed of analog up- and down-conversion, local oscillator and digital signal processing systems. Analog devices are easily affected by temperature, and it is usually necessary to add a constant temperature system to these analog devices to ensure stable performance. The cavity power monitoring system is mainly composed of: directional couplers, detectors, AD sampling modules and digital signal processing systems. The system is complex, and the detector can only detect signals with a single spectrum. It is difficult to detect the power of different frequency signals in multiple spectrum components. The overall stability of the system is poor and the cost is high. Based on this, we propose an integrated system for accelerator low-level control and power monitoring to optimize the shortcomings of existing technologies. Summary of the Invention

[0005] The object of the present invention is to provide an integrated system for low-level control and power monitoring of an accelerator to solve the problems raised in the above background technology.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] An integrated system for accelerator low-level control and power monitoring includes a CPCI chassis, an FPGA board, a CompactPCI blade, a directional coupler, a radio frequency transmission system, and an accelerating cavity. The system is characterized in that the FPGA board has the functions of low-level control, power detection, and standing wave ratio protection; the FPGA board is provided with an accelerator low-level control system, a power detection and standing wave ratio protection system, and a DDS module; the CompactPCI blade transmits data with the FPGA board via a PCI bus; the CompactPCI blade uses a Linux operating system; and has EPICS control and a CSS graphical display interface.

[0008] As a further solution of the present invention: the digital signal sent by the accelerator low-level control system is converted into an analog signal through a DAC, and then the radio frequency signal is sent to the acceleration cavity through a radio frequency transmission system after filtering and amplification. The radio frequency signal coupled from the acceleration cavity is sent to the AD of the low-level control system for sampling, and the digital signal after AD sampling is sent to the FPGA board for low-level control.

[0009] As a further solution of the present invention, a directional coupler is provided at the entrance of the accelerating cavity. The directional coupler at the entrance of the accelerating cavity sends the coupled forward and reverse signals to the AD of the power detection and standing wave ratio protection system for sampling. The detected power and standing wave ratio protection are calculated in real time through the digital signal processing algorithm flow in the FPGA. The detected power and other data are then transmitted to the CompactPCI blade via the PCI bus. The CompactPCI blade monitors and controls the integrated low-level control, power detection, and standing wave ratio protection system through the use of the Linux operating system, EPICS control, and CSS graphical display interface.

[0010] As a further solution of the present invention: the RF signal source input to the accelerating cavity is the accelerator low-level control system, and the power detection and standing wave ratio protection system and the accelerator low-level control system share the same FPGA board. The power detection and standing wave ratio protection system uses a shared DDS module with the accelerator low-level control system to accurately demodulate the I and Q values, and accurately calculate the power of the RF signal sent to the accelerating cavity based on the I and Q values.

[0011] As a further solution of the present invention: the accelerator low-level control system includes AD sampling, direct IQ demodulation module, IIR filtering, amplitude-phase conversion module, PI feedback controller, digital up-conversion module, switch and DAC chip. In the accelerator low-level control system, the amplitude and phase information of the acceleration field are obtained in sequence through AD sampling, direct IQ demodulation, IIR filtering, and amplitude-phase conversion module, and then closed-loop control is performed through the PI feedback controller. The required digital signal is output through the digital up-conversion module. The output digital signal includes a signal of the cavity field amplitude, phase and frequency and is transmitted to the DAC chip. The signal output by the DAC chip is filtered and amplified, and then a high-power signal is transmitted to the acceleration cavity through a coaxial feed tube. Finally, the amplitude, phase, frequency and other parameters of the signal are displayed through the CSS graphical display interface in the CompactPCI blade.

[0012] As a further scheme of the present invention: described power detection and standing wave ratio protection system comprises AD sampling, IQ demodulation module, IIR filtering, power calculation module and standing wave ratio protection module, in described power detection and standing wave ratio protection system, radio frequency signal passes through AD sampling, IQ demodulation module, after IIR filtering, calculates power through power calculation module successively, then the forward power and reverse power calculated are sent to standing wave ratio protection module, judge whether to carry out standing wave ratio protection, after standing wave ratio protection takes place, standing wave ratio protection module outputs protection signal and gives to accelerator low-level control system, the output of radio frequency signal is cut off by the switch in the accelerator low-level control system, next pulse recovery, when the number of times of standing wave ratio protection exceeds set value, the output of low-level radio frequency signal will be permanently cut off, up to manual recovery.

[0013] As a further solution of the present invention, the accelerator low-level control system achieves frequency modulation of the radio frequency signal by controlling the frequency control of the DDS module. The radio frequency signal for power detection is the amplified signal output by the accelerator low-level control system, so the frequencies of the two signals are the same. The power detection and standing wave ratio protection system and the accelerator low-level control system share the same FPGA board. Therefore, the two orthogonal signals output by the DDS module of the accelerator low-level control system are directly sent to the power detection and standing wave ratio protection system for I / Q demodulation. The demodulated signal of any frequency in the system is demodulated, thereby calculating the power value.

[0014] As a further solution of the present invention, the DDS module can accurately output two orthogonal signals to demodulate the digital down-converted signal. The basic principle is expressed by the following formula:

[0015] The RF signal coupled out by the directional coupler is given in Equation 1:

[0016] The sampling equation is shown in Equation 2, where T is the period of the sampling clock,

[0017] CLK=δ[t]+δ[tT]+δ[t-2T]+δ[t-3T]+… (2)

[0018] With sampling clock f clk The sampling sequence data of the RF signal coupled by the sampling directional coupler is:

[0019]

[0020] The DDS output reference signal in FPGA is but

[0021]

[0022] This system uses a first-order IIR filter to increase data processing speed. FPGA only needs one clock cycle to complete the calculation of a single data point during data processing. The IIR filter has a good filtering effect on signals other than DC. The filter formula used is shown in Equation 6:

[0023]

[0024] Where x[n] is the input I or Q sequence, and the I and Q values ​​of the zero-frequency component are obtained after filtering.

[0025]

[0026] The power of the RF signal is thus measured

[0027] In formula 9, b is the coupling degree of the directional coupler plus the attenuation of the cable, in dB. This value can be directly measured through the network. The coefficient k in formula 9 is calculated as follows: directly input a small signal V to the AD test , the signal frequency is consistent with the measured frequency, the signal unit is dBm, and the I corresponding to the demodulated signal is read from the FPGA test ,Q test The coefficient k can be calculated by the following formula:

[0028] After calculating the values ​​of coefficients k and b, the power value of the signal can be obtained in real time using Formula 9.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] 1. In the present invention, by making the accelerator low-level control system and the power detection and standing wave ratio protection system share the same FPGA board, the two-way orthogonal signals output by the low-level control system DDS can be directly sent to the power detection module for I,Q demodulation, and the functions of low-level control, power detection, and standing wave ratio protection can be achieved simultaneously. When performing low-level control, no analog devices such as up- and down-conversion and local oscillators are required. When performing radio frequency power detection within a wide frequency range, no detector is required. The power value of each spectral component contained in the signal is detected, and the power in the acceleration cavity can be accurately detected, thereby simplifying the power detection link, ensuring system stability, and reducing the system's operating cost. It has advantages in power detection of multiple spectral components mixed in the signal, and has good social and economic benefits.

[0031] 2. In the present invention, by optimizing the digital signal processing algorithm, the entire low-level control system can operate within a wide frequency range and can demodulate signals of any frequency within the frequency band while keeping the AD sampling clock frequency unchanged.

[0032] 3. The present invention can monitor the power values ​​of different frequencies in a signal containing multiple frequency components in real time, which is more optimized and has better performance than the detector power measurement method. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is the overall schematic diagram of the integrated system for accelerator low-level control and power monitoring.

[0034] Figure 2 This is the block diagram of the FPGA digital signal processing algorithm in the integrated system of accelerator low-level control and power monitoring.

[0035] Figure 3 This is the logic block diagram of the standing wave ratio protection in the integrated system of accelerator low-level control and power monitoring.

[0036] Figure 4 Schematic diagram of the amplitude-frequency response curve of the IIR filter in the integrated system of accelerator low-level control and power monitoring.

[0037] Figure 5 This is a block diagram of the mixed signal power measurement in Example 1 of the integrated system for accelerator low-level control and power monitoring. DETAILED DESCRIPTION

[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0039] See also Figures 1 to 5 In an embodiment of the present invention, an integrated system for accelerator low-level control and power monitoring includes a CPCI chassis, an FPGA board, a CompactPCI blade, a directional coupler, a radio frequency transmission system, and an accelerating cavity. The FPGA board has the functions of low-level control, power detection, and standing wave ratio protection. No detector is required for power detection, and the inlet and outlet power can be accurately detected. The FPGA board is equipped with an accelerator low-level control system, a power detection and standing wave ratio protection system, and a DDS module. The CompactPCI blade transmits data with the FPGA board via a PCI bus. The CompactPCI blade uses the Linux operating system and has EPICS control and a CSS graphical display interface.

[0040] The digital signal sent by the accelerator's low-level control system is converted into an analog signal through a DAC, and then the RF signal is sent to the acceleration cavity through the RF transmission system after filtering and amplification. The RF signal coupled from the acceleration cavity is sent to the AD of the low-level control system for sampling, and the digital signal after AD sampling is sent to the FPGA board for low-level control.

[0041] A directional coupler is provided at the entrance of the accelerating cavity. The directional coupler at the entrance of the accelerating cavity sends the coupled forward signal and reverse signal to the AD of the power detection and standing wave ratio protection system for sampling. The digital signal processing algorithm in the FPGA (such as Figure 2 The detected power and VSWR protection are calculated in real time, and then the detected power and other data are transmitted to the CompactPCI blade through the PCI bus. The CompactPCI blade completes the monitoring and control of the low-level control, power detection and VSWR protection integrated system through the Linux operating system, EPICS control and CSS graphical display interface.

[0042] The RF signal source input to the accelerating cavity is the accelerator's low-level control system, while the power detection and standing wave ratio protection system shares the same FPGA board with the accelerator's low-level control system. The power detection and standing wave ratio protection system uses the same DDS module with the accelerator's low-level control system to accurately demodulate the I and Q values, and accurately calculate the power of the RF signal sent to the accelerating cavity based on the I and Q values.

[0043] The accelerator's low-level control system includes AD sampling, direct IQ demodulation module, IIR filtering, amplitude-phase conversion module, PI feedback controller, digital up-conversion module, switch and DAC chip. In the accelerator's low-level control system, the amplitude and phase information of the acceleration field are obtained in sequence through AD sampling, direct IQ demodulation, IIR filtering, and amplitude-phase conversion module, and then closed-loop control is performed through the PI feedback controller. The required digital signal is output through the digital up-conversion module. The output digital signal includes the cavity field amplitude, phase and frequency signal and is transmitted to the DAC chip. The signal output by the DAC chip is filtered and amplified, and then the high-power signal is transmitted to the acceleration cavity through the coaxial feed tube. Finally, the amplitude, phase, frequency and other parameters of the signal are displayed through the CSS graphical display interface in the CompactPCI blade.

[0044] The power detection and standing wave ratio protection system includes AD sampling, IQ demodulation module, IIR filtering, power calculation module and standing wave ratio protection module. In the power detection and standing wave ratio protection system, the RF signal passes through AD sampling, IQ demodulation module, IIR filtering in turn, and then the power is calculated by the power calculation module. The calculated forward power and reverse power are then sent to the standing wave ratio protection module to determine whether standing wave ratio protection is performed. After standing wave ratio protection occurs, the standing wave ratio protection module outputs a protection signal to the accelerator low-level control system. The switch in the accelerator low-level control system cuts off the output of the RF signal and the next pulse is restored. When the number of standing wave ratio protections exceeds the set value, the output of the low-level RF signal will be permanently cut off until it is manually restored. The standing wave ratio protection logic block diagram is as follows Figure 3 shown.

[0045] IQ demodulation of radio frequency (RF) signals essentially involves down-converting the RF signal to baseband to obtain spatially orthogonal I and Q signals that contain the RF signal's amplitude and phase information. Considering that the BNCT low-level control system operates in variable-frequency mode within the 181MHz-179MHz frequency range, if quadruple sampling is used, the FPGA's operating frequency must change with the RF signal's frequency in each cycle, hindering the FPGA's pipeline operation. Therefore, undersampling is employed in this system to achieve spectrum shifting.

[0046] The accelerator low-level control system realizes the frequency modulation of the RF signal by controlling the frequency control of the DDS module. The RF signal of the power detection is the amplified signal output by the accelerator low-level control system, so the frequencies of the two signals are the same. The power detection and standing wave ratio protection system and the accelerator low-level control system share the same FPGA board. Therefore, the two orthogonal signals output by the DDS module of the accelerator low-level control system are directly sent to the power detection and standing wave ratio protection system for I,Q demodulation. Therefore, this system can demodulate the signal of any frequency in the system without using a detector, thereby calculating the power value.

[0047] The DDS module can accurately output two orthogonal signals and demodulate the digital down-converted signal. The signal demodulation process is as follows: Figure 2 As shown, the basic principle is expressed by the following formula:

[0048] The RF signal coupled out by the directional coupler is given in Equation 1:

[0049] The sampling equation is shown in Equation 2, where T is the period of the sampling clock,

[0050] CLK=δ[t]+δ[tT]+δ[t-2T]+δ[t-3T]+… (2)

[0051] With sampling clock f clk The sampling sequence data of the RF signal coupled by the sampling directional coupler is:

[0052]

[0053] The DDS output reference signal in FPGA is but

[0054]

[0055] The filter adopts IIR filter. The amplitude-frequency response curve of IIR filter is as follows: Figure 4 shown.

[0056] This system uses a first-order IIR filter to increase the data processing speed. When FPGA processes data, it only needs one clock cycle to complete the calculation of a single data. Figure 4 From the amplitude-frequency response curve, we can see that the IIR filter has a good filtering effect on signals other than DC. The filter formula used is as shown in Equation 6:

[0057]

[0058] Where x[n] is the input I or Q sequence, and the I and Q values ​​of the zero-frequency component are obtained after filtering.

[0059]

[0060] The power of the RF signal is thus measured

[0061] In formula 9, b is the coupling degree of the directional coupler plus the attenuation of the cable, in dB. This value can be directly measured through the network. The coefficient k in formula 9 is calculated as follows: directly input a small signal V to the AD test , the signal frequency is consistent with the measured frequency, the signal unit is dBm, and the I corresponding to the demodulated signal is read from the FPGA test ,Q test The coefficient k can be calculated by the following formula:

[0062]

[0063] After calculating the values ​​of coefficients k and b, the power value of the signal can be obtained in real time using Formula 9.

[0064] Example 1

[0065] This system can measure the power values ​​of different frequency components in the signal in real time. The basic principle is the same as above.

[0066] Taking the superposition of two frequency signals as an example, the principle block diagram is as follows Figure 5 As shown, the low-level output RF signal is the superposition of two frequency signals, including frequencies ω1 and ω2. The signal coupled by the directional coupler is as follows:

[0067] V rf =A1sin(ω1t+φ1)+A2sin(ω2t+φ2), when performing power detection, it is only necessary to send the reference signal of DDS to the digital up-conversion in the low-level control system. All signals are sent to the power detection and standing wave ratio protection system for demodulation. The demodulated signals are filtered by IIR to obtain zero-frequency I1, Q1, I2, Q2 sequences, and then the formula is used: Calculate the power values ​​corresponding to the radio frequency signals with frequencies ω1 and ω2.

[0068] Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An integrated system for low-level control and power monitoring of an accelerator, comprising a CPCI chassis, an FPGA board, a CompactPCI blade, and a directional coupler, characterized by: The FPGA board has the functions of low-level control, power detection and standing wave ratio protection. The FPGA board is provided with an accelerator low-level control system, a power detection and standing wave ratio protection system and a DDS module. The CompactPCI blade transmits data with the FPGA board through the PCI bus. The CompactPCI blade adopts the Linux operating system and has EPICS control and a CSS graphical display interface. The accelerator low-level control system includes AD sampling, direct IQ demodulation module, IIR filtering, amplitude-phase conversion module, PI feedback controller, digital up-conversion module, switch and DAC chip. In the accelerator low-level control system, the amplitude and phase information of the acceleration field are obtained in sequence through AD sampling, direct IQ demodulation, IIR filtering, and amplitude-phase conversion modules, and then closed-loop control is performed through the PI feedback controller. The required digital signal is output through the digital up-conversion module. The output digital signal includes the cavity amplitude, phase and frequency signals and is transmitted to the DAC chip. The signal output by the DAC chip is filtered and amplified and then transmitted to the acceleration cavity through the coaxial feed tube as a high-power signal. Finally, the amplitude, phase, frequency and other parameters of the signal are displayed through the CSS graphical display interface in the CompactPCI blade, based on the low-level control, power detection and standing wave ratio protection system of the same FPGA board.

2. The integrated system for low-level control and power monitoring of an accelerator according to claim 1, characterized in that: The digital signal sent by the accelerator's low-level control system is converted into an analog signal through a DAC, and then the radio frequency signal is sent to the acceleration cavity through a radio frequency transmission system after filtering and amplification. The radio frequency signal coupled from the acceleration cavity is sent to the AD of the low-level control system for sampling, and the digital signal after AD sampling is sent to the FPGA board for low-level control.

3. The integrated system for low-level control and power monitoring of an accelerator according to claim 2, characterized in that: A directional coupler is provided at the entrance of the accelerating cavity. The directional coupler at the entrance of the accelerating cavity sends the coupled forward signal and reverse signal to the AD of the power detection and standing wave ratio protection system for sampling. The detected power and standing wave ratio protection are calculated in real time through the digital signal processing algorithm flow in the FPGA. Then, the detected power and other data are transmitted to the CompactPCI blade through the PCI bus. The CompactPCI blade completes the monitoring and control of the low-level control, power detection and standing wave ratio protection integrated system through the use of the Linux operating system, EPICS control and CSS graphical display interface.

4. The integrated system for low-level control and power monitoring of an accelerator according to claim 2 or 3, characterized in that: The RF signal source input to the accelerating cavity is the accelerator's low-level control system, while the power detection and standing wave ratio protection system shares the same FPGA board with the accelerator's low-level control system. The power detection and standing wave ratio protection system uses the same DDS module with the accelerator's low-level control system to accurately demodulate the I and Q values, and accurately calculate the power of the RF signal sent to the accelerating cavity based on the I and Q values.

5. The integrated system for low-level control and power monitoring of an accelerator according to claim 1, characterized in that: The power detection and standing wave ratio protection system includes AD sampling, IQ demodulation module, IIR filtering, power calculation module and standing wave ratio protection module. In the power detection and standing wave ratio protection system, the radio frequency signal is sequentially passed through the AD sampling, IQ demodulation module and IIR filtering, and then the power is calculated by the power calculation module. The calculated forward power and reverse power are then sent to the standing wave ratio protection module to determine whether standing wave ratio protection is performed. After standing wave ratio protection occurs, the standing wave ratio protection module outputs a protection signal to the accelerator low-level control system. A switch in the accelerator low-level control system cuts off the output of the radio frequency signal, and the next pulse is restored. When the number of standing wave ratio protections exceeds a set value, the output of the low-level radio frequency signal is permanently cut off until manual restoration is performed.

6. The integrated system for low-level control and power monitoring of an accelerator according to claim 1, characterized in that: The accelerator low-level control system achieves frequency modulation of the RF signal by controlling the frequency of the DDS module. The RF signal for power detection is the amplified signal output by the accelerator low-level control system, so the frequencies of the two signals are the same. The power detection and standing wave ratio protection system and the accelerator low-level control system share the same FPGA board. Therefore, the two orthogonal signals output by the DDS module of the accelerator low-level control system are directly sent to the power detection and standing wave ratio protection system for I,Q demodulation. The signal of any frequency in the system is demodulated, thereby calculating the power value.

7. The integrated system for low-level control and power monitoring of an accelerator according to claim 1, characterized in that: The DDS module can accurately output two orthogonal signals to demodulate the digital down-converted signal. The basic principle is expressed by the following formula: The RF signal coupled out by the directional coupler is given in Equation 1: The sampling equation is shown in Equation 2, where T is the period of the sampling clock, With sampling clock f clk The sampling sequence data of the RF signal coupled by the sampling directional coupler is: The DDS output reference signal in FPGA is but This system uses a first-order IIR filter to increase data processing speed. FPGA only needs one clock cycle to complete the calculation of a single data point during data processing. The IIR filter has a good filtering effect on signals other than DC. The filter formula used is shown in Equation 6: in The I or Q sequence is input, and the I and Q values ​​of the zero-frequency component are obtained after filtering. The power of the RF signal is thus measured In formula 9, b is the coupling degree of the directional coupler plus the attenuation of the cable, in dB. This value can be directly measured through the network. The coefficient k in formula 9 is calculated as follows: directly input a small signal V to the AD test , the signal frequency is consistent with the measured frequency, the signal unit is dBm, and the I corresponding to the demodulated signal is read from the FPGA test , Q test The coefficient k can be calculated by the following formula: After calculating the values ​​of coefficients k and b, the power value of the signal can be obtained in real time using Formula 9.

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