Low Dropout Linear Regulator

Abstract

An embodiment of the present disclosure provides a low-dropout linear regulator, comprising: an error amplifier, an output power tube, first and second resistors, first and second capacitors, and a loop control circuit. The first input terminal of the error amplifier is coupled to the first ends of the first and second resistors via a feedback node. The second input terminal of the error amplifier is coupled to a reference voltage terminal. The output terminal of the error amplifier is coupled to the control terminal of the output power tube. The second terminal of the output power tube is coupled to the second end of the first resistor and the first ends of the first and second capacitors. The second end of the first capacitor is coupled to the feedback node. The loop control circuit causes the second end of the second capacitor to be charged to a reference voltage from the reference voltage terminal when the voltage of the feedback node is lower than the target voltage, and stops charging the second end of the second capacitor and causes the second end of the second capacitor to be coupled to the feedback node when the voltage of the feedback node rises to the target voltage. The target voltage is less than or equal to the reference voltage.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, to a low-dropout linear regulator. Background Art

[0002] Low-dropout linear regulators (LDOs) are widely used in integrated circuits to provide the internal power supply voltage. In practical applications, LDOs are expected to have advantages such as high stability, high power supply rejection ratio (PSRR), low output voltage noise, and fast load transient response. Summary of the Invention

[0003] Embodiments described herein provide a low dropout linear regulator.

[0004] According to a first aspect of the present disclosure, a low-voltage dropout linear regulator is provided. The low-voltage dropout linear regulator includes an error amplifier, an output power transistor, a first resistor, a second resistor, a first capacitor, a second capacitor, and a loop control circuit. A first input of the error amplifier is coupled to the first end of the first resistor and the first end of the second resistor via a feedback node. A second input of the error amplifier is coupled to a reference voltage terminal. An output of the error amplifier is coupled to a control electrode of the output power transistor. The first electrode of the output power transistor is coupled to the first voltage terminal. The second electrode of the output power transistor is coupled to the second end of the first resistor, the first end of the first capacitor, the first end of the second capacitor, and the output of the low-voltage dropout linear regulator. The second end of the first capacitor is coupled to the feedback node. The second end of the second resistor is coupled to the second voltage terminal. The loop control circuit is configured to charge the second end of the second capacitor to a reference voltage from the reference voltage terminal when the voltage of the feedback node is lower than a target voltage, and to stop charging the second end of the second capacitor and couple the second end of the second capacitor to the feedback node when the voltage of the feedback node rises to the target voltage. The target voltage is less than or equal to the reference voltage.

[0005] In some embodiments of the present disclosure, the capacitance value of the first capacitor is smaller than the capacitance value of the second capacitor.

[0006] In some embodiments of the present disclosure, the loop control circuit includes: a pre-charge control circuit, a pre-charge circuit, and a switching circuit. The pre-charge control circuit is configured to generate a pre-charge control signal based on the voltage of the feedback node and the reference voltage and provide the pre-charge control signal to the pre-charge circuit and the switching circuit via the first node. The pre-charge control signal is at a valid level when the voltage of the feedback node is lower than the target voltage, and flips to an invalid level when the voltage of the feedback node rises to the target voltage. The pre-charge circuit is configured to charge the second end of the second capacitor to the reference voltage when the pre-charge control signal is at a valid level, and stop charging the second end of the second capacitor when the pre-charge control signal is at an invalid level. The switching circuit is configured to couple the second end of the second capacitor to the feedback node when the pre-charge control signal is at an invalid level.

[0007] In some embodiments of the present disclosure, the precharge control circuit includes a voltage comparator, wherein a first input terminal of the voltage comparator is coupled to a reference voltage terminal, a second input terminal of the voltage comparator is coupled to a feedback node, and an output terminal of the voltage comparator is coupled to the first node.

[0008] In some embodiments of the present disclosure, an offset voltage exists between the second input terminal and the first input terminal of the voltage comparator. The target voltage is equal to the reference voltage minus the offset voltage.

[0009] In some embodiments of the present disclosure, a pre-charge circuit includes a driver circuit and a first switching circuit. The driver circuit is configured to generate a driving voltage based on a reference voltage and provide the driving voltage to the first switching circuit. The driving voltage has a voltage value equal to the reference voltage. The first switching circuit is configured to couple an output terminal of the driver circuit to a second terminal of a second capacitor to charge the second terminal of the second capacitor with the driving voltage when a pre-charge control signal is at an active level, and to disconnect the output terminal of the driver circuit from the second capacitor when the pre-charge control signal is at an inactive level.

[0010] In some embodiments of the present disclosure, the first switch circuit includes a first transistor, wherein a control electrode of the first transistor is coupled to a first node, and a first electrode of the first transistor is provided with a driving voltage.

[0011] The second electrode of the first transistor is coupled to the second end of the second capacitor.

[0012] In some embodiments of the present disclosure, a switching circuit includes a ramp signal generating circuit and a second switching circuit. The ramp signal generating circuit is configured to generate a ramp signal and provide the ramp signal to the second switching circuit when a precharge control signal is at an inactive level. The second switching circuit is configured to slowly switch the voltage at the second terminal of the second capacitor to the voltage of the feedback node as the ramp signal increases.

[0013] In some embodiments of the present disclosure, a ramp signal generating circuit includes: a second transistor, a bias current source, and a third capacitor. A control electrode of the second transistor is coupled to a first node. A first electrode of the second transistor is coupled to a second voltage terminal. A second electrode of the second transistor is coupled to a first terminal of the third capacitor. The bias current source is configured to provide a bias current to a first terminal of the third capacitor to generate a ramp signal at the first terminal of the third capacitor. A second terminal of the third capacitor is coupled to the second voltage terminal.

[0014] In some embodiments of the present disclosure, the second switch circuit includes a third transistor, a control electrode of the third transistor being provided with a ramp signal, a first electrode of the third transistor being coupled to the feedback node, and a second electrode of the third transistor being coupled to the second end of the second capacitor.

[0015] According to a second aspect of the present disclosure, a low-voltage-dropout linear regulator is provided. The low-voltage-dropout linear regulator includes an error amplifier, an output power transistor, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor, a voltage comparator, a drive circuit, a first transistor, a second transistor, a third transistor, and a bias current source. A first input of the error amplifier is coupled to the first end of the first resistor and the first end of the second resistor via a feedback node. A second input of the error amplifier is coupled to a reference voltage terminal. An output of the error amplifier is coupled to the control electrode of the output power transistor. A first electrode of the output power transistor is coupled to the first voltage terminal. A second electrode of the output power transistor is coupled to the second end of the first resistor, the first end of the first capacitor, the first end of the second capacitor, and the output of the low-voltage-dropout linear regulator. A second end of the first capacitor is coupled to the feedback node. A second end of the second resistor is coupled to the second voltage terminal. A first input of the voltage comparator is coupled to the reference voltage terminal. A second input of the voltage comparator is coupled to the feedback node. An output of the voltage comparator is coupled to the control electrode of the first transistor and the control electrode of the second transistor. An offset voltage exists between the second input of the voltage comparator and the first input. The drive circuit is configured to generate a drive voltage based on a reference voltage and provide the drive voltage to the first electrode of the first transistor. The drive voltage has a voltage value equal to the voltage value of the reference voltage. The second electrode of the first transistor is coupled to the second terminal of the second capacitor. The first electrode of the second transistor is coupled to the second voltage terminal. The second electrode of the second transistor is coupled to the first terminal of a third capacitor and the control electrode of the third transistor. The bias current source is configured to provide a bias current to the first terminal of the third capacitor. The second terminal of the third capacitor is coupled to the second voltage terminal. The first electrode of the third transistor is coupled to the feedback node. The second electrode of the third transistor is coupled to the second terminal of the second capacitor.

[0016] According to a third aspect of the present disclosure, a chip is provided, which includes the low-dropout linear regulator according to the first aspect or the second aspect of the present disclosure.

[0017] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising the chip according to the third aspect of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0019] Figure 1 is an exemplary circuit diagram of a low dropout linear regulator;

[0020] Figure 2 is a schematic block diagram of a low dropout linear regulator according to an embodiment of the present disclosure;

[0021] Figure 3 yes Figure 2 A further schematic block diagram of the low dropout linear regulator shown; and

[0022] Figure 4 yes Figure 3 An exemplary circuit diagram of a low dropout linear regulator is shown.

[0023] In the drawings, reference numerals having the same last two digits correspond to the same elements. It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0026] In all embodiments of the present disclosure, since the source and drain of the metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of the N-type transistor and the P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle end of the MOS transistor is referred to as the control electrode, and the other two ends of the MOS transistor are referred to as the first electrode and the second electrode, respectively. In addition, for the convenience of unified expression, in this context, the base of the bipolar transistor (BJT) is referred to as the control electrode, the emitter of the BJT is referred to as the first electrode, and the collector of the BJT is referred to as the second electrode. In addition, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0027] Figure 1An exemplary circuit diagram of a low voltage difference linear regulator 100 is shown. The low voltage difference linear regulator 100 includes: an error amplifier EA, an output power tube Mpout, a first resistor R1, a second resistor R2 and a capacitor Cff. Among them, the non-inverting input terminal of the error amplifier EA is coupled to the first end of the first resistor R1 and the first end of the second resistor R2. The inverting input terminal of the error amplifier EA is coupled to the reference voltage terminal Vref. The output terminal of the error amplifier EA is coupled to the control terminal of the output power tube Mpout. The first terminal of the output power tube Mpout is coupled to the power supply voltage terminal VDD. The second terminal of the output power tube Mpout is coupled to the second end of the first resistor R1, the first end of the capacitor Cff and the output terminal Vout of the low voltage difference linear regulator 100. The second end of the second resistor R2 is grounded GND. Figure 1 In the example, the output power tube Mpout is a PMOS transistor.

[0028] In the low-dropout linear regulator 100 , connecting a capacitor Cff in parallel across the first resistor R1 may have the following advantages: improving loop stability, increasing PSRR, reducing output voltage noise, and improving load transient response speed.

[0029] The larger the capacitance of capacitor Cff is, the more significant the above advantages are. Therefore, the capacitance of capacitor Cff is usually designed to be large in LDO circuits. However, as the capacitance of capacitor Cff increases, the settling time of output voltage Vout will increase significantly. The reasons are as follows: Figure 1 As shown in , current I0 = Vfb / R2. Where Vfb represents the feedback voltage value, and R2 represents the resistance value of the second resistor R2. If the input transistor inside the error amplifier EA is a BJT, current I2 is the bias current of the input stage of the error amplifier EA. If the input transistor of the error amplifier EA is a MOS tube, current I2 = 0A. Current I1 = (Vout-Vfb) / R1. Where Vout represents the output voltage value, Vfb represents the feedback voltage value, and R1 represents the resistance value of the first resistor R1. The charging current Ic of the capacitor Cff = I0-I1-I2. Therefore, as the output voltage Vout increases, the current I1 will gradually increase, and the charging current Ic will gradually decrease. In this way, the voltage across the capacitor Cff will build up more and more slowly, especially in the application scenario of low-power LDO, the current I0 will be extremely small (nA level), and then Ic = I0-I1-I2 will be even smaller. Since the capacitance value of the capacitor Cff is very large, the build-up time of the output voltage Vout will be extremely large.

[0030] The embodiments of the present disclosure provide a low voltage dropout linear regulator, which aims to retain the advantages of a large-capacitance capacitor Cff while solving the problem of slow settling time of the output voltage Vout when using a large-capacitance capacitor Cff. Figure 2 A schematic block diagram of a low-dropout linear regulator 200 according to an embodiment of the present disclosure is shown. The low-dropout linear regulator 200 includes an error amplifier EA, an output power transistor Mpout, a first resistor R1, a second resistor R2, a first capacitor Cff1, a second capacitor Cff2, and a loop control circuit 210. During startup of the low-dropout linear regulator 200, the voltages at the two input terminals of the error amplifier EA gradually become equal.

[0031] A first input terminal of the error amplifier EA is coupled to a first end of a first resistor R1 and a first end of a second resistor R2 via a feedback node FB. A second input terminal of the error amplifier EA is coupled to a reference voltage terminal Vref. An output terminal of the error amplifier EA is coupled to a control terminal of the output power transistor Mpout. A first terminal of the output power transistor Mpout is coupled to a first voltage terminal V1. A second terminal of the output power transistor Mpout is coupled to a second end of the first resistor R1, a first end of a first capacitor Cff1, a first end of a second capacitor Cff2, and an output terminal Vout of the low-dropout linear regulator 200. A second end of the first capacitor Cff1 is coupled to the feedback node FB. A second end of the second resistor R2 is coupled to a second voltage terminal V2.

[0032] The loop control circuit 210 is coupled to the reference voltage terminal Vref, the feedback node FB, and the second end of the second capacitor Cff2. The loop control circuit 210 is configured to charge the second end of the second capacitor Cff2 to (equal to) the reference voltage Vref from the reference voltage terminal Vref when the voltage Vfb of the feedback node FB is lower than a target voltage. Furthermore, when the voltage Vfb of the feedback node FB rises to the target voltage, charging of the second end of the second capacitor Cff2 is stopped and the second end of the second capacitor Cff2 is coupled to the feedback node FB. It should be noted that when the voltage Vfb of the feedback node FB is lower than the target voltage, the second end of the second capacitor Cff2 is not coupled to the feedback node FB. Here, the target voltage is less than or equal to the reference voltage Vref.

[0033] In some embodiments of the present disclosure, the target voltage is set according to the reference voltage Vref. For example, the target voltage is equal to the reference voltage Vref minus ΔV. ΔV can be set small enough so that when the second end of the second capacitor Cff2 is coupled to the feedback node FB, the voltage Vfb of the feedback node FB has already risen to the reference voltage Vref.

[0034] In some embodiments of the present disclosure, the capacitance of the first capacitor Cff1 is smaller than the capacitance of the second capacitor Cff2. In further embodiments of the present disclosure, the capacitance of the first capacitor Cff1 is much smaller than the capacitance of the second capacitor Cff2.

[0035] exist Figure 2 In the example, a high voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The output power tube Mpout is a PMOS transistor. The first input terminal of the error amplifier EA is the non-inverting input terminal. The second input terminal of the error amplifier EA is the inverting input terminal. Those skilled in the art should understand that based on the above invention concept, Figure 2 The variation of the circuit shown should also fall within the scope of protection of the present disclosure. In this variation, the above-mentioned transistor and voltage terminal may also have the same Figure 2 Examples of different setups are shown.

[0036] In the low-voltage dropout linear regulator 200 according to an embodiment of the present disclosure, before the output voltage Vout is established, only the first capacitor Cff1 with a small capacitance value is connected to the loop, while the second capacitor Cff2 with a large capacitance value is precharged by the loop control circuit 210. The second capacitor Cff2 is connected to the loop only after the voltage at the second end of the second capacitor Cff2 is charged to the reference voltage Vref. The capacitance of the first capacitor Cff1 can be set to be small enough to maintain the stability of the low-voltage dropout linear regulator 200 while speeding up the settling time of the output voltage Vout. Since the second capacitor Cff2 with a large capacitance value is precharged by the loop control circuit 210, its charging speed is very fast and does not affect the settling time of the output voltage Vout. After being charged to the reference voltage Vref, the second capacitor Cff2 with a large capacitance value is connected to the loop in parallel with the first capacitor Cff1, thereby improving the PSRR, reducing the output voltage noise, and improving the load transient response speed.

[0037] Figure 3 Show Figure 2 A further schematic block diagram of a low dropout linear regulator is shown in FIG. The loop control circuit 310 may include a pre-charge control circuit 311 , a pre-charge circuit 312 , and a switching circuit 313 .

[0038] The precharge control circuit 311 is coupled to the reference voltage terminal Vref and the feedback node FB. The precharge control circuit 311 is also coupled to the precharge circuit 312 and the switching circuit 313 via the first node N1. The precharge control circuit 311 is configured to generate a precharge control signal based on the voltage Vfb of the feedback node FB and the reference voltage Vref and provide the precharge control signal to the precharge circuit 312 and the switching circuit 313 via the first node N1. The precharge control signal is at an active level when the voltage Vfb of the feedback node FB is lower than the target voltage, and flips to an inactive level when the voltage Vfb of the feedback node FB rises to the target voltage. In this way, the precharge control signal can indicate whether the voltage Vfb of the feedback node FB rises to the target voltage.

[0039] The precharge circuit 312 is coupled to the precharge control circuit 311 and the switching circuit 313 via the first node N1. The precharge circuit 312 is coupled to the reference voltage terminal Vref and the second end of the second capacitor Cff2. The precharge circuit 312 is configured to charge the second end of the second capacitor Cff2 to the reference voltage Vref when the precharge control signal is at an active level, and to stop charging the second end of the second capacitor Cff2 when the precharge control signal is at an inactive level.

[0040] The switching circuit 313 couples the pre-charge control circuit 311 and the pre-charge circuit 312 via the first node N1. The switching circuit 313 couples the feedback node FB and the second end of the second capacitor Cff2. The switching circuit 313 is configured to couple the second end of the second capacitor Cff2 to the feedback node FB when the pre-charge control signal is at an inactive level. At this point, the second capacitor Cff2 is connected to the loop in parallel with the first capacitor Cff1. In some embodiments of the present disclosure, the second capacitor Cff2 is slowly connected to the loop.

[0041] Figure 4 Show Figure 3 An exemplary circuit diagram of a low dropout linear regulator is shown in FIG. Figure 4 In the loop control circuit 410 shown, the pre-charge control circuit 411 includes: a voltage comparator CMP. The first input terminal of the voltage comparator CMP is coupled to the reference voltage terminal Vref. The second input terminal of the voltage comparator CMP is coupled to the feedback node FB. The output terminal of the voltage comparator CMP is coupled to the first node N1. In some embodiments of the present disclosure, there is an offset voltage Vos between the second input terminal and the first input terminal of the voltage comparator CMP. The target voltage is equal to the reference voltage Vref minus the offset voltage Vos. The offset voltage Vos can be set to be small enough so that when the second end of the second capacitor Cff2 is coupled to the feedback node FB, the voltage Vfb of the feedback node FB has risen to the reference voltage Vref.

[0042] The precharge circuit may include a driver circuit 4121 and a first switch circuit 4122. The driver circuit 4121 is coupled to the reference voltage terminal Vref and the first switch circuit 4122. The driver circuit 4121 is configured to generate a driving voltage based on the reference voltage Vref and provide the driving voltage to the first switch circuit 4122. The driving voltage has a voltage value equal to the voltage value of the reference voltage Vref. To reduce noise and improve PSRR, leakage current is not allowed at the input of the error amplifier EA. Therefore, the reference voltage terminal Vref does not have driving capability. This problem can be solved by providing the driver circuit 4121.

[0043] The first switch circuit 4122 is configured to: when the pre-charge control signal is at an active level, couple the output end of the driver circuit 4121 to the second end of the second capacitor Cff2 to charge the second end of the second capacitor Cff2 with a driving voltage; and when the pre-charge control signal is at an inactive level, disconnect the output end of the driver circuit 4121 from the second capacitor Cff2. In some embodiments of the present disclosure, the first switch circuit 4122 includes a first transistor M1. The control electrode of the first transistor M1 is coupled to the first node N1. The driving voltage is applied to the first electrode of the first transistor M1. The second electrode of the first transistor M1 is coupled to the second end of the second capacitor Cff2.

[0044] The switching circuit may include a ramp signal generating circuit 4131 and a second switching circuit 4132. The ramp signal generating circuit 4131 is coupled to the output terminal of the voltage comparator CMP via the first node N1. The output terminal of the ramp signal generating circuit 4131 is coupled to the second switching circuit 4132. The ramp signal generating circuit 4131 is configured to generate a ramp signal when the precharge control signal is at an inactive level and provide the ramp signal to the second switching circuit 4132. The second switching circuit 4132 is coupled to the second terminal of the second capacitor Cff2, the feedback node FB, and the output terminal of the ramp signal generating circuit 4131. The second switching circuit 4132 is configured to slowly switch the voltage at the second terminal of the second capacitor Cff2 to the voltage Vfb of the feedback node FB as the ramp signal increases.

[0045] In some embodiments of the present disclosure, the ramp signal generating circuit 4131 includes a second transistor M2, a bias current source Ib, and a third capacitor CD. A control electrode of the second transistor M2 is coupled to a first node N1. A first electrode of the second transistor M2 is coupled to a second voltage terminal V2. A second electrode of the second transistor M2 is coupled to a first terminal of the third capacitor CD. The bias current source Ib is configured to provide a bias current to a first terminal of the third capacitor CD to generate a ramp signal at the first terminal of the third capacitor CD. A second terminal of the third capacitor CD is coupled to the second voltage terminal V2.

[0046] In some embodiments of the present disclosure, the second switch circuit 4132 includes a third transistor M3 , a control electrode of which is provided with a ramp signal, a first electrode of the third transistor M3 coupled to a feedback node FB, and a second electrode of the third transistor M3 coupled to the second end of the second capacitor Cff2 .

[0047] exist Figure 4In the example, a high voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The output power tube Mpout is a PMOS transistor. The first transistor M1 to the third transistor M3 are NMOS transistors. The first input terminal of the error amplifier EA is the non-inverting input terminal. The second input terminal of the error amplifier EA is the inverting input terminal. The first input terminal of the voltage comparator CMP is the non-inverting input terminal. The second input terminal of the voltage comparator CMP is the inverting input terminal. Those skilled in the art should understand that based on the above inventive concept, Figure 4 The variation of the circuit shown should also fall within the scope of protection of the present disclosure. In this variation, the above-mentioned transistor and voltage terminal may also have the same Figure 4 Examples of different setups are shown.

[0048] The following combination Figure 4 The working process of the low-dropout linear regulator according to the embodiment of the present disclosure is explained with an example.

[0049] In the low-dropout linear regulator according to an embodiment of the present disclosure, the initial state of the voltage Vfb of the feedback node FB is 0V. The voltage at the second input terminal of the voltage comparator CMP is equal to 0+Vos. Since Vos is less than the reference voltage Vref, the precharge control signal output by the voltage comparator CMP is at an effective level (high level). The first transistor M1 and the second transistor M2 are turned on. The driving voltage charges the second end of the second capacitor Cff2 through the first transistor M1. The second transistor M2 is turned on so that the first end of the third capacitor Cd is at a low level (grounded). Therefore, the third transistor M3 is turned off, and the second end of the second capacitor Cff2 is not coupled to the feedback node FB.

[0050] As the low-dropout linear regulator starts, the voltage Vfb of the feedback node FB gradually increases. When the voltage Vfb of the feedback node FB rises to the target voltage (Vref-Vos), the pre-charge control signal output by the voltage comparator CMP flips to an invalid level (low level). The first transistor M1 and the second transistor M2 are turned off. The driving voltage stops charging the second end of the second capacitor Cff2. The bias current source Ib begins to slowly charge the third capacitor Cd. The ramp signal slowly increases, and the third transistor M3 slowly turns on. Because Vfb=Vref-Vos is still rising at this time, and the second end of the second capacitor Cff2 has been charged to Vref, if the third transistor M3 is turned on quickly, it will discharge the second end of the second capacitor Cff2, and the output voltage Vout will also fluctuate. Therefore, the ramp signal needs to increase slowly so that the on-resistance of the third transistor M3 slowly changes from large to small, that is, the second capacitor Cff2 is slowly connected to the feedback node FB. Finally, Vfb=Vref, and the output voltage Vout=Vref×(R1+R2) / R2, and the output voltage Vout is quickly established.

[0051] The embodiments of the present disclosure further provide a chip. The chip includes a low voltage dropout linear regulator according to the embodiments of the present disclosure. The chip is, for example, a power management chip.

[0052] An embodiment of the present disclosure further provides an electronic device. The electronic device includes a chip according to an embodiment of the present disclosure. The electronic device is, for example, a smart terminal device such as a tablet computer, a smart phone, etc.

[0053] In summary, the low-dropout linear regulator according to the embodiments of the present disclosure can accelerate the output voltage settling time, improve the PSRR, reduce the output voltage noise, and improve the load transient response speed.

[0054] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0055] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present application.

[0056] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A low-dropout linear regulator, comprising: an error amplifier, an output power tube, a first resistor, a second resistor, a first capacitor, a second capacitor, and a loop control circuit, The first input terminal of the error amplifier is coupled to the first end of the first resistor and the first end of the second resistor via a feedback node, the second input terminal of the error amplifier is coupled to the reference voltage terminal, and the output terminal of the error amplifier is coupled to the control electrode of the output power tube; The first electrode of the output power tube is coupled to the first voltage terminal, and the second electrode of the output power tube is coupled to the second end of the first resistor, the first end of the first capacitor, the first end of the second capacitor and the output end of the low voltage difference linear regulator; The second terminal of the first capacitor is coupled to the feedback node; The second end of the second resistor is coupled to the second voltage end; The loop control circuit is configured to: charge the second terminal of the second capacitor to a reference voltage from the reference voltage terminal when the voltage of the feedback node is lower than a target voltage, and stop charging the second terminal of the second capacitor and couple the second terminal of the second capacitor to the feedback node when the voltage of the feedback node increases to the target voltage, wherein the target voltage is less than or equal to the reference voltage; The loop control circuit includes a pre-charge control circuit, a pre-charge circuit, and a switching circuit. The precharge control circuit is configured to: generate a precharge control signal according to the voltage of the feedback node and the reference voltage, and provide the precharge control signal to the precharge circuit and the switching circuit via the first node, wherein the precharge control signal is at an active level when the voltage of the feedback node is lower than the target voltage, and flips to an inactive level when the voltage of the feedback node rises to the target voltage; The pre-charging circuit is configured to: enable the second end of the second capacitor to be charged to the reference voltage when the pre-charging control signal is at the active level, and stop charging the second end of the second capacitor when the pre-charging control signal is at the inactive level; The switching circuit is configured to couple the second end of the second capacitor to the feedback node when the precharge control signal is at the inactive level.

2. The low-dropout linear regulator according to claim 1, wherein: The capacitance value of the first capacitor is smaller than the capacitance value of the second capacitor.

3. The low-dropout linear regulator according to claim 1, wherein: The pre-charge control circuit includes: a voltage comparator, The first input terminal of the voltage comparator is coupled to the reference voltage terminal, the second input terminal of the voltage comparator is coupled to the feedback node, and the output terminal of the voltage comparator is coupled to the first node.

4. The low-dropout linear regulator according to claim 3, wherein: An offset voltage exists between the second input terminal and the first input terminal of the voltage comparator, and the target voltage is equal to the reference voltage minus the offset voltage.

5. The low dropout linear regulator according to claim 1, wherein: The pre-charging circuit includes: a driving circuit and a first switching circuit. The driving circuit is configured to: generate a driving voltage according to the reference voltage and provide the driving voltage to the first switching circuit, wherein a voltage value of the driving voltage is equal to a voltage value of the reference voltage; The first switching circuit is configured to: when the pre-charge control signal is at the valid level, couple the output end of the driving circuit to the second end of the second capacitor to charge the second end of the second capacitor using the driving voltage; and when the pre-charge control signal is at the invalid level, disconnect the output end of the driving circuit from the second capacitor.

6. The low-dropout linear regulator according to claim 5, wherein: The first switch circuit includes: a first transistor, The control electrode of the first transistor is coupled to the first node, the first electrode of the first transistor is provided with the driving voltage, and the second electrode of the first transistor is coupled to the second end of the second capacitor.

7. The low dropout linear regulator according to claim 1, wherein: The switching circuit includes: a ramp signal generating circuit and a second switch circuit. The ramp signal generating circuit is configured to: generate a ramp signal and provide the ramp signal to the second switch circuit when the pre-charge control signal is at the invalid level; The second switch circuit is configured to slowly switch the voltage at the second end of the second capacitor to the voltage of the feedback node as the ramp signal increases.

8. The low-dropout linear regulator according to claim 7, wherein: The ramp signal generating circuit includes: a second transistor, a bias current source, and a third capacitor; the control electrode of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the second voltage terminal, and the second electrode of the second transistor is coupled to the first terminal of the third capacitor; the bias current source is configured to: provide a bias current to the first terminal of the third capacitor to generate the ramp signal at the first terminal of the third capacitor; the second terminal of the third capacitor is coupled to the second voltage terminal.

9. The low-dropout linear regulator according to claim 7, wherein: The second switch circuit includes: a third transistor; a control electrode of the third transistor is provided with the ramp signal, a first electrode of the third transistor is coupled to the feedback node, and a second electrode of the third transistor is coupled to the second end of the second capacitor.

10. A low-dropout linear regulator, comprising: an error amplifier, an output power tube, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor, a voltage comparator, a drive circuit, a first transistor, a second transistor, a third transistor, and a bias current source, The first input terminal of the error amplifier is coupled to the first end of the first resistor and the first end of the second resistor via a feedback node, the second input terminal of the error amplifier is coupled to the reference voltage terminal, and the output terminal of the error amplifier is coupled to the control electrode of the output power tube; The first electrode of the output power tube is coupled to the first voltage terminal, and the second electrode of the output power tube is coupled to the second end of the first resistor, the first end of the first capacitor, the first end of the second capacitor and the output end of the low voltage difference linear regulator; The second terminal of the first capacitor is coupled to the feedback node; The second end of the second resistor is coupled to the second voltage end; A first input terminal of the voltage comparator is coupled to the reference voltage terminal, a second input terminal of the voltage comparator is coupled to the feedback node, an output terminal of the voltage comparator is coupled to the control electrode of the first transistor and the control electrode of the second transistor, and an offset voltage exists between the second input terminal and the first input terminal of the voltage comparator; The driving circuit is configured to: generate a driving voltage according to the reference voltage and provide the driving voltage to the first electrode of the first transistor, wherein a voltage value of the driving voltage is equal to a voltage value of the reference voltage; The second electrode of the first transistor is coupled to the second end of the second capacitor; A first electrode of the second transistor is coupled to the second voltage terminal, and a second electrode of the second transistor is coupled to the first terminal of the third capacitor and the control electrode of the third transistor; The bias current source is configured to: provide a bias current to the first end of the third capacitor; The second terminal of the third capacitor is coupled to the second voltage terminal; A first electrode of the third transistor is coupled to the feedback node, and a second electrode of the third transistor is coupled to the second end of the second capacitor.

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