A driving circuit and a display panel

Abstract

This invention provides a driving circuit and a display panel. By setting a signal trigger conversion unit in the driving circuit, the signal trigger conversion unit can output a second enable signal based on the first enable signal output by the first-stage shift register. This enables the driving circuit to simultaneously output the first enable signal and the second enable signal with opposite levels, eliminating the need to add a new driving circuit to the display panel and thus reducing the power consumption of the display panel. Furthermore, the driving circuit provided by this invention has a simple structure, reducing the wiring difficulty of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display driving technology, and more specifically, to a driving circuit and a display panel. Background Technology

[0002] The bezel area of ​​the display device includes a driving circuit, and the display area of ​​the display device includes multiple pixel units. Each pixel unit includes a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit is electrically connected to the driving circuit in the bezel area. The driving circuit provides an enable signal to the pixel circuit to control the pixel circuit to provide driving current to the light-emitting element.

[0003] Pixel circuits are composed of transistors and capacitors. To improve pixel circuit performance, existing methods combine N-type and P-type transistors, such as LTPO (Low Temperature Polycrystalline Oxide) pixel circuits. These circuits require both a high-level enable signal to control the N-type transistors and a low-level enable signal to control the P-type transistors. However, current driver circuits can only provide a single-level enable signal and cannot simultaneously output both low-level and high-level enable signals. Therefore, two independent driver circuits are needed in the display device to provide the high-level and low-level enable signals respectively, increasing both power consumption and wiring complexity. Summary of the Invention

[0004] In view of this, the present invention provides a driving circuit and a display panel, which effectively solves the technical problems existing in the prior art. The driving circuit can realize the function of simultaneously outputting a first enable signal and a second enable signal with opposite levels, without the need to add a new driving circuit in the display panel, thereby reducing the power consumption of the display panel. Furthermore, the driving circuit provided by the present invention has a simple structure, which reduces the wiring difficulty of the display panel.

[0005] To achieve the above objectives, the technical solution provided by the present invention is as follows:

[0006] A driving circuit includes: a first-stage shift register, a second-stage shift register, and a signal trigger conversion unit;

[0007] The first-stage shift register and the second-stage shift register are cascaded, and the first-stage shift register and the second-stage shift register output the first enable signal in sequence;

[0008] The output terminal of the first-stage shift register is electrically connected to the first control terminal of the signal trigger conversion unit, and the output terminal of the second-stage shift register is electrically connected to the second control terminal of the signal trigger conversion unit. The signal trigger conversion unit is used to output a second enable signal triggered by a first enable signal output by the first-stage shift register, and to output a de-enable signal triggered by a first enable signal output by the second-stage shift register. The first enable signal and the second enable signal have opposite levels, and the first enable signal and the de-enable signal have the same level.

[0009] Accordingly, the present invention also provides a display panel, the display panel including the driving circuit described above.

[0010] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0011] This invention provides a driving circuit and a display panel. The driving circuit includes: a first-stage shift register, a second-stage shift register, and a signal trigger conversion unit. The first-stage shift register and the second-stage shift register are cascaded, and the first-stage shift register and the second-stage shift register sequentially output a first enable signal. The output terminal of the first-stage shift register is electrically connected to a first control terminal of the signal trigger conversion unit, and the output terminal of the second-stage shift register is electrically connected to a second control terminal of the signal trigger conversion unit. The signal trigger conversion unit is used to output a second enable signal triggered by the first enable signal output by the first-stage shift register, and to output a de-enable signal triggered by the first enable signal output by the second-stage shift register. The first enable signal and the second enable signal have opposite levels, and the first enable signal and the de-enable signal have the same level.

[0012] As can be seen from the above, the technical solution provided by the present invention, by setting a signal trigger conversion unit in the driving circuit, can output a second enable signal according to the first enable signal output by the first-stage shift register, so that the driving circuit can simultaneously output the first enable signal and the second enable signal with opposite levels, without the need to add a new driving circuit to the display panel, thereby reducing the power consumption of the display panel; and the driving circuit provided by the present invention has a simple structure, reducing the wiring difficulty of the display panel. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0014] Figure 1 A schematic diagram of a driving circuit provided in an embodiment of the present invention;

[0015] Figure 2 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0017] Figure 4 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0018] Figure 5 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0019] Figure 6 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0020] Figure 7 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0021] Figure 8 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0022] Figure 9 A timing diagram of a driving circuit provided in an embodiment of the present invention;

[0023] Figure 10 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0024] Figure 11 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0025] Figure 12 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0026] Figure 13 A timing diagram of a pixel circuit provided in an embodiment of the present invention;

[0027] Figure 14 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0028] Figure 15 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] As described in the background section, pixel circuits are composed of transistors and capacitors. To improve pixel circuit performance, existing methods combine N-type and P-type transistors, such as the LTPO pixel circuit. This requires both a high-level enable signal to control the N-type transistors and a low-level enable signal to control the P-type transistors. However, existing driver circuits can only provide a single-level enable signal and cannot simultaneously output both low-level and high-level enable signals. Therefore, two independent driver circuits are needed in the display device to provide the high-level and low-level enable signals respectively, increasing both power consumption and wiring complexity.

[0031] Based on this, embodiments of the present invention provide a driving circuit and a display panel, which effectively solve the technical problems existing in the prior art. The driving circuit can realize the function of simultaneously outputting a first enable signal and a second enable signal with opposite levels, without the need to add a new driving circuit in the display panel, thereby reducing the power consumption of the display panel. Furthermore, the driving circuit provided by the embodiments of the present invention has a simple structure, which reduces the wiring difficulty of the display panel.

[0032] To achieve the above objectives, the technical solutions provided by the embodiments of the present invention are as follows, in detail... Figures 1 to 15 The technical solutions provided in the embodiments of the present invention will be described in detail.

[0033] refer to Figure 1 The diagram shows a schematic of a driving circuit according to an embodiment of the present invention. The driving circuit includes a first-stage shift register 110, a second-stage shift register 120, and a signal trigger conversion unit 200. The first-stage shift register 110 and the second-stage shift register 120 are cascaded, that is, the output terminal of the first-stage shift register 110 is electrically connected to the input terminal of the second-stage shift register 120, and the first-stage shift register 110 and the second-stage shift register 120 sequentially output a first enable signal.

[0034] The output terminal of the first-stage shift register 110 is electrically connected to the first control terminal of the signal trigger conversion unit 200, and the output terminal of the second-stage shift register 120 is electrically connected to the second control terminal of the signal trigger conversion unit 200. The signal trigger conversion unit 200 is used to output a second enable signal SP2 triggered by a first enable signal output by the first-stage shift register 110, and to output a de-enable signal SPx triggered by a first enable signal output by the second-stage shift register 120. The first enable signal and the second enable signal SP2 have opposite levels, and the first enable signal and the de-enable signal SPx have the same level. That is, when the first enable signal is low, the second enable signal is high and the de-enable signal is low; and when the first enable signal is high, the first enable signal is low and the de-enable signal is high.

[0035] It is understood that the technical solution provided by the embodiments of the present invention, by setting a signal trigger conversion unit in the driving circuit, the signal trigger conversion unit can output a second enable signal according to the first enable signal output by the first-stage shift register, so that the driving circuit can realize the function of simultaneously outputting the first enable signal and the second enable signal with opposite levels, without the need to add a new driving circuit in the display panel, thereby reducing the power consumption of the display panel; and the driving circuit provided by the embodiments of the present invention has a simple structure, reducing the wiring difficulty of the display panel.

[0036] refer to Figure 2 The diagram shown is a schematic diagram of another driving circuit provided in an embodiment of the present invention. The signal triggering conversion unit 200 provided in the embodiment of the present invention includes: a first triggering module 210 and a second triggering module 220.

[0037] The input terminal of the first trigger module 210 is connected to the second enable signal SP2. The control terminal of the first trigger module 210 is the first control terminal of the signal trigger conversion unit 200, and the control terminal of the first trigger module 210 is electrically connected to the output terminal of the first-stage shift register 110. The input terminal of the second trigger module 220 is connected to the de-enable signal SPx. The control terminal of the second trigger module 220 is the second control terminal of the signal trigger conversion unit 200, and the control terminal of the second trigger module 220 is electrically connected to the output terminal of the second-stage shift register 120. The output terminals of the first trigger module 210 and the second trigger module 220 are electrically connected to form the output terminal of the signal trigger conversion unit 200.

[0038] Understandably, the signal triggering conversion unit provided in this embodiment of the invention has two triggering modules: a first triggering module and a second triggering module. The first triggering module responds to the control of the first enable signal output by the first-stage shift register and outputs a second enable signal. The signal triggering conversion unit maintains the output of the second enable signal until the second-stage shift register outputs the first enable signal. Then, the second-stage shift register outputs the first enable signal, and the second triggering module responds to the control of the first enable signal output by the second-stage shift register and outputs a de-enabled signal until the first-stage shift register outputs the first enable signal again, causing the signal triggering conversion unit to output the second enable signal again. Therefore, the driving circuit provided in this embodiment of the invention can output both a first enable signal and a second enable signal with opposite levels to control the conduction states of the N-type transistor and the P-type transistor in the pixel circuit, respectively.

[0039] refer to Figure 3 The diagram shows a schematic of another driving circuit provided in an embodiment of the present invention. The first trigger module 210 provided in this embodiment includes a first enable input circuit 211 and a first latch conversion circuit 212. The input terminal of the first enable input circuit 211 is connected to a first enable voltage Vk1. The control terminal of the first enable input circuit 211 is electrically connected to the output terminal of the first-stage shift register 110. The output terminal of the first enable input circuit 211 is electrically connected to the latch control terminal of the first latch conversion circuit 212. The input terminal of the first latch conversion circuit 212 is connected to a second enable signal SP2. The output terminal of the first latch conversion circuit 212 is electrically connected to the output terminal of the signal trigger conversion unit 200, i.e., the output terminal of the first latch conversion circuit 212 is the output terminal of the first trigger module 210.

[0040] Furthermore, the second trigger module 220 provided in this embodiment of the invention includes: a second enable input circuit 221 and a second latch conversion circuit 222; the input terminal of the second enable input circuit 221 is connected to a second enable voltage Vk2, the control terminal of the second enable input circuit 221 is electrically connected to the output terminal of the second-stage shift register 120, and the output terminal of the second enable input circuit 221 is electrically connected to the latch control terminal of the second latch conversion circuit 222; the input terminal of the second latch conversion circuit 222 is connected to the de-enable signal SPx, and the output terminal of the second latch conversion circuit 222 is electrically connected to the output terminal of the signal trigger conversion unit 200.

[0041] Understandably, in the first trigger module provided in this embodiment of the invention, the control terminal of the first enable input circuit is electrically connected to the output terminal of the first-stage shift register. Then, according to the first enable signal output by the first-stage shift register, the first enable voltage is transmitted to the latch control terminal of the first latch conversion circuit. The first enable voltage is latched by the first latch conversion circuit, and the first enable voltage controls the first latch conversion circuit to transmit a second enable signal to the output terminal of the signal trigger conversion unit. Until the second-stage shift register outputs the first enable signal, the second enable input circuit, according to the control of the first enable signal output by the second-stage shift register, transmits the second enable voltage to the control terminal of the second latch conversion circuit. The second enable voltage is latched by the second latch conversion circuit, and the second enable voltage controls the second latch conversion circuit to transmit a non-enable signal to the output terminal of the signal trigger conversion unit, thereby achieving the purpose of the drive circuit simultaneously outputting a first enable signal and a second enable signal with opposite levels.

[0042] Furthermore, to avoid crosstalk between the output of a second enable signal and a non-enable signal in the signal triggering conversion unit, the trigger module provided in this embodiment of the invention can also be equipped with a shutdown circuit to turn off the second trigger module when the first trigger module outputs a second enable signal, and to turn off the first trigger module when the second trigger module outputs a non-enable signal. See details. Figure 4 The diagram shows a schematic of another driving circuit provided in an embodiment of the present invention. The first trigger module 210 provided in this embodiment of the present invention further includes a first shutdown circuit 213, and / or the second trigger module 220 further includes a second shutdown circuit 223. The control terminal of the first shutdown circuit 213 is electrically connected to the output terminal of the first stage shift register 110, the input terminal of the first shutdown circuit 213 is connected to a first shutdown voltage Vo1, and the output terminal of the first shutdown circuit 213 is electrically connected to the latch control terminal of the second latch conversion circuit 222.

[0043] The control terminal of the second shutdown circuit 223 is electrically connected to the output terminal of the second-stage shift register 120, the input terminal of the second shutdown circuit 223 is connected to the second shutdown voltage Vo2, and the output terminal of the second shutdown circuit 223 is electrically connected to the latch control terminal of the first latch conversion circuit 212.

[0044] Understandably, in the first trigger module provided in this embodiment of the invention, the first enable input circuit controls the first enable voltage to be transmitted to the latch control terminal of the first latch conversion circuit according to the first enable signal output by the first stage shift register. At the same time, the first turn-off circuit controls the first turn-off voltage to be transmitted to the latch control terminal of the second latch conversion circuit according to the first enable signal output by the first stage shift register. The second latch conversion circuit latches the first turn-off voltage and remains in the off state in response to the control of the first turn-off voltage, so as to prevent the second latch conversion circuit from transmitting a non-enable signal to the output terminal of the signal trigger conversion unit. Until the output of the second-stage shift register outputs the first enable signal, the second enable input circuit, controlled by the first enable signal output by the second-stage shift register, transmits the second enable voltage to the latch control terminal of the second latch conversion circuit. At the same time, the second turn-off circuit, controlled by the first enable signal output by the second-stage shift register, transmits the second turn-off voltage to the latch control terminal of the first latch conversion circuit. The first latch conversion circuit latches the second turn-off voltage and remains in the off state in response to the control of the second turn-off voltage, preventing the first latch conversion circuit from transmitting the second enable signal to the output of the signal trigger conversion unit.

[0045] It should be noted that, in addition to being electrically connected to the output of the first-stage shift register, the control terminal of the first shutdown circuit provided by this invention can also be connected to an independent enable signal terminal or electrically connected to the output of other structures in other embodiments of this invention, as long as the enable signal connected to the control terminal of the first shutdown circuit has the same enable stage as the first enable signal output by the first-stage shift register. Similarly, in addition to being electrically connected to the output of the second-stage shift register, the control terminal of the second shutdown circuit provided by this invention can also be connected to an independent enable signal terminal or electrically connected to the output of other structures in other embodiments of this invention, as long as the enable signal connected to the control terminal of the second shutdown circuit has the same enable stage as the first enable signal output by the second-stage shift register. This invention does not impose specific limitations on this.

[0046] In one embodiment of the present invention, the first conversion module and the second conversion module provided by the present invention may be composed of at least one of electronic components such as transistors and capacitors, including the input circuit, latch conversion circuit, and shutdown circuit. See details. Figure 5The diagram shows a schematic of another driving circuit provided in an embodiment of the present invention. The first enable input circuit 211 provided in this embodiment includes a first transistor M1, and the first latch conversion circuit 212 includes a second transistor M2 and a first capacitor C1. The gate of the first transistor M1 is electrically connected to the output terminal of the first-stage shift register 110. The first terminal of the first transistor M1 is connected to the first enable voltage Vk1, and the second terminal of the first transistor M1 is electrically connected to the second plate of the first capacitor C1 and the gate of the second transistor M2. The first plate of the first capacitor C1 is connected to a reference voltage Vref. The first terminal of the second transistor M2 is connected to the second enable signal SP2, and the second terminal of the second transistor M2 is electrically connected to the output terminal of the signal trigger conversion unit 200.

[0047] refer to Figure 5 As shown, the second enable input circuit 221 provided in this embodiment of the invention includes a third transistor M3, and the second latch conversion circuit 222 includes a fourth transistor M4 and a second capacitor C2. The gate of the third transistor M3 is electrically connected to the output terminal of the second-stage shift register 120. The first terminal of the third transistor M3 is connected to the second enable voltage Vk2, and the second terminal of the third transistor M3 is electrically connected to the second plate of the second capacitor C2 and the gate of the fourth transistor M4. The first terminal of the fourth transistor M4 is connected to the de-enable signal SPx, and the second terminal of the fourth transistor M4 and the first plate of the second capacitor C2 are both electrically connected to the output terminal of the signal trigger conversion unit 200. Alternatively, the first plate of the second capacitor provided in this embodiment of the invention can also be connected to an auxiliary reference voltage, as detailed in the following reference. Figure 6 In the driving circuit shown, the first plate of the second capacitor C2 is connected to the auxiliary reference voltage Vref', which also enables the second capacitor C2 to latch the voltage at its second plate.

[0048] Continue to refer to Figure 5As shown, the first shutdown circuit 213 provided in this embodiment of the invention includes a fifth transistor M5, and the second shutdown circuit 223 includes a sixth transistor M6. The gate of the fifth transistor M5 is electrically connected to the output terminal of the first-stage shift register 110, the first terminal of the fifth transistor M5 is connected to the first shutdown voltage Vo1, and the second terminal of the fifth transistor M5 is electrically connected to the latch control terminal of the second latch conversion circuit 222, that is, the second terminal of the fifth transistor M5 is electrically connected to the gate of the fourth transistor M4 and the second plate of the second capacitor C2. The gate of the sixth transistor M6 is electrically connected to the output terminal of the second-stage shift register 120, the first terminal of the sixth transistor M6 is connected to the second shutdown voltage Vo2, and the second terminal of the sixth transistor M6 is electrically connected to the latch control terminal of the first latch conversion circuit 212, that is, the second terminal of the sixth transistor M6 is electrically connected to the gate of the second transistor M2 and the second plate of the first capacitor C1.

[0049] It should be noted that, in addition to being electrically connected to the output of the first-stage shift register, the gate of the fifth transistor provided by this invention can also be connected to an independent enable signal terminal or to the output of other structures in other embodiments of this invention, as long as the enable signal connected to the gate of the fifth transistor has the same enable stage as the first enable signal output by the first-stage shift register. Similarly, in addition to being electrically connected to the output of the second-stage shift register, the gate of the sixth transistor provided by this invention can also be connected to an independent enable signal terminal or to the output of other structures in other embodiments of this invention, as long as the enable signal connected to the gate of the sixth transistor has the same enable stage as the first enable signal output by the second-stage shift register. This invention does not impose specific limitations in this regard.

[0050] Understandably, the signal triggering conversion unit provided in this embodiment of the invention, when the first-stage shift register outputs a first enable signal, controls the first transistor and the fifth transistor to turn on. The first transistor transmits a first turn-on voltage to the second plate of the first capacitor for latching, and the second transistor turns on in response to the first turn-on voltage, transmitting a second enable signal to the output of the signal triggering conversion unit; and the fifth transistor transmits a first turn-off voltage to the second plate of the second capacitor for latching, and the fourth transistor turns off in response to the first turn-off voltage, preventing the fourth transistor from transmitting a non-enable signal to the output of the signal triggering conversion unit. This continues until the second-stage shift register outputs a first enable signal, controlling the third transistor and the sixth transistor to turn on. The third transistor transmits a second turn-on voltage to the second plate of the second capacitor for latching, and the fourth transistor turns on in response to the second turn-on voltage, transmitting a non-enable signal to the output of the signal triggering conversion unit; and the sixth transistor transmits a second turn-off voltage to the second plate of the first capacitor for latching, and the second transistor turns off in response to the second turn-off voltage, preventing the second transistor from transmitting a second enable signal to the output of the signal triggering conversion unit.

[0051] In one embodiment of the present invention, any one of the first to sixth transistors provided by the present invention can be an N-type transistor or a P-type transistor, and the present invention does not impose specific limitations on this. Optionally, the first, third, fifth, and sixth transistors provided in the embodiments of the present invention are all turned on in response to a first enable signal; therefore, the first, third, fifth, and sixth transistors have the same conduction type. Furthermore, the second and fourth transistors provided in the embodiments of the present invention can have the same conduction type as the aforementioned four transistors to facilitate the fabrication of transistors of the same type. (Reference) Figure 7 The diagram shows another driving circuit provided in an embodiment of the present invention. In this embodiment, when the second transistor M2 and the fourth transistor M4 have the same conduction type, the first turn-on voltage Vk1 and the second turn-on voltage Vk2 can be reused as the same turn-on voltage, and the first turn-off voltage Vo1 and the second turn-off voltage Vo2 can be reused as the same turn-off voltage. This reduces the number of voltage ports and simplifies the wiring structure of the driving circuit. Furthermore, the reference voltage Vref provided in this embodiment can be reused with the first turn-off voltage Vo1 and the second turn-off voltage Vo2 as the same turn-off voltage, further reducing the number of voltage ports.

[0052] refer to Figure 8The diagram shown is a schematic diagram of another driving circuit provided in an embodiment of the present invention. The first-stage shift register 110 and the second-stage shift register 120 provided in this embodiment of the present invention have the same composition structure. Any one of the shift registers in the first-stage shift register 110 and the second-stage shift register 120 includes: a first shift transistor MP1, a second shift transistor MP2, a third shift transistor MP3, a fourth shift transistor MP4, a fifth shift transistor MP5, a sixth shift transistor MP6, a seventh shift transistor MP7, an eighth shift transistor MP8, a first shift capacitor CP1, and a second shift capacitor CP2.

[0053] In the first-stage shift register 110: the gates of the first shift transistor MP1, the second shift transistor MP2, and the first terminal of the fourth shift transistor MP4 are all electrically connected to the first clock signal line CK. The first terminal of the first shift transistor MP1 is connected to the enable signal IN. The second terminal of the first shift transistor MP1 is electrically connected to the first terminal of the third shift transistor MP3, the gate of the fourth shift transistor MP4, and the first terminal of the fifth shift transistor MP5. The first terminal of the second shift transistor MP2 is connected to the first level VGL. The second terminal of the second shift transistor MP2 is electrically connected to the gates of the sixth shift transistor MP6, the eighth shift transistor MP8, the second terminal of the fourth shift transistor MP4, and the first plate of the second shift capacitor CP2. The gate of the third shift transistor MP3 is connected to the first level VGL. The second terminal of the third shift transistor MP3 is electrically connected to the first plate of the first shift capacitor CP1 and the gate of the seventh shift transistor MP7. The gate of the fifth shift transistor MP5 is electrically connected to the second clock signal line CKB. The second terminal of the fifth shift transistor MP5 is electrically connected to the first terminal of the sixth shift transistor MP6. The second terminal of the sixth shift transistor MP6, the second plate of the second shift capacitor CP2, and the second terminal of the eighth shift transistor MP8 are all connected to the second level VGH. The first terminal of the seventh shift transistor MP7 is electrically connected to the second clock signal line CKB. The second terminal of the seventh shift transistor MP7, the second plate of the first shift capacitor CP1, and the first terminal of the eighth shift transistor MP8 are all connected to the output terminal SP11 of the first-stage shift register 110. The clock signals output from the first clock signal line CPK and the second clock signal line CPKB are out of phase; the first level VGL and the second level VGH are opposite levels, i.e., when the first level VGL is low, the second level VGH is high; and when the first level VGL is high, the second level VGL is low. The third shift transistor MP3 is a normally open shift transistor controlled by the first level VGL.

[0054] Furthermore, in the second-stage shift register 120: the gates of the first shift transistor MP1, the second shift transistor MP2, and the first terminal of the fourth shift transistor MP4 are all electrically connected to the second clock signal line CKB. The first terminal of the first shift transistor MP1 is electrically connected to the output terminal SP11 of the first-stage shift register 110. The second terminal of the first shift transistor MP1 is electrically connected to the first terminal of the third shift transistor MP3, the gate of the fourth shift transistor MP4, and the first terminal of the fifth shift transistor MP5. The first terminal of the second shift transistor MP2 is connected to the first level VGL. The second terminal of the second shift transistor MP2 is electrically connected to the gates of the sixth shift transistor MP6, the eighth shift transistor MP8, the second terminal of the fourth shift transistor MP4, and the first plate of the second shift capacitor CP2. The gate of the third shift transistor MP3 is connected to the first level VGL. The second terminal of the third shift transistor MP3 is electrically connected to the first plate of the first shift capacitor CP1 and the gate of the seventh shift transistor MP7. The gate of the fifth shift transistor MP5 is electrically connected to the first clock signal line CK. The second terminal of the fifth shift transistor MP5 is electrically connected to the first terminal of the sixth shift transistor MP6. The second terminal of the sixth shift transistor MP6, the second plate of the second shift capacitor CP2, and the second terminal of the eighth shift transistor MP8 are all connected to the second level VGH. The first terminal of the seventh shift transistor MP7 is electrically connected to the first clock signal line CK. The second terminal of the seventh shift transistor MP7, the second plate of the first shift capacitor CP1, and the first terminal of the eighth shift transistor MP8 are all connected to form the output terminal SP12 of the second-stage shift register. The third shift transistor MP3 is a normally open shift transistor controlled by the first level VGL.

[0055] It should be noted that the first to eighth shift transistors provided in the embodiments of the present invention can be N-type transistors or P-type transistors, and the present invention does not impose specific limitations on them. The following is in conjunction with... Figure 8 and Figure 9 The working process of the driving circuit provided in the embodiments of the present invention will be described in detail, wherein... Figure 9 This is a timing diagram of a driving circuit provided in an embodiment of the present invention. For ease of description, this embodiment of the present invention uses an example in which all transistors in the driving circuit are P-type transistors. The first level VGL is low, the second level VGH is high, the first enable signal is low, the second enable signal SP2 is high, and the disable signal SPx is low. The operation of the driving circuit includes a first stage T1, a second stage T2, and a third stage T3 performed sequentially.

[0056] In the first stage T1, the first clock signal line CK outputs a low level, the second clock signal line CKB outputs a high level, and the enable signal IN is low. At this time, in the first-stage shift register 110: the fifth shift transistor MP5 is off, while the first shift transistor MP1, the second shift transistor MP2, the fourth shift transistor MP4, the sixth shift transistor MP6, the seventh shift transistor MP7, and the eighth shift transistor MP8 are all on. The output terminal SP11 outputs the second clock signal line CKB and the second level VGH at a high level.

[0057] In the second stage T2, the first clock signal line CK outputs a high level, the second clock signal line CKB outputs a low level, and the enable signal IN is converted to a high level. At this time, in the first-stage shift register 110: the first shift transistor MP1, the second shift transistor MP2, the sixth shift transistor MP6, and the eighth shift transistor MP8 are all off; the fifth shift transistor MP5 is turned on due to the low level of the second clock signal line CKB; and, due to the function of the first shift capacitor CP1 in maintaining the node potential, the fourth shift transistor MP4 and the seventh shift transistor MP7 are turned on. The output terminal SP11 outputs a low level of the second clock signal line CKB, that is, the output terminal SP11 outputs the first enable signal. The first enable signal output by the output terminal SP11 controls the first transistor M1 and the fifth transistor M5 to turn on. The first transistor M1 transmits the first turn-on voltage Vk1 to the first capacitor C1 and the gate of the second transistor M2, controlling the second transistor M2 to turn on so as to transmit the second enable signal SP2 to the output terminal OUT of the signal trigger conversion unit. Furthermore, in the second-stage shift register 120: the fifth shift transistor MP5 is turned off, while the first shift transistor MP1, the second shift transistor MP2, the fourth shift transistor MP4, the sixth shift transistor MP6, the seventh shift transistor MP7, and the eighth shift transistor MP8 are all turned on, and the output terminal SP12 outputs the first clock signal line CK and the high level of the second level VGH.

[0058] In the third stage T3, the first clock signal line CK outputs a low level, the second clock signal line CKB outputs a high level, and the enable signal IN is high. At this time, in the first-stage shift register 110: the fourth shift transistor MP4, the fifth shift transistor MP5, and the seventh shift transistor MP7 are all off, while the first shift transistor MP1, the second shift transistor MP2, the sixth shift transistor MP6, and the eighth shift transistor MP8 are all on, and the output terminal SP11 outputs a high level of the second level VGH. In the second-stage shift register 120: the first shift transistor MP1, the second shift transistor MP2, the sixth shift transistor MP6, and the eighth shift transistor MP8 are all off, the fifth shift transistor MP5 is on due to the low level of the second clock signal line CKB; and, due to the function of the first shift capacitor CP1 in maintaining the node potential, the fourth shift transistor MP4 and the seventh shift transistor MP7 are on, and the output terminal SP12 outputs a low level of the first clock signal line CK, that is, the output terminal SP12 outputs the first enable signal. The first enable signal output from the output terminal SP12 controls the third transistor M3 and the sixth transistor M6 to turn on. The third transistor M3 transmits the second turn-on voltage Vk2 to the second capacitor C1 and the gate of the fourth transistor M4, controlling the fourth transistor M4 to turn on so as to transmit the non-enable signal SPx to the output terminal OUT of the signal trigger conversion unit.

[0059] It should be noted that the shift register provided in the embodiments of the present invention is not limited to the above-described types. Figure 8 The components and connection structures shown may be used for other circuit structures in other embodiments of the present invention, depending on the specific application.

[0060] Accordingly, embodiments of the present invention also provide a display panel, the display panel including the aforementioned driving circuit. (See reference) Figure 10 The diagram shown is a schematic representation of a display panel according to an embodiment of the present invention. The display panel includes a display area AA and a border area NA surrounding the display area AA. The border area NA surrounds the display area AA. The border area NA includes a driving circuit 10 as described in any of the above embodiments.

[0061] Optionally, the driving circuit 10 provided in the embodiments of the present invention can be disposed on at least one side of the display area AA in the first direction X; and the border area NA further includes a chip bonding area 20, which is disposed on one side of the display area AA in the second direction Y, wherein the first direction X and the second direction Y are perpendicular.

[0062] refer to Figure 11The diagram shows another display panel structure provided in an embodiment of the present invention. The display panel provided in this embodiment includes cascaded first-stage driving circuits 101 to Nth-stage driving circuits 10n, where N is an integer greater than or equal to 2. The first-stage shift register 110 of the (i+1)th-stage driving circuit reuses the second-stage shift register 120 of the i-th-stage driving circuit, where i is an integer greater than 0 and less than N. Taking the first-stage driving circuit 101 and the second-stage driving circuit 102 as examples, the second-stage shift register 120 of the first-stage driving circuit 101 is also reused as the first-stage shift register 110 of the second-stage driving circuit 102. Therefore, in conjunction with the appendix... Figure 8 and Figure 9 The operation of the driving circuit shown is as follows: when the first-stage shift register 110 of the first-stage driving circuit 101 outputs the first enable signal, the signal trigger conversion unit 200 of the first-stage driving circuit 101 outputs the second enable signal; then when the first-stage shift register 110 of the second-stage driving circuit 101 outputs the first enable signal, the signal trigger conversion unit 200 of the second-stage driving circuit 101 outputs the second enable signal, and so on, with the first-stage driving circuit 101 to the Nth-stage driving circuit 10n outputting the first enable signal and the second enable signal step by step.

[0063] refer to Figure 12 The diagram shown is a schematic representation of a pixel circuit according to an embodiment of the present invention. The pixel circuit includes a driving transistor M0, a reset transistor Mf, an auxiliary reset transistor Mff, a data writing transistor Md, a connection transistor Mj, a first light-emitting control transistor Me1, a second light-emitting control transistor Me2, and a storage capacitor C. The pixel circuit is an LTPO pixel circuit. The reset transistor Mf and the connection transistor Mj can be N-type transistors, while the driving transistor M0, the auxiliary reset transistor Mff, the data writing transistor Md, the first light-emitting control transistor Me1, and the second light-emitting control transistor Me2 are P-type transistors.

[0064] The gate of reset transistor Mf is connected to the reset control signal Sf, and the first terminal of reset transistor Mf is connected to the reset voltage Vref. The second terminal of reset transistor MF is electrically connected to the gate of driving transistor M0. The gate of auxiliary reset transistor Mff is connected to the auxiliary reset control signal Sff, the first terminal of auxiliary reset transistor Mff is connected to the auxiliary reset voltage Vreff, and the second terminal of auxiliary reset transistor Mff is electrically connected to the anode of light-emitting element 700. The gate of data writing transistor Md is connected to the data control signal Sd, the first terminal of data writing transistor Md is connected to the data voltage Vdata, and the second terminal of data writing transistor Md is electrically connected to the first terminal of driving transistor M0. The first terminal of connection transistor Mj is electrically connected to the second terminal of driving transistor M0, the second terminal of connection transistor Mj is electrically connected to the gate of driving transistor M0, and the gate of connection transistor Mj is connected to the connection control signal Sj. One end of the first light-emitting control transistor Me1 is electrically connected to the power supply voltage terminal Vpvdd. The second end of the first light-emitting control transistor Me1 is electrically connected to the first end of the driving transistor M0. The first end of the second light-emitting control transistor Me2 is electrically connected to the first end of the driving transistor M0. The second end of the second light-emitting control transistor Me2 is electrically connected to the anode terminal of the light-emitting element. The cathode terminal of the light-emitting element is electrically connected to the cathode voltage terminal Vpvee. The gates of both the first and second light-emitting control transistors Me1 and Me2 are connected to the light-emitting control signal EMIT. The two plates of the storage capacitor C are electrically connected to the power supply voltage terminal Vpvdd and the gate of the driving transistor M0, respectively.

[0065] It should be noted that the pixel circuit provided in the embodiments of the present invention is not limited to the transistor structure described above. In other embodiments of the present invention, the pixel circuit may also be other connection structures. (See references) Figure 13 The diagram shown is a timing diagram of a pixel circuit provided in an embodiment of the present invention. The operation of the pixel circuit includes a reset phase Tx1, a data writing phase Tx2, and a light emission control phase Tx3 performed sequentially, wherein:

[0066] During the reset phase Tx1, the reset control signal Sf is enabled at a high level, the auxiliary reset control signal Sff is enabled at a low level, the reset transistor Mf and the auxiliary reset transistor Mff are turned on, the reset transistor Mf transmits the reset voltage Vref to the gate of the driving transistor M0 for reset, and the auxiliary reset transistor Mff transmits the auxiliary reset voltage Vreff to the anode of the light-emitting element for reset.

[0067] During the data writing stage Tx2, the data control signal Sd is enabled at a low level, the connection control signal Sj is enabled at a high level, and the data writing transistor Md and the connection transistor Mj are turned on so that the data voltage Vdata is transmitted to the gate of the driving transistor M0 through the data writing transistor Md, the driving transistor M0 and the connection transistor Mj.

[0068] During the light emission control stage Tx3, the light emission control signal EMIT is enabled at a low level, and the first light emission control transistor Me1 and the second light emission control transistor Me2 are turned on to transmit the driving current generated by the driving transistor M0 to the light emission element, which then emits light in response to the driving current.

[0069] Therefore, the LTPO pixel circuit provided in this embodiment of the invention first requires a set of high-level and low-level enable signals to control the N-type reset transistor and the P-type auxiliary reset transistor to conduct, respectively; and then requires a set of high-level and low-level enable signals to control the N-type connection transistor and the data write transistor to conduct, respectively. Thus, when the first enable signal is low and the second enable signal is high, in adjacent driving circuits, the first and second enable signals of the previous driving circuit can enable and control the auxiliary reset transistor and the reset transistor of the LTPO pixel circuit, respectively, and the first and second enable signals of the next driving circuit can enable and control the connection transistor and the data write transistor of the LTPO pixel circuit, respectively. See details. Figure 14 The diagram shown illustrates the structure of another display panel according to an embodiment of the present invention. The display area AA of the display panel includes pixels in rows P1 to P(n-1) in rows N-1. Each row of pixels Pi includes multiple pixel circuits (not shown). Each row of pixels includes a reset control terminal Sf', an auxiliary reset control terminal Sff', a data control terminal Sd', and a connection control terminal Sj'. The reset control signal for each pixel circuit in each row is provided by the reset control terminal Sf', the auxiliary reset control signal is provided by the auxiliary reset control terminal Sff', the data control signal is provided by the data control terminal Sd', and the connection control signal is provided by the connection control terminal Sj'. The reset control signal and the connection control signal are enabled when they are high, and the data control signal and the auxiliary reset control signal are enabled when they are low. The first enable signal is a low-level signal, and the second enable signal is a high-level signal.

[0070] In the adjacent i-th and (i+1)-th driving circuits, the output of the first-stage shift register 110 of the i-th driving circuit is electrically connected to the auxiliary reset control terminal Sff' of the i-th row pixel, and the output of the signal trigger conversion unit 200 of the i-th driving circuit is electrically connected to the reset control terminal Sf' of the i-th row pixel. Similarly, the output of the first-stage bit register 110 of the (i+1)-th driving circuit is electrically connected to the data control terminal Sd' of the i-th row pixel, and the output of the signal trigger conversion unit 200 of the (i+1)-th driving circuit is electrically connected to the connection control terminal Sj' of the i-th row pixel, where i is an integer greater than 0 and less than N.

[0071] Understandably, taking the first-stage driving circuit and the second-stage driving circuit as examples, the first-stage driving circuit simultaneously outputs a first enable signal and a second enable signal to provide an auxiliary reset control signal and a reset control signal to effectively enable the first row of pixels, controlling the pixel circuit of the first row of pixels to perform the reset phase operation; then, the second-stage driving circuit simultaneously outputs a first enable signal and a second enable signal to provide a data control signal and a connection control signal to effectively enable the first row of pixels, controlling the pixel circuit of the first row of pixels to perform the data writing phase operation, and so on, to complete the scanning control of all rows of pixels.

[0072] refer to Figure 15 The diagram shown is a structural schematic of another display panel provided in an embodiment of the present invention, wherein the display panel 1000 provided in this embodiment of the present invention can be applied to a mobile terminal.

[0073] It should be noted that the display panel provided in the embodiments of the present invention can also be applied to laptops, tablets, computers, wearable devices, etc., and the present invention does not impose specific limitations on them.

[0074] This invention provides a driving circuit and a display panel. The driving circuit includes a first-stage shift register, a second-stage shift register, and a signal trigger conversion unit. The first-stage shift register and the second-stage shift register are cascaded, and the first-stage shift register and the second-stage shift register sequentially output a first enable signal. The output terminal of the first-stage shift register is electrically connected to a first control terminal of the signal trigger conversion unit, and the output terminal of the second-stage shift register is electrically connected to a second control terminal of the signal trigger conversion unit. The signal trigger conversion unit is used to output a second enable signal triggered by the first enable signal output by the first-stage shift register, and to output a de-enable signal triggered by the first enable signal output by the second-stage shift register. The first enable signal and the second enable signal have opposite levels, and the first enable signal and the de-enable signal have the same level.

[0075] As can be seen from the above, the technical solution provided by the embodiments of the present invention, by setting a signal trigger conversion unit in the driving circuit, the signal trigger conversion unit can output a second enable signal according to the first enable signal output by the first-stage shift register, so that the driving circuit can realize the function of simultaneously outputting the first enable signal and the second enable signal with opposite levels, without the need to add a new driving circuit in the display panel, thereby reducing the power consumption of the display panel; and the driving circuit provided by the embodiments of the present invention has a simple structure, reducing the wiring difficulty of the display panel.

[0076] In the description of this invention, it should be understood that terms such as "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0077] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0078] In this invention, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between components; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0079] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0080] In this invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0081] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A driving circuit, characterized in that, include: First-stage shift register, second-stage shift register, and signal trigger conversion unit; The first-stage shift register and the second-stage shift register are cascaded, and the first-stage shift register and the second-stage shift register output the first enable signal in sequence; The output terminal of the first-stage shift register is electrically connected to the first control terminal of the signal trigger conversion unit, and the output terminal of the second-stage shift register is electrically connected to the second control terminal of the signal trigger conversion unit. The signal trigger conversion unit is used to output a second enable signal triggered by a first enable signal output by the first-stage shift register, and to output a de-enable signal triggered by a first enable signal output by the second-stage shift register. The first enable signal and the second enable signal have opposite levels, and the first enable signal and the de-enable signal have the same level. The signal triggering conversion unit includes: a first triggering module and a second triggering module; The input terminal of the first trigger module is connected to the second enable signal, the control terminal of the first trigger module is the first control terminal of the signal trigger conversion unit, and the control terminal of the first trigger module is electrically connected to the output terminal of the first stage shift register. The input terminal of the second trigger module is connected to the non-enable signal, the control terminal of the second trigger module is the second control terminal of the signal trigger conversion unit, the control terminal of the second trigger module is electrically connected to the output terminal of the second stage shift register, and the output terminal of the first trigger module and the output terminal of the second trigger module are electrically connected to the output terminal of the signal trigger conversion unit. The first trigger module includes: a first enable input circuit and a first latch conversion circuit; The input terminal of the first enable input circuit is connected to the first enable voltage, the control terminal of the first enable input circuit is electrically connected to the output terminal of the first stage shift register, and the output terminal of the first enable input circuit is electrically connected to the latch control terminal of the first latch conversion circuit. The input terminal of the first latch conversion circuit is connected to the second enable signal, and the output terminal of the first latch conversion circuit is electrically connected to the output terminal of the signal trigger conversion unit.

2. The driving circuit according to claim 1, characterized in that, The first enable input circuit includes a first transistor, and the first latch conversion circuit includes a second transistor and a first capacitor; The gate of the first transistor is electrically connected to the output of the first stage shift register, the first terminal of the first transistor is connected to the first turn-on voltage, the second terminal of the first transistor is electrically connected to the second plate of the first capacitor and the gate of the second transistor, and the first plate of the first capacitor is connected to the reference voltage. The first terminal of the second transistor is connected to the second enable signal, and the second terminal of the second transistor is electrically connected to the output terminal of the signal trigger conversion unit.

3. The driving circuit according to claim 1, characterized in that, The second trigger module includes: a second enable input circuit and a second latch conversion circuit; The input terminal of the second enable input circuit is connected to the second enable voltage, the control terminal of the second enable input circuit is electrically connected to the output terminal of the second stage shift register, and the output terminal of the second enable input circuit is electrically connected to the latch control terminal of the second latch conversion circuit. The input terminal of the second latch conversion circuit is connected to the non-enable signal, and the output terminal of the second latch conversion circuit is electrically connected to the output terminal of the signal trigger conversion unit.

4. The driving circuit according to claim 3, characterized in that, The second enable input circuit includes a third transistor, and the second latch conversion circuit includes a fourth transistor and a second capacitor; The gate of the third transistor is electrically connected to the output of the second-stage shift register, the first terminal of the third transistor is connected to the second turn-on voltage, and the second terminal of the third transistor is electrically connected to the second plate of the second capacitor and the gate of the fourth transistor. The first terminal of the fourth transistor is connected to the non-enable signal, and the second terminal of the fourth transistor and the first plate of the second capacitor are both electrically connected to the output terminal of the signal trigger conversion unit; or, the first plate of the second capacitor is connected to an auxiliary reference voltage.

5. The driving circuit according to claim 3, characterized in that, The first trigger module further includes a first shutdown circuit, and / or the second trigger module further includes a second shutdown circuit; The control terminal of the first shutdown circuit is electrically connected to the output terminal of the first-stage shift register, the input terminal of the first shutdown circuit is connected to the first shutdown voltage, and the output terminal of the first shutdown circuit is electrically connected to the latch control terminal of the second latch conversion circuit. The control terminal of the second shutdown circuit is electrically connected to the output terminal of the second-stage shift register, the input terminal of the second shutdown circuit is connected to the second shutdown voltage, and the output terminal of the second shutdown circuit is electrically connected to the latch control terminal of the first latch conversion circuit.

6. The driving circuit according to claim 5, characterized in that, The first shutdown circuit includes a fifth transistor, and the second shutdown circuit includes a sixth transistor; The gate of the fifth transistor is electrically connected to the output terminal of the first-stage shift register, the first terminal of the fifth transistor is connected to the first turn-off voltage, and the second terminal of the fifth transistor is electrically connected to the latch control terminal of the second latch conversion circuit. The gate of the sixth transistor is electrically connected to the output of the second-stage shift register, the first terminal of the sixth transistor is connected to the second turn-off voltage, and the second terminal of the sixth transistor is electrically connected to the latch control terminal of the first latch conversion circuit.

7. A display panel, characterized in that, The display panel includes the driving circuit according to any one of claims 1-6.

8. The display panel according to claim 7, characterized in that, The display panel includes all the driving circuits that are cascaded from the first stage driving circuit to the Nth stage driving circuit, where N is an integer greater than or equal to 2; The first-stage shift register of the (i+1)th stage driver circuit reuses the second-stage shift register of the i-th stage driver circuit, where i is an integer greater than 0 and less than N.

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