Display module

Abstract

The present disclosure relates to a source driving integrated circuit for display module and a display module, the source driving integrated circuit comprising a data signal output end and a privacy signal output end arranged integrally, the data signal output end being used for outputting display signals, and the privacy signal output end being used for outputting privacy signals, so that the source driving integrated circuit can be used to arrange the output ends for outputting the display signals and the privacy signals integrally, the space on the source driving integrated circuit and the output pins thereof can be utilized fully, and thus the privacy signal circuit can be arranged separately, the space occupation of the circuit board layout area is reduced, the size of the circuit board is reduced, and the miniaturization design of the display module is facilitated.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a display module. BACKGROUND

[0002] In the information age, users have higher and higher requirements for the security of terminal devices. Among many display technologies, the importance of anti-peep display is increasingly prominent for terminal devices used for display. Anti-peep display limits the display angle of a display screen within a certain range, so that a complete display image can only be observed within a certain viewing angle range, and outside the viewing angle range, the display image cannot be observed or a distorted display image can be observed, thereby ensuring the information security of the user of the terminal device.

[0003] In the current anti-peep display, a circuit for generating an anti-peep signal usually needs to be arranged in a printed circuit board. The circuit occupies a certain space in the printed circuit board, increases the space occupation of the circuit board layout area, is not conducive to the reduction of the size of the circuit board, and is not conducive to the miniaturization design of the display module using the circuit board. SUMMARY

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a source drive integrated circuit for a display module and a display module.

[0005] The present disclosure provides a source drive integrated circuit for a display module, comprising: a data signal output end and an anti-peep signal output end arranged integrally, the data signal output end being used for outputting a display signal, and the anti-peep signal output end being used for outputting an anti-peep signal.

[0006] The present disclosure also provides a display module comprising the above source drive integrated circuit.

[0007] The technical solution provided by the present disclosure has the following advantages compared with the prior art:

[0008] In the source drive integrated circuit for a display module and the display module provided by the present disclosure, the source drive integrated circuit comprises a data signal output end and an anti-peep signal output end arranged integrally, the data signal output end is used for outputting a display signal, and the anti-peep signal output end is used for outputting an anti-peep signal. Thus, the output ends for outputting the display signal and the anti-peep signal can be arranged integrally by using the source drive integrated circuit, the space on the source drive integrated circuit and the output pins thereof can be fully utilized, thereby avoiding the separate arrangement of an anti-peep signal circuit, reducing the space occupation of the circuit board layout area, being conducive to the reduction of the size of the circuit board, and further being conducive to the miniaturization design of the display module. BRIEF DESCRIPTION OF DRAWINGS

[0009] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the disclosure.

[0010] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, those skilled in the art can further obtain other drawings according to these drawings without any creative effort.

[0011] Figure 1 A structural schematic diagram of a display module provided by the related art is shown;

[0012] Figure 2 A structural schematic diagram of a peep-proof driving circuit provided by the related art is shown;

[0013] Figure 3 A structural schematic diagram of a source driving integrated circuit provided by the embodiments of the present disclosure is shown;

[0014] Figure 4 A structural schematic diagram of another source driving integrated circuit provided by the embodiments of the present disclosure is shown;

[0015] Figure 5 A structural schematic diagram of still another source driving integrated circuit provided by the embodiments of the present disclosure is shown;

[0016] Figure 6 A structural schematic diagram of still another source driving integrated circuit provided by the embodiments of the present disclosure is shown;

[0017] Figure 7 A structural schematic diagram of a display module provided by the embodiments of the present disclosure is shown;

[0018] Figure 8 A peep-proof timing diagram provided by the embodiments of the present disclosure is shown;

[0019] Figure 9 A structural schematic diagram of another display module provided by the embodiments of the present disclosure is shown;

[0020] Figure 10 A structural schematic diagram of a gating circuit provided by the embodiments of the present disclosure is shown;

[0021] Figure 11 Another peep-proof timing diagram provided by the embodiments of the present disclosure is shown;

[0022] Figure 12 A structural schematic diagram of still another display module provided by the embodiments of the present disclosure is shown;

[0023] Figure 13 A structural schematic diagram of a privacy driving circuit provided by an embodiment of the present disclosure is shown.

[0024] In the related art: 01, liquid crystal display panel (Liquid Crystal Display, LCD); 02, rigid circuit board, i.e. printed circuit board (Printed Circuit Board, PCB), which can also be referred to as circuit board; 03, flexible circuit board, i.e. flexible printed circuit board (Flex Printed Circuit Board, FPCB or FPC); 011, display area; 012, source driving integrated circuit; 021, display driving circuit; 022, privacy driving circuit; 023, backlight driving circuit; 024, VCOM driving circuit; 025, connector for display, which can be referred to as B / L CNT; 0220, connector for privacy signal, which can be referred to as CNT; 0221, single-chip microcomputer; 0222, storage module; 0223, level conversion module;

[0025] In the present disclosure: 10, source driving integrated circuit, which can be referred to as Source IC; 101, signal input end; 102, data signal output end; 103, privacy signal output end; 21, display panel; 22, rigid circuit board; 23, flexible circuit board; 211, display area; 212, non-display area; 221, timing controller; 222, connector; 223, storage module; 224, level conversion circuit; 225, gating circuit; M0, control switch; M1, data switch; M11, first data switch; M12, second data switch; M13, third data switch; 226, micro control unit (Micro Controller Unit, MCU). DETAILED DESCRIPTION

[0026] In order to more clearly understand the above-mentioned purposes, features and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0027] In the following description, many specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure can also be implemented in other ways different from those described herein; obviously, the embodiments in the description are only some of the embodiments of the present disclosure, not all the embodiments.

[0028] First, the related art of the present disclosure will be described in combination with Figure 1 and Figure 2 The privacy display in the related art is exemplarily described, and the technical problems existing therein and the improvements made by the embodiments of the present disclosure to solve the technical problems are further clarified.

[0029] In the related art, the privacy display mainly includes white-state privacy display and black-state privacy display. The white-state privacy display can be realized by increasing the vertical electric field to make the liquid crystal rise and the dark-state light leakage at large viewing angle increase, thereby the contrast ratio decreases rapidly. The black-state privacy display can be realized by adding a privacy film and a dimming film in the backlight. The technical solution proposed in the embodiments of the present disclosure is mainly improved for the white-state privacy display.

[0030] Exemplarily, Figure 1 A structure diagram of a display module in the related art is shown, taking a medium-size privacy display as an example, wherein the functional modules of the display module and their spatial relative position relationship are specifically shown. In other structure display modules, other forms of privacy display driving circuit can also be constructed, which is not discussed in the present embodiment. As shown in the figure, Figure 1 The display module can include a liquid crystal display panel 01, a printed circuit board 02 and a flexible circuit board 03. The printed circuit board 02 is connected to the liquid crystal display panel 01 through the flexible circuit board 03 to transmit display signals to the liquid crystal display panel 01 by using the lines in the flexible circuit board 03. The display signals can include display driving signals, backlight driving signals, privacy driving signals, common electrode signals and other signals known to those skilled in the art, which are not described and limited here. The liquid crystal display panel 01 can include a display area 011 and a non-display area adjacent to at least one side of the display area. The non-display area is used to place the peripheral wiring and circuit. Exemplarily, a source driving integrated circuit 012 is located in the non-display area. The number and position of the flexible circuit board 03 can be set based on the wiring requirements of the display module. Exemplarily, Figure 1Three flexible circuit boards 03 are shown in the middle, respectively identified as FPC1-1, FPC1-2 and FPC2. The printed circuit board 02 is provided with a display driving circuit 021, an anti-peep driving circuit 022, a backlight driving circuit 023, a VCOM driving circuit 024 and a B / L CNT 025; the display driving circuit 021 includes an interaction module, a level shift module, a timing control module, a storage module and a power management module; the interaction module can be a connector for connecting the main processor for transmitting the internal circuit module processable signal converted by the main processor for external interaction signal; the level shift module can be a level shift circuit for outputting a level signal meeting the use requirement; the timing control module can be a timing controller for controlling the line synchronization and field synchronization of the display signal; the storage module is used for storing display parameters and associated relationships, and the storage module can be any kind of memory; the power management module can be a power management chip for outputting a power signal. The backlight driving circuit 023 can include one, two or more backlight driving modules, when the backlight uses a light emitting diode (Light Emitting Diode, LED), the backlight driving module can correspond to an LED driving module. The VCOM driving circuit 024 can include a VCOM driving module for providing a common electrode signal. The anti-peep driving circuit 022 can include a storage module, a single-chip microcomputer and a level shift module (OPQC is shown in the figure); based on this, the anti-peep signal is transmitted to the liquid crystal display panel 01 through the flexible circuit board 03 after being amplified by a level shift module through the addition of an anti-peep timing generation module on the architecture of the printed circuit board 02; wherein the anti-peep driving circuit 022 and the display driving circuit 021 also need to be synchronized through a synchronization (sync) signal.

[0031] Exemplarily, Figure 2 A kind of anti-peep driving circuit in the prior art is shown, wherein the connection relationship between the components in the anti-peep driving circuit and the corresponding signal transmission relationship are specifically shown. As Figure 2 As shown, external control I / O port ( Figure 2The switch of the privacy state is implemented (as shown by the connector 0220); the privacy state can include a privacy state and a sharing state, and the transmission of the privacy state corresponding signal can be implemented based on a 24-pin (Pin24). Correspondingly, the single-chip microcomputer 0221 receives the privacy state corresponding signal and generates a privacy signal waveform. The switch of the privacy waveform is implemented through the communication between the single-chip microcomputer 0221 and the storage module 0222, and the potential of the privacy signal waveform generated by the single-chip microcomputer 0221 is low, so a level conversion module 0223 needs to be added to perform voltage conversion, so that the voltage transmitted to the liquid crystal display panel 01 reaches the corresponding level. The privacy electrode can be formed by using an ITO electrode layer, and the corresponding driving signal can be represented as an ITO signal; CSCL represents a serial clock signal, which is used to generate a synchronous clock pulse, and CSDA represents a serial data signal, which is used to transmit serial data. CSCL and CSDA are signals transmitted by an IIC bus.

[0032] Based on the above, in the related art, in order to realize privacy display, a separate privacy driving circuit needs to be added, which can cause the following problems:

[0033] First, due to the additional privacy driving circuit, the hardware cost is relatively high.

[0034] Second, since the privacy driving circuit is arranged in the printed circuit board, the layout area of the printed circuit board is increased, which is not conducive to the reduction of the size of the printed circuit board and the miniaturization design of the display module.

[0035] Third, since the privacy driving circuit and the display driving circuit need to be additionally synchronized, it is inconvenient for factory line testing.

[0036] Fourth, the current privacy enablement is only provided with one pin to realize simple privacy switch switching, that is, only switching between turning on and turning off the privacy exists. The privacy function realized based on this is single, and the signal of the privacy cannot be adjusted, which cannot flexibly meet the privacy requirements under different ambient light.

[0037] Fifth, it cannot meet the privacy requirements of multi-view angle adjustment.

[0038] To solve at least one of the above technical problems, the present disclosure provides a source driving integrated circuit and a display module to provide a low-cost, less-occupied, convenient factory line electrical measurement, and multi-view angle adjustable anti-peep display solution. In the present disclosure, the circuit (or module) in the display driving circuit is multiplexed in the anti-peep driving circuit, for example, the source driving integrated circuit is multiplexed, which reduces the increase of components in the hardware circuit structure, thereby saving the hardware cost, and reducing the occupation of the printed circuit board layout area, which is conducive to the reduction of the size of the printed circuit board, and thus conducive to the miniaturization design of the display module. In some embodiments, the timing of the anti-peep signal can also be controlled by the existing timing controller to achieve synchronization with the display without setting additional synchronization signals, thereby facilitating factory line electrical measurement. In some embodiments, the size of the anti-peep signal can also be adjusted, that is, multi-gray scale (corresponding to multiple gears or multiple voltages) adjustment is achieved, so that the size of the signal transmitted to the ITO anti-peep electrode can be adjusted, so that the liquid crystal molecules deflect at different angles, and the diversity of the anti-peep display effect is achieved; and through gray scale adjustment, multiple anti-peep viewing angle adjustments of different gears can be achieved, thereby flexibly meeting the anti-peep requirements under different ambient light.

[0039] It should be noted that the circuit module in the present disclosure can be implemented in the form of an integrated circuit chip. The anti-peep display in the present disclosure refers to the display picture that can only be seen at the normal viewing angle, and the normal display picture cannot be seen at other angles; and the multi-view angle in the present disclosure refers to the anti-peep viewing angle for different environments.

[0040] The source driving integrated circuit and the display module provided by the present disclosure will be described below with reference to the accompanying drawings.

[0041] Exemplarily, Figure 3 、 Figure 4 、 Figure 5 and Figure 6 respectively show the source driving integrated circuits of different structures, and the spatial relative position relationship of each different function pin is shown in detail. As Figures 3-6 As shown in any of the figures, the display module using the source driving integrated circuit 10 can include: an integrated data signal output end 102 and an anti-peep signal output end 103, the data signal output end 102 is used to output a display signal, and the anti-peep signal output end 103 is used to output an anti-peep signal.

[0042] With this configuration, the source driver integrated circuit 10 for the display module provided in this embodiment integrates the output terminals for both the display signal and the privacy signal. This allows for full utilization of the space on the source driver integrated circuit 10 and its output pins, thereby avoiding the need for a separate privacy signal circuit, reducing the space occupied by the circuit board layout area, facilitating the reduction of the circuit board size, and ultimately contributing to the miniaturization of the display module design. Specifically, by outputting the privacy signal through the privacy signal output terminal 103 in the source driver integrated circuit 10 for the display module, the fixed-level privacy signal input from the signal input terminal 101 can be directly boosted to a target-level privacy signal suitable for use on the display panel, and then output to the display panel via the privacy signal output terminal 103. This eliminates the need for additional level converters for the privacy signal waveform, saving components and reducing space occupation. The fixed-level privacy signal carries information related to the target level, which is then boosted to the target level using the source driver integrated circuit 10.

[0043] In some embodiments, continue to refer to Figures 3-6 In any figure, the source driver integrated circuit 10 may also include a signal input terminal 101, and based thereon implement the signal input for the privacy display.

[0044] In some embodiments, such as Figure 3 or Figure 4 As shown, in the source driver integrated circuit 10, the data signal output terminals 102 are arranged in a row; the privacy signal output terminals 103 are disposed on at least one side of the rows of data signal output terminals 102, and the arrangement direction of the privacy signal output terminals 103 intersects with the arrangement direction of the data signal output terminals 102.

[0045] For example, with Figure 3 and Figure 4 Taking the orientation shown in the figure as an example, the data signal output terminals 102 are arranged in rows along the first direction, for example, arranged in two rows along the second direction Y; the anti-peeping signal output terminals 103 are arranged along the second direction Y, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y can be perpendicular to each other or intersect at other angles, which is not limited here.

[0046] For example, refer to Figure 3 The privacy signal output terminal 103 is located on one side of the data signal output terminal 102; Figure 3 Taking the shown orientation as an example, the privacy signal output terminal 103 is located to the left of the data signal output terminal 102. In other embodiments, the privacy signal output terminal 103 may also be located to the right of the data signal output terminal 102, which is not limited here.

[0047] For example, refer to Figure 4The privacy signal output end 103 is arranged on both sides of the data signal output end 102.

[0048] Thus, the data signal output end 102 and the privacy signal output end 103 can be arranged on the space of the source driving integrated circuit 10 for display.

[0049] In some embodiments, as shown in Figure 5 the privacy signal output end 103 is arranged in the arrangement space of the data signal output end 102.

[0050] In the source driving integrated circuit 10, the signal output ends are arranged in rows. When the number of output ends used by the data signal output end 102 is less than the total number of signal output ends, there will be redundant signal output ends. At least part of the redundant signal output ends can be used as the privacy signal output end, so as to realize full use of the signal output ends and avoid occupying other space to additionally arrange the privacy signal output end. In addition, since the signal output ends are arranged in the same direction and parallel to the arrangement direction of the signal input ends, the connection mode between the signal input and output is simple, and the mutual influence between the signals is small.

[0051] In some embodiments, as shown in Figure 6 the privacy signal output end 103 is arranged in rows and the arrangement direction is parallel to the arrangement direction of the data signal output end 102.

[0052] For example, as shown in Figure 6 , the privacy signal output end 103 can be arranged on the upper side of the data signal output end of the source driving integrated circuit 01 to realize the privacy signal leading out from the upper side.

[0053] In the source driving integrated circuit 10, the privacy signal output end 103 can be arranged on at least one side of the data signal output end 102 to correspond to the output of the privacy signal.

[0054] It should be noted that Figures 3-6 only the relative position between the privacy signal output end 103 and the data signal output end 102 is shown in the above examples, and the number thereof is not limited.

[0055] In the above embodiments, Figures 3-6 the cross-shaped structure in the above examples can be a position alignment mark used for position alignment during the process of connecting the source driving integrated circuit to the display panel.

[0056] Based on the above embodiments, this disclosure also provides a display module, which may include any of the source driver integrated circuits that integrate display signal output terminal and privacy signal output terminal provided in the above embodiments, and can achieve the corresponding beneficial effects.

[0057] In some embodiments, Figure 7 , Figure 9 and Figure 12 Different display modules with different structures are shown. For example... Figure 7 , Figure 9 or Figure 12 As shown, the display module may also include a display panel 21, a flexible circuit board 23, and a rigid circuit board 22; the source driver integrated circuit 10 is disposed in the non-display area 212 of the display panel 21, and the timing controller 221 is disposed in the rigid circuit board 22. The timing controller 221 and the source driver integrated circuit 10 are connected through the lines in the flexible circuit board 23.

[0058] For example, the display panel 21 may include a display area 211 and a non-display area 212. The display area 211 is used to controllably implement privacy protection, and the non-display area 212 may house the source driver integrated circuit 10, as well as other peripheral circuit structures, which will not be elaborated here. In other embodiments, the source driver integrated circuit 10 may also be disposed in the flexible circuit board 23 and led to the display panel 21; or, the source driver integrated circuit 10 may also be disposed in other locations in the display module known to those skilled in the art, which are not limited here.

[0059] For example, the display panel 21 may be a liquid crystal display panel, and privacy display under different viewing angles can be achieved through grayscale control of the privacy signal. In other embodiments, the display panel 21 may also be other types of display panels based on molecular deflection that are known to those skilled in the art, and are not limited here.

[0060] For example, the flexible circuit board 23 can be an FPC; compared with related technologies, since this embodiment reuses the source driver integrated circuit output data signal and privacy signal, there is no need to set up an additional privacy-protecting FPC. For example, Figure 7 and Figure 1 In comparison, FPC2 is saved.

[0061] For example, the rigid circuit board 22 may be a PCB, in which circuit components for privacy display are provided, such as timing controller 211, and the connection relationship between the components and the signal transmission process will be described by example below.

[0062] Exemplarily, the mounting manner between the flexible circuit board 23 and the display panel 21 is FOG, i.e., the FPC is mounted on the glass panel; the mounting manner between the flexible circuit board 23 and the rigid circuit board 22 can be FOB, i.e., the FPC is mounted on the PCB. The FOG / FOB process can be completed by different pressing heads on the same platform, which is not limited herein.

[0063] Exemplarily, the rigid circuit board 22 and the display panel 21 are connected through the flexible circuit board 23, so as to facilitate folding the rigid circuit board 22 to the back of the display panel 21 by the bendability of the flexible circuit board 23, thereby reducing the non-display area of the front of the display panel 21.

[0064] In the above embodiments, the timing controller 221 can be a display timing controller, or a timing controller additionally arranged for the privacy and display synchronization, which is not limited herein, and only the former is taken as an example for description hereinafter.

[0065] In some embodiments, continuing to refer to Figure 7 The display module can further include a connector 222 and a display timing controller 221; the connector 222 is connected between the system circuit of the display module and the input end of the timing controller 221, and the connector 222 is used to transmit the privacy level signal to the timing controller 221; the output end of the timing controller 221 is connected to the source driving integrated circuit 10 and the display circuit of the display module; the timing controller 221 is used to identify the privacy level signal, and control the source driving integrated circuit 10 to output the privacy signal corresponding to different amplitudes, and is used to synchronously control the display circuit to output the display signal.

[0066] The system circuit can be the circuit on the mainboard of the display module, and the system circuit can identify and process the user operation, and transmit the privacy level signal generated in response to the user operation to the timing controller 221 through the connector 222.

[0067] In the display module provided by the embodiments of the present disclosure, the time sequence controller 221 replaces the single-chip microcomputer in the related art, and the source driving integrated circuit 10 replaces the level conversion module for preventing peeping in the related art, so that circuit components can be saved. The time sequence controller 221 can control the source driving integrated circuit 10 to output a privacy signal (Privacy Signal, which can be abbreviated as P.S, and the corresponding voltage signal can be represented as P.S_O) of different amplitudes corresponding to the privacy level signal and synchronously control the display circuit to output a display signal. Thus, the display and the privacy are synchronously controlled based on the time sequence controller 221 for display, and additional synchronization setting is avoided. Meanwhile, the time sequence controller 221 controls the source driving integrated circuit 10 to output the privacy signal of different amplitudes by identifying the privacy level signal indicated by the connector 222, so that the dynamic privacy display with multiple viewing angle adjustment can be realized.

[0068] For example, the privacy level signal can be a level signal represented by high / low (H / L) levels. The time sequence controller 221 is connected with the connector 222 through a Pin port. The time sequence controller 221 identifies the H / L level of the Pin port, controls the source driving integrated circuit 10 to output the privacy signal of different amplitudes based on the combination between different privacy level signals. For example, the number of Pin ports is N, and the number of output signals is also N, which can be represented as A0, A1, …, AN-1, or A1, A2, …, AN. The signals are generated corresponding to the external control signal. The signal output by each Pin can be identified by the time sequence controller 221 in terms of H / L level, and the privacy signal of different amplitudes can be output by combination. The example will be described below. Figure 8

[0069] In some embodiments, the connector 222 has N privacy level output ends, and the time sequence controller 221 is correspondingly provided with N privacy level input ends. The privacy level output ends are connected with the privacy level input ends one by one, N≥2, and N is an integer. The time sequence controller 221 is configured to identify the high / low level signals of the N privacy level input ends and determine the corresponding privacy signal. The amplitude of the privacy signal is equal to M1 / M of the amplitude of the display gray scale signal, and |M|≥|M1|.

[0070] The positive and negative of the privacy signal are consistent with the positive and negative of the display gray scale signal. The amplitude of the privacy signal is equal to or less than the amplitude of the display gray scale signal, that is, the relative size between the absolute values satisfies |M|≥|M1|. The corresponding relationship between the amplitude of the specific privacy signal and different privacy levels can be set based on the requirements of the display module, which is not limited herein.

[0071] ​Exemplarily, the display gray scale signal can be +5.2V, and the corresponding privacy signal can be +3.4V, or +5.2V, or other positive voltage signals less than 5.2V; or, the display gray scale signal can be -5.2V, and the corresponding privacy signal can be -3.4V, or -5.2V, or other negative voltage signals greater than -5.2V.

[0072] Exemplarily, Figure 8 A privacy timing diagram provided by the embodiment of the present disclosure is shown, and a dynamic multi-view angle adjustment privacy timing is shown by taking three frames as an example. As shown in Figure 8 , different frames are divided by the rising edge of a synchronization signal as a time node, the synchronization signal is shown by VSYNC, A0 and A1 represent two privacy level signals, the privacy level signal can be a high / low level signal, corresponding to the data processing logic, the high level can be 1 and the low level can be 0; VGM1 and VGM2 represent the high / low level signals corresponding to the display gray scale; P.S_O represents the privacy signal. Among them, the amplitude of the output waveform corresponding to the privacy signal can divide the gray scale voltage corresponding to the display gray scale into several parts to achieve multi-view angle privacy.

[0073] Exemplarily, Figure 8 as shown in the timing, in the first frame, both of the two privacy level signals are low level signals, that is, A0&A1=0, corresponding to P.S, no privacy signal is output; in the second frame and the third frame, when there is a high level signal in the privacy level signal, for example, A0=1&A1=1, or A0=0&A1=1, the P.S outputs the privacy signal, and the amplitude of the output waveform is any level of 0~VGM1 potential or any level of 0~VGM2 potential, for example: 1 / 2(VGM1), or VGM2, and the same applies to the same, different amplitude privacy signals can be output to achieve multi-view angle dynamic adjustment.

[0074] In other embodiments, the adjustment of at most 2 N different privacy levels can also be realized by different arrangement combinations between the control signals corresponding to the privacy levels. Among them, N is the number of control signals corresponding to the level adjustment, which can correspond to Pin1…PinN.

[0075] Exemplarily, taking N=2 as an example, Pin1 can be 0 or 1, and Pin2 can also be 0 or 1, and the arrangement combination can include 00, 01, 10 and 11, which can correspond to four different privacy signals respectively, so as to realize the adjustment of four privacy levels.

[0076] Or, taking N=3 as an example, at most 2 3 , that is, eight different privacy levels can be adjusted.

[0077] In other embodiments, N can also be 1, 4 or any other positive integer value, which is not limited here.

[0078] In the display module provided by the embodiments of the present disclosure, the anti-peep driving circuit reuses the modules / circuits / chips in the display driving circuit, specifically, the timing controller 221 for display is used to control the source driving integrated circuit 10 to output the anti-peep signal, thereby avoiding the need for additional synchronization setting between anti-peep and display; and the source driving integrated circuit 10 not only outputs the display data signal, but also outputs the anti-peep signal controlled by the timing controller 221, the timing controller 221 outputs the anti-peep signal with a fixed level to the source driving integrated circuit 10, and the anti-peep signal with a fixed level can be pulled up to the anti-peep signal with a target level through the source driving integrated circuit 10 to meet the voltage level requirement of the display panel 21, thereby eliminating the need for additional level conversion modules; and the anti-peep signal with a target level output by the source driving integrated circuit 10 can be a voltage signal corresponding to different gray scales, thereby enabling dynamic multi-view anti-peep adjustment.

[0079] In some embodiments, continuing to refer to Figure 9 The display module further includes a connector 222, a timing controller 221 for display, a gating circuit 225 and a level conversion circuit 224; the anti-peep signal output end 103 of the source driving integrated circuit 10 is connected to the input end of the gating circuit 225 in one-to-one correspondence, and the output end of the gating circuit 225 is used to output the anti-peep signal; the level conversion circuit 224 is connected between the control end of the gating circuit 225 and the output end of the connector 222, and is used to identify the anti-peep level signal and convert it into a corresponding level that can be used by the display module, so as to correspond to an input end and an output end of the gating circuit 225; the timing controller 221 is used to control the synchronization output of the display signal and the anti-peep signal.

[0080] In the display module provided by the embodiments of the present disclosure, by adding the gating circuit 225, different anti-peep levels can be selected according to the selection of the user based on the use scenario, thereby realizing different anti-peep effects. The gating circuit 225 can be arranged in the display panel or the hard circuit board, which is not limited here.

[0081] The timing controller 221 controls the source driving integrated circuit 10 to output the corresponding waveform of the selectable anti-peep signal, and transmits it to the gating circuit 225, so that the gating circuit 225 can select and output it in response to the selection of the user.

[0082] The external control signal triggered by the user based on the use scenario is transmitted to the connector 222 via the system circuit, and the corresponding connector 222 converts the control instruction (PinN shown in the figure, representing Pin0 / Pin1 / …, corresponding to A0 / A1 / …) into H / L level suitable for the display module through the level conversion circuit 224 after data transmission, and the level conversion circuit 224 is converted into the gate control signal of the gating circuit 225. The gating circuit 225 is controlled to select one of the waveforms of the anti-peep signal output by the source driving integrated circuit 10 as the anti-peep signal output to the display area 211 of the display panel 21, so as to realize anti-peep display under the corresponding viewing angle.

[0083] In some embodiments, continuing to refer to Figure 9 , the level conversion circuit 224 is arranged in the hard circuit board 22, the gating circuit 225 is arranged in the display panel 21, and the level conversion circuit 224 and the gating circuit 225 are connected through the lines in the flexible circuit board 23.

[0084] Among them, the gating circuit 225 is controlled to gate the anti-peep signal output by the source driving integrated circuit 10 and transmitted to the display panel 21. By arranging the gating circuit 225 in the display panel 21, the line connection between the gating circuit 225 and the source driving integrated circuit 10 can be relatively simple, thereby reducing the wiring difficulty. Alternatively, the gating circuit 225 can be arranged on the side of the source driving integrated circuit 10 facing the display panel 21, thereby simplifying the wiring mode between the gating circuit 225 and the display panel 21 and reducing the wiring difficulty.

[0085] Among them, the connector 222 is connected with the level conversion circuit 224. By arranging the level conversion circuit 224 in the hard circuit board 22, the wiring can be simplified and the difficulty can be reduced.

[0086] In some embodiments, the level conversion circuit 224 and the display level conversion circuit 224 are the same level conversion circuit, so that the display level conversion circuit 224 can be reused as the anti-peep level conversion circuit, further saving components and reducing space occupation.

[0087] In some embodiments, Figure 10 a structure of the gating circuit in Figure 9 is shown, Figure 11 corresponding Figure 10 a control timing is shown. In combination with Figures 9-11 , the gating circuit 225 in the display module can include: a control switch M0 and at least two data switches M1, Figure 10Three data switches M1 are shown in the figure, which are a first data switch M10, a second data switch M11 and a third data switch M12 respectively; the control end of the control switch M0 and the control end of the data switch M1 are connected to the level conversion circuit 224, for controlled opening or closing, to realize the gating of the anti-peep signal under control; the input end of the data switch M1 is connected to the output end 103 of the anti-peep signal of the source driving integrated circuit 10 as the input end of the gating circuit 225; the output end of the data switch M1 is connected to the input end of the control switch M0, and the output end of the data switch M1 is the output end of the gating circuit 225.

[0088] Exemplarily, Figure 10 The gating circuit shown in the figure can be realized by a gate, which is connected to the source driving integrated circuit 10 and the level conversion circuit 224 through the pin Pin, which is not limited here.

[0089] Exemplarily, the control switch M0 is used for anti-peep enable control, and the data switch M1 is used for anti-peep gear adjustment; the control switch M0 and the data switch M1 can both be high-level opening and low-level closing switches. In order to facilitate the description of the anti-peep logic, the control signals output by the connector are denoted as Pin0 and Pin1…PinN, which can be the signals output by the corresponding pins of the connector; the level conversion circuit 224 receives the control signals Pin0 and Pin1…PinN output by the connector 222 and converts them into high-low level signals, which are output to the gating circuit 225 to realize the switch control of the control switch M0 and the data switch M1 in the gating circuit 225, thereby realizing the control of the anti-peep state opening and the adjustment of the anti-peep gear; exemplarily, the signals output by the level conversion circuit corresponding to Pin0 and Pin1…PinN are denoted as A0 and A1…AN, and A0, A1, A2 and A3 are taken as examples in the following description; when multi-gear adjustment is performed, Pin1…PinN can be divided into N different H / L level signal outputs, corresponding to the transmission of N different control signals, to realize the adjustment of N different anti-peep gears.

[0090] When Pin0=0, the control signal received by the control switch M0 can be a low-level signal, i.e. A0=VGL, at this time, the control switch M0 is closed, and no matter whether Pin1=0 or 1, the anti-peep function is not opened, and the gating circuit 225 does not output the anti-peep signal, i.e. P.S_O is floating, as shown in the 4th frame in the figure. Figure 11

[0091] When Pin0=1, the control signal received by the control switch M0 can be a high-level signal, i.e. A0=VGH, at this time, the control switch M0 is opened, and the anti-peep signal transmitted by the data switch M1 in the opened state can be gated.

[0092] ​For example, if Pin1=1, then A1=VGH, A2=A3=VGL, at this time the first data switch M11 is opened, the second data switch M12 and the third data switch M13 are closed, and the privacy signal output by the gating circuit 225 is the signal of the input terminal I / O1 of the first data switch M11, as shown in the first frame of FIG. 6. Figure 11 The privacy signal is shown as 1 / 6 (VGM1) in the first frame of FIG. 6.

[0093] In other embodiments, the voltage of the privacy signal can also be equal to the voltage value of the common electrode, that is, it can be a privacy reset signal (i.e., a Reset signal), which can correspond to a privacy display with a maximum viewing angle.

[0094] For example, if Pin2=1, then A2=VGH, A1=A3=VGL, at this time the second data switch M12 is opened, the first data switch M11 and the third data switch M13 are closed, and the privacy signal output by the gating circuit 225 is the signal of the input terminal I / O2 of the second data switch M12, as shown in the second frame of FIG. 6. Figure 11 The privacy signal is shown as 1 / 3 (VGM2) in the second frame of FIG. 6.

[0095] Similarly, if Pin3=1, then A3=VGH, A1=A2=VGL, at this time the third data switch M13 is opened, the first data switch M11 and the second data switch M12 are closed, and the privacy signal output by the gating circuit 225 is the signal of the input terminal I / O3 of the third data switch M13, as shown in the third frame of FIG. 6. Figure 11 The privacy signal is shown as 2 / 3 (VGM1) in the third frame of FIG. 6.

[0096] In this way, the more I / O ports for outputting the privacy signal (e.g., N) of the source driving integrated circuit 10, the more different (corresponding to N) privacy signals with different levels that can be selected by the gating circuit 225, and the more privacy gears that can be adjusted. The specific number can be set based on the privacy requirements, which is not limited herein.

[0097] In this article, the strength of the privacy display effect can be realized based on the adjustment of the level of the privacy signal. For example, the source driving integrated circuit can currently output voltages corresponding to different gray scales of G0~255. Only by fixing the source driving integrated circuit to output the privacy signal with the required gray scale, the privacy display under the corresponding viewing angle can be realized.

[0098] It should be noted that, Figure 10 Only one structure of the gating circuit is exemplarily shown in the above description, and other structures known to those skilled in the art can also be used in other embodiments, which are not limited herein. Meanwhile, Figure 10The switch structure shown in the figures can be a thin film transistor structure, which can be formed synchronously with the pixel driving circuit and the peripheral driving circuit in the process of forming the display panel, and only the patterns in the patterning process need to be set correspondingly to form the switch with the above connection relationship on the basis of the related art.

[0099] Meanwhile, Figure 11 In the embodiments, VGM1 and VGM2 are used to show the high and low gray scale voltage signals, the high and low of the anti-peep signal are consistent with the high and low of the gray scale signal, the size of the anti-peep signal can be 1 / 6, 1 / 3 or 2 / 3 of the size of the gray scale signal, in other embodiments, the size relationship of the anti-peep signal relative to the gray scale signal can also be set to other fractions less than 1, which is not elaborated here and is not limited.

[0100] In some embodiments, continuing to refer to Figure 12 , and referring to Figure 13 The display module can further include a micro control unit 226, a connector 222, a display timing controller 221 and a level conversion circuit 224; the micro control unit 226 is connected between the connector 222 and the level conversion circuit 224, used to identify the anti-peep parity signal output by the connector 222, and control the level conversion circuit 224 to generate a corresponding anti-peep signal by boosting; the level conversion circuit 224 is also connected with the timing controller 221, and the timing controller 221 is used to control the synchronization output of the display signal and the anti-peep signal.

[0101] The display module provided by the embodiments of the present disclosure provides a scheme of external MCU, and realizes the parity processing of the anti-peep signal based on the micro control unit 226 and the level conversion circuit 224, and the synchronization control of the anti-peep signal and the display signal based on the display timing controller 221. In order to avoid the mutual influence between the display parity and the anti-peep parity, the level conversion circuit 224 can be a separate level conversion circuit which is independent of the display level conversion circuit; in other embodiments, the anti-peep and the display can also share the same level conversion circuit, which is not limited here. The source driving integrated circuit 10 can be any one of the source driving integrated circuits in the above embodiments, or can be an anti-peep circuit for outputting only the display signal in the related art, which is not limited here.

[0102] The connector 222 transmits the anti-peep control instruction corresponding to the external control signal to the micro control unit 226, and the micro control unit 226 controls the level conversion circuit 224 to generate the anti-peep signal corresponding to the anti-peep control instruction. Figure 12The control instruction (indicated by Pin: A0 / A1 / … in the figure) is transmitted to the micro control unit 226, the micro control unit 226 determines the anti-peep level signal based on the control instruction and transmits to the level conversion circuit 224; the level conversion circuit 224 boosts the anti-peep signal with a certain level generated by the timing controller 221 to obtain an anti-peep signal with a target level, and the anti-peep signal with the target level is transmitted to the display area of the display panel 21 to realize anti-peep display.

[0103] In some embodiments, continuing to refer to Figure 12 , the display module can further include a power management circuit 227; the power management circuit 227 is in communication connection with the micro control unit 226, for example, through IIC communication connection, and the micro control unit 226 adjusts the adjustment signal of the power management circuit 227 for the anti-peep signal level based on the anti-peep level signal.

[0104] For example, the power management circuit can include a power management chip (Power IC, or PMU IC). The anti-peep power management chip and the display power management chip can be two independent power management chips respectively.

[0105] In the display module provided by the embodiments of the present disclosure, the H / L level of Pin0 and Pin1 of the connector 222 is identified through the I / O port of the micro control unit 226, and based on the H / L logic, the micro control unit 226 executes different IIC instructions to adjust the VGH / VGL potential of the PMU IC and transmits to the level conversion circuit 224; and then the level conversion circuit 224 boosts the anti-peep signal with a certain level generated by the timing controller 221 to obtain an anti-peep signal with a target level.

[0106] In some embodiments, as Figure 13 shown, wherein HSCL and HSDA represent IIC communication pins between the micro control unit 226 and the power management circuit 227; the micro control unit 226 identifies the H / L level of Pin0 and Pin1 of the connector 222 through the I / O port, and based on the H / L logic, the micro control unit 226 executes different IIC instructions to adjust the VGH / VGL potential output by the power management circuit 227; at the same time, the timing controller 221 generates an anti-peep signal with a certain level based on the power management circuit 227 and transmits to the level conversion circuit 224; the level conversion circuit 224 adjusts the anti-peep signal based on the VGH / VGL potential to generate and output an anti-peep signal with a target level.

[0107] The display module provided by the above embodiments can be used in terminal devices, such as smart phones, tablets, computers, vehicle-mounted displays, or other devices with display functions known to those skilled in the art, to realize display and dynamically adjustable anti-peep display.

[0108] It has to be noted that, in the present document, relational terms are intended to encompass the various possible relationships between alternatives, such as those individuals or entities that have been discussed in the foregoing description. For example, without limitation, the term "first" can mean the first alternative, or it can simply mean the alternative that is sited first in the claims; the term "second" can mean the second alternative, or it can simply mean the alternative that is sited second, and so on. As such, relational terms do not require a hard-wired or logical relationship to be present between items. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. As such, the terms sited "above," "below," "upper," "lower," "front," "back," "side," "end," "vertical," "horizontal," and the like can mean devices in planar orientations (e.g., vertical or horizontal) or in other orientations depending on the context in which the terms are used. The terms of degree such as "substantially", "about", and "approximately" which are used herein with respect to one or more characteristics of a device, material, or process, are used

[0109] The foregoing description of embodiments of the disclosure has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the scope of the disclosure be limited not with this detailed description, but rather by the claims appended hereto.

Claims

1. A display module, characterized in that, include: Source driver integrated circuits, display panels, connectors, timing controllers for displays, gating circuits, level conversion circuits, flexible circuit boards, and rigid circuit boards; The source driver integrated circuit is disposed in the non-display area of ​​the display panel. The source driver integrated circuit includes an integrated data signal output terminal and a privacy signal output terminal. The data signal output terminal is used to output a display signal, and the privacy signal output terminal is used to output a privacy signal. The data signal output terminals are arranged in a row. The level conversion circuit is connected between the control terminal of the gating circuit and the output terminal of the connector. It is used to identify the privacy level signal and convert it into a corresponding level that the display module can use, so as to select one input terminal and one output terminal of the gating circuit. The privacy signal output terminal of the source driver integrated circuit is connected to the input terminal of the gating circuit one by one, and the output terminal of the gating circuit is used to output the privacy signal. The timing controller is disposed in the rigid circuit board, and the timing controller is connected to the source driver integrated circuit through the lines in the flexible circuit board; the timing controller is used to control the synchronous output of the display signal and the privacy signal; The privacy signal output terminal is disposed on at least one side of the data signal output terminals arranged in a row, and the arrangement direction of the privacy signal output terminal intersects with the arrangement direction of the data signal output terminal. Alternatively, the privacy signal output terminal may be integrated and arranged within the arrangement space of the data signal output terminal; Alternatively, the privacy signal output terminals are arranged in rows, and the arrangement direction is parallel to the arrangement direction of the data signal output terminals.

2. The display module according to claim 1, characterized in that, It also includes connectors and timing controllers for the display; The connector is connected between the system circuit of the display module and the input terminal of the timing controller, and the connector is used to transmit the anti-peeping level signal to the timing controller; The output of the timing controller is connected to the source driver integrated circuit and the display circuit of the display module; the timing controller is used to identify the anti-peeping level signal, control the source driver integrated circuit to output anti-peeping signals with different amplitudes, and synchronously control the display circuit to output display signals.

3. The display module according to claim 2, characterized in that, The connector has N privacy screen output terminals, and the timing controller is correspondingly configured with N privacy screen input terminals. The privacy screen output terminals are connected to the privacy screen input terminals in a one-to-one correspondence, N≥2, and N is an integer. The timing controller is used to identify the high and low level signals of N anti-spy level input terminals and determine the corresponding anti-spy signal; The amplitude of the privacy signal is equal to M1 / M of the amplitude of the grayscale signal used for display; where |M|≥|M1|.

4. The display module according to claim 1, characterized in that, The level conversion circuit is disposed in the rigid circuit board, the gating circuit is disposed in the display panel, and the level conversion circuit and the gating circuit are connected through lines in the flexible circuit board.

5. The display module according to claim 1 or 4, characterized in that, The gating circuit includes a control switch and at least two data switches; Both the control terminal of the control switch and the control terminal of the data switch are connected to the level conversion circuit for controlled opening or closing. The input terminal of the data switch serves as the input terminal of the gating circuit and is connected one-to-one with the privacy signal output terminal of the source driver integrated circuit. The output terminals of the data switches are all connected to the input terminals of the control switches, and the output terminals of the data switches serve as the output terminals of the gating circuit.

6. The display module according to claim 1 or 4, characterized in that, The level conversion circuit mentioned is the same level conversion circuit used for display.

7. The display module according to claim 1, characterized in that, It also includes a microcontroller unit, connectors, a timing controller for display, and a level conversion circuit; The microcontroller unit is connected between the connector and the level conversion circuit, and is used to identify the privacy level signal output by the connector and control the level conversion circuit to boost and generate the corresponding privacy signal. The level conversion circuit is also connected to the timing controller, which is used to control the synchronous output of the display signal and the privacy signal.

8. The display module according to claim 7, characterized in that, Also includes: Power management circuitry; The power management circuit is communicatively connected to the microcontroller unit, and the microcontroller unit adjusts the adjustment signal output by the power management circuit for the privacy signal level based on the privacy level signal.

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