Data readout circuit, data readout method and memory
By generating sub-fetch signals in DRAM to adjust the data fetch time, the problem of unbalanced transmission time between column select signals and global data lines was solved, tCCD was optimized, and the read and write speed of DRAM was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-03-03
- Publication Date
- 2026-06-26
Smart Images
Figure CN116741223B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to a data readout circuit, a data readout method, and a memory. Background Technology
[0002] In Dynamic Random Access Memory (DRAM), during a read operation, the word line WL is first activated. Data in the corresponding memory cell (selected by the word line WL and the bit line BL) is transferred to the local data line LIO via the bit line BL. The column selection signal YS drives the column decoding module Ydec to transfer the data from the local data line LIO to the global data line YIO. The data is then transferred to the read / write control module RWCB via the global data line YIO. After being captured by the read / write control module RWCB, the data is transferred to the transmission bus DQ via the global data line YIO, thus completing the data readout.
[0003] Due to the positional relationship between the column decoding module and the read / write control module, and the high RC load of the column selection signal YS, the actual activation time of the column selection signal YS varies in different memory regions. In cases where the transmission directions of the column selection signal YS and the global data line YIO are opposite in different memory regions, the read / write control module RWCB needs to be activated after the data transmission on the global data line YIO is complete. During continuous read operations, in some memory regions, the global data line YIO transmission time is long, but the column selection signal YS activates earlier; in other memory regions, the global data line YIO transmission time is short, but the column selection signal YS activates latest, severely limiting the improvement of DRAM's tCCD (Cas to Cas delay).
[0004] When the column select signal YS and the global data line YIO in different memory regions have the same transmission direction, during continuous read operations, the global data line YIO in some memory regions has a longer transmission time, and the corresponding column select signal YS is turned on later. However, since the column select signal YS has a high RC load, the actual time it takes for the column select signal YS to take effect in different memory regions will still vary. If the time for the read / write control module RWCB to capture the global data line YIO is fixed, the capture time of the read / write control module RWCB needs to be set according to the effect time of the slowest column select signal YS. This will waste the time for the global data line YIO to perform equalization adjustment, which will also limit the DRAM's tCCD (Cas to Cas delay) and affect the DRAM's read / write speed. Summary of the Invention
[0005] This disclosure provides a data readout circuit and a data readout method memory to optimize the DRAM's tCCD by unifying the time interval between the time when the read / write control module RWCB receives data transmitted from the global data line YIO from different storage areas and the time of the corresponding sub-fetch signal for that storage area.
[0006] This disclosure provides a data readout circuit applied to a memory, which includes a read / write control module, a column decoding module, and multiple storage areas. The circuit includes a delay generation module configured to generate a sub-grab signal for each storage area based on an initial grab signal and the data transmission delay of each storage area, and to generate a grab enable signal based on all sub-grab signals. The data transmission delay of the storage area closer to the column decoding module is less than the data transmission delay of the storage area farther from the column decoding module. The time interval between the time the read / write control module receives data transmitted from the global data line to each storage area and the time it receives the sub-grab signal corresponding to the storage area satisfies a preset range. The read / write control module is configured to read data from the global data line to the data bus based on the grab enable signal. The global data line is configured to read data from the storage area through the column decoding module based on a column selection signal.
[0007] This embodiment generates a sub-fetch signal for each storage area based on the initial fetch signal to adjust the data fetch time for each storage area. The data is fetched by the read / write control module at different times, so as to unify the time interval between the time when the read / write control module receives data transmitted from the global data line from different storage areas and the time of the corresponding sub-fetch signal for the storage area, thereby optimizing the DRAM's tCCD.
[0008] Additionally, the delay generation module includes: a delay unit configured to generate a sub-grab signal corresponding to each storage region; and an integration unit configured to generate a grab enable signal based on the sub-grab signal corresponding to the storage region to which the enabled state word line belongs.
[0009] In addition, the delay unit includes multiple delay sub-units; the multiple delay sub-units are connected in series; among the multiple delay sub-units connected in series, the input terminal of the first-level delay sub-unit is used to receive the initial grab signal, the connection line between two adjacent delay sub-units and the output terminal of the last-level delay sub-unit are used to output sub-grab signals corresponding to different storage areas; wherein, different sub-grab signals have different data transmission delays.
[0010] In addition, each delay subunit has an even number of inverters, and the number of inverters in some delay subunits is not the same.
[0011] In addition, each delay subunit is equipped with an even number of inverters, and the number of inverters in each delay subunit is the same.
[0012] Additionally, the integration unit includes: multiple primary NAND gates, each corresponding to a memory region. One input of each primary NAND gate receives a region indication signal for the corresponding memory region, and the other input receives a sub-grab signal for the corresponding memory region. The region indication signal is used to characterize the memory region to which the word line in the enabled state belongs. The outputs of the multiple primary NAND gates are connected to the same output OR gate, which outputs a grab enable signal. By integrating the valid levels of the multiple valid sub-grab signals into the same valid level, the grab enable signal is obtained, thereby driving the multiple selected memory regions based on the grab enable signal to achieve continuous read and write operations on different memory regions.
[0013] In addition, the delay unit includes a delay transmission line that connects to the input terminals of multiple primary NAND gates, and a signal terminal that receives the initial capture signal. The distance between the signal terminal and the connection point of the primary NAND gate input terminal is positively correlated with the data transmission delay corresponding to the primary NAND gate.
[0014] In addition, the integration unit also includes: multiple secondary NAND gates, the number of secondary NAND gates being less than the number of primary NAND gates, and each secondary NAND gate being connected to at least two primary NAND gates; the output terminals of the multiple primary NAND gates are connected to the same output OR gate, and the output OR gate is used to output a capture enable signal, including: the output terminals of the multiple secondary NAND gates being connected to the same output OR gate.
[0015] Additionally, the delay generation module includes: a processing unit configured to obtain the memory region to which the enabled word line address belongs based on the enabled word line address, and obtain a preset value corresponding to the memory region based on the location of the memory region; a counting unit connected to the processing unit configured to receive an initial grab signal, count based on a clock signal, and output a sub-grab signal for the corresponding memory region when the count value equals the preset value; and an integration unit configured to generate a grab enable signal based on the sub-grab signal corresponding to the memory region to which the enabled word line belongs.
[0016] In addition, the delay generation module also includes a pre-storage unit and a connection processing unit, which are configured to pre-storage the preset values corresponding to each storage area.
[0017] In addition, the clock signal is the internal clock signal of the memory.
[0018] In addition, the time interval between the time the read / write control module receives the data transmitted from the global data line for each storage area and the time it receives the sub-fetch signal corresponding to the storage area is equal, so as to further optimize the DRAM's tCCD.
[0019] In addition, the data transmission delay is equal to the transmission delay of data on the global data line between the storage area and the read / write control module.
[0020] This disclosure also provides a data readout method applied to the aforementioned data readout circuit, comprising: reading data from a storage cell to a global data line based on a column selection signal; providing an initial grab signal; generating a sub-grab signal gxEn for each storage area based on the initial grab signal gEn and the data transmission delay of each storage area, such that the time interval between the time when the read / write control module receives data transmitted from the global data line from each storage area and the time when it receives the sub-grab signal corresponding to the storage area meets a preset range; wherein the data transmission delay corresponding to the storage area closer to the column decoding module is less than the data transmission delay corresponding to the storage area farther from the column decoding module; generating a grab enable signal based on all sub-grab signals; and reading data from the global data line to the data bus based on the grab enable signal.
[0021] In addition, based on all sub-grabbing signals, a grab enable signal is generated, including: integrating the effective level of each sub-grabbing signal onto the same signal to generate a grab enable signal; or, integrating the effective level common to some sub-grabbing signals onto the secondary grab signal, integrating the effective level of each secondary grab signal onto the same signal to generate a grab enable signal.
[0022] In addition, based on the initial grab signal and the data transmission delay of the global data line between the storage area and the read / write control module, a sub-grab signal corresponding to each storage area is generated, including: obtaining the data transmission delay of the global data line between each storage area and the read / write control module; and generating a sub-grab signal corresponding to each storage area based on the initial grab signal and the data transmission delay.
[0023] In addition, based on the initial grab signal and the data transmission delay of the global data line between the storage area and the read / write control module, a sub-grab signal corresponding to each storage area is generated, including: obtaining the address of the enabled word line; obtaining the storage area to which the enabled word line belongs, and obtaining the preset value corresponding to the storage area based on the location of the storage area; counting based on the initial grab signal and the clock signal, and when the count value is equal to the preset value, outputting the sub-grab signal of the storage area corresponding to the preset value.
[0024] In addition, the data transmission delay is equal to the transmission delay of data on the global data line between the storage area and the read / write control module.
[0025] This disclosure also provides a memory, multiple storage areas, and a column decoding module; each storage area is connected to a global data line YIO, and based on the column selection signal YS, the data stored in the storage unit is read out to the global data line YIO through the column decoding module; the data on the global data line is read out using the data readout circuit provided in the above embodiments. Attached Figure Description
[0026] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0027] Figure 1 A partial structural diagram of a DRAM for data storage provided in an embodiment of this disclosure;
[0028] Figure 2 A timing diagram of the initial grasping signal and the sub-grabbing signal provided in an embodiment of this disclosure;
[0029] Figure 3 The data readout circuit provided in one embodiment of this disclosure provides the signal readout timing for different storage regions;
[0030] Figure 4 and Figure 5 This is a schematic diagram of the structure of a delay generation module provided in an embodiment of the present disclosure;
[0031] Figure 6 This is a schematic diagram of the structure of a delay unit provided in an embodiment of the present disclosure;
[0032] Figure 7 This is a schematic diagram of the structure of an integrated unit provided in an embodiment of the present disclosure;
[0033] Figure 8 This is a schematic flowchart of a data readout method provided in another embodiment of the present disclosure. Detailed Implementation
[0034] Due to the positional relationship between the column decoding module and the read / write control module, when the transmission directions of the column selection signal YS and the global data line YIO are opposite in different memory areas, the read / write control module RWCB needs to be turned on after the data transmission on the global data line YIO is completed. During continuous read operations, the global data line YIO transmission time is long in some memory areas, but the column selection signal YS is turned on earliest; the global data line YIO transmission time is short in some memory areas, but the column selection signal YS is turned on latest. This severely limits the improvement of DRAM's tCCD (Cas to Cas delay, the time interval between CAS commands, CAS refers to Column Address Strobe).
[0035] When the column select signal YS and global data line YIO of different storage regions have the same transmission direction, during continuous read operations, the transmission time of the global data line YIO in some storage regions is long, and the corresponding column select signal YS is turned on later. However, due to the high RC load of the column select signal YS, the actual time it takes for the column select signal YS to take effect varies in different storage regions. If the time for the read / write control module RWCB to capture the global data line YIO is fixed, the capture signal time of the read / write control module RWCB needs to be set according to the effect time of the slowest column select signal YS. This will waste the time for the global data line YIO to perform equalization adjustment, thereby limiting the DRAM's tCCD (Cas to Cas delay) and affecting the DRAM's read / write speed. One embodiment of this disclosure provides a data readout circuit to unify the time interval between the time when the read / write control module RWCB receives data transmitted from the global data line YIO in different storage regions and the time of the corresponding sub-capture signal for that storage region, thereby optimizing the DRAM's tCCD.
[0036] refer to Figure 1 For some DRAM configurations, since the process cannot reduce the capacitance of the bit line BL, the read / write speed of the DRAM can be improved by driving the column select signal YS at both ends. In this case, the transmission direction of the column select signal YS and the global data line YIO is the same in some memory areas. For example, taking a DRAM data bank divided into 72 memory areas as an example, the transmission direction of the column select signal YS and the global data line YIO is the same in memory areas 36 to 71. The tCCD of this part of the memory area is easy to control. The transmission direction of the column select signal YS and the global data line YIO is opposite in some memory areas, such as memory areas 0 to 35. The same problem exists.
[0037] This embodiment uses Figure 1The structure shown, based on storage regions 0 to 35, provides a detailed description of tCCD optimization for storage regions where the transmission directions of column select signal YS and global data line YIO are opposite. This does not constitute a limitation on this embodiment and is equally applicable to storage regions 36 to 71. In other embodiments, if the DRAM is not configured to drive column select signal YS at both ends, the features mentioned in this embodiment are still applicable to storage regions in the DRAM.
[0038] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.
[0039] Figure 1 This is a partial structural diagram of the DRAM used for data storage in this embodiment. Figure 2 This is a timing diagram of the initial grasping signal and the sub-grabbing signal provided in this embodiment. Figure 3 The data readout circuit provided in this embodiment provides the signal readout timing for different storage areas. Figure 4 and Figure 5 This is a schematic diagram of the delay generation module provided in this embodiment. Figure 6 This is a schematic diagram of the delay unit provided in this embodiment. Figure 7 This is a schematic diagram of the integrated unit provided in this embodiment. The data readout circuit provided in this embodiment will be further described in detail below with reference to the accompanying drawings:
[0040] refer to Figure 1 The data readout circuit is applied to the memory, including a column decoding module 102 and multiple storage areas 101, including:
[0041] The delay generation module 104 is configured to generate a sub-grab signal gxEn for each storage area 101 based on the initial grab signal gEn and the data transmission delay of each storage area 101, and generate a grab enable signal Gen based on all sub-grab signals gxEn.
[0042] Specifically, the data transmission delay of the storage area closer to the column decoding module 102 is less than the data transmission delay of the storage area farther from the column decoding module 102, that is, the data transmission delay of the storage area closer to the read / write control module 103 is greater than the data transmission delay of the storage area farther from the read / write control module 103.
[0043] Specifically, for Figure 1 In the circuit shown, for storage areas 0-35, storage area 35 is farther from the read / write control module 103, resulting in a longer data transmission time from storage area 35 to the read / write control module 103 via the global data line YIO, meaning the data transmission delay of storage area 35 is large. Storage area 0 is closer to the read / write control module 103, resulting in a shorter data transmission time from storage area 0 to the read / write control module 103 via the global data line YIO, meaning the data transmission delay of storage area 0 is small. Similarly, for storage areas 36-71, storage area 71 is farther from the read / write control module 103, resulting in a longer data transmission time from storage area 71 to the read / write control module 103 via the global data line YIO, meaning the data transmission delay of storage area 71 is large. Storage area 36 is closer to the read / write control module 103, resulting in a shorter data transmission time from storage area 36 to the read / write control module 103 via the global data line YIO, meaning the data transmission delay of storage area 36 is small.
[0044] The time interval between the time when the read / write control module RWCB receives the data transmitted from the global data line YIO in each storage area 101 and the time when it receives the sub-grab signal gxEn corresponding to the storage area 101 meets a preset range.
[0045] In some embodiments, the data transmission delay is greater than or equal to the data transmission delay on the global data line YIO between storage area 101 and read / write control module 103.
[0046] Furthermore, in some embodiments, the value of the data transmission delay is equal to the data transmission delay on the global data line YIO between the storage area 101 and the read / write control module 103.
[0047] For storage regions 0 to 35, as shown in the figure, for the column selection signal YS issued by column decoding module 102, the storage region farther from column decoding module 102 receives the column selection signal YS at a faster time than the storage region closer to column decoding module 102; Reference Figure 1 Assuming that a column selection signal YS is provided at time 0, the time when storage area 0 receives the column selection signal YS is T0, and the time delay when storage areas 1 to 35 receive the column selection signal YS is T0 + ΔT0 (ΔT0 is different for different storage areas 101).
[0048] As can be seen from the above, the data transmission delay corresponding to the storage area closer to the column decoding module 102 is less than the data transmission delay corresponding to the storage area farther away from the column decoding module 102; Reference Figure 1Assume that the delay for data in storage area 0 to be transmitted to the read / write control module 103 via the global data line is T1, and the delay for data in storage areas 1 to 35 to be transmitted to the read / write control module 103 via the global data line is T1 + ΔT1 (ΔT1 is different for different storage areas 101).
[0049] In an ideal scenario (without delay of the column select signal YS and without global data line data transmission delay), the time for data transmission from storage area 101 to read / write control module 103 is T0+T1. However, in reality, the time for data transmission from storage area 101 to read / write control module 103 is T0+ΔT0+T1+ΔT1. By generating a sub-grab signal gxEn for each storage area 101 based on the initial grab signal gEn, the data grabbing time for each storage area is adjusted. The data is grabbed by read / write control module 103 at different times to unify the time interval between the time when read / write control module 103 receives data transmitted from global data line YIO from different storage areas 101 and the time when it receives the corresponding sub-grab signal gxEn. This ensures that the time interval between the time when read / write control module 103 receives data transmitted from global data line YIO from each storage area 101 and the time when it receives the corresponding sub-grab signal gxEn for the storage area 101 meets a preset range.
[0050] Specifically, refer to Figure 2 and Figure 3 For storage areas 101 close to column decoding module 102, such as storage area 0, the column selection signal YS can be received relatively quickly, i.e., T0 + ΔT0 is small. For this storage area 101, after the signal transmission time d of the local input / output circuit, a read operation enable signal RdEn is generated. Under the action of the read operation enable signal RdEn, the data transmission of the global data line YIO can be performed relatively quickly, i.e., T1 + ΔT1 is small. At this time, the time for the read / write control module 103 to receive the read data transmitted from this storage area 101 is small, i.e., T0 + ΔT0 + T1 + ΔT1 is small. The read / write control module 103 is controlled to capture data in advance by the sub-grab signal gxEn, so that the time interval t meets the preset range.
[0051] Continue to refer to Figure 2 and Figure 3For storage areas 101 far from column decoding module 102, such as storage area 35, the column selection signal YS needs to be received slowly, i.e., T0 + ΔT0 is relatively large. For this storage area 101, after the signal transmission time d of the local input / output circuit, a read operation enable signal RdEn is generated. Under the action of the read operation enable signal RdEn, the data transmission of the global data line YIO needs to be performed slowly, i.e., T1 + ΔT1 is relatively large. The time for the read / write control module 103 to receive the read data transmitted from this storage area 101 is relatively large, i.e., T0 + ΔT0 + T1 + ΔT1 is large. The read / write control module 103 captures data by delaying the sub-grab signal gxEn, so that the time interval t meets the preset range.
[0052] For storage access 36 to 71, based on the above assumptions, the time delay for storage areas 36 to 71 to receive the column selection signal YS is T0 + ΔT0 (ΔT0 is different for different storage areas 101); the delay for data from storage areas 36 to 71 to be transmitted to the read / write control module 103 via the global data line is T1 + ΔT1 (ΔT1 is different for different storage areas 101).
[0053] For storage areas 101 close to column decoding module 102, such as storage area 71, the column selection signal YS can be received relatively quickly, i.e., T0 + ΔT0 is small. For this storage area 101, the data transmission of global data line YIO needs to be slow, i.e., T1 + ΔT1 is large. For storage areas 101 far from column decoding module 102, such as storage area 36, the column selection signal YS needs to be received slowly, i.e., T0 + ΔT0 is large. For this storage area 101, the data transmission of global data line YIO can be fast, i.e., T1 + ΔT1 is small. Because the column selection signal YS has a high RC load, the time T0+△T0+T1+△T1 for the read / write control module 103 to receive read data transmitted from different storage areas 101 will still differ. Specifically, the larger T0+△T0 is, the larger T0+△T0+T1+△T1 is. That is, for storage areas 101 closer to the column decoding module 102, the read / write control module 103 needs to be controlled to capture data in advance through the sub-grab signal gxEn so that the time interval t meets the preset range; for storage areas 101 farther from the column decoding module 102, the read / write control module 103 needs to be controlled to capture data with a delay through the sub-grab signal gxEn so that the time interval t meets the preset range.
[0054] Each sub-grab signal gxEn is used to configure the corresponding storage area 101 to complete data reading. If data is read continuously, the effective levels in the corresponding sub-grab signals gxEn are integrated into the same signal according to the storage area to be read, generating a grab enable signal GEn. The grab enable signal GEn is used to instruct the corresponding storage area to complete continuous data reading. The read / write control module 103 is configured to read data on the global data line YIO to the data bus DQ based on the grab enable signal GEn.
[0055] The global data line YIO is configured to read data from storage area 101 through column decoding module 102 based on column selection signal YS.
[0056] In some embodiments, in order to further optimize the tCCD of the DRAM, the time interval between the time when the read / write control module 103 receives the data transmitted from the global data line YIO for each storage region 101 and the time when it receives the sub-grab signal gxEn corresponding to the storage region 101.
[0057] In some embodiments, reference Figure 4 The delay generation module 104 includes:
[0058] The delay unit 114 is configured to generate a sub-fetch signal gxEn corresponding to each storage region 101.
[0059] Integration unit 124 is configured to generate a grab enable signal GEn based on the sub-grab signal gxEn corresponding to the storage region 101 to which the enabled state word line belongs.
[0060] In one example, the delay unit 104 includes multiple delay sub-units 201 connected in series. Among the multiple delay sub-units 201 connected in series, the input terminal of the first-stage delay sub-unit 201 is used to receive the initial grab signal gEn, and the connection line between two adjacent delay sub-units 201 and the output terminal of the last-stage delay sub-unit 201 are used to output sub-grab signals corresponding to different storage areas. Among them, different sub-grab signals gxEn have different data transmission delays.
[0061] refer to Figure 5The first-level delay subunit 201 is used to receive the initial grasping signal gEn and generate the sub-grab signal gxEn0; the second-level delay subunit 201 is used to receive the sub-grab signal gxEn0 and generate the sub-grab signal gxEn1; the third-level delay subunit 201 is used to receive the sub-grab signal gxEn1 and generate the sub-grab signal gxEn2; the fourth-level delay subunit 201 is used to receive the sub-grab signal gxEn2 and generate the sub-grab signal gxEn3. The fifth-level delay subunit 201 is used to receive the sub-grab signal gxEn3 and generate the sub-grab signal gxEn4; the sixth-level delay subunit 201 is used to receive the sub-grab signal gxEn4 and generate the sub-grab signal gxEn5; the seventh-level delay subunit 201 is used to receive the sub-grab signal gxEn5 and generate the sub-grab signal gxEn6; the eighth-level delay subunit 201 is used to receive the sub-grab signal gxEn6 and generate the sub-grab signal gxEn7.
[0062] for Figure 1 In the circuit shown, each sub-grab signal gxEn is used for data reading from four storage areas 101. Specifically, sub-grab signal gxEn0 is used for data storage in storage areas 0 to 3, sub-grab signal gxEn1 is used for data storage in storage areas 4 to 7, sub-grab signal gxEn2 is used for data storage in storage areas 8 to 11, sub-grab signal gxEn3 is used for data storage in storage areas 12 to 15, and so on. It should be noted that in other embodiments, each sub-grab signal can be used for data reading from any number of storage areas, and the number of storage areas applied is relatively small. The more precise the control of data reading from storage areas, the more storage areas it can be applied to, which can save the consumption of memory data reading.
[0063] In some embodiments, each delay subunit 201 is provided with an even number of inverters, and the number of inverters in some delay subunits 201 is different, that is, different delay subunits are used to generate different data delays; in other embodiments, each delay subunit 201 is provided with an even number of inverters, and the number of inverters in some delay subunits 201 is the same, that is, each delay subunit is used to generate the same data delay.
[0064] In some embodiments, reference Figure 6 Integration unit 124 includes:
[0065] Multiple primary NAND gates 301, each primary NAND gate 301 corresponding to at least one storage area, wherein one input of the primary NAND gate 301 is used to receive the area indication signal of the corresponding storage area 101, and the other input is used to receive the sub-grab signal of the corresponding storage area.
[0066] The region indication signal is used to identify the memory region 101 to which the word line in the enabled state belongs.
[0067] The outputs of multiple primary NAND gates 301 are connected to the same output OR gate 303, which is used to output the grab enable signal Gen.
[0068] By integrating the valid levels of multiple valid sub-fetch signals gxEn into the same valid level, a fetch enable signal Gen is obtained, thereby driving multiple selected memory regions 101 based on the fetch enable signal Gen, so as to realize continuous read and write of different memory regions 101.
[0069] It should be noted that, Figure 6 The following is a detailed description using eight primary NAND gates 301 as an example. That is, the storage areas 101 of 4 share one primary NAND gate 301, which does not constitute a limitation on this embodiment. In other embodiments, one primary NAND gate 301 can be used to correspond to any number of storage areas 101 for specific settings.
[0070] In some embodiments, the integration unit 124 further includes:
[0071] Multiple secondary NAND gates 302, the number of secondary NAND gates 302 is less than the number of primary NAND gates 301, and each secondary NAND gate 302 is connected to at least two primary NAND gates 301.
[0072] The outputs of multiple primary NAND gates are connected to the same output OR gate 303. The output OR gate 303 is used to output the grab enable signal Gen, including: the outputs of multiple secondary NAND gates 302 are connected to the same output OR gate 303.
[0073] By performing an AND operation on the sub-fetch signals gxEn of multiple primary NAND gates using secondary NAND gates, a new enable signal is obtained to drive multiple memory regions simultaneously. In some embodiments, the sub-fetch signal gxEn can be directly set to drive multiple memory regions 101.
[0074] In some embodiments, the delay unit 114 includes a delay transmission line connected to the input terminals of a plurality of primary NAND gates 301, and also includes a signal terminal for receiving an initial capture signal gEn. The distance between the signal terminal and the connection point of the primary NAND gate 301 input terminal is positively correlated with the data transmission delay corresponding to the primary NAND gate 301.
[0075] In some embodiments, reference Figure 7 The delay generation module 104 includes:
[0076] The processing unit 401 is configured to obtain the storage region 101 of the enabled word line address based on the enabled word line address, and obtain the preset value corresponding to the storage region 101 based on the location of the storage region 101.
[0077] The counting unit 402, connected to the processing unit 401, is configured to receive the initial grab signal gEn, count based on the clock signal Clk, and output the sub-grab signal gxEn corresponding to the storage area when the count value equals a preset value.
[0078] Integration unit 403 is configured to generate a grab enable signal GEn based on the sub-grab signal gxEn corresponding to the storage region to which the enabled state word line belongs.
[0079] Furthermore, in some examples, the delay generation module 104 further includes a pre-storage unit 404 connected to the processing unit 401, configured to pre-storage preset values corresponding to each storage area 101.
[0080] It should be noted that in this embodiment, the clock signal Clk used by the counting unit 402 is the internal clock signal of the memory. In other embodiments, the clock signal used by the counting unit can be set to be obtained according to an external clock signal.
[0081] This embodiment generates a sub-grab signal gxEn for each storage region 101 based on the initial grab signal gEn, in order to adjust the data grab time for each storage region. The data is grabbed by the read / write control module 103 at different times, so as to unify the time interval between the time when the read / write control module 103 receives data transmitted from the global data line YIO from different storage regions 101 and the time of the corresponding sub-grab signal gxEn, thereby optimizing the DRAM tCCD.
[0082] All units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this disclosure, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this disclosure; however, this does not mean that other units are absent from this embodiment.
[0083] It should be noted that the features disclosed in the data readout circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain new data readout circuit embodiments.
[0084] Another embodiment of this disclosure provides a data readout method to optimize the DRAM's tCCD by unifying the time interval between the time when the read / write control module receives data transmitted from the global data line from different storage areas and the time of the sub-fetch signal corresponding to that storage area.
[0085] Figure 8 This is a flowchart illustrating the data reading method provided in this embodiment. The following is a detailed description of the data reading method provided in this embodiment with reference to the accompanying drawings:
[0086] refer to Figure 8 Data readout methods include:
[0087] Step 501: Based on the column selection signal, read the data in the storage cell to the global data line.
[0088] Step 502: Provide the initial grab signal.
[0089] Step 503: Based on the initial grab signal and the data transmission delay of each storage area, generate a sub-grab signal for each storage area.
[0090] Specifically, based on the initial grab signal and the data transmission delay of each storage area, a sub-grab signal for each storage area is generated so that the time interval between the time when the read / write control module receives the data transmitted from the global data line of each storage area and the time when it receives the sub-grab signal corresponding to the storage area meets a preset range.
[0091] Specifically, the data transmission latency of the storage area closer to the column decoding module is less than that of the storage area farther away from the column decoding module.
[0092] In some embodiments, the data transmission delay is greater than or equal to the data transmission delay on the global data line YIO between storage area 101 and read / write control module 103.
[0093] Furthermore, in some embodiments, the value of the data transmission delay is equal to the data transmission delay on the global data line YIO between the storage area 101 and the read / write control module 103.
[0094] In one example, a sub-grab signal corresponding to each storage area is generated based on the initial grab signal and the data transmission delay of the global data line between the storage area and the read / write control module. This includes: obtaining the data transmission delay of the global data line between each storage area and the read / write control module, and generating a sub-grab signal corresponding to each storage area based on the initial grab signal and the data transmission delay.
[0095] In one example, based on the initial grab signal and the data transmission delay of the global data line between the storage area and the read / write control module, a sub-grab signal corresponding to each storage area is generated. This includes: obtaining the address of the enabled word line, obtaining the storage area to which the enabled word line address belongs, obtaining the preset value corresponding to the storage area based on the location of the storage area, counting based on the initial grab signal and the clock signal, and when the count value equals the preset value, outputting the sub-grab signal of the storage area corresponding to the preset value.
[0096] For storage regions 0 to 35, as shown in the figure, for the column selection signal YS issued by column decoding module 102, the storage region farther from column decoding module 102 receives the column selection signal YS at a faster time than the storage region closer to column decoding module 102; Reference Figure 1 Assuming that a column selection signal YS is provided at time 0, the time when storage area 0 receives the column selection signal YS is T0, and the time delay when storage areas 1 to 35 receive the column selection signal YS is T0 + ΔT0 (ΔT0 is different for different storage areas 101).
[0097] As can be seen from the above, the data transmission delay corresponding to the storage area closer to the column decoding module 102 is less than the data transmission delay corresponding to the storage area farther away from the column decoding module 102; Reference Figure 1 Assume that the delay for data in storage area 0 to be transmitted to the read / write control module 103 via the global data line is T1, and the delay for data in storage areas 1 to 35 to be transmitted to the read / write control module 103 via the global data line is T1 + ΔT1 (ΔT1 is different for different storage areas 101).
[0098] In an ideal scenario (without delay of the column select signal YS and without global data line data transmission delay), the time for data transmission from storage area 101 to read / write control module 103 is T0+T1. However, in reality, the time for data transmission from storage area 101 to read / write control module 103 is T0+ΔT0+T1+ΔT1. By generating a sub-grab signal gxEn for each storage area 101 based on the initial grab signal gEn, the data grabbing time for each storage area is adjusted. The data is grabbed by read / write control module 103 at different times to unify the time interval between the time when read / write control module 103 receives data transmitted from global data line YIO from different storage areas 101 and the time when it receives the corresponding sub-grab signal gxEn. This ensures that the time interval between the time when read / write control module 103 receives data transmitted from global data line YIO from each storage area 101 and the time when it receives the corresponding sub-grab signal gxEn for the storage area 101 meets a preset range.
[0099] Specifically, refer to Figure 2 and Figure 3 For storage areas 101 close to column decoding module 102, such as storage area 0, the column selection signal YS can be received relatively quickly, i.e., T0 + ΔT0 is small. For this storage area 101, after the signal transmission time d of the local input / output circuit, a read operation enable signal RdEn is generated. Under the action of the read operation enable signal RdEn, the data transmission of the global data line YIO can be performed relatively quickly, i.e., T1 + ΔT1 is small. At this time, the read / write control module 103 receives the read data transmitted from this storage area 101 earlier, i.e., T0 + ΔT0 + T1 + ΔT1 is small. The read / write control module 103 is controlled to capture data in advance by the sub-grab signal gxEn, so that the time interval t meets the preset range.
[0100] Continue to refer to Figure 2 and Figure 3 For storage areas 101 far from column decoding module 102, such as storage area 35, the column selection signal YS needs to be received slowly, i.e., T0 + ΔT0 is relatively large. For this storage area 101, after the signal transmission time d of the local input / output circuit, a read operation enable signal RdEn is generated. Under the action of the read operation enable signal RdEn, the data transmission of the global data line YIO needs to be performed slowly, i.e., T1 + ΔT1 is relatively large. The time for the read / write control module 103 to receive the read data transmitted from this storage area 101 is relatively large, i.e., T0 + ΔT0 + T1 + ΔT1 is large. The read / write control module 103 captures data by delaying the sub-grab signal gxEn, so that the time interval t meets the preset range.
[0101] For storage access 36 to 71, based on the above assumptions, the time delay for storage areas 36 to 71 to receive the column selection signal YS is T0 + ΔT0 (ΔT0 is different for different storage areas 101); the delay for data from storage areas 36 to 71 to be transmitted to the read / write control module 103 via the global data line is T1 + ΔT1 (ΔT1 is different for different storage areas 101).
[0102] For storage areas 101 close to column decoding module 102, such as storage area 71, the column selection signal YS can be received relatively quickly, i.e., T0 + ΔT0 is small. For this storage area 101, the data transmission of global data line YIO needs to be slow, i.e., T1 + ΔT1 is large. For storage areas 101 far from column decoding module 102, such as storage area 36, the column selection signal YS needs to be received slowly, i.e., T0 + ΔT0 is large. For this storage area 101, the data transmission of global data line YIO can be fast, i.e., T1 + ΔT1 is small. Because the column selection signal YS has a high RC load, the time T0+△T0+T1+△T1 for the read / write control module 103 to receive read data transmitted from different storage areas 101 will still differ. Specifically, the larger T0+△T0 is, the larger T0+△T0+T1+△T1 is. That is, for storage areas 101 closer to the column decoding module 102, the read / write control module 103 needs to be controlled to capture data in advance through the sub-grab signal gxEn so that the time interval t meets the preset range; for storage areas 101 farther from the column decoding module 102, the read / write control module 103 needs to be controlled to capture data with a delay through the sub-grab signal gxEn so that the time interval t meets the preset range.
[0103] Each sub-grab signal gxEn is used to configure the corresponding storage area 101 to complete data reading. If data is read continuously, the effective level of the corresponding sub-grab signal gxEn is integrated into the same signal according to the storage area to be read, generating a grab enable signal GEn. The grab enable signal GEn is used to instruct the corresponding storage area to complete continuous data reading.
[0104] Step 504: Generate a grab enable signal based on all sub-grab signals.
[0105] Specifically, the effective level of each sub-grabbing signal is integrated onto the same signal to generate a grab enable signal; or, the effective level common to some sub-grabbing signals is integrated onto the secondary grab signal, and the effective level of each secondary grab signal is integrated onto the same signal to generate a grab enable signal.
[0106] Step 505: Based on the capture enable signal, read the data on the global data line to the data bus.
[0107] This embodiment generates a sub-grab signal for each storage area based on the initial grab signal to adjust the data to be written in each storage area. The data is grabbed by the read / write control module at different times, thereby unifying the time interval between the data received from the global data line and the received column selection signal in different storage areas. This ensures that the time interval between the sub-grab signal and the column selection signal applied to each storage area meets the preset range, thus unifying the time interval between the column selection signal and the data in different storage areas after transmission on the global data line, and optimizing the DRAM's tCCD.
[0108] Since the above embodiments correspond to this embodiment, this embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments remain valid in this embodiment, and the technical effects achievable in the above embodiments can also be achieved in this embodiment. To reduce repetition, they will not be repeated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.
[0109] Another embodiment of this disclosure provides a memory including multiple storage regions and a column decoding module. Each storage region is connected to a global data line YIO, and based on a column selection signal YS, the column decoding module reads the data stored in the storage cell to the global data line YIO. The data readout circuit provided in the above embodiment is used to read the data on the global data line, so as to unify the time interval between the time when the read / write control module RWCB receives the data transmitted from the global data line YIO from different storage regions and the time of the sub-fetch signal corresponding to the storage region, thereby optimizing the DRAM's tCCD.
[0110] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the DRAM chip conforms to the DDR2 memory specification.
[0111] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the DRAM chip conforms to the DDR3 memory specification.
[0112] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the DRAM chip conforms to the DDR4 memory specification.
[0113] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the DRAM chip conforms to the DDR5 memory specification.
[0114] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.
Claims
1. A data readout circuit applied to a memory, the memory comprising a read / write control module, a column decoding module, and multiple storage areas, characterized in that, include: The delay generation module is configured to generate a sub-grab signal for each of the storage regions based on the initial grab signal and the data transmission delay of each of the storage regions, and to generate a grab enable signal based on all the sub-grab signals. The data transmission delay corresponding to the storage area closer to the column decoding module is less than the data transmission delay corresponding to the storage area farther from the column decoding module. The time interval between the time when the read / write control module receives the data transmitted from the global data line to each of the storage areas and the time when it receives the sub-grab signal corresponding to the storage area meets a preset range; The read / write control module is configured to read data from the global data line to the data bus based on the capture enable signal. The global data line is configured to read data from the storage area based on the column selection signal via the column decoding module.
2. The data readout circuit according to claim 1, characterized in that, The delay generation module includes: The delay unit is configured to generate the sub-fetch signal corresponding to each of the storage regions; The integration unit is configured to generate the grab enable signal based on the sub-grab signal corresponding to the storage region to which the enabled state word line belongs.
3. The data readout circuit according to claim 2, characterized in that, The delay unit includes multiple delay sub-units; Multiple delay sub-units are connected in series; In the series of multiple delay sub-units, the input terminal of the first-level delay sub-unit is used to receive the initial grab signal, and the connection line between two adjacent delay sub-units and the output terminal of the last-level delay sub-unit are used to output the sub-grab signals corresponding to different storage regions. Different sub-grabbing signals have different data transmission delays.
4. The data readout circuit according to claim 3, characterized in that, Each of the delay sub-units is provided with an even number of inverters, and the number of inverters in some of the delay sub-units is not the same.
5. The data readout circuit according to claim 3, characterized in that, Each of the delay sub-units is provided with an even number of inverters, and the number of inverters in each delay sub-unit is the same.
6. The data readout circuit according to claim 2, characterized in that, The integration unit includes: Multiple primary NAND gates, each primary NAND gate corresponding to a storage region, wherein one input terminal of the primary NAND gate is used to receive a region indication signal corresponding to the storage region, and the other input terminal is used to receive a sub-grabbing signal corresponding to the storage region; The region indication signal is used to characterize the memory region to which the word line in the enabled state belongs; The outputs of multiple primary NAND gates are connected to the same output OR gate, which is used to output the grasp enable signal.
7. The data readout circuit according to claim 6, characterized in that, The delay unit includes a delay transmission line that connects to the input terminals of multiple primary NAND gates, and also includes a signal terminal that receives the initial capture signal. The distance between the signal terminal and the connection point of the primary NAND gate input terminal is positively correlated with the data transmission delay corresponding to the primary NAND gate.
8. The data readout circuit according to claim 6, characterized in that, The integration unit further includes: Multiple secondary NAND gates, wherein the number of secondary NAND gates is less than the number of primary NAND gates, and each secondary NAND gate is connected to at least two primary NAND gates; The outputs of the plurality of primary NAND gates are connected to the same output OR gate, and the output OR gate is used to output the grasp enable signal, including: the outputs of the plurality of secondary NAND gates are connected to the same output OR gate.
9. The data readout circuit according to claim 1, characterized in that, The delay generation module includes: The processing unit is configured to obtain the storage region to which the enabled word line address belongs based on the enabled word line address, and obtain a preset value corresponding to the storage region based on the location of the storage region. The counting unit, connected to the processing unit, is configured to receive the initial grasping signal, count based on a clock signal, and output the sub-grab signal corresponding to the storage area when the count value equals the preset value. The integration unit is configured to generate the grab enable signal based on the sub-grab signal corresponding to the storage region to which the enabled state word line belongs.
10. The data readout circuit according to claim 9, characterized in that, The delay generation module further includes a pre-storage unit connected to the processing unit, configured to pre-storage the preset values corresponding to each of the storage areas.
11. The data readout circuit according to claim 9, characterized in that, The clock signal is the internal clock signal of the memory.
12. The data readout circuit according to claim 1, characterized in that, The time interval between the time the read / write control module receives data transmitted from the global data line to each of the storage areas and the time it receives the sub-grab signal corresponding to the storage area is equal.
13. The data readout circuit according to claim 1, characterized in that, The value of the data transmission delay is equal to the transmission delay of the data on the global data line between the storage area and the read / write control module.
14. A data readout method, applied to the data readout circuit of any one of claims 1 to 13, characterized in that, include: Based on the column selection signal, the data in the storage unit is read out to the global data line; Provide the initial grasp signal; Based on the initial capture signal and the data transmission delay of each storage area, a sub-capture signal for each storage area is generated, so that the time interval between the time when the read / write control module receives the data transmitted from the global data line of each storage area and the time when it receives the sub-capture signal corresponding to the storage area meets a preset range; The data transmission delay of the storage area closer to the column decoding module is less than the data transmission delay of the storage area farther away from the column decoding module. Based on all the aforementioned sub-grab signals, a grab enable signal is generated; Based on the capture enable signal, the data on the global data line is read out to the data bus.
15. The data reading method according to claim 14, characterized in that, The step of generating a grab enable signal based on all the sub-grabbing signals includes: The effective level of each of the sub-grabbing signals is integrated onto the same signal to generate the grab enable signal; Alternatively, the effective level common to some of the sub-grabbing signals can be integrated onto the secondary grabbing signal, and the effective level of each of the secondary grabbing signals can be integrated onto the same signal to generate the grabbing enable signal.
16. The data reading method according to claim 14, characterized in that, The process of generating a sub-grabbing signal corresponding to each storage region based on the initial grabbing signal and the data transmission delay of the global data line between the storage region and the read / write control module includes: Obtain the data transmission latency of the global data line between each of the storage areas and the read / write control module; Based on the initial fetch signal and the data transmission delay, a sub-fetch signal corresponding to each storage region is generated.
17. The data reading method according to claim 14, characterized in that, The process of generating a sub-grabbing signal corresponding to each storage region based on the initial grabbing signal and the data transmission delay of the global data line between the storage region and the read / write control module includes: Get the address of the enabled word line; Obtain the storage area to which the enabled word line belongs, and obtain the preset value corresponding to the storage area based on the location of the storage area; Based on the initial grab signal and clock signal, a count is performed. When the count value equals the preset value, the sub-grab signal corresponding to the preset value in the storage area is output.
18. The data reading method according to claim 14, characterized in that, The value of the data transmission delay is equal to the transmission delay of the data on the global data line between the storage area and the read / write control module.
19. A memory, characterized in that, include: Read / write control module, column decoding module, and multiple storage areas; Each of the aforementioned storage areas is connected to the global data line, and based on the column selection signal, the data stored in the storage unit is read out to the global data line through the column decoding module; The data on the global data line is read out using the data readout circuit of any one of claims 1 to 13.