Cameras and electronic equipment

Abstract

The present invention relates to an image pickup device and an electronic device. The image pickup device may include: a photoelectric conversion unit configured to convert received light into electric charges; a holding unit configured to hold electric charges transferred from the photoelectric conversion unit; and a light shielding unit configured to shield light between the photoelectric conversion unit and the holding unit, wherein the photoelectric conversion unit, the holding unit, and the light shielding unit are formed in a semiconductor substrate having a predetermined thickness, and the light shielding unit in a transmission area that transfers the electric charges from the photoelectric conversion unit to the holding unit is formed as a non-penetrating light shielding unit that does not penetrate the semiconductor substrate, and the light shielding unit outside the transmission area is formed as a penetrating light shielding unit that penetrates the semiconductor substrate.

Description

[0001] This application is a divisional application of a patent application with application number 201880018106.0, whose application date is March 9, 2018 and invention name is “Camera device and electronic device”. Technical Field

[0002] The present invention relates to an imaging device and an electronic device, for example, to an imaging device and an electronic device capable of obtaining a better pixel signal. Background Art

[0003] Image pickup devices such as complementary metal oxide semiconductor (CMOS) image sensors and charge coupled devices (CCDs) are widely used in digital still cameras, digital video cameras, and the like.

[0004] For example, incident light on a CMOS image sensor undergoes photoelectric conversion in a photodiode (PD) included in a pixel. Then, the charge generated in the PD is transferred to a floating diffusion (FD) through a transfer transistor and converted into a pixel signal having a level according to the amount of received light.

[0005] Meanwhile, in conventional CMOS image sensors, since a mechanism of sequentially reading pixel signals from individual pixels row by row (a so-called rolling shutter mechanism) is generally adopted, image distortion sometimes occurs due to differences in exposure time.

[0006] Therefore, for example, Patent Document 1 discloses a CMOS image sensor that adopts a scheme of simultaneously reading pixel signals from all pixels by providing a charge holding portion in each pixel, i.e., a so-called global shutter scheme, and has a full-pixel synchronized electronic shutter function. By adopting the global shutter scheme, the exposure time for all pixels becomes the same, making it possible to avoid distortion in the image.

[0007] Reference List

[0008] Patent Literature

[0009] Patent Document 1:

[0010] Japanese Patent Application Publication No. 2008-103647 Summary of the invention

[0011] Technical Problems to be Solved by the Invention

[0012] Since the pixel layout is limited in the case of adopting a structure in which a charge retention unit is provided in the pixel, the aperture ratio is reduced, and there is a problem that the PD sensitivity may be reduced or the capacity of the PD and the charge retention unit may be reduced. In addition, there is a problem that light incident on the charge retention unit while retaining the charge may generate optical noise.

[0013] The present invention has been proposed in view of the above circumstances, and is capable of obtaining a better pixel signal.

[0014] Solutions to technical problems

[0015] According to one aspect of the present invention, an imaging device includes: a photoelectric conversion unit, which is configured to convert received light into electric charges; a holding unit, which is configured to hold the electric charges transferred from the photoelectric conversion unit; and a light shielding unit, which is configured to shield light between the photoelectric conversion unit and the holding unit, wherein the photoelectric conversion unit, the holding unit and the light shielding unit are formed in a semiconductor substrate having a predetermined thickness, and the light shielding unit in a transmission area that transfers the electric charges from the photoelectric conversion unit to the holding unit is formed as a non-penetrating light shielding unit that does not penetrate the semiconductor substrate, and the light shielding unit outside the transmission area is formed as a penetrating light shielding unit that penetrates the semiconductor substrate.

[0016] An electronic device according to one aspect of the present invention includes: an imaging device, including: a photoelectric conversion unit, which is configured to convert received light into electric charges; a holding unit, which is configured to hold the electric charges transmitted from the photoelectric conversion unit; and a shading unit, which is configured to shield light between the photoelectric conversion unit and the holding unit, wherein the photoelectric conversion unit, the holding unit and the shading unit are formed in a semiconductor substrate having a predetermined thickness, the shading unit in a transmission area that transmits the electric charges from the photoelectric conversion unit to the holding unit is formed as a non-penetrating shading unit that does not penetrate the semiconductor substrate, and the shading unit outside the transmission area is formed as a penetrating shading unit that penetrates the semiconductor substrate; and a processing unit, which is configured to process a signal from the imaging device.

[0017] An image pickup device according to one aspect of the present invention includes: a photoelectric conversion unit configured to convert received light into electric charges; a holding unit configured to hold electric charges transferred from the photoelectric conversion unit; and a light shielding unit configured to shield light between the photoelectric conversion unit and the holding unit. The photoelectric conversion unit, the holding unit, and the light shielding unit are formed in a semiconductor substrate having a predetermined thickness, and the light shielding unit in a transfer area that transfers the electric charges from the photoelectric conversion unit to the holding unit is formed as a non-penetrating light shielding unit that does not penetrate the semiconductor substrate, and the light shielding unit outside the transfer area is formed as a penetrating light shielding unit that penetrates the semiconductor substrate.

[0018] An electronic device according to one aspect of the present invention includes the imaging device.

[0019] Beneficial effects of the present invention

[0020] According to one aspect of the present invention, a better pixel signal can be obtained.

[0021] Note that the effects described here are not necessarily limiting, and any effects described in the present disclosure may be applied. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a diagram showing the configuration of an image sensor.

[0023] Figure 2 is a diagram showing the structure of a pixel.

[0024] Figure 3 It is a diagram for explaining the influence of reflected light.

[0025] Figure 4 is a diagram showing the configuration of one embodiment of a pixel to which the present invention is applied.

[0026] Figure 5 is a plan view showing the configuration of a pixel.

[0027] Figure 6 is a cross-sectional view showing the configuration of a pixel.

[0028] Figure 7 It is a figure for demonstrating the light shielding part.

[0029] Figure 8 It is a diagram for explaining the depth of the light shielding portion.

[0030] Fig. 9 It is a diagram for explaining the depth of the light shielding portion.

[0031] Fig.10 is a plan view showing another configuration of a pixel.

[0032] Fig.11 is a plan view showing another configuration of a pixel.

[0033] Fig.12 is a plan view showing another configuration of a pixel.

[0034] Fig.13 is a plan view showing another configuration of a pixel.

[0035] Fig.14 is a plan view showing another configuration of a pixel.

[0036] Fig.15 is a plan view showing another configuration of a pixel.

[0037] Fig.16 is a plan view showing another configuration of a pixel.

[0038] Fig.17 is a plan view showing another configuration of a pixel.

[0039] Fig.18 is a plan view showing another configuration of a pixel.

[0040] Fig.19 is a plan view showing another configuration of a pixel.

[0041] Fig. 20 is a plan view showing another configuration of a pixel.

[0042] Fig.21 is a plan view showing another configuration of a pixel.

[0043] Fig. 22 is a plan view showing another configuration of a pixel.

[0044] Fig.23 is a plan view showing another configuration of a pixel.

[0045] Fig.24 is a plan view showing another configuration of a pixel.

[0046] Fig.25 is a plan view showing another configuration of a pixel.

[0047] Fig.26 is a plan view showing another configuration of a pixel.

[0048] Fig. 27 is a plan view showing another configuration of a pixel.

[0049] Fig.28 is a plan view showing a common structure of pixels.

[0050] Fig.29 It is a diagram for explaining the arrangement of on-chip lenses.

[0051] Fig.30 It is a diagram for explaining the arrangement of on-chip lenses.

[0052] Fig.31 It is a diagram for explaining the arrangement of on-chip lenses.

[0053] Fig.32 It is a diagram for explaining the arrangement of on-chip lenses.

[0054] Fig.33 It is a diagram for explaining the arrangement of on-chip lenses.

[0055] Fig.34 It is a diagram for explaining the arrangement of on-chip lenses.

[0056] Fig.35 It is a diagram for explaining the arrangement of on-chip lenses.

[0057] Fig.36 It is a diagram for explaining the arrangement of on-chip lenses.

[0058] Fig.37 This is a diagram for explaining the manufacturing of pixels.

[0059] Fig.38 This is a diagram for explaining the manufacturing of pixels.

[0060] Fig.39 This is a diagram for explaining the manufacturing of pixels.

[0061] Fig.40 This is a diagram for explaining the manufacturing of pixels.

[0062] Fig.41 This is a diagram for explaining the manufacturing of pixels.

[0063] Fig.42 A diagram for explaining the structure of an electronic device. DETAILED DESCRIPTION

[0064] Hereinafter, modes for carrying out the present invention (hereinafter referred to as embodiments) will be described.

[0065] <Structure of the imaging device>

[0066] Figure 1 is a block diagram showing an exemplary configuration of a complementary metal oxide semiconductor (CMOS) image sensor as an image pickup device to which the present invention is applied.

[0067] The CMOS image sensor 30 includes a pixel array section 41, a vertical drive section 42, a column processing section 43, a horizontal drive section 44, and a system control section 45. The pixel array section 41, the vertical drive section 42, the column processing section 43, the horizontal drive section 44, and the system control section 45 are formed on a semiconductor substrate (chip) not shown.

[0068] In the pixel array section 41, the unit pixel ( Figure 2 The pixels 50 in the image processing unit are arranged in a matrix in a two-dimensional manner, and each unit pixel includes a photoelectric conversion element that generates and internally accumulates a photoelectric charge of a charge amount that depends on the amount of incident light. Note that, hereinafter, the photoelectric charge of a charge amount that depends on the amount of incident light may be simply described as a "charge", and the unit pixel may be simply described as a "pixel".

[0069] Furthermore, in the pixel array section 41, a pixel drive line 46 is formed along the horizontal direction in the drawing (the arrangement direction of pixels in the pixel row) for each row of the matrix pixel array, and a vertical signal line 47 is formed along the vertical direction in the drawing (the arrangement direction of pixels in the pixel column) for each column. One end of each pixel drive line 46 is connected to an output terminal corresponding to each row of the vertical drive section 42.

[0070] The CMOS image sensor 30 further includes a signal processing unit 48 and a data storage unit 49. The signal processing unit 48 and the data storage unit 49 may be external signal processing units disposed on a substrate different from the CMOS image sensor 30, for example, processed by a digital signal processor (DSP) or software; or, the signal processing unit 48 and the data storage unit 49 may be mounted on the same substrate as the CMOS image sensor 30.

[0071] The vertical drive section 42 is a pixel drive section including a shift register, an address decoder, etc., and drives each pixel of the pixel array section 41 in a manner of simultaneously driving all pixels, pixels of each row, etc. The vertical drive section 42 includes a read scanning system, a scan-out scanning system, or batch scanning and batch transfer, but the description of its specific configuration is omitted.

[0072] The read scanning system sequentially selects and scans the unit pixels of each row of the pixel array section 41 so as to read signals from the unit pixels. In the case of row driving (rolling shutter operation), regarding the sweep out, the read row for the read scanning is swept out by the read scanning system at the time of the shutter speed before the read scanning. In addition, in the case of global exposure (global shutter operation), the batch scanning is performed at the time of the shutter speed before the batch transfer.

[0073] By this scanning, unnecessary charges are swept out (reset) from the photoelectric conversion element of the unit pixel of the read row. Then, the so-called electronic shutter operation is performed by sweeping out (resetting) unnecessary charges. Here, the electronic shutter operation is an operation of discarding the photoelectric conversion element's photocharge and restarting exposure (starting to accumulate photocharge).

[0074] The signal read by the reading operation of the reading scanning system corresponds to the amount of light incident after the previous reading operation or the electronic shutter operation. In the case of row driving, the period from the reading moment of the previous reading operation or the sweeping moment of the electronic shutter operation to the reading moment of the current reading operation is the photocharge accumulation period (exposure period) in the unit pixel. In the case of global exposure, the period from batch sweeping to batch transfer is the accumulation period (exposure period).

[0075] The pixel signal output from each unit pixel of the pixel row selected and scanned by the vertical drive section 42 is supplied to the column processing section 43 through each vertical signal line 47. The column processing section 43 performs predetermined signal processing on the pixel signal output from each unit pixel of the selected row through the vertical signal line 47 for each pixel column of the pixel array section 41, and temporarily holds the pixel signal subjected to the signal processing.

[0076] Specifically, the column processing section 43 performs at least noise removal processing, for example, correlated double sampling (CDS) processing as signal processing. Fixed pattern noise unique to pixels such as reset noise and threshold value variation of an amplifier transistor are removed by the correlated double sampling performed by the column processing section 43. Note that, for example, the column processing section 43 can be made to have, for example, an analog-to-digital (AD) conversion function in addition to the noise removal processing, and output a signal level as a digital signal.

[0077] The horizontal driving section 44 includes a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns of the column processing section 43. Through the selection and scanning performed by the horizontal driving section 44, the pixel signals subjected to the signal processing by the column processing section 43 are sequentially output to the signal processing section 48.

[0078] The system control section 45 includes a timing generator that generates various timing signals and the like, and controls driving of the vertical driving section 42 , the column processing section 43 , the horizontal driving section 44 and the like based on the various timing signals generated by the timing generator.

[0079] The signal processing section 48 has at least an addition processing function, and performs various types of signal processing such as addition processing on the pixel signal output from the column processing section 43. While the signal processing section 48 performs signal processing, the data storage section 49 temporarily stores data necessary for the processing.

[0080] <Unit Pixel Structure>

[0081] In the following, it will be explained Figure 1 Detailed structure of the unit pixels 50 arranged in a matrix in the pixel array section 41. Figure 2 is a diagram showing an exemplary cross-sectional configuration of the pixel 50 .

[0082] use Figure 2 The pixel 50a shown can prevent light from leaking into the charge holding region 68 and can prevent the generation of optical noise. Figure 4 The pixel 50b shown in FIG. 1 can further suppress the incidence of light on the charge holding region 68 (parasitic sensitivity (PLS): a phenomenon similar to tailing) (the influence of the incidence of light is reduced).

[0083] First, refer to Figure 2 , the structure of pixel 50a having a structure for preventing light from leaking into charge holding region 68 will be described.

[0084] like Figure 2 As shown, pixel 50a has Figure 2 The lower side of the semiconductor substrate 63 has a structure in which a wiring layer 61, an oxide film 62, a semiconductor substrate 63, a light shielding layer 64, a color filter layer 65, and an on-chip lens 66 are stacked in order. In addition, in the pixel 50a, the area where the PD 51 is formed in the semiconductor substrate 63 is the PD area 67, and the area where the charge holding portion 54 is formed in the semiconductor substrate 63 is the charge holding area 68.

[0085] Note that the image sensor 30 is a so-called back-illuminated CMOS image sensor in which incident light is irradiated on the rear surface ( Figure 2 On a surface facing upward in the middle, a wiring layer 61 is provided on a semiconductor substrate 63 at the front surface.

[0086] For example, the wiring layer 61 is supported by a substrate support member (not shown) provided therebelow and has a structure in which a plurality of wirings 71 are embedded in an interlayer insulating film 72 , wherein the plurality of wirings 71 perform processing such as reading charges of the PD 51 formed in the semiconductor substrate 63 .

[0087] Furthermore, in the wiring layer 61, a TRX gate 73 constituting a transfer transistor is arranged below the semiconductor substrate 63 via an oxide film 62 in a region between the PD 51 and the charge holding portion 54. In response to application of a predetermined voltage to the TRX gate 73, the charge accumulated in the PD 51 is transferred to the charge holding portion 54.

[0088] The oxide film 62 has insulating properties and insulates the surface side of the semiconductor substrate 63. In the semiconductor substrate 63, an N-type region constituting the PD 51 and an N-type region constituting the charge holding portion 54 are formed.

[0089] Furthermore, a surface pinning layer 74-1 is formed on the back side of the PD 51 and the charge holding portion 54, and a surface pinning layer 74-2 is formed on the front side of the PD 51 and the charge holding portion 54. Furthermore, in the semiconductor substrate 63, an inter-pixel separation region 75 for separating the pixel 50a and another adjacent pixel 50a is formed so as to surround the periphery of the pixel 50a.

[0090] The light shielding layer 64 is formed by embedding a light shielding portion 76 including a material having a light shielding property in a high dielectric constant material film 77. For example, the light shielding portion 76 includes a material such as tungsten (W), aluminum (Al) or copper (Cu) and is connected to a ground terminal (GND) not shown. The high dielectric constant material film 77 includes a material such as silicon dioxide (SiO2), hafnium dioxide (HfO2), tantalum pentoxide (Ta2O5) or zirconium dioxide (ZrO2).

[0091] Furthermore, the light shielding portion 76 includes a cover portion 76A provided to cover the semiconductor substrate 63, and an embedded portion 76B embedded in a vertical groove formed in the semiconductor substrate 63 so as to surround the PD 51 and the charge holding portion 54. In other words, the cover portion 76A is formed substantially parallel to each layer constituting the pixel 50a, and the embedded portion 76B is formed to a predetermined depth so as to extend in a direction substantially orthogonal to the cover portion 76A.

[0092] Here, in addition to the configuration in which the embedded portion 76B of the light shielding portion 76 is formed in the inter-pixel separation region 75 so as to surround the PD 51 and the charge holding portion 54, the embedded portion 76B may have a configuration in which, for example, the embedded portion 76B is formed at the periphery of the charge holding portion 54, or a configuration in which the embedded portion 76B is formed between the PD 51 and the charge holding portion 54. In other words, it is at least required that the embedded portion 76B is formed between the PD 51 and the charge holding portion 54, and that the PD 51 and the charge holding portion 54 are separated by the embedded portion 76B.

[0093] Furthermore, in the light shielding portion 76, an opening 76C for allowing light to enter the PD 51 is formed. In other words, the opening 76C is formed in a region corresponding to the PD 51, and other regions such as the region where the charge holding portion 54, the FD 55, etc. are formed are shielded by the light shielding portion 76.

[0094] In addition, Figure 2 In the example shown, the light shielding portion 76 is formed so that a part of the embedded portion 76B penetrates the semiconductor substrate 63. In other words, the light shielding portion 76 is formed so that the embedded portion 76B penetrates the semiconductor substrate 63 in an area other than the area between the PD 51 and the charge holding portion 54 (that is, other than an area serving as a transfer path for transferring charges from the PD 51 to the charge holding portion 54).

[0095] In other words, the shading portion cannot be formed in the area for charge transfer between the PD 51 and the charge holding portion 54, but by forming an embedded portion 76B outside this area, this can effectively suppress light leakage from areas other than the PD 51 of the same pixel 50a into the charge holding portion 54.

[0096] In the following description, the light shielding portion 76 that penetrates the semiconductor substrate 63 is described as the penetrating light shielding portion 76, and the light shielding portion 76 that does not penetrate the semiconductor substrate 63 is described as the non-penetrating light shielding portion 76. Figure 2 , the light shielding portion 76 surrounding the pixel 50a is a penetrating light shielding portion 76, and the light shielding portion 76 formed between the PD 51 and the charge holding portion 54 is a non-penetrating light shielding portion. In addition, the penetrating light shielding portion 76 also does not penetrate the position where the transistor is provided or other positions.

[0097] In the color filter layer 65 , filters that transmit light of a color corresponding to each pixel 50 a are provided, and for example, filters that transmit green, blue, and red light are provided in a so-called Bayer array in each pixel 50 a .

[0098] The on-chip lens 66 is a small lens on the PD 51 for concentrating incident light incident on the pixel 50 a .

[0099] As described above, the pixel 50a includes the light shielding portion 76 in which the embedded portion 76B is formed at least between the PD 51 and the charge holding portion 54. With this configuration, as shown in FIG. Figure 2 As shown by the hollow arrow in , even if light is incident from an oblique direction and passes through PD 51, the light can be shielded by embedded portion 76B, thereby preventing the light from leaking into charge holding region 68. Therefore, the generation of optical noise that may be generated when light leaks into charge holding region 68 can be prevented.

[0100] <About Light Entering the Charge Retention Region>

[0101] for Figure 2 In the pixel 50a shown, since the light that passes through the PD 51 and enters the charge holding portion 54 is incident in an oblique direction, it is shielded by the light shielding portion 76, and as described above, it is possible to prevent the generation of optical noise that may be generated when the light leaks into the charge holding region 68. In addition, the effect of reducing the light reflected by the wiring layer 61 will be described.

[0102] Figure 3 Again, it shows Figure 2 Pixel 50a shown. Figure 3 As shown by the hollow arrow in FIG. 5 , among the light incident on the PD 51, some light passes through the PD 51 and reaches the wiring layer 61. Part of the light reaching the wiring layer 61 is reflected by the wiring 71 and is incident on the charge holding portion 54. Therefore, there is a possibility that light can be incident on the charge holding portion 54 not only from the PD 51 side but also from the wiring layer 61 side.

[0103] A description will be given of a method of the pixel 50 for reducing the influence of the light component from the wiring layer 61 side to further suppress the generation of optical noise that may be generated in the case where light leaks to the charge holding region 68 .

[0104] <Other pixel structures>

[0105] Figure 4 is a diagram showing another configuration of the pixel 50. Figure 4 In the subsequent figures of the pixel 50 , illustration of the wiring layer 61 , the light shielding layer 64 , the color filter layer 65 , and the on-chip lens 66 will be omitted.

[0106] When compared Figure 4 The pixel 50b and Figure 2 In the case of pixel 50a shown in FIG. 1 , the charge holding region 68 is constructed differently. The charge holding region 68b of pixel 50b is constructed in the same manner as Figure 2 The pixel 50a shown includes a surface pinning layer 74-1b, a charge holding portion 54b, and a surface pinning layer 74-2b in a similar manner, but the thickness of each layer, particularly the thickness of the charge holding portion 54b, is thin.

[0107] Figure 4 The thickness of the charge holding portion 54b of the pixel 50b shown is a thickness that satisfies the conditions to be described below. It is assumed that the thickness of the semiconductor substrate 63 is thickness T1, and the thickness of half T1 is thickness T2. It is assumed that the thickness of the charge holding portion 54b and the pinning layer 74-1b is thickness T3. The charge holding portion 54b and the pinning layer 74-1b serve as a holding area (memory) for holding charges, and the thickness T3 of the memory is formed to be equal to or less than the thickness T2 of half the thickness of the semiconductor substrate 63.

[0108] Therefore, by forming only the thickness T3 of the charge holding portion 54 b and the pinning layer 74 - 1 b to be equal to or smaller than the thickness T2 which is half the thickness of the semiconductor substrate 63 , PLS can be suppressed.

[0109] Refer again Figure 3 , the light reflected by the wiring layer 61 is likely to reach the upper part of the charge holding region 68 (the upper side in the figure), that is, the upper part of the charge holding portion 54 (the side not on the wiring layer 61 side), and undergo photoelectric conversion. Figure 4 As shown, the structure in which the charge holding portion 54 is not provided on the upper portion of the charge holding region 68 can prevent the light reflected by the wiring layer 61 from being incident on the charge holding portion 54 .

[0110] Therefore, this structure can reduce the influence of light reflected by the wiring layer 61 and can prevent the generation of optical noise that may be generated in the case where light leaks to the charge holding region 68 .

[0111] <Structure of light shielding section>

[0112] As described above, providing the light shielding portion 76 , particularly the embedded portion 76B provided between the PD 51 and the charge holding portion 54 b , can prevent the generation of optical noise that may be generated when light penetrates the PD 51 and leaks into the charge holding region 68 .

[0113] Furthermore, the thickness of the charge holding portion 54 b is formed equal to or less than half the thickness of the semiconductor substrate 63 , so that generation of optical noise that may be generated when light is reflected by the wiring layer 61 and leaks into the charge holding region 68 can be prevented.

[0114] At the same time, the embedded portion 76B provided between the PD 51 and the charge holding portion 54b is provided as, for example, a light shielding portion 76 which does not penetrate the semiconductor substrate 63, as shown in FIG. Figure 4 If the embedded portion 76B provided between the PD 51 and the charge holding portion 54b is formed to penetrate the semiconductor substrate 63, the charge transfer from the PD 51 to the charge holding portion 54b cannot be performed. Therefore, the embedded portion 76B provided between the PD 51 and the charge holding portion 54b needs to have a structure that does not hinder the transfer from the PD 51 to the charge holding portion 54b.

[0115] At the same time, refer again Figure 3 If the embedded portion 76B provided between the PD 51 and the charge holding portion 54b penetrates the semiconductor substrate 63, it is considered that the light reflected by the wiring layer 61 is shielded by the embedded portion 76B and the light can be prevented from leaking into the charge holding portion 54b.

[0116] Therefore, the configuration of the embedding portion 76B that prevents light reflected by the wiring layer 61 from leaking into the charge holding portion 54 b without hindering the transfer of charges from the PD 51 to the charge holding portion 54 b will be described.

[0117] Figure 5 From below ( Figure 4 When observing from the lower side of Figure 4 A plan view of pixel 50b is shown. Figure 4 The pixel 50b shown is Figure 5 A schematic cross-sectional structure of the pixel 50 b in the cross section of arrow AB is shown.

[0118] The OFD 121 is located at the lower right in the figure. The OFD 121 indicates a drain connected to the reset gate of the PD 51. The OFD 121 is connected to the PD 51 via the OFG gate 122.

[0119] The charge holding region 68b is provided on the upper side of the PD 51. When the pixel 50b is viewed from below, the TRX gate 73b is provided in a region where the charge holding region 68b (charge holding portion 54b) is arranged. The TRX gate 73b is provided to control charge transfer from the PD 51 to the charge holding portion 54b.

[0120] The floating diffusion region 125 (FD 125 ) is provided on the left side of the charge holding region 68 b in the figure via the TRX gate 73 b . The TRG gate 124 is provided for transferring the charge from the charge holding portion 54 b to the floating diffusion region 125 .

[0121] The light shielding portion 76B-1 is formed in the upper portion of the charge holding region 68b (upper side in the figure). Although both ends of the light shielding portion 76B-1 are partially formed in a non-penetrating manner due to the provision of a transistor, etc., basically, the light shielding portion 76B-1 is formed as a penetrating light shielding portion that penetrates the semiconductor substrate 63 in order to prevent light leakage between pixels.

[0122] Similarly, the shading portion 76B-3 is formed in the lower portion of the PD region 67 (the lower side in the figure), and the area where the transistor 123 and the like are arranged is formed in a non-penetrating manner, but basically, in order to prevent light leakage between pixels, the shading portion 76B-3 is formed as a penetrating shading portion that penetrates the semiconductor substrate 63.

[0123] The transmissive light shielding portion 76B- 3 is a light shielding portion provided between the pixels 50 b and is the same as the transmissive light shielding portion 76B- 1 , but is denoted by a different reference numeral for convenience of explanation.

[0124] The light shielding portion 76B-2 is formed in a boundary portion between the charge holding region 68b and the PD 51. The light shielding portion 76B-2 will be referred to below. Figure 7 A part of the light shielding portion 76B-2 is a transmissive light shielding portion, and the other part is a non-transmissive light shielding portion.

[0125] In addition, the layout has Figure 5 The light shielding portion 76B-4 is provided in the region of the transistor 123 on the left side, and Figure 5 The light shielding portions 76B- 5 in the region of the OFG gate 122 on the middle right are all non-transmissive.

[0126] Between the pixels 50b, light leakage between the pixels is blocked by the penetrating light shielding portion 76B, except for the portion where the transistor is arranged, etc. In addition, light leaking from the PD 51 side to the charge holding portion 54b is blocked, and the penetrating light shielding portion 76B also blocks light reflected by the wiring layer 61, except for some portions between the PD region 67 (PD51) and the charge holding region 68b (charge holding portion 54b).

[0127] In other words, Figure 5 In the illustrated pixel 50 b , the light shielding portion 76 formed in a region other than a region for providing a transistor and a region required for charge transfer is a penetrating light shielding portion 76B that penetrates the semiconductor substrate 63 .

[0128] Figure 5 The schematic cross-sectional configuration of the pixel 50b in the cross section of the arrow AB is Figure 4 Pixel 50b is shown. Figure 5 The schematic cross-sectional configuration of the pixel 50b in the cross section indicated by arrow CD is Figure 6 Pixel 50b is shown. Figure 4 The pixel 50b and Figure 6 The pixel 50b shown has basically a similar cross-sectional configuration, but differs in that the light shielding portion 76B-2 formed between the PD 51 and the charge holding portion 54b is formed in a non-transmitting manner ( Figure 4 ) or in a penetrating manner ( Figure 6 ) formed.

[0129] In addition, reference will be made to Figure 7 The light shielding portion 76B-2 provided between the PD region 67 and the charge holding region 68b is described. The transistor 123 is arranged in the region from the position P0 to the position P1 on the left side in the figure, and the light shielding portion 76B-2 provided in this region is non-transmissive.

[0130] In the region from position P3 to position P5 where the PD 51 is arranged, the light shielding portion 76B- 2 provided in the region from position P3 to position P4 is transmissive, and the light shielding portion 76B- 2 provided in the region from position P4 to position P5 is non-transmissive.

[0131] exist Figure 7 In the example shown, the penetration light shielding portion 76B-2 is set starting from the position P2 located between the position P1 and the position P3, but the position P2 may be the same position as the position P3. In other words, the penetration light shielding portion may start from the same position as the end of the PD 51, or may start from a position different from the end of the PD 51.

[0132] exist Figure 7 In the example, the light shielding portion 76B- 2 provided in the region from the position P5 which is the position of the end of the OFG gate 122 to the position P6 which is the boundary position of the pixel 50 b is non-penetrating.

[0133] Therefore, a portion of the shading portion 76B-2 arranged between the PD region 67 and the charge holding region 68b is formed as a penetrating shading portion that penetrates the semiconductor substrate 63, and the shading portion 76B-2 arranged in an area where transistors, etc. are arranged and in an area for transferring charges from the PD 51 to the charge holding portion 54b is formed as a non-penetrating shading portion that does not penetrate the semiconductor substrate 63.

[0134] By making a part of the light shielding portion 76B- 2 provided between the PD region 67 and the charge holding region 68 b a transmission light shielding portion, it is possible to prevent the light reflected by the wiring layer 61 from leaking into the charge holding portion 54 b .

[0135] In addition, since the portion for transferring the charge from the PD 51 to the charge holding portion 54b is a non-penetrating light shielding portion, the transfer is not hindered. In other words, the area from the position P4 to the position P5 is a non-penetrating light shielding portion, and the transfer can be performed from the opening. For example, when the size from the position P3 of the end of the PD 51 to the position P5 of the end of the OFG gate 122 is 1, the opening needs to be formed to have a size of at least 1 / 5 or more.

[0136] In addition, for example, the light shielding portion 76B-2 (non-transmitting light shielding portion 76B-2) formed in a part of the opening needs to be formed at least to Figure 8 and Fig. 9 At the depth shown. Figure 8 and Fig. 9 In Figure 4 As shown, the thickness of the semiconductor substrate 63 is a thickness T1 , and half the thickness of the semiconductor substrate 63 is a thickness T2 .

[0137] like Figure 8 As shown, the depth T11 of the non-penetrating light shielding portion 76B-2 may be deeper than the thickness T2, where the thickness T2 is half the thickness of the semiconductor substrate 63. Figure 8 In the illustrated example, the excavated amount of the non-transmitting light shielding portion 76B- 2 is larger than the thickness T2 which is half the thickness of the semiconductor substrate 63 .

[0138] Or, if Fig. 9 As shown in FIG. 1 , the depth T12 of the non-penetrating light shielding portion 76B- 2 may be shallower than the thickness T2 which is half the thickness of the semiconductor substrate 63. In other words, Fig. 9 In the illustrated example, the excavated amount of the non-transmitting light shielding portion 76B- 2 is smaller than the amount of the thickness T2 which is half the thickness of the semiconductor substrate 63 .

[0139] In the case where the non-penetrating light shielding portion 76B-2 is provided to suppress PLS, it is necessary to perform P-type ion implantation to ensure a hole in the non-penetrating light shielding portion 76B-2. Figure 8As shown, when the excavation amount of the non-penetrating shading portion 76B-2 is set to be more than half of the film thickness of the excavated semiconductor substrate 63, the effect of suppressing PLS can be enhanced, but there is a possibility of reducing the charge transfer characteristics from PD51 to the charge holding portion 54b.

[0140] At the same time, if Fig. 9 As shown, when the excavation amount of the non-penetrating shading portion 76B-2 is set to be less than only half of the film thickness of the semiconductor substrate 63, there is a possibility that the effect of suppressing PLS is reduced, but charge can be provided without reducing the charge transfer characteristics from the PD 51 to the charge holding portion 54b.

[0141] Since the transfer characteristic has a trade-off relationship with the number of saturated electrons, the balance between suppressing PLS and the number of saturated electrons is considered, and the digging amount of the non-transmitting light shielding portion 76B- 2 is designed to obtain the performance required for the pixel 50 b .

[0142] <Other pixel structures>

[0143] Other configurations of the pixel 50 will be described.

[0144] Fig.10 is a plan view showing another configuration of the pixel 50. In contrast, Fig.10 The pixel 50c shown is Figure 5 The pixel 50b shown is different in that the light shielding portions 76B-2c formed between the PD region 67 and the charge holding region 68b (charge holding portion 54b) are all formed as non-transmitting light shielding portions, and the other portions are the same.

[0145] Similar reference numerals are used to represent Figure 5 The parts similar to the parts of the pixel 50b shown in FIG. 1 and the description thereof will be omitted. In addition, in the following description, similar reference numerals will also be used to describe the parts similar to the parts of the pixel 50b shown in FIG. Figure 5 A portion of pixel 50b is shown that is similar to the portion thereof.

[0146] As reference Figure 4 As described above, by forming a thin charge holding portion 54b, the influence of light reflected by the wiring layer 61 can be suppressed (PLS can be suppressed), and therefore even if all the shading portions 76c-2 formed between the PD 51 and the charge holding portion 54b are formed as non-penetrating shading portions, PLS can be suppressed.

[0147] However, Fig.10 The pixel 50c shown may have a lower PLS suppression performance than the reference pixel 50c. Figure 5 At the same time, with this configuration, the transfer from PD 51 to charge holding portion 54b is compared to the reference Figure 5 The pixel 50b described above is more advantageous in that the W length is increased.

[0148] In addition, in Fig.11 In the pixel 50d shown, all the light shielding portions 76B-1d and the light shielding portions 76B-3d formed between the pixels 50 may be formed as non-penetrating light shielding portions. Fig.11 In the pixel 50d shown, all the light shielding portions 76 are formed as non-transmitting light shielding portions.

[0149] exist Fig.11 In the configuration of pixel 50d shown, the performance of suppressing PLS may be lower than Fig.10 The pixel 50c shown in the figure does not have a mixture of the non-transmitting light-shielding portion and the transmitting light-shielding portion, so there is no need to produce the non-transmitting light-shielding portion and the transmitting light-shielding portion separately during manufacturing, thereby reducing the number of manufacturing steps.

[0150] Fig.12 is a plan view showing another configuration of the pixel 50. In contrast, Fig.12 The pixel 50e shown is Figure 5 The pixel 50 b shown is different in that the light shielding portion 76B- 4 and the light shielding portion 76B- 5 formed between the PD regions 67 are deleted, and the other parts are the same.

[0151] The light shielding portion 76B-4 and the light shielding portion 76B-5 formed between the PD regions 67 effectively suppress color mixing generated when light leaks from one PD 51 to another PD 51, but the light shielding portion 76B-4 and the light shielding portion 76B-5 may be deleted from the perspective of preventing light from leaking from the PD 51 to the charge holding portion 54b and light from the wiring layer 61. The light shielding portion 76B-4 and the light shielding portion 76B-5 formed between the PD regions 67 may be formed as needed.

[0152] Fig.13 is a plan view showing another configuration of the pixel 50. In contrast, Fig.13 The pixel 50f shown is Figure 5 The pixel 50b shown is different in that a light shielding portion 76B-6 and a light shielding portion 76B-7 are also formed between the charge holding regions 68b, and the other parts are the same.

[0153] Since the TRX gate 73 b and the TRG gate 124 are provided, the light shielding portion 76B- 6 and the light shielding portion 76B- 7 formed between the charge holding regions 68 b are non-transmitting light shielding portions.

[0154] The light shielding portion 76 is also provided between the charge holding regions 68 b , so that light can be prevented from leaking from one charge holding region 68 b to another charge holding region 68 b , and PLS can be suppressed more.

[0155] Fig.14 is a plan view showing another configuration of the pixel 50. In contrast, Fig.14 The pixel 50g shown is Figure 5 The pixel 50b shown is different in that the charge holding region 68g is provided at a position offset by half a pitch relative to the PD region 67g.

[0156] Fig.14 The PD region 67g-1 and the PD region 67g-2 adjacent to each other are shown. The charges accumulated in the PD region 67g-1 are transferred to the charge holding region 68g-1 formed under the TRX gate 73g-1. The PD region 67g-1 and the charge holding region 68g-1 are arranged at positions offset by half a pitch.

[0157] By setting the charge holding region 68g-1 at a position offset by half a pitch relative to the PD region 67g-1, the TRG gate 124g-1 can be set in the central portion of the charge holding region 68g-1 (TRX gate 73g-1). The TRG gate 124g-1 set in the central portion of the charge holding region 68b-1 can shorten the transfer length in the charge holding region 68b-1 and can improve the transfer efficiency.

[0158] Fig.15 is a plan view showing another configuration of the pixel 50. In contrast, Fig.15 The pixel 50h shown is Fig.14 The pixel 50g shown is different in that the light shielding portion 76B-4-1 (light shielding portion 76B-4-2) and the light shielding portion 76B-5-1 (light shielding portion 76B-5-2) formed between the PDs 51 are deleted, and the other parts are the same.

[0159] The structure and structure of the light shielding portions 76B-4 and 76B-5 formed between the PDs 51 are deleted. Fig.12 The pixel 50e shown in FIG. 5 is similar to the pixel 50e shown in FIG. 5 , and the PD region 67g and the charge holding region 68g of the pixel 50e are arranged at positions offset by half a pitch, thereby obtaining Fig.15 Pixel 50h of the construction shown.

[0160] As in Fig.12 The pixel 50e and Fig.15 In the pixel 50h shown in FIG. Fig.14) are effective in suppressing color mixing between the PDs 51, but the light shielding portions 76B-4 and 76B-5 may be deleted from the perspective of preventing light from leaking from the PDs 51 to the charge holding portion 54h and light from the wiring layer 61. The light shielding portions 76B-4 and 76B-5 formed between the PDs 51 may be formed as necessary.

[0161] Fig.16 is a plan view showing another configuration of the pixel 50. In contrast, Fig.16 The pixel 50i shown is Fig.14 The pixel 50g shown is different in that a light shielding portion 76B-6-1 (light shielding portion 76B-6-2) and a light shielding portion 76B-7-1 (light shielding portion 76B-7-2) are formed between the charge holding regions 68i, and the other parts are the same.

[0162] The structure of adding a light shielding portion 76B-6-1 (light shielding portion 76B-6-2) and a light shielding portion 76B-7-1 (light shielding portion 76B-7-2) between the charge holding regions 68i is similar to that of Fig.13 The pixel 50f shown in FIG. 5 is similar to the pixel 50f shown in FIG. 5, and the charge holding region 68f is arranged at a position offset by half a pitch relative to the PD region 67f of the pixel 50f, thereby obtaining Fig.16 Pixel 50i of the configuration shown.

[0163] As in Fig.13 The pixel 50f and Fig.16 In the pixel 50i shown, a light shielding portion 76 is also provided between the charge holding regions 68i, which can prevent light from leaking from one charge holding region 68i to another charge holding region 68i and can further suppress PLS.

[0164] Fig.17 is a plan view showing another configuration of the pixel 50 . Fig.17 The pixel 50j shown is Figure 5 The pixel 50b shown in FIG. 5 is different in that a TRY gate 201j is added, and the other configurations are similar.

[0165] Fig.17 The TRY gate 201j of the unit pixel 50j shown in FIG. 1 serves as a gate for preventing charges from flowing back from the charge holding region 68j to the PD region 67, and Fig.17 As shown, the TRY gate 201 j is disposed between the PD region 67 and the TRX gate 73 j.

[0166] The TRY gate 201 j is provided so that when the charge is transferred from the PD 51 to the charge holding portion 54 j , the TRY gate 201 j is turned on and then turned off so that the charge does not flow back into the PD 51 , thereby preventing the charge from flowing back into the PD 51 .

[0167] In addition, the TRY gate 201j has a storage function of accumulating charges. The storage function of the TRY gate 201j may be provided in the charge holding region 68j, or may be provided separately from the charge holding region 68j.

[0168] In the pixel 50 j having such a configuration, the TRY gate 201 j functions as a gate when charges are transferred from the PD 51 to the charge holding portion 54 j , and can also function as a gate for preventing charges from flowing back from the charge holding portion 54 j to the PD 51 .

[0169] Furthermore, the TRX gate 201 j functions as a gate when charges are transferred from the PD 51 j to the charge holding portion 54 j , and also functions as a gate for causing the charge holding portion 54 j to hold charges.

[0170] Fig.18 is a plan view showing another configuration of the pixel 50. Fig.17 Like the pixel 50j shown, Fig.18 The pixel 50k shown includes a TRY gate 201k and as shown in FIG. Fig.14 In the pixel 50g shown, the pixel 50k has a structure in which the charge holding region 68k is offset by half a pitch relative to the PD region 67k.

[0171] exist Fig.18 In the pixel 50k shown, the TRY gate 201k-1 is arranged at the upper right of the PD 51-1, and the TRX gate 73k-1 is arranged on the right side of the TRY gate 201k-1. In this arrangement, the TRX gate 73k-1 of the pixel 50k-1 is located at the upper left of the pixel 50k-2 on the right side of the pixel 50k-1.

[0172] Therefore, a configuration can be provided in which the TRX gate 73k-1 is located on the adjacent pixel 50k. In this arrangement, the charge from the PD 51k-1 is transferred to the TRX gate 73k-1 located on the right side of the TRY gate 201k-1 through the TRY gate 201k-1 located on the upper right.

[0173] Fig.19 is a plan view showing another configuration of the pixel 50. Fig.17 Like the pixel 50j shown, Fig.19 The pixel 50m shown includes a TRY gate 201m, but its layout is different.

[0174] exist Fig.19 In the pixel 50m shown in FIG. 1 , a TRY gate 201m, a TRX gate 73m, and a TRG gate 124m are sequentially arranged from the right in the lateral direction. Fig.19 In the example shown, the TRY gate 201m, the TRX gate 73m, and the TRG gate 124m are arranged at positions away from each other. Therefore, the respective gates can be arranged at positions away from each other in the lateral direction.

[0175] Fig. 20 is a plan view showing another configuration of the pixel 50. Fig.19 The same pixel as shown in 50m, Fig. 20 The pixel 50n shown includes a TRY gate 201n and is connected to Fig.14 Like the illustrated pixel 50g, the pixel 50n has a configuration in which the charge holding region 68n is offset by half a pitch relative to the PD region 67n.

[0176] exist Fig. 20 In the pixel 50n shown, the TRY gate 201n-1 is disposed at the upper right portion of the PD 51-1, and the TRX gate 73n-1 is disposed in the middle of the TRY gate 201n-1. In addition, the TRG gate 124n-1 is disposed at the upper center of the TRX gate 73n-1, and the FD 125n-1 is disposed in the central portion of the TRG gate 124n-1.

[0177] Therefore, the pixel 50 may further include a TRY gate 201 .

[0178] At the same time, as described above, the non-transmitting light shielding portion, for example, again referring to Figure 7 , the light shielding portion 76B-2 from position P4 to position P6 is formed as a non-penetrating light shielding portion. However, since P-type ion implantation is required to ensure a hole in the non-penetrating light shielding portion, there is a possibility of reducing the transmission efficiency from PD 51 to the charge holding portion 54. Therefore, the following describes a layout designed to read from PD 51.

[0179] Figure 21 to Figure 26 is a plan view of a pixel 50 having a layout designed for reading from a PD 51 . Figure 21 to Figure 26 Each of the pixels 50 shown in is formed in such a manner that a gate electrode located in the non-transmitting light shielding portion protrudes toward the PD 51 side.

[0180] Fig.21 is a plan view showing another configuration of the pixel 50 . Fig.21 The pixel 50p shown has Figure 5 The pixel 50b shown in FIG. 1 is similar in structure to the pixel 50b shown in FIG. 1 , but differs in that the TRX gate 73p protrudes into the PD 51. In other words, in Fig.21 In the illustrated pixel 50 p , the TRX gate 73 p is formed in a shape protruding toward the PD 51 side in the region of the light shielding portion 76B- 2 formed in a non-transmitting manner.

[0181] Therefore, when the TRX gate 73p is formed in a shape protruding toward the PD 51 side, the cross section of the pixel 50p is as follows: Figure 4 Refer again Figure 4 , a TRX gate 73 b is also formed on the lower side of the PD 51 .

[0182] Therefore, in addition to covering the charge holding region 68, the TRX gate 73 can be formed into a shape extending to the PD region 67 side. In addition, the extended portion can be a portion where the light shielding portion 76 is non-penetrating, in other words, it can be an opening opened for transmission from the PD 51 to the charge holding portion 54.

[0183] Fig. 22 is a plan view showing another configuration of the pixel 50 . Fig. 22 The pixel 50q shown has a Fig.15 The pixel 50h shown in FIG. 1 is similar in structure to the pixel 50h shown in FIG. 1 , but differs in that the TRX gate 73q protrudes into the PD 51. The TRX gate 73q is arranged in a manner similar to that of the pixel 50h. Fig.21 The pixel 50 p shown is formed in a shape protruding into the PD 51 in the same manner, and the TRX gate 73 q is formed in a shape protruding toward the PD 51 side in the region of the light shielding portion 76B- 2 formed in a non-transmitting manner.

[0184] Fig.23 is a plan view showing another configuration of the pixel 50 . Fig.23 The pixel 50r shown has Fig.17 The pixel 50j shown is constructed in the same manner as the pixel 50j and includes a TRY gate 201r, but differs in that the TRY gate 201y protrudes into the PD 51. The TRY gate 201r is formed in the same manner as the pixel 50j. Fig.21 The pixel 50p shown in the figure is formed in a shape protruding into the PD 51, and in the region of the light shielding portion 76B-2 formed in a non-penetrating manner, the TRY gate 201r is formed in a shape protruding to the PD 51 side instead of the TRX gate 73p ( Fig.21 ).

[0185] Note that also in Fig.23 In the case of the structure of the pixel 50r shown in FIG. Figure 4The pixel 50b shown in FIG. 5A is similar to the pixel 50b shown in FIG. 5B , and in this configuration, a portion of the TRX gate 73b is the TRY gate 201r, and the TRY gate 201r is formed on the lower side of the PD 51. Therefore, in addition to covering the charge holding region 68, the TRY gate 201 can be formed in a shape extending to the PD region 67 side. In addition, the extended portion can be a portion of the non-penetrating light shielding portion 76, in other words, it can be an opening opened for transmission from the PD 51 to the charge holding portion 54.

[0186] Fig.24 is a plan view showing another configuration of the pixel 50 . Fig.24 The pixel 50s shown has Fig.18 The pixel 50k shown is constructed in the same manner as the pixel 50k and includes a TRY gate 201s, but differs in that the TRY gate 201s protrudes into the PD 51. Fig.23 The pixel 50 r shown is formed in a shape protruding into the PD 51 in the same manner, and the TRY gate 201 s is formed in a shape protruding toward the PD 51 side in the region of the light shielding portion 76B- 2 formed in a non-transmitting manner.

[0187] Fig.25 is a plan view showing another configuration of the pixel 50 . Fig.25 The pixel 50t shown has Fig.19 The pixel 50m shown in FIG. 1 is constructed in the same manner as the pixel 50m and includes a TRY gate 201t, but differs in that the TRY gate 201t protrudes into the PD 51. Fig.23 The pixel 50 r shown is formed in a shape protruding into the PD 51 in the same manner, and the TRY gate 201 t is formed in a shape protruding toward the PD 51 side in the region of the light shielding portion 76B- 2 formed in a non-penetrating manner.

[0188] Fig.26 is a plan view showing another configuration of the pixel 50 . Fig.26 The pixel 50u shown has Fig. 20 The pixel 50n shown in FIG. 1 is constructed in the same manner as the pixel 50n and includes a TRY gate 201u, but differs in that the TRY gate 201u protrudes into the PD 51. Fig.24 The pixel 50s shown is formed in a shape protruding into the PD 51 in the same manner, and the TRY gate 201u is formed in a shape protruding toward the PD 51 side in the region of the light shielding portion 76B-2 formed in a non-penetrating manner.

[0189] Therefore, by forming the gate electrode protruding into the PD region 67 , it is possible to prevent the transfer efficiency from the PD 51 to the charge holding portion 54 from being reduced.

[0190] <About the structure of transistors>

[0191] Therefore, in the pixel 50 to which the present invention is applied, in the light shielding portion 76B-2 formed between the PD region 67 and the charge holding region 68, the portion where the transistor is provided and the portion for transferring the charge from the PD portion 51 to the charge holding portion 54 are formed as non-transmitting light shielding portions, and the other portions are formed as transmissive light shielding portions. For example, as the transistor 123 formed as the non-transmitting light shielding portion, Fig. 27 The transistor is shown as an example.

[0192] In the region of the transistor 123 , a reset (RST) transistor 301 , an amplification (AMP) transistor 302 , and a selection (SEL) transistor 303 are provided.

[0193] The reset transistor 301 is connected between an unillustrated power supply Vrst and the FD 125, and resets the FD 125 by applying a drive signal RST to the gate electrode. The amplifier transistor 302 has its drain electrode connected to an unillustrated power supply Vdd, its gate electrode connected to the FD 125, and reads the voltage of the FD 125.

[0194] For example, the drain electrode of the selection transistor 303 is connected to the source electrode of the amplifier transistor 302, the source electrode of the selection transistor 303 is connected to the vertical signal line, and the drive signal SEL is applied to the gate electrode to select the pixel 50 from which the pixel signal should be read. Note that a configuration in which the selection transistor 303 is connected between the power supply Vdd and the drain electrode of the amplifier transistor 302 may be employed.

[0195] Furthermore, a configuration in which a plurality of pixels 50 share the transistor 123 may be employed. Fig.28 A configuration is shown in which a plurality of pixels 50 share the transistor 123 .

[0196] Fig.28 1 shows a configuration in which four pixels of 2×2 share the transistor 123, and shows a case where the above-described reset transistor 301, amplification transistor 302, and selection transistor 303 are provided as the transistor 123. In addition, Fig.28 The example shown shows a pixel with Figure 5 The structure of the pixel 50b shown.

[0197] The reset transistor 301 is arranged between the pixel 50b-1 and the pixel 50b-2 to span a portion of the non-transmitting light shielding portion of the light shielding portion 76B-2-1 of the pixel 50b-1 and a portion of the non-transmitting light shielding portion of the light shielding portion 76B-2-2 of the pixel 50b-2.

[0198] The amplification transistor 302 is provided between the pixel 50b-1 and the pixel 50b-2. The selection transistor 303 is provided between the pixel 50b-3 and the pixel 50b-4.

[0199] A dummy portion 331 may be provided between the pixel 50b-3 and the pixel 50b-4 so as to span a portion of the non-penetrating light shielding portion of the light shielding portion 76B-2-3 of the pixel 50b-3 and a portion of the non-penetrating light shielding portion of the light shielding portion 76B-2-4 of the pixel 50b-4. The dummy portion 331 is provided when it is desired to ensure symmetry, etc. In addition, a transistor for switching conversion efficiency may be provided instead of the dummy portion 331.

[0200] therefore, Fig.28 The illustrated example has a configuration in which four pixels 50 b share a reset transistor 301 , an amplification transistor 302 , and a selection transistor 303 .

[0201] Therefore, a configuration in which a plurality of pixels share the transistor 123 can expand the area allocated to one transistor. Expanding the area allocated to one transistor allows a configuration capable of extending the distance between the source and drain of the transistor, and a configuration capable of preventing leakage.

[0202] In addition, if Fig.28 As shown, the reset transistor 301, the amplifying transistor 302, and the selecting transistor 303 can be divided and arranged separately. For example, dividing (separating) and arranging these transistors enables the L length of the amplifying transistor 302 to be increased and random noise to be reduced.

[0203] Furthermore, the configuration in which a plurality of pixels share the transistor 123 can achieve miniaturization.

[0204] <About Arrangement Position of On-Chip Lens>

[0205] Next, the arrangement position of the on-chip lens 66 will be described.

[0206] Figures 29 to 36 Each of the diagrams is a diagram for explaining the arrangement position of the on-chip lens 66 and is a plan view of the pixel 50. Figures 29 to 36 (Apart from Fig.34 ) Figure 5 The pixel 50 b shown is used as an example for description, but the following description can also be applied to other pixels 50 .

[0207] In addition, Figures 29 to 36 In FIG. 1 , for convenience of explanation, as in the above case, a plan view viewed from the wiring layer 61 side is used, and the on-chip lens 66 is shown in the plan view, but the on-chip lens 66 is provided on the incident side.

[0208] In addition, refer to Fig.29The pixel 50b shown, for example, as shown in FIG. Figure 4 As described above, the cover portion 76A of the shading portion 76 is formed on the charge holding region 68b to block incident light, and the shading portion 76 (cover portion 76A) is also arranged on the side where the on-chip lens 66 is provided, but for the sake of convenience of explanation, when viewed from the wiring layer 61 side, it is explained by an illustration superimposed on the plan view.

[0209] exist Fig.29 In the illustrated pixel 50 b , the on-chip lens 66 is arranged so that the center of the light-collecting diameter is located in the central portion of the PD region 67 (PD 51 ).

[0210] Note that Figures 29 to 36 In FIG. 6 , although the on-chip lens 66 is represented by a circle, the size of the circle does not represent the size of the on-chip lens 66 but represents the size of the focusing diameter of the on-chip lens 66. Therefore, for example, although Fig.29 The on-chip lens 66 shown as a circle in the figure is illustrated to be consistent with the PD area 67, but in fact the focusing diameter is consistent with the PD area 67, and the on-chip lens 66 itself is larger than the PD area 67.

[0211] For example, the shielded charge holding region 68 is provided beside the PD region 67, and the on-chip lens 66 may also be formed in the charge holding region 68. In other words, the on-chip lens 66 itself may be formed to be large.

[0212] exist Fig.29 In the pixel 50b shown, the PD region 67 is not blocked by the light shielding portion 76 but is open. The open region is the opening region 401a. For example, the opening region 401a corresponds to Figure 4 The opening 76C of the pixel 50b shown in FIG. 4 is formed to have the largest area so as to ensure sensitivity. Then, the on-chip lens 66 is arranged so that the center of (the focusing diameter of) the on-chip lens 66a coincides with the center of the opening area 401a.

[0213] exist Fig.30 In the pixel 50b shown, the opening area 401b is very small. Fig.30 In the pixel 50b shown, the on-chip lens 66b is arranged so that the center of (the focusing diameter of) the on-chip lens 66b coincides with the center of the PD region 67, and only the region in which the focusing diameter of the on-chip lens 66b is matched is the opening region 401b.

[0214] Therefore, by reducing the opening area 401b to an area where light can be concentrated by the on-chip lens 66b, it can be assumed that the F-number sensitivity is slightly reduced, but since useless PLS components can be cut, the influence of the PLS components can be further suppressed.

[0215] Fig.31 66 is a diagram for explaining another arrangement position of the on-chip lens 66. Fig.31 In the pixel 50b shown, Fig.29 As in the pixel 50b shown, an opening region 401c having the largest area is formed to ensure sensitivity. Then, the on-chip lens 66c is arranged so that the center of (the focusing diameter of) the on-chip lens 66c is located on the left side of the opening region 401c in the figure.

[0216] The on-chip lens 66c is disposed as far as possible from the transfer section that transfers the charge from the PD 51 to the charge holding section 54, in other words, the light shielding section 76B-2 formed in a non-transmitting manner performs the transfer, and the position of the light focusing diameter of the on-chip lens 66c coincides with the opening area 401c. Therefore, by disposing the on-chip lens 66c at a position away from the non-transmitting light shielding section (transfer section), the PLS can be improved.

[0217] exist Fig.32 In the pixel 50b shown, the opening area 401c is small. Fig.32 In the pixel 50b shown, the on-chip lens 66d is arranged so that the center of the on-chip lens 66d (focusing diameter) is away from the transfer portion that transfers charges from the PD 51 to the charge holding portion 54, and only the area where the focusing diameter of the on-chip lens 66d coincides is the opening area 401d.

[0218] Therefore, by reducing the opening area 401d to the area where light can be concentrated by the on-chip lens 66d, it can be assumed that the F-number sensitivity is slightly reduced, but since useless PLS components can be cut off, the influence of the PLS components can be further suppressed.

[0219] For example, Fig.29 and Fig.30 In the pixel 50b shown in FIG. 1 , when the on-chip lens 66 is disposed in the center portion of the PD region 67, the pixels 50b can be arranged in an array while maintaining optical symmetry. Fig.31 and Fig.32 As shown, in the case where the on-chip lens 66 is provided in a portion deviated from the central portion of the PD region 67 , the optical symmetry is maintained in some arrangements, and the optical symmetry is not maintained in other arrangements.

[0220] Therefore, if Fig.32 As shown, the following will refer to Figure 33 to Figure 36 A case will be described in which the on-chip lens 66 is provided at a portion deviated from the center of the PD region 67 , the pixels 50 b are arranged in an array, and the opening region 401 is reduced to a light-collecting diameter of the on-chip lens 66 .

[0221] exist Figure 33 to Figure 36 In the example, four 2×2 pixels are extracted and displayed from the pixel groups arranged in an array. In addition, Fig.33 and Fig.34 The example shown is a diagram when the pixel arrangement is periodically expanded (periodic expansion). Fig.35 and Fig.36 The example shown is a diagram when the pixel arrangement is folded and unfolded (mirror unfolding).

[0222] Fig.33 The illustrated example shows a case where the pixels 50b are arranged in the lateral direction, and in pixels 50b adjacent in the lateral direction, for example, in the pixel 50b-1 and the pixel 50b-2, the region where the OFG gate 122 is provided and the region where the transistor 123 is provided are adjacent to each other.

[0223] When the pixels 50b are arranged in an array in this manner, the pixels 50b are similar in that the opening area 401d is provided on the lower left side of the pixel 50b, and the on-chip lens 66d is formed in the opening area 401d. Fig.33 The example shown is an exemplary arrangement that preserves optical symmetry.

[0224] Fig.34 The example shown differs in that Fig.33 The pixel 50b in the example shown has a configuration in which the PD region 67 and the charge holding region 68 are offset by half a pitch. Even if the PD region 67 and the charge holding region 68 are offset by half a pitch, the arrangement of the PD region 67 is similar to Fig.33 The arrangement of the PD region 67 is shown.

[0225] Therefore, the pixels 50b arranged in an array are similar in that the opening region 401d is provided on the lower left side of the pixel 50b, and the on-chip lens 66d is formed in the opening region 401d. Fig.33 The example shown is an exemplary arrangement that preserves optical symmetry.

[0226] Fig.35 An example in which pixels 50b are arranged in the vertical direction is shown. Fig.35 The illustrated example shows a case where, in pixels 50 b adjacent in the vertical direction, for example, in the pixel 50 b - 1 and the pixel 50 b - 3 , regions where the transistors 123 are arranged are adjacent to each other.

[0227] When the pixels 50b are arranged in an array in this manner, for example, an opening area 401d is provided on the lower left side of the pixel 50b-1, and an on-chip lens 66d-1 is formed in the opening area 401d-1. In the pixel 50b-3 adjacent to the pixel 50b-1 in the vertical direction, an opening area 401d-3 is provided on the upper left side, and an on-chip lens 66d-3 is formed in the opening area 401d-3.

[0228] exist Fig.35 In the example shown, when observing the vertically adjacent pixel 50b, the position where the on-chip lens 66 is set in the pixel 50b is different. Fig.35 The examples shown are exemplary arrangements that do not preserve optical symmetry.

[0229] Fig.36 An example of pixels 50b arranged in the lateral direction is shown. Fig.36 The illustrated example shows a case where, in pixels 50 b adjacent in the lateral direction, for example, in the pixel 50 b - 1 and the pixel 50 b - 2 , regions where the transistors 123 are arranged are adjacent to each other.

[0230] When the pixels 50b are arranged in an array in this manner, for example, an opening region 401d is provided on the lower right side of the pixel 50b-1, and an on-chip lens 66d-1 is formed in the opening region 401d-1. In the pixel 50b-2 adjacent to the pixel 50b-1 in the lateral direction, an opening region 401d-2 is provided on the lower left side, and an on-chip lens 66d-2 is formed in the opening region 401d-2.

[0231] exist Fig.36 In the example shown, when viewing the pixels 50b adjacent in the lateral direction, the positions at which the on-chip lenses 66 are arranged in the pixels 50b are different. Fig.36 The examples shown are exemplary arrangements that do not preserve optical symmetry.

[0232] Fig.35 and Fig.36 The illustrated exemplary arrangement of on-chip lens 66 that does not maintain optical symmetry has the advantage that multiple pixels 50b can share transistors. Fig.36 The pixels 50b-1 to 50b-4 shown in FIG. Fig.28 The pixels 50 b - 1 to 50 b - 4 shown in FIG. 5 are arranged in a similar manner. Fig.28 3 is a diagram showing a configuration in which four pixels share a reset transistor 301 , an amplifying transistor 302 , and a selecting transistor 303 .

[0233] Therefore, we can Fig.36 The arrangement of the on-chip lens 66 shown is applied to Fig.28The structure of multiple pixels 50b sharing transistors as shown in FIG. Fig.36 In the case of a structure in which an on-chip lens 66 is provided and a plurality of pixels 50b share a transistor, as shown in FIG. Fig.28 In the above case, the area allocated to one transistor can be increased, leakage can be prevented, the L length of the amplifier transistor 302 can be increased, random noise can be reduced, and miniaturization can be achieved.

[0234] In addition, the number of saturated electrons (dynamic range) can be increased by increasing the area allocated to the PD 51 and the charge holding portion 54. However, as described above, since optical symmetry cannot be maintained and sensitivity and spatial resolution may be reduced, they may be reduced in some products, and signal processing that does not reduce them must be adopted as appropriate in some cases.

[0235] <About Manufacturing>

[0236] Will refer to Figures 37 to 41 The manufacturing of the above-mentioned pixel 50 will be described. Here, the description will be continued by taking the case of manufacturing the pixel 50b as an example.

[0237] First, in Fig.37 In the illustrated pixel 50 b , a process of manufacturing the pixel 50 b in the cross section of arrow AB will be described.

[0238] In step S11, an SOI substrate is provided. Here, a case where an SOI substrate is used and the charge accumulation layer is an n-type will be described as an example, but the present invention can also be applied to a case where a bulk substrate is used and the charge accumulation layer is a p-type.

[0239] Furthermore, in step S11, a well of the transistor is also formed by ion implantation. Furthermore, an etching stop layer 501 is also formed.

[0240] In step S12, the PD 51 and the charge holding portion 54b are formed as n-type regions by ion implantation. In the case where a p-type region is generated in the charge holding region 68b, a p-type region is generated in step S12.

[0241] In step S13, the OFG gate 122 and the TRX gate 73 are formed. For example, the gate portions of these transistors are formed by polysilicon deposition by CVD and patterning by photolithography.

[0242] In step S14, a hole accumulation diode (HAD) is formed by ion implantation. The HAD is formed by generating a p-type pinning layer 74-1 in the PD 51. Dark current can be significantly suppressed by forming the HAD.

[0243] In step S15 , the OFD 121 as an n-type region is formed by ion implantation.

[0244] Furthermore, in step S16 , the wiring layer 61 is stacked.

[0245] In step S17 ( Fig.39 ), an adhesive layer is formed on the surface side of the wiring layer 61, and after laminating the supporting substrate 502, as shown in step S18, the entire device is turned over, and the rear surface of the semiconductor substrate 63 is ground by physical grinding.

[0246] In step S19, the layer on the rear side of the etching stop layer 501 of the semiconductor substrate 63 is etched by wet etching. At this time, the etching is stopped by the etching stop layer 501 containing a high concentration of p-type impurities to expose the etching stop layer 501.

[0247] Furthermore, after the etching stop layer 501 is removed, the rear surface of the semiconductor substrate 63 is polished by a chemical mechanical polishing (CMP) method, thereby thinning the rear side of the semiconductor substrate 63 .

[0248] Therefore, after forming the PD region 67 and the charge holding region 68, the light shielding portion 76 is formed. In the description of the formation of the light shielding portion 76, as shown in FIG. Fig.40 As shown, the cross section when the adjacent pixels 50b-1 and 50b-2 are cut through by arrow CD is taken as an example for explanation.

[0249] As shown in step S20 ( Fig.41 ), in the above steps, the PD 51-1 and the charge holding portion 54-1 of the pixel 50b-1 and the PD 51-2 of the pixel 50b-2 are formed.

[0250] In step S21, a portion corresponding to the light shielding portion 76 to be penetrated is slightly dug. Fig.40 The light shielding portion 76B-3 located below the pixel 50b-1 and the light shielding portion 76B-1 located above the pixel 50b-1 are shown. Fig.41 As shown, each of the left side of the PD 51-1 and the right side of the charge holding portion 54-1 which will become the penetrating light shielding portion 76B is slightly dug.

[0251] In step S22, the non-penetrating light-shielding portion 76 and the penetrating light-shielding portion 76 are excavated. The penetrating light-shielding portion 76 that has been excavated a little is further excavated to become penetrating.

[0252] In step S23 , the light shielding portion 76 is formed by filling the dug portion with metal such as tungsten.

[0253] Note that in the excavation, after first forming a resist on the rear surface of the semiconductor substrate 63, the resist layer is exposed and developed so that an opening is formed in the region where the embedded portion 76B of the light shielding portion 76 is to be formed. Then, dry etching is performed using the resist layer as a mask to form a groove portion. By repeating this process, a non-penetrating groove portion and a penetrating groove portion are formed.

[0254] Furthermore, a high dielectric constant material film 77 is deposited on the side and bottom surfaces of the groove portion and the rear surface of the semiconductor substrate 63. Subsequently, a light shielding portion 76 is deposited on the rear surface and in the groove portion 84 from the rear side of the high dielectric constant material film 77.

[0255] Through this process, the cap portion 76A is formed on the rear side of the high dielectric constant material film 77 , and the light shielding portion 76 in which the embedded portion 76B is formed within the groove portion 84 is formed.

[0256] The light shielding portion 76 is formed by, for example, chemical vapor deposition (CVD) using tungsten as a material. Then, the light shielding portion 76 is processed by dry etching to open the opening 76C. Thereafter, for example, an atomic layer deposition (ALD) method is used to stack and flatten the high dielectric constant material film 77 relative to the light shielding portion 76.

[0257] Thereafter, a color filter layer 65 and an on-chip lens 66 are formed using a conventional method. Thus, the pixel 50b is manufactured.

[0258] The present invention can reduce the influence of unnecessary light components. In addition, it is possible to manufacture a pixel that can reduce the influence of unnecessary light components.

[0259] <Electronic equipment>

[0260] The present invention is not limited to application to an image pickup device, but can be applied to all electronic devices that use an image pickup device in an image acquisition unit (photoelectric conversion component), including image pickup devices such as digital cameras and video cameras, mobile terminal devices with an image pickup function such as mobile phones, and copiers that use an image pickup device in an image reader, etc. Note that in some cases, a modular form (that is, a camera module) mounted on an electronic device is used as the image pickup device.

[0261] Fig.42 1 is a block diagram showing an exemplary configuration of an image pickup device as one example of the electronic device of the present invention. Fig.42 As shown, the camera device 600 of the present invention includes an optical system including a lens group 601, a camera device 602, a digital signal processor (DSP) circuit 603 as a camera signal processing unit, a frame memory 604, a display device 605, a recording device 606, an operating system 607, a power supply system 608, etc.

[0262] Then, a configuration is used in which a DSP circuit 603, a frame memory 604, a display device 605, a recording device 606, an operation system 607, and a power supply system 608 are connected to one another via a bus 609. A central processing unit (CPU) 610 controls each unit in the imaging device 600.

[0263] The lens group 601 receives incident light (image light) from a subject and forms an image on an imaging surface of the imaging device 602. The imaging device 602 converts the light amount of the incident light of the image formed on the imaging surface by the lens group 601 into an electrical signal in a pixel unit and outputs the electrical signal as a pixel signal. As the imaging device 602, the imaging device (image sensor) according to the above-described embodiment can be used.

[0264] The display device 605 includes a panel type display device such as a liquid crystal display device or an organic electroluminescent (EL) display device, and displays a moving image or a still image imaged by the camera device 602. The recording device 606 records the moving image or the still image imaged by the camera device 602 on a recording medium such as a video tape or a digital versatile disc (DVD).

[0265] The operating system 607 issues operating commands for various functions of the camera under the operation of the user. The power supply system 608 appropriately supplies various power supplies to the DSP circuit 603, the frame memory 604, the display device 605, the recording device 606 and the operating system 607, and these power supplies are used as operating power supplies for these power supply targets.

[0266] Such an image pickup device 600 can be applied to a camera module of a mobile device such as a video camera, a digital still camera, and a mobile phone, etc. Then, in the image pickup device 600 , the image pickup device according to the above-described embodiment can be used as the image pickup device 602 .

[0267] In this specification, a system means the entire apparatus including a plurality of devices.

[0268] Note that the effects described in this specification are merely illustrative and non-restrictive, and other effects may be produced.

[0269] Note that the embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

[0270] Note that the present invention may also have the following configurations. (1)

[0272] A camera device, comprising:

[0273] a photoelectric conversion unit configured to convert received light into electric charges;

[0274] a holding portion configured to hold the charge transferred from the photoelectric conversion portion; and

[0275] a light shielding portion configured to shield light between the photoelectric conversion portion and the holding portion,

[0276] wherein the photoelectric conversion unit, the holding unit, and the light shielding unit are formed in a semiconductor substrate having a predetermined thickness, and

[0277] The light shielding portion in a transfer region that transfers the charge from the photoelectric conversion portion to the holding portion is formed as a non-transmitting light shielding portion that does not penetrate the semiconductor substrate, and the light shielding portion outside the transfer region is formed as a transmitting light shielding portion that penetrates the semiconductor substrate. (2)

[0279] The imaging device according to (1), wherein:

[0280] When the length of one side of the photoelectric conversion portion is 1, the length of the non-transmitting light-shielding portion is 1 / 5 or more. (3)

[0282] The imaging device according to (1) or (2), wherein:

[0283] The non-transmitting light shielding portion is formed at a depth greater than or equal to half the thickness of the semiconductor substrate. (4)

[0285] The imaging device according to (1) or (2), wherein:

[0286] The non-transmitting light shielding portion is formed at a depth that is less than or equal to half the thickness of the semiconductor substrate. (5)

[0288] The imaging device according to any one of (1) to (4), further comprising an OFG gate, wherein:

[0289] The non-penetrating light shielding portion is formed on a side where the OFG gate is arranged. (6)

[0291] The imaging device according to any one of (1) to (5), wherein:

[0292] The holding portion is provided at a position offset by half a pitch with respect to the photoelectric conversion portion. (7)

[0294] The imaging device according to any one of (1) to (6), further comprising

[0295] A backflow prevention gate is configured to prevent the charge from flowing back from the holding portion to the photoelectric conversion portion. (8)

[0297] The imaging device according to (7), wherein:

[0298] The backflow prevention gate is a part of the non-penetrating light shielding portion and is formed in a shape protruding toward the photoelectric conversion portion. (9)

[0300] The imaging device according to any one of (1) to (6), wherein:

[0301] A transfer control gate that controls transfer of the charge from the photoelectric conversion portion to the holding portion is formed in a portion of the non-transmitting light shielding portion in a shape that protrudes toward the photoelectric conversion portion. (10)

[0303] The imaging device according to any one of (1) to (9), wherein:

[0304] An on-chip lens is provided so that the center of the on-chip lens is located in a central portion of the photoelectric conversion portion. (11)

[0306] The imaging device according to any one of (1) to (9), wherein:

[0307] The on-chip lens is provided on the photoelectric conversion portion at a position away from the non-transmitting light shielding portion. (12)

[0309] The imaging device according to (10) or (11), wherein:

[0310] The light shielding portion is formed in a region other than a region that coincides with a light-collecting diameter of the on-chip lens on the photoelectric conversion portion. (13)

[0312] The imaging device according to any one of (10) to (12), wherein:

[0313] When arranged in an array, the on-chip lenses are arranged so as to maintain optical symmetry. (14)

[0315] The imaging device according to any one of (1) to (13), wherein:

[0316] The light shielding portion formed between pixels penetrates the semiconductor substrate. (15)

[0318] An electronic device, comprising:

[0319] A camera device, the camera device comprising:

[0320] a photoelectric conversion unit configured to convert received light into electric charges;

[0321] a holding portion configured to hold the charge transferred from the photoelectric conversion portion; and

[0322] a light shielding portion configured to shield light between the photoelectric conversion portion and the holding portion,

[0323] The photoelectric conversion unit, the holding unit, and the light shielding unit are formed in a semiconductor substrate having a predetermined thickness,

[0324] The light shielding portion of the transfer region that transfers the charge from the photoelectric conversion portion to the holding portion is formed as a non-penetrating light shielding portion that does not penetrate the semiconductor substrate, and the light shielding portion outside the transfer region is formed as a penetrating light shielding portion that penetrates the semiconductor substrate; and

[0325] A processing unit is configured to process the signal from the camera device.

[0326] Reference numerals list

[0327] 30 Camera device

[0328] 50 pixels

[0329] 51PD

[0330] 54 Charge retention unit

[0331] 61 Wiring layer

[0332] 62 Oxide layer

[0333] 63 Semiconductor substrate

[0334] 64 Shading layer

[0335] 65 Color filter layer

[0336] 66 On-chip lens

[0337] 71 Wiring

[0338] 72 interlayer insulation film

[0339] 73 TRX gate

[0340] 74 Surface pinning layer

[0341] 75 pixels between separation areas

[0342] 76 shading part

[0343] 77 High dielectric constant material film

[0344] 121OFD

[0345] 122 OFG gate

[0346] 123 Transistor

[0347] 124 TRG gate

[0348] 125FD

[0349] 301 Reset transistor

[0350] 302 Amplifier transistor

[0351] 303 Select transistor

Claims

1. A camera device, comprising: a photoelectric conversion unit configured to convert received light into electric charges; a holding section configured to hold the charge transferred from the photoelectric conversion section; a first light shielding portion configured to shield light between the photoelectric conversion portion and the holding portion; and a second light shielding portion, the second light shielding portion being formed above the holding portion to shield incident light, wherein the photoelectric conversion unit, the holding unit, and the first light shielding unit are formed in a semiconductor substrate having a predetermined thickness, wherein the first light shielding portion that transfers the charge from the photoelectric conversion portion to the transfer region of the holding portion is formed as a non-transmitting light shielding portion that does not penetrate the semiconductor substrate, wherein the first light shielding portion outside the transmission region is formed as a penetrating light shielding portion penetrating the semiconductor substrate, and The holding portion is arranged at a position offset by half a pitch relative to the photoelectric conversion portion, so that a transfer control gate that controls the transfer of the charge from the photoelectric conversion portion to the holding portion is formed between the photoelectric conversion portion and another photoelectric conversion portion adjacent to the photoelectric conversion portion in the vertical direction.

2. The imaging device according to claim 1, wherein: When the length of one side of the photoelectric conversion portion is 1, the length of the non-transmitting light-shielding portion is 1 / 5 or more.

3. The imaging device according to claim 1, wherein: The non-transmitting light shielding portion is formed at a depth greater than or equal to half the thickness of the semiconductor substrate.

4. The imaging device according to claim 1, wherein: The non-transmitting light shielding portion is formed at a depth that is less than or equal to half the thickness of the semiconductor substrate.

5. The imaging device according to claim 1, further comprising an overflow gate OFG, wherein: The non-penetrating light shielding portion is formed on one side where the OFG is arranged.

6. The imaging device according to claim 1, further comprising A backflow prevention gate is configured to prevent the charge from flowing back from the holding portion to the photoelectric conversion portion.

7. The imaging device according to claim 6, wherein: The backflow prevention gate is a part of the non-penetrating light shielding portion and is formed in a shape protruding toward the photoelectric conversion portion.

8. The imaging device according to claim 1, wherein: An on-chip lens is provided so that the center of the on-chip lens is located in a central portion of the photoelectric conversion portion.

9. The imaging device according to claim 1, wherein: An on-chip lens is provided on the photoelectric conversion portion at a position away from the non-transmitting light shielding portion.

10. The imaging device according to claim 9, wherein: The second light shielding portion is formed in a region other than a region that coincides with a light-collecting diameter of the on-chip lens on the photoelectric conversion portion.

11. The imaging device according to claim 9, wherein: When arranged in an array, the multiple on-chip lenses are arranged so as to maintain optical symmetry.

12. The imaging device according to claim 1, wherein: The first light shielding portion formed between pixels penetrates the semiconductor substrate.

13. An electronic device comprising: A camera device, the camera device comprising: a photoelectric conversion unit configured to convert received light into electric charges; a holding section configured to hold the charge transferred from the photoelectric conversion section; a first light shielding portion configured to shield light between the photoelectric conversion portion and the holding portion; and a second light shielding portion, the second light shielding portion being formed above the holding portion to shield incident light, wherein the photoelectric conversion unit, the holding unit, and the first light shielding unit are formed in a semiconductor substrate having a predetermined thickness, wherein the first light shielding portion that transfers the charge from the photoelectric conversion portion to the transfer region of the holding portion is formed as a non-transmitting light shielding portion that does not penetrate the semiconductor substrate, and wherein the first light shielding portion outside the transmission region is formed as a penetrating light shielding portion penetrating the semiconductor substrate, and wherein the holding portion is disposed at a position offset by half a pitch relative to the photoelectric conversion portion, so that a transfer control gate for controlling the transfer of the charge from the photoelectric conversion portion to the holding portion is formed between the photoelectric conversion portion and another photoelectric conversion portion adjacent to the photoelectric conversion portion in a vertical direction; and A processing unit is configured to process the signal from the camera device.

14. The electronic device according to claim 13, wherein: The non-transmitting light shielding portion is formed at a depth that is less than or equal to half the thickness of the semiconductor substrate.

15. The electronic device according to claim 13, further comprising an overflow gate OFG, wherein: The non-penetrating light shielding portion is formed on one side where the OFG is arranged.

16. The electronic device according to claim 13, wherein: An on-chip lens is provided so that the center of the on-chip lens is located in a central portion of the photoelectric conversion portion.

17. The electronic device according to claim 13, wherein: An on-chip lens is provided on the photoelectric conversion portion at a position away from the non-transmitting light shielding portion.

18. The electronic device according to claim 17, wherein: The second light shielding portion is formed in a region other than a region that coincides with a light-collecting diameter of the on-chip lens on the photoelectric conversion portion.

19. The electronic device according to claim 17, wherein: When arranged in an array, the multiple on-chip lenses are arranged so as to maintain optical symmetry.

20. The electronic device according to claim 13, wherein: The first light shielding portion formed between pixels penetrates the semiconductor substrate.

Images