Semiconductor device, semiconductor device control method, and semiconductor device manufacturing method

Abstract

A semiconductor device according to the present disclosure includes: a drift layer including first pillar regions of a first conductivity type and second pillar regions of a second conductivity type alternately arranged; a base region of a second conductivity type disposed on the first main surface side of the drift layer; a gate insulating film disposed so as to be in contact with the base region; a gate electrode disposed so as to sandwich the gate insulating film; a charge holding region of the first conductivity type disposed between the base region and the second pillar region; and an emitter region of the first conductivity type disposed on a surface layer of the base region on the first main surface side, the lower end of the second pillar region, which is an end portion on the second main surface side, being located closer to the second main surface side than the lower end of the first pillar region, which is an end portion on the second main surface side. Wp3gt, where wp1 is the width of the upper end of the second column region that is the end on the first main surface side, wp2 is the width of the second column region at the same position as the lower end of the first column region, and wp3 is the width of the lower end of the second column region; wp1, wp2 and wp1gt; wp1, wp2.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a control method of a semiconductor device, and a manufacturing method of a semiconductor device. Background Art

[0002] The superjunction structure, which alternately arranges n-type column regions and p-type column regions in a plan view, is mainly used in the drift layer structure of power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). By reducing the spacing between n-type column regions and p-type column regions, the n-type column region can be highly concentrated (lower resistance). Compared with conventional power MOSFETs (power MOSFETs that do not adopt superjunction structure), power MOSFETs that adopt superjunction structure can obtain lower on-voltage at the same withstand voltage.

[0003] In a super junction IGBT (Insulated Gate Bipolar Transistor) formed by applying a super junction structure to an IGBT (Insulated Gate Bipolar Transistor), holes injected from the p-type collector layer on the back side exert an IE (Injection Enhanced) effect to enhance conductivity modulation, as in conventional IGBTs (IGBTs that do not adopt a super junction structure), thereby expecting further reductions in the on-state voltage.

[0004] The following technology is disclosed: in a conventional IGBT, an n-type charge holding region is provided between an n-type drift region and a p-type base region to restrict the movement of holes injected from a p-type collector layer on the back side, thereby achieving low on-resistance (see, for example, Patent Document 1).

[0005] In addition, a technology is disclosed in which, in a super junction IGBT, the trade-off relationship between the collector-emitter on-voltage Vce(sat) and the turn-off loss Eoff can be improved compared with a conventional IGBT (see, for example, Patent Document 2).

[0006] Furthermore, a superjunction structure in which an n-type column region and a p-type column region are vertically formed in the depth direction is disclosed (for example, refer to Non-Patent Document 1).

[0007] Patent Document 1: Japanese Patent No. 3288218

[0008] Patent Document 2: Japanese Patent Application No. 2009-525610

[0009] Non-patent document 1: T. Tamaki, “Vertical Charge Imbalance Effect on 600V-class Trench-Filling Superjunction Power MOSFETs”, the 23rd International Symposium on Power Semiconductor Devices & IC's, May 23-26, 2011, p.308-311 Summary of the invention

[0010] Problem that the invention aims to solve

[0011] Patent Documents 1, 2, and Non-Patent Document 1 do not disclose a superjunction structure that can take into account both the reduction of the on-state voltage and the robustness of the withstand voltage. For example, in Patent Document 2, the p-type column region is electrically connected to the p-type base region, and the holes injected from the back in the on state are discharged to the emitter terminal via the p-type column region and the p-type base region. Therefore, in order to reduce the on-state voltage, it is necessary to highly concentrate the n-type column region by reducing the spacing between the n-type column region and the p-type column region. However, there is a limit to the manufacturing technology for reducing the spacing. In addition, by highly concentrating the n-type column region, the electrons tend to flow through the n-type column region and the holes tend to flow through the p-type column region, so there is a limit to the reduction of the on-state voltage.

[0012] In addition, in a structure in which an n-type column region and a p-type column region are formed vertically in the depth direction as in Non-Patent Document 1, the device withstand voltage becomes more sensitive to the concentration of the column region, and thus there is a disadvantage that the withstand voltage robustness against manufacturing variations is significantly impaired.

[0013] The present disclosure has been made to solve such a problem, and an object of the present disclosure is to provide a semiconductor device having a superjunction structure capable of achieving both reduction in on-voltage and robustness in withstand voltage, a control method for the semiconductor device, and a manufacturing method for the semiconductor device.

[0014] Solutions for solving problems

[0015] In order to solve the above-mentioned problems, the semiconductor device involved in the present disclosure has a first main surface and a second main surface facing the first main surface, and is provided with: a drift layer, including a first column region of a first conductivity type and a second column region of a second conductivity type alternately arranged in a direction parallel to the first main surface and the second main surface; a base region of the second conductivity type selectively arranged on the first main surface side of the drift layer; a gate insulating film arranged in a manner of contacting the base region; a gate electrode arranged in a manner of facing the base region through the gate insulating film; a charge holding region of the first conductivity type arranged on the base region and the second column region; and an emitter region of the first conductive type, which is selectively arranged on the surface layer on the first principal surface side of the base region, and the lower end of the end portion of the second column region as the second principal surface side is located closer to the second principal surface side than the lower end of the end portion of the first column region as the second principal surface side, and when the width of the upper end of the end portion of the second column region as the first principal surface side is set to wp1, the width of the second column region at the same position as the lower end of the first column region is set to wp2, and the width of the lower end of the second column region is set to wp3, wp3>wp2 and wp1>wp2.

[0016] Effects of the Invention

[0017] According to the present disclosure, it is possible to achieve both reduction in on-state voltage and robustness of withstand voltage.

[0018] The objects, features, methods and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment.

[0020] Figure 2 This is a diagram for explaining the relationship between the ratio of the impurity amount in the p-type column region to the impurity amount in the n-type column region and the breakdown voltage of the semiconductor device.

[0021] Figure 3 This is a diagram for explaining the relationship between the ratio of the impurity amount in the p-type column region to the impurity amount in the n-type column region and the breakdown voltage of the semiconductor device.

[0022] Figure 4 1 is a diagram for explaining the relationship between the ratio of the impurity amount in the p-type column region to the impurity amount in the n-type column region and the 4-voltage of the semiconductor device.

[0023] Figure 5 This is a diagram for explaining the relationship between the ratio of the impurity amount in the p-type column region to the impurity amount in the n-type column region and the breakdown voltage of the semiconductor device.

[0024] Figure 6This is a graph showing an example of the electric field intensity along the direction from the first main surface to the second main surface in the semiconductor device.

[0025] Figure 7 This is a cross-sectional view showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

[0026] Figure 8 This is a cross-sectional view showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

[0027] Fig. 9 This is a cross-sectional view showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

[0028] Fig.10 This is a cross-sectional view showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

[0029] Fig.11 This is a cross-sectional view showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

[0030] Fig.12 This is a cross-sectional view showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

[0031] Fig.13 This is a cross-sectional view showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

[0032] Fig.14 This is a cross-sectional view showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

[0033] Fig.15 This is a cross-sectional view showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

[0034] Fig.16 This is a cross-sectional view showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

[0035] Fig.17 This is a cross-sectional view showing an example of a manufacturing process of the semiconductor device according to the first embodiment.

[0036] Fig.18 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a modification of the first embodiment.

[0037] Fig.19 This is a cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment.

[0038] Fig. 20This is a cross-sectional view showing an example of the structure of a semiconductor device according to Modification 1 of Embodiment 2.

[0039] Fig.21 This is a cross-sectional view showing an example of the structure of a semiconductor device according to Modification 2 of Embodiment 2.

[0040] Fig. 22 This is a cross-sectional view showing an example of the structure of a semiconductor device according to the third embodiment.

[0041] Fig.23 This is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to the third embodiment.

[0042] Fig.24 This is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to the third embodiment.

[0043] Fig.25 This is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to the third embodiment.

[0044] Fig.26 This is a cross-sectional view showing an example of a manufacturing process of a semiconductor device according to the third embodiment.

[0045] Fig. 27 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a modification of the third embodiment.

[0046] Fig.28 This is a plan view showing an example of the upper surface layout of the semiconductor device involved in the fourth embodiment.

[0047] Fig.29 yes Fig.28 A1-A2 cross-sectional view.

[0048] Fig.30 This is a graph showing an example of a timing chart of a first gate voltage and a second gate voltage for driving the semiconductor device according to the fourth embodiment.

[0049] Fig.31 This is a graph showing an example of the delay time dependency of the second gate voltage on the surge voltage and the turn-off loss in the semiconductor device according to the fourth embodiment.

[0050] Fig.32 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a modification of the fourth embodiment. DETAILED DESCRIPTION

[0051] Hereinafter, the embodiments of the present disclosure will be described with reference to the drawings. In addition, in the following embodiments, the first conductivity type is set to n-type, and the second conductivity type is set to p-type. The same numbers are attached to the same parts in the figures. In addition, the terminal structure located in the peripheral area of ​​the device (semiconductor device) is not shown in the figure, and the cross-sectional structure of the unit cell is shown in the figure. The semiconductor substrate used in the device can be a wafer manufactured by the MCZ (Magnetic field applied Czochralski: magnetron direct pulling) method, a wafer manufactured by the FZ (Floating Zone: zone melting) method, or an epitaxial substrate manufactured by the CZ (Czochralski: direct pulling) method, etc., regardless of the manufacturing method of the substrate, and can be a substrate manufactured using the substrate manufacturing technology required for the manufacture of the device appropriately.

[0052] In addition, the device may be a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using an n-type drain layer instead of a p-type collector layer on the back, or may be a device in which an n-type collector layer is partially patterned in addition to a p-type collector layer. Alternatively, it may be an RC (Reverse-Conducting) type IGBT in which both a MOSFET region and a diode region are provided on the surface, a p-type collector region is arranged on the back of a semiconductor substrate directly below the MOSFET region, and an n-type cathode region is arranged on the back of a semiconductor substrate directly below the diode region.

[0053] <Implementation Method 1>

[0054] <Structure of Semiconductor Device According to Embodiment 1>

[0055] Figure 1 This is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment. Figure 1 The semiconductor device shown is a planar gate super junction IGBT element manufactured using a silicon semiconductor substrate. Below, a semiconductor device with a withstand voltage of about 1200 volts between the emitter and the collector is used as an example for specific description, but it can also be applied to super junction IGBT elements with other withstand voltage values ​​or semiconductor devices with other super junction structures.

[0056] Figure 1 The semiconductor device shown has a first main surface and a second main surface facing the first main surface. Figure 1 The upper side of the paper surface in FIG. 1 corresponds to the surface of the semiconductor device. In addition, the second main surface is Figure 1 The lower side of the paper in FIG. 1 corresponds to the back side of the semiconductor device.

[0057] The drift layer 10 includes n-type column regions 107 (first column regions of the first conductivity type) and p-type column regions 108 (second column regions of the second conductivity type) alternately arranged in a direction parallel to the first main surface and the second main surface. The p-type base region 105 is selectively arranged on the first main surface side of the drift layer 10. The n-type emitter region 103 and the p-type body contact region 104 are selectively arranged on the surface layer on the first main surface side of the p-type base region 105. The n-type charge holding region (Carrier Stored region: CS region) 106 is arranged between the p-type base region 105 and the p-type column region 108. The gate insulating film 101 is arranged in contact with the p-type base region 105. The gate electrode 102 is arranged to face the p-type base region 105 via the gate insulating film 101. The lower end of the end portion of the p-type column region 108 on the second main surface side is located closer to the second main surface side than the lower end of the end portion of the n-type column region 107 on the second main surface side. When the width of the upper end of the end portion of the p-type column region 108 on the first main surface side is set to wp1, the width of the p-type column region 108 at the same position (same depth position) as the lower end of the n-type column region 107 is set to wp2, and the width of the lower end of the p-type column region 108 is set to wp3, wp3>wp2 and wp1>wp2.

[0058] The n-type bottom layer 109 is disposed on the second main surface side of the drift layer 10. The n-type buffer layer 110 is disposed on the second main surface side of the n-type bottom layer 109. The p-type collector layer 111 is disposed on the second main surface side of the n-type buffer layer 110. The collector electrode 112 is disposed on the second main surface side of the p-type collector layer 111.

[0059] A plurality of stripe-shaped gate electrodes 102 are disposed above the n-type column region 107. The gate electrodes 102 are also disposed on the n-type column region 107 in the same manner as the p-type column region 108. Figure 1 They are arranged in stripes in the depth direction of the paper (the direction perpendicular to the paper), thereby forming a MOSFET with a planar gate structure.

[0060] exist Figure 1 In the example, one gate electrode 102 is provided above one n-type column region 107 and the n-type column region 107 and the gate electrode 102 have the same width direction interval, but the widths of the n-type column region 107 and the gate electrode 102 may be different in width direction.

[0061] <Function of Semiconductor Device According to Embodiment 1>

[0062] Next, the operation of the semiconductor device according to Embodiment 1 will be described.

[0063] Figure 2 to Figure 5It is a graph for explaining the relationship between the ratio of the impurity amount in the p-type column region to the impurity amount in the n-type column region and the breakdown voltage of the semiconductor device. In Figure 5 it, the horizontal axis represents the ratio (Qp / Qn) of the impurity amount (Qp) in the p-type column region to the impurity amount (Qn) in the n-type column region, and the vertical axis represents the breakdown voltage of the semiconductor device. Figure 2 to Figure 4 The structures A to C shown are superstructures. Structures A and B are the superstructures of the semiconductor devices related to the comparative examples, and structure C is the superstructure of the semiconductor device related to Embodiment 1. Figure 5 It shows the simulation results related to Figure 2 to Figure 4 the influence of the impurity ratio in the structures A to C shown on the breakdown voltage.

[0064] Figure 6 It is a graph showing an example of the electric field strength in the semiconductor device along the direction (depth direction) from the first main surface to the second main surface. Figure 6 The structures A to C shown correspond to Figure 2 to Figure 5 the structures A to C shown.

[0065] It explains the operation of the semiconductor device related to the comparative example. As Figure 2 and Figure 3 shown, the semiconductor device related to the comparative example is a semiconductor device including a drift layer having an n-type column region and a p-type column region constituting a superstructure (structure A or structure B).

[0066] Taking the collector electrode as the positive electrode and the emitter electrode as the negative electrode, by applying a voltage between the collector electrode and the emitter electrode, the depletion layer extends from the pn junction interface of the p-type column region and the n-type column region to the p-type column region and the n-type column region respectively. At this time, by setting the distance interval or impurity concentration of the p-type column region and the n-type column region so that the depletion layers extending from the adjacent column regions can penetrate each other, the breakdown voltage can be ensured.

[0067] The breakdown voltage of the semiconductor device depends on the impurity ratio in the drift layer. When the impurity amount (Qn) in the n-type column region is equal to the impurity amount (Qp) in the p-type column region, that is, "Qn = Qp", the expansion of the depletion layer corresponding to the voltage is the largest and the breakdown voltage is the largest. In contrast, if, for example, due to manufacturing process deviations or the like, the impurity amount of one side becomes larger, that is, "Qn > Qp" or "Qn < Qp", the depletion layer does not expand sufficiently and the breakdown voltage decreases.

[0068] In addition, according to the shape of the pillar region, the sensitivity of the impurity mass ratio of the drift layer to the breakdown voltage of the semiconductor device changes. For example, when the upper width and the lower width (the width at the bottom) of the p-type pillar region are equal and the p-type pillar region is formed in the vertical direction, the sensitivity of the change in the impurity mass of the pillar region to the influence of the breakdown voltage becomes high. At the breakdown voltage maximum of "Qn = Qp", the space charge density in the drift layer is almost zero, and the electric field intensity distribution in the depth direction becomes flat, maximizing the breakdown voltage. In this way, the state in which the impurity mass (Qn) of the n-type pillar region is equal to the impurity mass (Qp) of the p-type pillar region and the charge balance is maintained is called the charge balance state.

[0069] On the other hand, the charge imbalance state in which either the impurity mass (Qn) of the n-type pillar region or the impurity mass (Qp) of the p-type pillar region is increased is called the charge imbalance state. In the case of "Qn>Qp", the drift layer with a positive space charge density maintains the applied voltage, and in the case of "Qn<Qp", the drift layer with a negative space charge density maintains the applied voltage. At this time, along the direction from the first main surface to the second main surface, a slope corresponding to the remaining charge amount ΔQ (ΔQ = Qp - Qn) is generated in the electric field intensity distribution in the drift layer. Therefore, the breakdown voltage in the charge imbalance state is lower than that in the charge balance state.

[0070] Regarding the suppression of the decrease in the breakdown voltage caused by the remaining charge amount in the drift layer, for example, as disclosed in Non-Patent Document 1, it can be achieved by forming a p-type pillar region in which the lower width is smaller than the upper width and has a positive conical shape from the first main surface to the second main surface. According to this method, the remaining charge amount is not uniform in the drift layer, and non-uniformity of the remaining charge amount in which the remaining charge amount in the drift layer decreases along the direction from the first main surface to the second main surface is generated, thereby resulting in an electric field distribution in which an electric field peak appears at a depth near the center of the drift layer in the charge balance state (Qn = Qp). At this time, in the case of Qn>Qp, the position of the electric field peak shifts toward the shallower side (toward the first main surface), and in the case of Qn<Qp, the position of the electric field peak shifts toward the deeper side (toward the second main surface). Therefore, even when the charge imbalance state is reached, the shape of the electric field intensity distribution does not change significantly compared to the charge balance state (it does not change as much as in the case of a vertically shaped p-type pillar region), so the sensitivity of the impurity mass ratio of the drift layer to the breakdown voltage can be reduced.

[0071] The effect of reducing the sensitivity of the impurity mass ratio of the drift layer to the withstand voltage of the semiconductor device and improving the withstand voltage of the semiconductor device described above can also be applied to super junction MOSFET elements. In the case of super junction MOSFET elements, the charge retention region acts as a current diffusion layer, thereby reducing the JFET resistance generated between the p-type base regions. However, even for super junction MOSFET elements, the resistance component of the bottom layer cannot be reduced, so it is difficult to fully reduce the on-resistance under this situation. Therefore, bipolar action can be performed by providing an n-type buffer region and a p-type collector region on the second main surface side, and the on-resistance can be further reduced by further providing a charge retention region.

[0072] When a positive voltage above the threshold voltage of MOS is applied to the gate electrode to set it to the on state, an inversion layer is formed on the surface of the p-type base region directly below the gate electrode, and electrons are injected from the emitter electrode to the drift layer via the n-type emitter region and the inversion layer. The electrons injected into the drift layer drift toward the second main surface due to the electric field, and move to the collector electrode through the n-type buffer layer and the p-type collector layer. The potential of the n-type buffer layer decreases due to the electrons moving from the first main surface, so the built-in potential of the pn junction on the second main surface side decreases, and holes are injected from the p-type collector layer. At this time, if the concentration of holes injected from the p-type collector layer is higher than the impurity concentration of the n-type base layer and the drift layer, conductivity modulation can be caused to reduce the on-resistance.

[0073] However, if Figure 5 As shown, regarding a semiconductor device using a p-type column region having a forward tapered shape ( Figure 3 The withstand voltage of the structure B) is comparable to that of a semiconductor device using a vertical p-type column region ( Figure 2 Compared with the structure A), the withstand voltage value decreases even in the charge balance state (Qn = Qp). This is because Figure 6 As shown, in a semiconductor device using a vertically shaped p-type column region, the electric field strength distribution in the depth direction is almost flat. In contrast, in a semiconductor device using a p-type column region set to a positive cone shape, the electric field strength distribution in the depth direction has a peak in the drift layer, and the electric field strength near the top and bottom of the p-type column region decreases.

[0074] In addition, when the upper end of the p-type column region is connected to the p-type base region, in the on-state, holes injected from the p-type collector layer into the n-type buffer layer and the n-type bottom layer are directly discharged to the emitter electrode via the p-type column region and the p-type base region. Therefore, the effect of conductivity modulation on the first main surface side of the drift layer is weakened, resulting in an increase in the on-voltage.

[0075] Therefore, in the semiconductor device ( Figure 4In the structure C), by making the upper end width (wp1) of the p-type column region 108 larger than the width (wp2) of the p-type column region 108 at the same depth as the lower end of the n-type column region 107 (wp1>wp2), the effect of reducing the sensitivity of the impurity ratio of the drift layer 10 to the withstand voltage is achieved. In addition, by arranging the n-type bottom layer 109 at the lower part of the drift layer 10, arranging the lower end of the p-type column region 108 at a position closer to the second main surface than the n-type column region 107, and making the maximum width (wp3) of the bottom of the p-type column region 108 in the n-type bottom layer 109 larger than wp2 (wp3>wp2), the electric field strength near the bottom of the p-type column region 108 can be increased, and the withstand voltage can also be improved. Furthermore, by providing an n-type charge holding region 106 between the upper end of the p-type column region 108 and the p-type base region 105, the n-type charge holding region 106 becomes a barrier for holes injected from the p-type collector layer 111, thereby exerting a hole accumulation effect (or IE effect), thereby being able to reduce the on-resistance.

[0076] like Figure 1 As shown, in the semiconductor device adopting the planar gate structure, the n-type charge holding region 106 is separated at the position just below the center of the gate electrode 102 (at a position corresponding to the center of the gate electrode 102). By separating the n-type charge holding region 106 just below the center of the gate electrode 102, the increase of the electric field at the bonding interface between the p-type base region 105 and the n-type charge holding region 106 can be suppressed, and the desired withstand voltage can be obtained. In addition, even if the n-type charge holding region 106 is separated directly below the center of the gate electrode 102, since the n-type charge holding region 106 is formed at a position deeper than the p-type base region 105 in a manner of enclosing the p-type base region 105, the planar size of the n-type charge holding region 106 (the width of the n-type charge holding region 106 in a direction parallel to the first main surface and the second main surface) is set to be larger than the planar size of the p-type base region 105 (the width of the p-type base region 105 in a direction parallel to the first main surface and the second main surface). Therefore, the charge retention function is not impaired when conductive, and the withstand voltage when non-conductive can be maintained.

[0077] The n-type charge holding region 106 and the p-type base region 105 are formed by ion implantation and diffusion, so that the impurity concentration of the n-type charge holding region 106 is higher than the impurity concentration of the p-type pillar region 108, thereby the p-type base region 105 and the p-type pillar region 108 are separated by the n-type charge holding region 106. Figure 1As shown, the p-type column region 108 separated from the p-type base region 105 by the n-type charge holding region 106 becomes floating (electrically suspended state). As a result, the n-type charge holding region 106 sandwiched by the p-type column region 108 and the p-type base region 105 can function as a charge accumulation layer. However, for example, in areas other than the active region that is the main part of the device, the p-type column region 108 does not necessarily have to be separated from the p-type base region 105. For example, in areas other than the main part of the device, by connecting the p-type column region 108 to the p-type base region 105, unnecessary carriers generated during the operation of the device can be discharged through the contact of the emitter electrode 100, and the long-term reliability and breakdown resistance of the device can be improved.

[0078] <Method for Manufacturing Semiconductor Device According to Embodiment 1>

[0079] Next, each wafer processing step in the method for manufacturing a semiconductor device according to the first embodiment will be described. First, mainly regarding the steps required for forming the first main surface side, the wafer processing step will be described using Figure 7 to Figure 15 Here, we will mainly explain the manufacturing Figure 1 The processing steps required for the main parts of the device shown. The thickness of the n-type bottom epitaxial layer 409 (n-type bottom layer 109) and the n-type top epitaxial layer 407 (drift layer 10) described later are exemplified as the thickness in a super junction IGBT element with a withstand voltage level of about 1200 volts. In addition, for example, it is possible to appropriately add steps that are not directly related to the present disclosure, such as a cleaning process before the gate oxide film, a sintering process of the interlayer film and metal wiring, or a passivation film forming process, a processing process required for the manufacture of the device terminal structure, and an assembly process for singulating the device and assembling it into a module.

[0080] First, if Figure 7 As shown, on an n-type silicon single crystal substrate 400 doped with antimony, for example, a 10 13 cm -3 In addition, on the n-type bottom epitaxial layer 409, a layer doped with, for example, 10 15 cm -3An n-type top epitaxial layer 407 of phosphorus of about the order of 100 is formed. In this way, a semiconductor wafer having an n-type bottom epitaxial layer 409 and an n-type top epitaxial layer 407 formed on an n-type silicon single crystal substrate 400 is prepared. Here, an n-type substrate is exemplified as a silicon single crystal substrate, but as described later, the n-type silicon single crystal substrate 400 is finally ground and removed, so a p-type substrate may be used instead of the n-type substrate. In addition, the impurity concentration of the semiconductor wafer is not limited, but in order to obtain the desired withstand voltage, it is preferred that the impurity concentration of the n-type bottom epitaxial layer 409 is lower than the impurity concentration of the n-type top epitaxial layer 407. In addition, the surface of the n-type top epitaxial layer 407 of the semiconductor wafer is set as the first main surface, and the surface on the side opposite to the first main surface is set as the second main surface.

[0081] Then, if Figure 8 As shown in FIG. 1 , a hard mask film 410 for forming a trench made of, for example, P-TEOS (Plasma-Tetraethylorthosilicate) is patterned on the first main surface. Then, the n-type top epitaxial layer 407 is dry-etched to the extent of reaching the n-type bottom epitaxial layer 409 using the hard mask film for forming the p-type column region trench 401 as a mask, thereby forming the p-type column region trench 401 (second column region trench). The mesa portion sandwiched by the p-type column region trench 401 becomes the n-type column region 107. In addition, the n-type bottom epitaxial layer 409 corresponds to the n-type bottom layer 109. Here, it is desired that the bottom of the p-type column region trench 401 reaches the n-type bottom epitaxial layer 409. However, if the impurities at the bottom of the p-type column region 108 reach the n-type bottom layer 109 by the thermal diffusion process described later, the bottom of the p-type column region trench 401 may not necessarily reach the n-type bottom epitaxial layer 409 at this point in time. In addition, at this time, boron ions may be implanted at the bottom of the p-type column region trench 401. Thereafter, the unnecessary hard mask film 410 is removed.

[0082] Then, if Fig. 9 As shown, buried epitaxial growth of a material doped with boron is performed on the p-type column region trench 401 to fill the p-type column region trench 401 with an epitaxial layer. At this time, an epitaxial overgrowth region 411 is also formed on the n-type column region 107 to completely fill the p-type column region trench 401.

[0083] Then, if Fig.10 As shown, by a planarization process using, for example, CMP (Chemical Mechanical Polishing), the overgrowth region 411 other than the trench 401 for the p-type column region is removed, and the first main surface of the semiconductor wafer is planarized. Fig.10The method of forming the superstructure structure by trench filling-epitaxial embedding is shown, but it can also be formed by a multi-layer epitaxial manufacturing method.

[0084] Then, if Fig.11 As shown, a gate oxide film is formed on almost the entire surface of the first main surface of the semiconductor wafer by thermal oxidation, and a polysilicon film (equivalent to the gate electrode 102) is formed thereon by, for example, low-pressure CVD (Chemical Vapor Deposition). Then, the polysilicon film and the gate oxide film are dry-etched by photolithography using a resist film as a mask to pattern the gate electrode 102 and the gate insulating film 101. Here, a Si oxide film of about 100 nm is exemplified as the gate insulating film 101, and a polysilicon film is exemplified as the material of the gate electrode 102, but amorphous silicon can also be used as the material of the gate electrode 102, and a metal material such as molybdenum can also be used. Thereafter, the unnecessary resist film is removed.

[0085] Then, if Fig.12 As shown, by taking, for example, 10 14 cm -2 Phosphorus is ion implanted at a dose of about 100 Å to form an n-type charge holding region 106 .

[0086] Then, if Fig.13 As shown, for example, a thermal diffusion treatment is performed at 1100° C. for about 140 minutes to diffuse the n-type charge holding region 106 to directly below the gate electrode 102, and to diffuse the boron at the bottom of the p-type column region 108 into the n-type bottom layer 109, thereby expanding the width of the bottom of the p-type column region 108.

[0087] Then, if Fig.14 As shown, by placing, for example, 3×10 14 cm -2 The p-type base region 105 is formed by ion implantation of boron with a dosage of about 10000 Nm, and then a thermal diffusion treatment is performed at 1100° C. for about 30 minutes to diffuse the p-type base region 105. At this time, it is self-evident that the bottom of the p-type pillar region 108 in the n-type charge holding region 106 and the n-type bottom layer 109 further diffuses.

[0088] Next, by photolithography, using the resist film as a mask, antimony, arsenic, etc. are deposited at 4×10 15 cm -2 The n-type emitter region 103 is formed by ion implantation at a dose of about 100 Å. Then, the unnecessary resist film for the n-type emitter region is removed. Thereafter, boron is implanted at a dose of 4×10 15 cm -2Ions are implanted at a dose of about 1000 Å to form the p-type body contact region 104. Thereafter, in order to activate the n-type emitter region 103 and the p-type body contact region 104, annealing is performed at, for example, about 1000°C by lamp heating or in a diffusion furnace.

[0089] Next, a PSG (Phospho-Silicate-Glass) film is formed on almost the entire first main surface of the semiconductor wafer by CVD. At this time, a BPSG (Boro-Phospho-Silicate Glass) film or an SOG (Spin on Glass) film may be superimposed and planarized.

[0090] Then, if Fig.15 As shown, a resist film for opening an emitter contact hole is formed, and the emitter contact hole is opened by dry etching using the resist film for opening the emitter contact hole as a mask. Then, the unnecessary resist film is removed. Thereafter, an aluminum-based metal layer is formed by sputtering or the like through a barrier metal film such as TiW and patterned to form the emitter electrode 100.

[0091] Next, use Fig.16 , Fig.17 The steps necessary for forming the second main surface side in each wafer processing step in the method for manufacturing the semiconductor device according to the first embodiment will be described.

[0092] like Fig.16 As shown, the n-type silicon single crystal substrate 400 located on the second main surface of the semiconductor wafer is completely removed, and the n-type bottom epitaxial layer 109 is exposed on the surface of the second main surface. At this time, if the grinding damage remains on the second main surface after grinding, the grinding damage layer can also be removed by chemical etching. In addition, when the second main surface is ground, it is desirable to protect the element structure formed on the first main surface side when the second main surface is ground, for example, by coating a protective resist on the first main surface or sticking a protective tape.

[0093] Then, if Fig.17 As shown, on the second main surface of the semiconductor wafer, for example, 5×10 12 cm -2 Phosphorus is ion-implanted at a dose of about 1×10 Å to form an n-type buffer layer 110. 13 cm -2 Boron ions are implanted at a dose of about 1000 Å to form p-type collector layer 111 at a position shallower than n-type buffer layer 110 (position on the second main surface side). Then, n-type buffer layer 110 and p-type collector layer 111 are activated using, for example, a laser annealing device.

[0094] <Variation of Implementation Example 1>

[0095] Fig.18 2 is a cross-sectional view schematically showing the structure of a semiconductor device according to a modification of the first embodiment. Fig.18 In, with Figure 1 The same parts are denoted by the same reference numerals and their description is omitted. The semiconductor device according to this modification example is different from the semiconductor device according to the first embodiment in that the semiconductor device according to the first embodiment is Fig.18 An n-type JFET region 121 having an impurity concentration higher than that of the n-type column region 107 is newly arranged between the stripe-shaped n-type charge holding regions 106 extending in a direction perpendicular to the paper surface.

[0096] In the semiconductor device according to this variation, when electrons are injected from the inversion layer formed on the surface of the adjacent p-type base region 105 into the upper portion of the n-type column region 107 to cause conduction, the width of the depletion layer extending from the p-type base region 105 can be suppressed by the n-type JFET region 121 .

[0097] In a structure where n-type charge holding regions 106 formed in strips are separated by n-type pillar regions 107 as in a conventional semiconductor device, if the cell pitch is shortened, the current path between adjacent n-type charge holding regions 106 becomes narrower due to the depletion layer extending from the p-type base region 105, which causes a problem of increasing the on-resistance of the semiconductor device. According to this modification, such a problem can be solved by providing the n-type JFET region 121, and the on-resistance can be reduced.

[0098] <Implementation Method 2>

[0099] Fig.19 is a cross-sectional view schematically showing the structure of a semiconductor device according to Embodiment 2. Fig.19 In, with Figure 1 The same reference numerals are given to the same parts and the description thereof is omitted. The semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that the p-type column bottom region 122 present at a position deeper than the lower end of the n-type column region 107 (position on the second main surface side) contains a higher concentration of impurities than the p-type column region 108 present at a position closer to the first main surface than the p-type column bottom region 122.

[0100] like Fig.19As shown in FIG. 1 , the p-type column bottom region 122 exists at a position deeper than the lower end of the n-type column region 107 and exists below the p-type column region 108. In addition, the impurity concentration of the p-type column bottom region 122 is higher than the impurity concentration of the p-type column region 108. Moreover, by providing such a p-type column bottom region 122, the electric field of the n-type bottom layer 109 can be further increased. Therefore, for example, in a case where the thickness of the drift layer 10 required to obtain a desired withstand voltage cannot be sufficiently ensured, by setting the impurity concentration of the p-type column bottom region 122 existing at a position deeper than the lower end of the n-type column region 107 to a higher concentration than the impurity concentration of the p-type column region 108 above the p-type column bottom region 122, the share of the voltage borne by the n-type bottom layer 109 can be increased, and thus the withstand voltage can be improved.

[0101] <Variations 1 and 2 of Implementation Example 2>

[0102] Fig. 20 : is a cross-sectional view schematically showing the structure of a semiconductor device according to a first variation of the second embodiment. Fig.21 2 is a cross-sectional view schematically showing the structure of a semiconductor device according to a second variation of the second embodiment. Fig. 20 , Fig.21 In, with Fig.19 The same parts are denoted by the same reference numerals and description thereof will be omitted.

[0103] Fig. 20 The semiconductor device according to the first modification shown is different from the semiconductor device according to the second embodiment in that the p-type column bottom regions 122 and 123 are composed of a plurality of regions having different widths and impurity concentrations in the depth direction. Fig. 20 The semiconductor device according to the modified example 1 shown is different from the semiconductor device according to the modified example 1 in that the p-type column bottom region 122 is always formed as an extension of the p-type column region 108 .

[0104] in addition, Fig.21 The semiconductor device according to the second modification shown is different from the semiconductor device according to the second embodiment in that an n-type JFET region 124 having a higher impurity concentration than the n-type column region 107 is provided between adjacent p-type column bottom regions 122. The n-type JFET region 124 is in contact with the lower end of the n-type column region 107. In the semiconductor device according to the second modification, the impurity concentration of the p-type column bottom region 122 is different from the impurity concentration of the p-type column region 108, which is the same as the second embodiment or the first modification.

[0105] exist Fig.19In the semiconductor device according to the second embodiment shown in the figure, a p-type column bottom region 122 having a higher impurity concentration than the p-type column region 108 located at a shallower position than the lower end of the n-type column region 107 is provided. Fig. 20 The semiconductor device according to the first modification shown has a plurality of p-type column bottom regions 123 arranged in the depth direction, and can perform more precise control of the electric field distribution.

[0106] Furthermore, when the impurity concentration of the p-type column bottom region 122 is increased to improve the withstand voltage, the on-voltage increases due to the expansion of the depletion layer between the adjacent p-type column bottom regions 122. As a countermeasure, Fig.21 In the semiconductor device according to the second modification shown, the n-type JFET region 124 having a higher impurity concentration than the n-type column region 107 is arranged between the p-type column bottom regions 122. Therefore, both the improvement of the withstand voltage and the reduction of the on-resistance can be achieved.

[0107] <Implementation Method 3>

[0108] <Structure of Semiconductor Device According to Embodiment 3>

[0109] Fig. 22 1 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 3. The semiconductor device according to Embodiment 3 is a trench gate super junction IGBT element manufactured using a silicon-based semiconductor substrate. The following is specifically described using a semiconductor device having an emitter-collector withstand voltage of about 1200 volts as an example, but it can also be applied to super junction IGBT elements having other withstand voltage values ​​or semiconductor devices having other super junction structures.

[0110] The semiconductor device involved in the third embodiment is different from the semiconductor device involved in the first embodiment in that the semiconductor device involved in the first embodiment is a planar gate MOS semiconductor device, while the semiconductor device involved in the third embodiment is a trench gate MOS semiconductor device.

[0111] like Fig. 22 As shown, the upper end of the p-type column region 108 is separated from the p-type base region 105 on the first main surface side selectively provided above the p-type column region 108 by the n-type charge holding region 106. The trench 201 is formed so as to penetrate the p-type base region 105 from the low-resistance n-type emitter region 103 provided on the surface layer of the p-type base region 105 and reach a part of the n-type charge holding region 106 so as to be selectively arranged above the n-type column region 107. In the trench 201, the gate electrode 102 is provided via the gate insulating film 101.

[0112] The depth of the bottom (lower end) of the trench 201 is shallower than the depth of the upper end of the p-type column region 108. Therefore, a decrease in withstand voltage due to an increase in the electric field between the upper portion of the p-type column region 108 and the trench 201 can be prevented.

[0113] <Method for Manufacturing Semiconductor Device According to Embodiment 3>

[0114] Next, regarding each wafer processing step in the method for manufacturing a semiconductor device according to the third embodiment, Figure 23 to Figure 26 Here, we will mainly explain the manufacturing Fig. 22 The processing steps required for the main parts of the device shown in FIG. 1 are the same as those for the steps up to the manufacture of the superstructure structure on the first main surface side. Figure 7 to Figure 10 The manufacturing method of the planar gate type super junction IGBT element shown in FIG. 1 is the same as that of FIG. 1 , and therefore the description thereof is omitted. Fig.16 The subsequent steps are the same, so only the different parts are described here.

[0115] After forming the superjunction structure on the first main surface side of the n-type silicon single crystal substrate 400, Fig.23 As shown, by taking, for example, 10 14 cm -2 Phosphorus is ion implanted at a dose of about 100 Å to form the n-type charge holding region 106 .

[0116] Then, if Fig.24 As shown, by placing, for example, 3×10 14 cm -2 Boron is ion implanted at a dose of about 100 Å to form the p-type base region 105 .

[0117] Then, if Fig.25 As shown, for example, a thermal diffusion treatment is performed at 1100° C. for about 140 minutes, and while the n-type charge holding region 106 and the p-type base region 105 are diffused, the boron at the bottom of the p-type column region 108 is diffused into the n-type bottom layer 109, thereby expanding the width of the bottom of the p-type column region 108.

[0118] Then, if Fig.26 As shown, a trench gate type MOSFET is formed in which a gate electrode 102 is buried in a trench 201 (trench for gate) via a gate insulating film 101 .

[0119] exist Fig.25 , Fig.26 In the embodiment, the trench gate structure is formed after the p-type base region 105 is formed. However, conversely, the trench gate structure may be formed first and then the p-type base region 105 may be formed.

[0120] <Variation of Implementation Example 3>

[0121] Fig. 27 is a cross-sectional view schematically showing the structure of a semiconductor device according to a modification of the third embodiment. Fig. 22 The same parts are given the same reference numerals and their description is omitted. The semiconductor device according to this modification is different from the semiconductor device according to the third embodiment in that, in the semiconductor device according to the third embodiment, the electrode formed in the trench 201 is only the gate electrode 102, whereas in some of the plurality of trenches in this modification, the n-type emitter region 103 is not provided on the first main surface side of the p-type base region 105 in contact with the side wall of the trench 201. Thus, in the trench 201 in contact with the p-type base region 105 in which the n-type emitter region 103 is not provided on the first main surface side, a dummy gate electrode 202 is formed via the gate insulating film 101. The dummy gate electrode 202 buried in the trench 201 of the trench dummy gate can be connected to either the gate electrode 102 or the emitter electrode 100.

[0122] The n-type emitter region 103 is not provided on the first main surface side of the p-type base region 105 in contact with the side wall of the trench 201 of the trench dummy gate, and electrons are not injected through the side wall of the trench 201 of the trench dummy gate, so it is distinguished from the original gate (trench gate) and is called a "trench dummy gate". In this modification, by arranging the trench dummy gate, for example, above the p-type pillar region 108, the hole accumulation effect can be improved and the on-voltage can be reduced.

[0123] In addition, if Fig. 22 As shown in FIG. 1 , in a semiconductor device consisting only of trench gates, if the spacing of the trenches 201 is reduced in order to reduce the on-resistance, the saturation current increases due to the increase in the channel density. If the saturation current is large, when a load such as a motor is short-circuited, a large current flows and there is a risk of the element being destroyed. Therefore, when the trench spacing is reduced without increasing the channel density, the use of a trench dummy gate structure becomes an effective means.

[0124] In addition, it is desirable that the trench 201 of the trench dummy gate is disposed above the p-type column region 108, and the trench 201 of the trench gate is disposed above the n-type column region 107. Thus, electrons are efficiently injected from the n-type emitter region 103 into the n-type charge holding region 106 and the n-type column region 107 thereunder via the inversion layer formed in the p-type base region 105 located near the sidewall of the trench 201 of the trench gate.

[0125] There is a possibility that a dynamic avalanche is generated due to the high charge generated during the switching operation, and the hot carriers generated in the avalanche are captured at the MOS interface of the trench dummy gate provided above the p-type column region 108. Therefore, when the p-type column region 108 is floating, the charge captured at the bottom of the trench 201 located above the p-type column region 108 is accumulated through long-term operation, thereby gradually breaking down the charge balance near the upper end of the p-type column region 108, resulting in a loss of long-term reliability. Therefore, by setting a structure in which the p-type column region 108 is connected to the p-type base region 105, for example, in a terminal structure region or a gate lead wiring region outside the active region, and the p-type column region 108 is separated from the p-type base region 105 in the active region, it is possible to achieve both reduction of on-resistance and assurance of long-term reliability.

[0126] <Implementation Method 4>

[0127] Fig.28 FIG. 2 is a plan view schematically showing the top surface layout of the semiconductor device according to Embodiment 4. Fig.28 As shown, the first gate electrode 203 and the second gate electrode 204 are alternately arranged in the active region. The plurality of first gate electrodes 203 arranged in the active region are bundled near the center of the upper surface layout (connected to the first gate wiring 304) and electrically connected to the first gate electrode pad 302. In addition, the plurality of second gate electrodes 204 arranged in the active region are bundled around the active region (connected to the second gate wiring 305) and electrically connected to the second gate electrode pad 303. As described later, by arranging the first gate electrode 203 above the n-type column region 107 and arranging the second gate electrode 204 above the p-type column region 108, each gate can be driven individually, and fine control suitable for reducing switching loss can be performed.

[0128] Fig.29 is a schematic diagram showing a semiconductor device according to Embodiment 4. Fig.28 The semiconductor device according to the fourth embodiment is a trench gate type super junction IGBT element manufactured using a silicon semiconductor substrate. The semiconductor device according to the fourth embodiment is different from the semiconductor devices according to the first to third embodiments in that it has two types of gates to which different voltages can be applied.

[0129] like Fig.29As shown, the upper end of the p-type column region 108 is separated from the p-type base region 105 on the first main surface side selectively provided above the p-type column region 108 by the n-type charge holding region 106. The trench 201 is formed so as to penetrate the p-type base region 105 from the low-resistance n-type emitter region 103 provided on the surface layer of the p-type base region 105 and reach a part of the n-type charge holding region 106 so as to be selectively arranged above the n-type column region 107. In the trench 201, the first gate electrode 203 is arranged so as to face the n-type column region 107 via the gate insulating film 101.

[0130] In addition, the trench 201 is formed so as to penetrate the p-type base region 105 from the low-resistance n-type emitter region 103 provided on the surface layer of the p-type base region 105 and reach a part of the n-type charge holding region 106 so as to be selectively arranged above the p-type column region 108. In the trench 201, a second gate electrode 204 is provided so as to face the p-type column region 108 via the gate insulating film 101.

[0131] like Fig.28 As shown, the first gate electrode 203 is arranged in a manner of dividing the active region of the semiconductor device, and the second gate electrode 204 is arranged from the periphery to the inside of the active region. The first gate electrode 203 is mounted on the first gate wiring 304, and the second gate electrode 204 is mounted on the second gate wiring 305. The first gate wiring 304 and the second gate wiring 305 are arranged on the upper surface of the semiconductor device, and the first gate wiring 304 is electrically connected to the first gate electrode pad 302, and the second gate wiring 305 is electrically connected to the second gate electrode pad 303. The first gate wiring 304 and the second gate wiring 305 can be formed of polycrystalline silicon or amorphous silicon, but in order to further reduce the delay of the gate signal, it is preferably formed of a metal wiring material such as aluminum.

[0132] exist Fig.28 In the example, the first gate electrode 203 is provided on the first gate wiring 304 in the active region so as to divide the active region of the semiconductor device, and the second gate electrode 204 is provided on the second gate wiring 305 at the periphery of the semiconductor device. However, it is also possible that the first gate electrode 203 is provided on the first gate wiring 304 at the periphery of the semiconductor device, and the second gate electrode 204 is provided on the second gate wiring 305 in the active region. In addition, it is self-evident that the same effect can be expected even if the layout is not a layout of gate wiring that divides the active region, but a layout in which the first gate electrode 203 and the second gate electrode 204 are alternately connected to the active region from the left and right or the top and bottom of the active region.

[0133] Fig.30: is a graph illustrating a timing chart of a first gate voltage and a second gate voltage for driving the semiconductor device according to Embodiment 4. The first gate voltage is applied to the first gate electrode pad 302 , and the second gate voltage is applied to the second gate electrode pad 303 .

[0134] <Operation of Semiconductor Device According to Embodiment 4>

[0135] The operation of the semiconductor device according to the fourth embodiment will be described.

[0136] The semiconductor device according to the fourth embodiment includes a drift layer 10 including an n-type column region 107 and a p-type column region 108 forming a superjunction structure.

[0137] When the emitter electrode 100 is grounded and a power supply voltage is applied to the collector electrode 112, and when the first gate voltage is lower than the gate threshold voltage of the MOSFET formed on the first main surface, a reverse bias is applied between the p-type base region 105 and the drift layer 10, and the current between the collector electrode 112 and the emitter electrode 100 is cut off.

[0138] Next, when voltages exceeding the gate threshold voltage of the MOSFET formed on the first main surface are simultaneously applied to the first gate electrode 203 and the second gate electrode 204 as the first gate voltage and the second gate voltage, an n-type inversion layer is formed in a portion of the p-type base region 105 that is in contact with the first gate electrode 203 and the second gate electrode 204 via the gate insulating film 101. Then, a current is conducted from the collector electrode 112 to the emitter electrode 100 via the inversion layer, thereby achieving an on-state from an off-state.

[0139] In order to turn the current flowing through the semiconductor device in the on state back to the off state, first, Fig.30 As shown, a zero bias or a negative bias is applied to the second gate electrode 204 as the second gate voltage, and after a time Δt has passed since the application, a zero bias or a negative bias is applied to the first gate electrode 203 as the first gate voltage. If the n-type inversion layer generated at the MOS interface of the p-type base region 105 that is in contact with the first gate electrode 203 and the second gate electrode 204 via the gate insulating film 101 disappears, the supply of electrons from the n-type emitter region 103 to the drift layer 10 stops. The accumulated carriers in the drift layer 10 and the n-type bottom layer 109 decay, the depletion layer between the p-type column region 108 and the n-type column region 107 in the drift layer 10 is penetrated, and the voltage between the collector electrode 112 and the emitter electrode 100 increases, and the state is turned off.

[0140] Here, Δt is preferably between 0.1 microseconds and 10 microseconds.

[0141] <Function and Effect of Semiconductor Device According to Embodiment 4>

[0142] The operation and effects of the semiconductor device according to the fourth embodiment will be described.

[0143] In the process of turning off the semiconductor device, a cutoff signal is first applied as a second gate voltage to the second gate electrode 204 disposed above the p-type column region 108. As a result, the n-type inversion layer generated at the MOS interface of the p-type base region 105 in contact with the second gate electrode 204 disappears, and the supply of electrons from the n-type emitter region 103 adjacent to the second gate electrode 204 via the gate insulating film 101 stops. At this time, a p-type inversion layer is formed in the portion of the n-type charge holding region 106 in contact with the second gate electrode 204 via the gate insulating film 101. Thus, a pnp bipolar transistor is formed in which the p-type column region 108 is a p-type emitter, the n-type charge holding region 106 is an n-type base, and the p-type inversion layer is a p-type collector. By forming such a pnp bipolar transistor, holes are discharged from the upper part of the p-type column region 108 to the p-type base region 105 via the n-type charge holding region 106 and the p-type inversion layer. Thus, carriers accumulated in the drift layer 10 are discharged, and the depletion layer extends to the pn junction between the p-type column region 108 and the n-type column region 107 in the drift layer 10 and a part of the n-type bottom layer. However, at this point in time, the super junction region is not completely depleted.

[0144] After a delay time Δt from the application of a cutoff signal as the second gate voltage to the second gate electrode 204, a zero bias or a negative bias is applied to the first gate electrode 203 as the first gate voltage. As a result, the n-type inversion layer generated at the MOS interface of the p-type base region 105 connected to the first gate electrode 203 via the gate insulating film 101 also disappears, so the supply of electrons from the n-type emitter region 103 is completely stopped. At this time, since a cutoff signal is first applied to the second gate electrode 204 as the second gate voltage, the time required to completely deplete the drift layer 10 becomes shorter as Δt increases. The results of this situation were confirmed by simulation, as shown in FIG. Fig.31 As shown in FIG. 1 , as Δt increases, the turn-off loss Eoff decreases and saturates at a certain point. On the other hand, when carriers are also accumulated in the n-type bottom layer 109, at the timing when either the first gate electrode 203 or the second gate electrode 204 is turned off, the depletion layer invades the n-type bottom layer 109, and the voltage between the collector and the emitter reaches a peak value, so the surge voltage Vcep has almost no effect on Δt. Therefore, by setting Δt>0, the surge voltage Vcep at the time of turn-off will not increase, and the turn-off loss Eoff can be reduced.

[0145] <Variation of Implementation Example 4>

[0146] Fig.32 is a cross-sectional view schematically showing the structure of a semiconductor device according to a modification of the fourth embodiment. Fig.29 The same reference numerals are used to designate the same parts, and description thereof will be omitted. The semiconductor device according to this modification example is different from the semiconductor device according to the fourth embodiment in that the semiconductor device according to this modification example has a planar gate structure.

[0147] In the semiconductor device according to the present modification, if a cutoff signal is applied as a second gate voltage to the second gate electrode 204 earlier than a cutoff signal is applied as a first gate voltage to the first gate electrode 203 by a time Δt, the n-type inversion layer generated at the MOS interface of the p-type base region 105 in contact with the second gate electrode 204 disappears, and the supply of electrons from the n-type emitter region 103 adjacent to the second gate electrode 204 via the gate insulating film 101 stops. At this time, a p-type inversion layer is formed in the portion of the n-type charge holding region 106 in contact with the second gate electrode 204 via the gate insulating film 101. Since the p-type inversion layer is connected to both the p-type base region 105 and the p-type pillar region 108, the accumulated carriers in the drift layer 10 are discharged to the emitter electrode 100 connected to the p-type base region 105 via the p-type pillar region 108 and the p-type inversion layer. Therefore, the time required for the drift layer 10 to be completely depleted is shortened when an off signal is applied as the first gate voltage to the first gate electrode 203. Therefore, the turn-off loss can be reduced without causing a surge voltage increase.

[0148] Furthermore, within the scope of the present disclosure, the various embodiments can be freely combined or the various embodiments can be appropriately modified or omitted.

[0149] The present disclosure has been described in detail, but the above description is illustrative in all aspects and not restrictive. It is understood that countless variations that are not exemplified can be conceived.

[0150] (Explanation of Reference Numerals)

[0151] 10: drift layer; 100: emitter electrode; 101: gate insulating film; 102: gate electrode; 103: n-type emitter region; 104: p-type body contact region; 105: p-type base region; 106: n-type charge holding region; 107: n-type pillar region; 108: p-type pillar region; 109: n-type bottom layer; 110: n-type buffer layer; 111: p-type collector layer; 112: collector electrode; 121: n-type JFET region; 122: p-type pillar bottom region; 123: p : bottom region of the p-type column; 124: n-type JFET region; 201: trench; 202: dummy gate electrode; 203: first gate electrode; 204: second gate electrode; 302: first gate electrode pad; 303: second gate electrode pad; 304: first gate wiring; 305: second gate wiring; 400: n-type silicon single crystal substrate; 401: trench for p-type column region; 407: n-type top epitaxial layer; 409: n-type bottom epitaxial layer; 410: hard mask film; 411: overgrowth region.

Claims

1. A semiconductor device having a first main surface and a second main surface facing the first main surface, comprising: The drift layer includes first column regions of a first conductivity type and second column regions of a second conductivity type alternately arranged in a direction parallel to the first main surface and the second main surface; A base region of a second conductivity type, selectively arranged on the first main surface side of the drift layer; a gate insulating film arranged in contact with the base region; a gate electrode arranged to face the base region via the gate insulating film; a charge holding region of a first conductivity type, disposed between the base region and the second pillar region; as well as An emitter region of the first conductivity type is selectively arranged in a surface layer on the first main surface side of the base region, The lower end of the end portion of the second pillar region on the second principal surface side is located closer to the second principal surface side than the lower end of the end portion of the first pillar region on the second principal surface side. When the width of the upper end of the second column region as the end on the first main surface side is wp1, the width of the second column region at the same position as the lower end of the first column region is wp2, and the width of the lower end of the second column region is wp3, wp3>wp2 and wp1>wp2.

2. The semiconductor device according to claim 1, wherein Also available: A bottom layer of a first conductivity type, arranged on the second main surface side of the drift layer; A buffer layer of a first conductivity type, disposed on the second main surface side of the bottom layer; and The second conductivity type collector layer is arranged on the second main surface side of the buffer layer.

3. The semiconductor device according to claim 1 or 2, wherein: The charge holding region is separated at a position corresponding to a center of the gate electrode in a direction parallel to the first main surface and the second main surface.

4. The semiconductor device according to claim 3, wherein: In a direction parallel to the first main surface and the second main surface, the width of the charge holding region is greater than the width of the base region.

5. The semiconductor device according to any one of claims 1 to 4, wherein: In the second column region, an impurity concentration contained in a region from the same position as the lower end of the first column region to the lower end of the second column region is higher than an impurity concentration contained in a region from the upper end of the second column region to the same position as the lower end of the first column region.

6. The semiconductor device according to claim 5, wherein: further comprising a first conductivity type JFET region, the first conductivity type JFET region being arranged on the second main surface side of the first column region so as to be in contact with a lower end of the first column region, The impurity concentration of the JFET region is higher than the impurity concentration of the first pillar region.

7. The semiconductor device according to any one of claims 1, 2, 5 or 6, wherein: The gate electrode penetrates the base region and reaches the charge holding region.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The second pillar region is connected to the base region.

9. The semiconductor device according to any one of claims 1 to 7, wherein: The second pillar region is partially separated from the base region.

10. The semiconductor device according to any one of claims 7 to 9, wherein: The gate electrode includes a first gate electrode and a second gate electrode, The first gate electrode is arranged to face the first pillar region via the gate insulating film. The second gate electrode is arranged to face the second pillar region with the gate insulating film interposed therebetween.

11. A method for controlling a semiconductor device, wherein: When switching from an on state in which current is conducted to an off state in which current is not conducted in the semiconductor device according to claim 10 , an off signal is applied to the second gate electrode before an off signal is applied to the first gate electrode.

12. A method for manufacturing a semiconductor device, comprising the following steps: (a) preparing a semiconductor wafer, wherein a bottom epitaxial layer of a first conductivity type is formed on a semiconductor substrate, and a top epitaxial layer of the first conductivity type is formed on a surface of the bottom epitaxial layer; (b) forming a second column region trench so as to penetrate the top epitaxial layer and reach the bottom epitaxial layer, and forming the top epitaxial layer other than the second column region trench as a first column region; (c) forming a second pillar region by performing buried epitaxial growth on the second pillar region trench using a material doped with impurities of the second conductivity type; (d) planarizing a first main surface of the semiconductor wafer, which is a surface on the top epitaxial layer side, so that the first pillar region and the second pillar region are exposed; (e) forming a gate insulating film so as to cover the first pillar region and extend from the first pillar region to a part of the second pillar region, and forming a gate electrode on the gate insulating film; (f) forming a charge holding region of the first conductivity type on a surface layer of the second pillar region by ion implantation from the first main surface side; (g) performing a thermal diffusion process to diffuse the charge holding region to directly below the gate electrode and diffuse an end portion of the second pillar region on the second main surface side facing the first main surface to directly below the first pillar region; and (h) forming a base region of the second conductivity type in the surface layer of the charge holding region by ion implantation from the first main surface side, When the width of the upper end of the second column region as the end on the first main surface side is wp1, the width of the second column region at the same position as the lower end of the first column region is wp2, and the width of the lower end of the second column region is wp3, wp3>wp2 and wp1>wp2.

13. A method for manufacturing a semiconductor device, comprising the following steps: (a) preparing a semiconductor wafer, wherein a bottom epitaxial layer of a first conductivity type is formed on a semiconductor substrate, and a top epitaxial layer of the first conductivity type is formed on a surface of the bottom epitaxial layer; (b) forming a second column region trench so as to penetrate the top epitaxial layer and reach the bottom epitaxial layer, and forming the top epitaxial layer other than the second column region trench as a first column region; (c) forming a second pillar region by performing buried epitaxial growth on the second pillar region trench using a material doped with impurities of the second conductivity type; (d) planarizing a first main surface of the semiconductor wafer, which is a surface on the bottom epitaxial layer side, so that the first pillar region and the second pillar region are exposed; (e) forming a charge holding region of the first conductivity type on the surface layer of the first pillar region and the second pillar region by ion implantation from the first main surface side; (f) forming a base region of the second conductivity type in a surface layer of the charge holding region by ion implantation from the first main surface side; (g) performing a thermal diffusion process to diffuse the charge holding region and the base region so that an end portion of the second pillar region on the second main surface side facing the first main surface is diffused to directly below the first pillar region; and (h) forming a gate trench so as to penetrate the base region and reach the charge holding region, forming a gate insulating film on the inner wall of the gate trench, and forming a gate electrode so as to fill the gate trench, When the width of the upper end of the second column region as the end on the first main surface side is wp1, the width of the second column region at the same position as the lower end of the first column region is wp2, and the width of the lower end of the second column region is wp3, wp3>wp2 and wp1>wp2.

14. The method for manufacturing a semiconductor device according to claim 12 or 13, wherein: It also has the following processes: (i) removing the entire semiconductor substrate from the second main surface side to expose the bottom epitaxial layer; (j) forming a buffer layer of the first conductivity type on the surface layer of the bottom epitaxial layer by ion implantation from the second main surface side; (k) forming a collector layer of the second conductivity type on the surface of the buffer layer by ion implantation from the second main surface side; (l) Activating the buffer layer and the collector layer.

15. The method for manufacturing a semiconductor device according to any one of claims 12 to 14, wherein: The semiconductor substrate is a substrate doped with impurities of a first conductivity type and formed by using a CZ method (ie, a Czochralski method), a MCZ method (ie, a magnetron Czochralski method), or a FZ method (ie, a melting zone method).

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