Includes a device for a synchronization circuit to perform near-field communication.

Abstract

Disclosed is an apparatus including synchronization circuitry for performing near-field communication. The apparatus is configured to receive a first carrier signal and transmit a second carrier signal, and has a phase-locked loop (PLL) including a first domain comprising an oscillator configured to generate a signal at a given frequency, and circuitry configured to generate information representing the frequency of the signal generated by the oscillator and to generate the second carrier signal and a clock signal, the first domain being timed by the first carrier signal; a second domain, timed by the clock signal, including circuitry configured to compare the frequency of the signal generated by the oscillator with the frequency of the first carrier signal and control the oscillator, and matching circuitry configured to transmit information representing the frequency of the signal generated by the oscillator from the first domain to the second domain.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of French Patent Application No. 2202164, filed on March 11, 2022, which is incorporated herein by reference. Technical Field

[0003] The implementation and embodiments of the present invention relate to near-field communication. Background Technology

[0004] Near Field Communication (NFC) is a short-range, high-frequency wireless communication technology that allows two contactless devices to exchange data over a short distance, such as 10 centimeters.

[0005] NFC technology is an open technology platform standardized in standards ISO / IEC 18092 and ISO / IEC 21481, but it incorporates many existing standards, such as the Type A and Type B protocols defined in standard ISO-14443, which can be communication protocols that can be used for NFC technology.

[0006] Near-field communication can be performed between the card reader and the device emulated in card mode. The card reader is then configured to generate a magnetic field via its antenna, which is typically a 13.56 MHz sine wave in commonly used standards. The magnetic field strength, expressed in root mean square (RMS), is between 0.5 and 7.5 amperes per meter.

[0007] Near-field communication can be performed in an active operating mode. In this mode, both the card reader and the device emulated in card mode generate electromagnetic fields. Typically, this operating mode is used when the device has its own power source (such as a battery), as is the case in cellular mobile phones, which then emulate in card mode.

[0008] Specifically, active load modulation (ALM) can be used to perform near-field communication. Active load modulation allows for signal synchronization between the card reader and the device emulated in card mode.

[0009] The card reader is configured to emit an electromagnetic field, and the device simulating the card mode is configured to modulate the amplitude of the non-beat frequency field. In response to the card reader, the device simulating the card mode generates a signal synchronized with the card reader's field so as to be in phase with the card reader's field. It is also important for the card reader to generate a sufficiently stable field so that it can detect minute changes in its field based on the distance between the card reader and the card simulator.

[0010] In reader or card emulator mode, it is important that the device generates the cleanest possible clock and ensures communication with minimal energy. This is achieved by reducing or even avoiding stray tones present in the generated clock.

[0011] The device simulated in card mode includes a phase-locked loop (PLL). The PLL includes a phase- and frequency-servo-controlled oscillator based on a signal having a reference frequency that may differ from 13.56 MHz. The signal with the reference frequency can be a signal from a field generated by the card reader. Alternatively, the signal with the reference frequency can be a signal generated by a crystal oscillator of the platform, which can be used for functions other than near-field communication. The oscillator is servo-controlled to obtain a signal with a desired frequency, for example, 13.56 MHz, at the output of the PLL. The oscillator is then servo-controlled to generate a signal with a frequency that is a multiple of the desired frequency, for example, 64 × 13.56 MHz for a desired frequency of 13.56 MHz. The device also includes circuitry that allows frequency division of the signal generated by the oscillator to obtain a signal with a desired frequency, for example, 13.56 MHz.

[0012] Oscillators can be analog or digitally controlled.

[0013] When the oscillator is controlled analogously, the divided signal is compared with a reference frequency signal. The comparison between the divided signal and the reference frequency signal is timed by the reference frequency signal. Therefore, the oscillator frequency will vary with each clock cycle of the reference frequency signal. This induces spurious tones in the output signal at both distances from the carrier frequency (Fref) and f*Fref, where f is between 0 and 1, on either side of the desired carrier frequency.

[0014] The oscillator can be digitally controlled. Then, by comparing the number of clock strokes of the reference frequency signal with the number of clock strokes of the signal generated by the oscillator, the oscillator can be servo-controlled. This comparison is also timed at the reference frequency. It also induces spurious tones in the output signal, on either side of the desired carrier frequency, at distances Fref from the carrier frequency and f*Fref from the carrier frequency, where f is between 0 and 1. The output signal is then noisy, thus degrading the quality of near-field communication.

[0015] Therefore, there is a need for a device configured for near-field communication that includes a synchronization circuit that allows for the reduction or even avoidance of spurious tones near the carrier frequency in the output signal. Summary of the Invention

[0016] An apparatus configured to perform non-communication via active load modulation without contact with a card reader is provided, comprising an input for receiving a first carrier signal transmitted by a card reader, an output for transmitting a second carrier signal, and a synchronization circuit configured to synchronize the first and second carrier signals. The synchronization circuit includes a phase-locked loop (PLL) comprising: a first domain including a digitally controlled oscillator configured to generate a signal of a given frequency; and circuitry configured to generate information representing the frequency of the signal generated by the oscillator, and to generate a second carrier signal and a clock signal from the signal generated by the oscillator, the frequency of which is between the frequency of the second carrier signal and the frequency of the signal generated by the oscillator. The first domain is timed by the first carrier signal.

[0017] The second domain includes circuitry configured to digitally compare the frequency of a signal generated by the oscillator with the frequency of the first carrier signal, and to control the oscillator based on the result of the comparison. The second domain is timed by the clock signal.

[0018] A frequency matching circuit between the first domain and the second domain is configured to receive information from the first domain representing the frequency of a signal generated by the oscillator at the frequency of the first carrier signal, and transmit that information to the second domain at the frequency of the clock signal.

[0019] In this device, a comparison is performed between the frequency of the signal generated by the oscillator and the frequency of the first carrier signal controlling the oscillator, at the frequency of a clock signal. However, the frequency of the clock signal is higher than the frequency of the first carrier signal. This allows spurious tones to be removed from the carrier in the second carrier signal. Thus, the output signal is easier for a card reader to read. Furthermore, using a clock signal to time the second domain allows for more responsive control of the oscillator.

[0020] Advantageously, the first domain includes a counter divider, which is configured to generate at the output:

[0021] The second carrier signal from the signal generated by the oscillator is such that the frequency of the second carrier signal is reduced by a given factor compared to the frequency of the signal generated by the oscillator; the clock signal from the signal generated by the oscillator represents information about the frequency of the signal generated by the oscillator by counting the number of clock strokes of the signal generated by the oscillator.

[0022] In an advantageous embodiment, the counter divider includes:

[0023] The first series of D flip-flops, each mounted as a frequency divider, divides the frequency of the signal generated by the oscillator to obtain the second carrier signal and the clock signal.

[0024] The second series of D flip-flops each receive a signal inverted relative to a reference frequency signal as a clock, and take a signal taken from the same stage of the first series of D flip-flops as a clock signal as an input, and generate a count value at the output as information representing the frequency of the signal generated by the oscillator.

[0025] Advantageously, the second domain includes:

[0026] An accumulator is configured to generate an output value by accumulating a value equal to the factor at each clock stroke of the first carrier signal.

[0027] A frequency comparator and a phase-shift adder are used to compare the signal generated by the oscillator with the first carrier signal.

[0028] A loop filter connected to the comparator output via a phase-shift adder.

[0029] Therefore, the comparator and loop filter are timed by a clock signal with a frequency higher than the reference frequency. This allows for increased speed of the phase-locked loop.

[0030] Preferably, the second domain further includes a Σ-Δ modulation circuit connected to the output of the loop filter and allowing control of the oscillator. Therefore, the Σ-Δ modulation circuit is timed by a clock signal having a frequency higher than the reference frequency. This improves the efficiency of the Σ-Δ modulation circuit by increasing the number of steps it can take.

[0031] In an advantageous embodiment, the frequency matching circuit includes a first-in-first-out (FIFO) register configured to receive information representing the frequency of a signal generated by an oscillator as input from a first domain of the phase-locked loop, and to output the information representing the frequency of the signal generated by the oscillator to a second domain of the phase-locked loop. The FIFO register is timed at its input by a reference frequency signal and at its output by a clock signal.

[0032] Advantageously, the FIFO register includes:

[0033] A Gray code counter is configured to count for each clock stroke of the reference frequency signal.

[0034] A demultiplexer has an input configured to receive information representing the frequency of a signal generated by the oscillator at the input of the FIFO register;

[0035] The selection input connected to the output of the Gray code counter; and

[0036] Multiple outputs, which can be selected based on the value of the Gray code counter received from the selected input.

[0037] Multiple registers, timed by the reference frequency signal, and each register having an input connected to a given output of the multiplexer, are configured to store information representing the frequency of the signal generated by the oscillator at each clock stroke of the reference frequency signal.

[0038] At least one register, timed by the clock signal, is configured to receive a value from the Gray counter.

[0039] A multiplexer has inputs to individual registers connected to multiple registers, a selection input connected to at least one register, and an output that allows information related to the frequency of a signal generated by an oscillator to be sent at the output of a FIFO register.

[0040] Advantageously, the frequency matching circuit also includes a D flip-flop timed by a reference frequency signal and has an input configured to receive frequency-related information about the signal generated by the oscillator from a first domain and an output configured to send that information at an input of the FIFO register.

[0041] Preferably, the first carrier signal has a carrier frequency on the order of 13.56 MHz, the oscillator is configured to transmit a frequency signal on the order of 868 MHz, the counter divider is configured to divide the frequency of the signal generated by the oscillator by 64, and the accumulator is configured to accumulate a value equal to 64 at each clock stroke of the reference frequency signal.

[0042] Advantageously, the synchronization circuit further includes a frequency-locked phase-locked loop, which includes:

[0043] A first domain includes a digitally controlled oscillator configured to generate a signal of a given frequency, and circuitry configured to generate information representing the frequency of the signal generated by the oscillator. The first domain is timed according to a reference clock signal.

[0044] The second domain includes circuitry configured to digitally compare the frequency of a signal generated by the oscillator with the frequency of the first carrier signal, and to control the oscillator based on the result of the comparison. The second domain is timed according to the clock signal.

[0045] A frequency matching circuit between the first domain and the second domain is configured to receive information from the first domain representing the frequency of a signal generated by the oscillator at the frequency of a signal generated by the internal reference oscillator, and transmit this information to the second domain at the frequency of the clock signal.

[0046] When the device is operating in card emulator mode, the reference clock signal can be generated either through an internal reference oscillator or by rendering a signal from the card reader.

[0047] Preferably, the token generation circuit is configured to generate a token signal each time the value of the Gray code counter changes, and each element of the second field is implemented when the token signal is generated. Attached Figure Description

[0048] Other advantages and features of the invention will become apparent upon examining the detailed features of the non-limiting embodiments and drawings, wherein:

[0049] Figure 1 An apparatus having a synchronization circuit including a phase-locked loop is shown;

[0050] Figure 2 A counter divider with a first series of flip-flops connected in series is shown, each flip-flop being mounted as a divider by two;

[0051] Figure 3 The FIFO register is shown;

[0052] Figure 4 A graph is shown representing oscillator control using a Σ-Δ modulation circuit;

[0053] Figure 5 The spectrum of the active load modulated output signal is shown; and

[0054] Figure 6 Another embodiment of a device configured to perform NFC via active load modulation is shown. Detailed Implementation

[0055] In order to communicate with the card reader, the device DIS includes, for example, Figure 1 The synchronization circuit MSYNC is shown. The synchronization circuit MSYNC includes a phase-locked loop (PLL) suitable for performing frequency synthesis.

[0056] The synchronization circuit MSYNC is configured to receive a first carrier signal Fref at a frequency of 13.56 MHz. This frequency is a reference frequency, and during communication from the device to the reader, the device DIS aims to synchronize using the synchronization circuit MSYNC at this reference frequency. The first carrier signal Fref is extracted from the electromagnetic field transmitted by the reader and received by the antenna. The extraction of the first carrier signal Fref is performed using a carrier signal extraction circuit (not shown) known to those skilled in the art.

[0057] The phase-locked loop (PLL) comprises two domains, ANLG and DGTL, which are clocked at different frequencies. The first domain, ANLG, is timed by a reference frequency signal, Fref. The first domain, ANLG, includes a digitally controlled oscillator (DCO). The DCO is powered by a regulator, LDO. Therefore, the DCO has inputs connected to the output of a register, which specifically stores D flip-flops (Dff) that allow the control of the DCO using words or bits.

[0058] The oscillator DCO is configured to generate a signal that is a multiple of the desired frequency (i.e., synchronized with a reference frequency signal, such as 13.56 MHz) of the output signal ALM with the synchronization circuit MSYNC. For example, the oscillator DCO can be configured to generate frequencies on the order of 868 MHz (64 * 13.56 MHz).

[0059] The first domain ANLG also includes a counter divider CNTD, which allows counting the number of rising edges of the signal generated by the oscillator DCO. The counter divider CNTD is configured to divide the frequency of the signal generated by the oscillator DCO to obtain an output signal ALM of the desired frequency.

[0060] More specifically, such as Figure 2 As shown, the counter divider CNTD includes a first series of D flip-flops FS connected in series, each flip-flop mounted as a divider by two. For example, the first series of D flip-flops FS may include six D flip-flops connected in series, each mounted as a divider by two. The first D flip-flops then receive the signal generated by the oscillator DCO as a clock. Each D flip-flop also has an inverted output connected to the input of the same D flip-flop and a non-inverted output that generates the clock signal for the next D flip-flop. In this way, each D flip-flop allows the frequency of the signal generated by the oscillator DCO to be divided by 2. Therefore, the sixth D flip-flop allows a signal with a frequency relative to the frequency of the signal generated by the oscillator DCO divided by 64. Thus, when the oscillator frequency is on the order of 868 MHz, the sixth D flip-flop allows a signal with a desired frequency of 13.56 MHz.

[0061] The counter divider (CNTD) is also configured to generate a clock signal CLK_54MHz with a frequency higher than the desired frequency. This clock signal CLK_54MHz is generated to synchronize with the frequency of the oscillator (DCO). For example, the counter divider (CNTD) is adapted to generate a frequency signal on the order of 54MHz obtained at the output of the fourth D flip-flop in the first series of D flip-flops. This clock signal is used for timing (clock control) of the second domain of the phase-locked loop (PLL).

[0062] The counter divider CNTD also includes a second series of D flip-flops (SS). For example, the second series of D flip-flops (SS) comprises six D flip-flops. Each D flip-flop receives an inverted signal of the reference frequency signal as its clock and takes a clock signal taken from the same rank (arrangement) of the first series of D flip-flops as its input. Therefore, the first D flip-flop of the second series (SS) takes the signal generated by the oscillator DCO as its input. Each of the second series of D flip-flops (SS) has an output, and the collection of these outputs allows the generation of the count value cnt_out.

[0063] The synchronization circuit MSYNC also includes a frequency matching circuit FADPT between the first domain ANLG and the second domain DGTL. The frequency matching circuit FADPT includes a D flip-flop at the output of the counter divider CNTD. This flip-flop D receives the reference frequency signal Fref as its clock. Therefore, the clock of this D flip-flop is inverted relative to the clock of the D flip-flops in the second series of D flip-flops SS of the counter divider CNTD. The D flip-flop at the output of the counter divider CNTD allows the count value to be stored by taking into account the propagation delay of the count value between the counter divider CNTD and the D flip-flops.

[0064] The frequency matching circuit FADPT also includes a FIFO register. The FIFO register is as follows: Figure 3As shown. The FIFO register includes a demultiplexer DMUX that receives the count value cnt_out at its input. The FIFO register also includes a register RG for each output of the demultiplexer DMUX. Each register RG uses the reference frequency signal Fref as its clock. The FIFO register also includes a multiplexer MUX with inputs for each register RG. Each register RG may include multiple D flip-flops. The FIFO register also includes a Gray code counter Gr_ptr, which uses the reference frequency signal Fref as its clock. Therefore, the Gray code counter is updated on each rising edge of the reference frequency signal Fref. Specifically, the Gray code counter allows modification of only one bit of its value at each clock stroke of the reference frequency signal Fref. The Gray code counter has an output connected to the selection input of the demultiplexer DMUX. Therefore, the value of the Gray code counter allows selection of the register RG connected to the demultiplexer DMUX, where the count value will be stored. The output of the Gray code counter is also connected to the input of the first register REG1 in a series of registers REG1, REG2 mounted in series. Each register REG1, REG2 includes multiple D flip-flops connected in parallel. The last register, REG2, has an output connected to the select input of the multiplexer MUX. These registers use a clock signal CLK_54MHz at a frequency higher than the desired frequency as their clock. This continuity of the registers ensures that the count value is indeed recorded in register RG of the FIFO register before being sent at the output of the FIFO register. Here, continuity includes two registers, REG1 and REG2. However, multiple registers can be provided in addition to these two. Therefore, the multiplexer allows the count value cnt_out to be sent at the output of the FIFO register at the frequency of the clock signal CLK_54MHz.

[0065] The output of the FIFO register is connected to the inverting input of comparator CMP1 in the MSYNC synchronization circuit. Comparator CMP1 also includes an input that receives the output from the accumulator ACC. The accumulator ACC has an input that receives a value equal to the desired value multiplied by the oscillator DCO (e.g., 64). The accumulator ACC also has an input connected to its output. The accumulator ACC uses the reference frequency signal Fref as its clock. Therefore, the accumulator ACC allows obtaining a value equal to the reference frequency multiplied by 64.

[0066] The output of comparator CMP1 corresponds to the error between the frequency of the signal generated by oscillator DCO (equal to the frequency of the signal at the output of the synchronization circuit multiplied by 64) and the reference frequency multiplied by 64.

[0067] The output of comparator CMP1 is connected to the input of adder ADD1 in the synchronous circuit MSYNC. Adder ADD1 also includes a second input configured to receive a value φ corresponding to the phase shift. offset This is to offset the edges of the reference frequency signal. Adding this phase offset allows for compensation of phase errors from the synchronization circuit to the antenna.

[0068] The output of adder ADD 1 is connected to the loop filter PLL_f. The loop filter PLL_f uses a clock signal CLK_54MHz with a frequency higher than the desired frequency as its clock.

[0069] The output of the loop filter PLL_f is connected to the input of the Σ-Δ modulation circuit. The Σ-Δ modulation circuit uses a signal with a frequency higher than the desired frequency, CLK_54MHz, as its clock. The output of the Σ-Δ modulation circuit is connected to the input of the register configured to store a value that allows control of the oscillator DCO. This register uses the reciprocal of the frequency signal CLK_54MHz, which is higher than the desired frequency, as its clock.

[0070] Timing the Σ-Δ modulation circuit with a clock signal improves Σ-Δ modulation. This effectively allows for more mixing steps at higher frequencies, bringing the average value at the output of the Σ-Δ modulation circuit closer to the desired value, thus allowing an output signal ALM at the desired frequency to be obtained at the output of the synchronization circuit. Furthermore, timing the Σ-Δ modulation circuit with a clock signal also allows for the removal of spurious tones from the carrier wave. These spurious tones can then be filtered more effectively by the loop filter PLL_f. This results in a quieter output signal. Figure 4 The diagram illustrates the oscillator control using this Σ-Δ modulation circuit. Specifically, curve 20 shows the digital control of the oscillator DCO, DCO_DGTL_CTRL, and curve 21 shows the analog control of the oscillator DCO over time t, DCO_ANLG_CTRL. As shown, the digital control DCO_DGTL_CTRL can take four values ​​N-1, N, N+1, and N+2 at the frequency of the clock signal (i.e., 54MHz). Higher frequencies allow for precise analog control DCO_ANLG_CTRL that closely approximates the desired value TRGT.

[0071] Furthermore, the comparator CMP 1, adder ADD 1, loop filter PLL_f, and Σ-Δ modulation circuitry can be configured such that they can only be implemented when a token signal is generated. Specifically, the domain DGTL includes a token generation circuit configured to generate a token signal whenever a change in the Gray counter value detected at frequency CLK_54MHz is observed, specifically by comparing the values ​​stored in registers REG1 and REG2. Thus, a token signal is issued with each update of the counter value in the domain ANLG. Therefore, the token signal allows these distinct elements to be implemented only once per clock stroke of the reference frequency signal, while awaiting the generation of the count value cnt_out.

[0072] Figure 5 The spectrum SPCTR of the output signal ALM is shown. The output signal has a carrier Fout of 13.56MHz. The fact that the second domain DGTL is timed allows for a spurious tone offset of 54MHz relative to the carrier Fout (the clock signal CLK_54MHz has a frequency of 54MHz).

[0073] Figure 6 A second embodiment of a device DIS configured to perform near-field communication via active load modulation is shown. This embodiment is advantageous for operation in card simulator mode. In card simulator mode, during the receive phase, the synchronization circuit MSYNC is configured to generate a desired frequency signal based on a reference frequency extracted from the field. Then, during the transmit phase when the reference frequency signal Fref is no longer available, the synchronization circuit MSYNC is configured to generate the desired frequency signal from a signal XOCK generated by the device DIS's internal oscillator (e.g., a quartz oscillator (not shown)).

[0074] The synchronization circuit MSYNC then comprises two loops. Specifically, the synchronization circuit MSYNC includes the loops mentioned earlier. Figure 1 The described phase-locked loop (PLL) is the same as the PLL described above. Therefore, this loop PLL specifically includes a counter divider (CNTD) with a reference frequency signal Fref as the clock, a D flip-flop located at the output of the counter divider Fref, and a FIFO register that allows data transfer between the domain ANLG, which is timed by the reference frequency signal, and the domain DGTL, which is timed by a clock signal CLK_54MHz with a frequency higher than the desired frequency.

[0075] The synchronization circuit also includes a frequency-locked phase-locked loop (FLL). Specifically, this loop includes the same counter divider (CNTD) as the FLL and has a clock signal (XOCK) generated by an internal oscillator. The FLL also includes a D flip-flop at the output of the counter divider (CNTD), which has the same clock signal (XOCK) and a FIFO register that allows data transfer between the ANLG and DGTL domains.

[0076] The loop also includes a differentiator with an input connected to the output of the FIFO register and an output connected to the second comparator CMP 2.

[0077] The synchronization circuit also includes a first loop filter PLL_d, whose input is configured to receive the output of adder ADD1. This loop filter PLL_d also has an output connected to the input of a third comparator CMP 2.

[0078] The synchronization circuit also includes a second loop filter, FLL_f. The loop filter FLL_f takes the output of the third comparator as its input.

[0079] The synchronization circuit also includes a multiplexer MX that takes the outputs of loop filters PLL_f and FLL_f as inputs. The multiplexer includes a selection input configured to receive a signal PLL_dual, which allows selection of which input of the multiplexer is sent to the Σ-Δ modulation circuit based on the desired operating mode of the synchronization circuit. Specifically, the signal PLL_dual allows operation with either a phase-locked loop (PLL) or a frequency-locked loop (FLL). When only the reader's reference frequency is available, operation using the PLL (specifically, using loop filter PLL_f) is selected. The value of the signal PLL_dual is then equal to zero. When the reference signal XOCK is used, operation using the frequency-locked loop (specifically, using loop filters PLL_d and FLL_f) is selected. The value of the signal PLL_dual is then equal to 1.

[0080] In this synchronization circuit MSYNC, the phase-locked loop (PLL) allows the frequency-locked loop (FLL) to be servo-controlled before the device responds to the reader. In this way, when the device responds to the reader, the frequency-locked loop (FLL) servo-controlled relative to the internal oscillator allows a signal of the desired frequency (e.g., 13.56 MHz) to be generated at the output of the synchronization circuit.

Claims

1. An apparatus configured to communicate via active load modulation without contact with a card reader, the apparatus comprising: Input, used to receive a first carrier signal emitted by the card reader; The output is used to transmit the second carrier signal; as well as A synchronization circuit, configured to synchronize the first carrier signal and the second carrier signal, the synchronization circuit including a phase-locked loop, the phase-locked loop comprising: A first domain includes: a digitally controlled oscillator configured to generate a signal of a given frequency; and a first circuit configured to generate information representing the frequency of the signal generated by the oscillator, and to generate a second carrier signal and a clock signal from the signal generated by the oscillator, the frequency of the clock signal being included between the frequency of the second carrier signal and the frequency of the signal generated by the oscillator, the first domain being timed by the first carrier signal; The second domain includes a second circuit configured to digitally compare the frequency of a signal generated by the oscillator with the frequency of the first carrier signal, and to control the oscillator based on the result of the comparison, the second domain being timed by the clock signal; and A frequency matching circuit, located between the first and second domains, is configured to receive information from the first domain representing the frequency of a signal generated by the oscillator at the frequency of the first carrier signal, and to transmit the information to the second domain at the frequency of the clock signal.

2. The apparatus of claim 1, wherein the first domain includes a counter divider configured to operate at the output as follows: The second carrier signal is generated from the signal generated by the oscillator, such that the second carrier signal has a frequency that is reduced by a given factor compared to the frequency of the signal generated by the oscillator; The clock signal is generated from the signal generated by the oscillator; and Information representing the frequency of the signal generated by the oscillator is generated by counting the number of clock strokes of the signal generated by the oscillator.

3. The apparatus of claim 2, wherein the counter divider comprises: The first series of D flip-flops, each of which is mounted as a frequency divider, is used to divide the frequency of the signal generated by the oscillator to obtain the second carrier signal and the clock signal; as well as The second series of D flip-flops, each receiving a signal inverted relative to the first carrier signal as a clock, and taking a signal taken from the same stage of the first series of D flip-flops as a clock as an input, and generating a count value at the output as information representing the frequency of the signal generated by the oscillator.

4. The apparatus of claim 2, wherein the second domain comprises: An accumulator is configured to generate an output value by accumulating a value equal to the factor at each clock stroke of the first carrier signal; A frequency comparator and a phase-shift adder are located between the signal generated by the oscillator and the first carrier signal; as well as A loop filter is connected to the comparator output via the phase-shift adder.

5. The apparatus of claim 4, wherein the second domain further comprises: A Σ-Δ modulation circuit is connected to the output of the loop filter and allows control of the oscillator.

6. The apparatus of claim 1, wherein the frequency matching circuit includes a FIFO register configured to receive information representing the frequency of a signal generated by the oscillator as input from a first domain of the phase-locked loop, and to output information representing the frequency of the signal generated by the oscillator to a second domain of the phase-locked loop, the FIFO register being timed at the input by the first carrier signal and at the output by the clock signal.

7. The apparatus of claim 6, wherein the FIFO register comprises: A Gray code counter is configured to count each clock stroke of the first carrier signal; A multiplexer has an input configured to receive information at the input of the FIFO register representing the frequency of a signal generated by the oscillator; Select an input and connect it to the output of the Gray code counter; And multiple outputs, which can be selected based on the value of the Gray code counter received from the selection input; Multiple registers, timed by the first carrier signal, and each register having an input connected to a given output of the multiplexer, so as to be able to store information representing the frequency of the signal generated by the oscillator at each clock stroke of the first carrier signal; At least one register, timed by the clock signal, is configured to receive a value from the Gray code counter; as well as A multiplexer has: an input connected to each of the plurality of registers; a selection input connected to at least one of the registers; and an output that allows information related to the frequency of the signal generated by the oscillator to be transmitted at the output of the FIFO register.

8. The apparatus of claim 7, wherein the frequency matching circuit further comprises a D flip-flop timed by the first carrier signal and has: an input configured to receive information relating to the frequency of a signal generated by the oscillator from the first domain; and an output configured to transmit the information at an input to the FIFO register.

9. The apparatus of claim 4, wherein the first carrier signal has a carrier frequency on the order of 13.56 MHz, the oscillator is configured to transmit a frequency signal on the order of 868 MHz, the counter divider is configured to divide the frequency of the signal generated by the oscillator by 64, and the accumulator is configured to accumulate a value equal to 64 in each clock stroke of the first carrier signal.

10. The apparatus of claim 1, wherein the synchronization circuit further comprises a frequency-locked phase-locked loop, the frequency-locked phase-locked loop comprising: A first domain includes: the digitally controlled oscillator configured to generate a signal of a given frequency; and a first circuit configured to generate information representing the frequency of the signal generated by the oscillator, the first domain being timed according to a reference clock signal; The second domain includes a second circuit configured to digitally compare the frequency of a signal generated by the oscillator with the frequency of the first carrier signal, and to control the oscillator based on the result of the comparison, the second domain being timed by the clock signal; and A frequency matching circuit, between the first domain and the second domain, is configured to: receive from the first domain information representing the frequency of a signal generated by the oscillator at the frequency of a signal generated by an internal reference oscillator, and transmit the information to the second domain at the frequency of the clock signal.

11. The apparatus of claim 7, further comprising a token generation circuit configured to generate a token signal whenever the value of the Gray code counter changes, wherein each element of the second field is implemented when the token signal is generated.

12. An apparatus configured to communicate via active load modulation without contact with a card reader, the apparatus comprising: Input, used to receive a first carrier signal emitted by the card reader; The output is used to transmit the second carrier signal; as well as A synchronization circuit, configured to synchronize the first carrier signal and the second carrier signal, the synchronization circuit including a phase-locked loop, the phase-locked loop comprising: The first domain includes: A digitally controlled oscillator is configured to generate a signal at a given frequency. A first circuit is configured to generate information representing the frequency of a signal generated by the oscillator, and to generate a second carrier signal and a clock signal from the signal generated by the oscillator, the frequency of the clock signal being included between the frequency of the second carrier signal and the frequency of the signal generated by the oscillator, the first domain being timed by the first carrier signal; and The counter divider is configured to operate at the output as follows: The second carrier signal is generated from the signal generated by the oscillator, such that the second carrier signal has a frequency that is reduced by a given factor compared to the frequency of the signal generated by the oscillator; Generate a clock signal from the signal generated by the oscillator; and Information representing the frequency of the signal generated by the oscillator is generated by counting the number of clock strokes of the signal generated by the oscillator. The second domain includes: a second circuit configured to digitally compare the frequency of a signal generated by the oscillator with the frequency of the first carrier signal, and to control the oscillator based on the result of the comparison, wherein the second domain is timed by the clock signal; and A frequency matching circuit, located between the first and second domains, is configured to receive information representing the frequency of a signal generated by the oscillator at the frequency of the first carrier signal from the first domain, and to transmit the information to the second domain at the frequency of the clock signal. The frequency matching circuit includes a FIFO register configured to receive information representing the frequency of the signal generated by the oscillator as input from the first domain of the phase-locked loop, and to output information representing the frequency of the signal generated by the oscillator to the second domain of the phase-locked loop. The FIFO register is timed at the input by the first carrier signal and at the output by the clock signal.

13. The apparatus of claim 12, wherein the counter divider comprises: The first series of D flip-flops, each of which is mounted as a frequency divider, is used to divide the frequency of the signal generated by the oscillator to obtain the second carrier signal and the clock signal; as well as The second series of D flip-flops, each receiving a signal inverted relative to the first carrier signal as a clock, and taking a signal taken from the same stage of the first series of D flip-flops as a clock as an input, and generating a count value at the output as information representing the frequency of the signal generated by the oscillator.

14. The apparatus of claim 12, wherein the second domain comprises: An accumulator is configured to generate an output value by accumulating a value equal to the factor at each clock stroke of the first carrier signal; A frequency comparator and a phase-shift adder are located between the signal generated by the oscillator and the first carrier signal; as well as A loop filter is connected to the comparator output via the phase-shift adder.

15. The apparatus of claim 14, wherein the second domain further comprises a Σ-Δ modulation circuit connected to the output of the loop filter and allowing control of the oscillator.

16. The apparatus of claim 12, wherein the FIFO register comprises: A Gray code counter is configured to count each clock stroke of the first carrier signal; A multiplexer has an input configured to receive information at the input of the FIFO register representing the frequency of a signal generated by the oscillator; Select an input and connect it to the output of the Gray code counter; And multiple outputs, which can be selected based on the value of the Gray code counter received from the selection input; Multiple registers, timed by the first carrier signal, and each register having an input connected to a given output of the multiplexer, so as to be able to store information representing the frequency of the signal generated by the oscillator at each clock stroke of the first carrier signal; At least one register, timed by the clock signal, is configured to receive a value from the Gray code counter; as well as A multiplexer has: an input connected to each of the plurality of registers; a selection input connected to at least one of the registers; and an output that allows information related to the frequency of a signal generated by the oscillator to be transmitted at the output of the FIFO register.

17. The apparatus of claim 16, wherein the frequency matching circuit further comprises a D flip-flop, the D flip-flop being timed by the first carrier signal and having: an input configured to receive information relating to the frequency of a signal generated by the oscillator from the first domain; and an output configured to transmit the information at an input to the FIFO register.

18. The apparatus of claim 14, wherein the first carrier signal has a carrier frequency on the order of 13.56 MHz, the oscillator is configured to transmit a frequency signal on the order of 868 MHz, the counter divider is configured to divide the frequency of the signal generated by the oscillator by 64, and the accumulator is configured to accumulate a value equal to 64 at each clock stroke of the first carrier signal.

19. The apparatus of claim 12, wherein the synchronization circuit further comprises a frequency-locked phase-locked loop, the frequency-locked phase-locked loop comprising: A first domain includes: a digitally controlled oscillator configured to generate a signal of a given frequency; and a first circuit configured to generate information representing the frequency of the signal generated by the oscillator, the first domain being timed according to a reference clock signal; The second domain includes a second circuit configured to digitally compare the frequency of a signal generated by the oscillator with the frequency of the first carrier signal, and to control the oscillator based on the result of the comparison, the second domain being timed by the clock signal; and A frequency matching circuit, located between the first domain and the second domain, is configured to: receive information from the first domain representing the frequency of a signal generated by the oscillator at the frequency of a signal generated by an internal reference oscillator, and transmit the information to the second domain at the frequency of the clock signal.

20. The apparatus of claim 16, further comprising a token generation circuit configured to generate a token signal whenever the value of the Gray code counter changes, wherein each element of the second field is implemented when the token signal is generated.

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