Safe power-on initialization methods, devices, equipment and storage media

Abstract

This invention belongs to the field of automotive display screen technology and discloses a safe power-on initialization method, apparatus, device, and storage medium. The method includes: configuring safety parameters of control pins in the timing control chip according to preset power-on requirements when the timing control chip begins power-on initialization; verifying each safety parameter of the control pins to determine whether each safety parameter is in a normal state; determining that the timing control chip has completed power-on initialization when all safety parameters of the control pins are in a normal state; reading the initialization status data of the timing control chip; and determining that the power-on initialization of the timing control chip is normal when the initialization status data matches the preset initialization status data, and then starting video transmission of the automotive display screen. Through the above method, safety verification is performed during chip power-on initialization to ensure normal chip power-on and to identify potential faults during the initialization process, avoiding problems such as yellow screens or black screens when the display screen is turned on, thus ensuring functional safety.

Description

Technical Field

[0001] This invention relates to the field of vehicle display technology, and in particular to a safe power-on initialization method, apparatus, device, and storage medium. Background Technology

[0002] OLED (Organic Light-Emitting Diode) displays are widely used in automotive displays and are highly sought after by customers. However, OLED displays occasionally exhibit issues such as yellow screens, black screens, and a bright line appearing upon power-on. The root cause of these problems is the initialization failure of the OLED display's TCON (Timing Controller) chip, or the initialization timing not meeting the chip's requirements. Currently, power-on is typically performed according to the TCON chip specifications, but safety checks are not performed on the power-on timing, making it impossible to identify anomalies during the power-on initialization process. This causes these anomalies to become potential faults, failing to meet functional requirements.

[0003] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The main objective of this invention is to provide a safe power-on initialization method, apparatus, device, and storage medium, aiming to solve the technical problem in the prior art that no safety verification is performed during power-on initialization, making it impossible to identify power-on initialization anomalies and affecting functional safety.

[0005] To achieve the above objectives, the present invention provides a safe power-on initialization method, the method comprising the following steps:

[0006] When the timing control chip starts power-on initialization, the safety parameters of the control pins in the timing control chip are configured according to the preset power-on requirements. The preset power-on requirements include at least a preset default level, a preset control level, a preset delay time, and a preset power-on sequence. The safety parameters include at least a default level, a control level, a delay time, and a power-on sequence.

[0007] Obtain the current safety parameters of the control pin, and verify each safety parameter of the control pin according to the preset power-on requirements and the current safety parameters to determine whether each safety parameter of the control pin is in a normal state;

[0008] When all safety parameters of the control pin are in normal condition, it is determined that the timing control chip has completed power-on initialization, and the initialization status data of the timing control chip is read.

[0009] When the initialization status data matches the preset initialization status data, it is determined that the timing control chip is powered on and initialized normally, and the video transmission of the vehicle display screen is started.

[0010] Optionally, the current safety parameters include the current default level, current control level, current delay time, and current power-on sequence. The step of obtaining the current safety parameters of the control pin, and verifying each safety parameter of the control pin according to the preset power-on requirements and the current safety parameters to determine whether each safety parameter of the control pin is in a normal state, includes:

[0011] Obtain the current default level of the control pin, compare the current default level with the preset default level, and determine that the default level of the control pin is in a normal state when the current default level matches the preset default level.

[0012] Obtain the current power-on sequence of the control pin, compare the current power-on sequence with the preset power-on sequence, and determine that the power-on sequence of the control pin is in a normal state when the current power-on sequence matches the preset power-on sequence.

[0013] The current control level of the control pin is obtained, and the current control level is compared with the preset control level. When the current control level meets the preset control level, the control level of the control pin is determined to be in a normal state.

[0014] The current delay time of the control pin is obtained, and the current delay time is compared with the preset delay time. When the current delay time meets the preset delay time, it is determined that the delay time of the control pin is in a normal state.

[0015] Optionally, obtaining the current control level of the control pin includes:

[0016] The configuration output count is obtained. When the configuration output count is less than or equal to a preset configuration count threshold, after a preset readback period, the current control level of the control pin is read and the configuration output count is updated.

[0017] After obtaining the number of configuration outputs, the process also includes:

[0018] When the number of configured outputs exceeds the preset configuration number threshold, an abnormal control level is identified as the current fault type, and fault information is generated and reported based on the current fault type.

[0019] Optionally, after obtaining the current default level of the control pin and comparing the current default level with the preset default level, the method further includes:

[0020] When the current default level does not conform to the preset default level, the default level of the control pin is determined to be abnormal, the abnormal default level is taken as the current fault type, and fault information is generated according to the current fault type and the fault information is reported.

[0021] After obtaining the current power-on sequence of the control pins and comparing the current power-on sequence with the preset power-on sequence, the method further includes:

[0022] When the current power-on sequence does not conform to the preset power-on sequence, the power-on sequence of the control pin is determined to be abnormal, the abnormal power-on sequence is taken as the current fault type, and fault information is generated according to the current fault type and the fault information is reported.

[0023] After obtaining the current control level of the control pin and comparing the current control level with the preset control level, the method further includes:

[0024] When the current control level does not conform to the preset control level, the control level of the control pin is determined to be abnormal, the abnormal control level is taken as the current fault type, and fault information is generated and reported according to the current fault type.

[0025] After obtaining the current delay time of the control pin and comparing the current delay time with the preset delay time, the method further includes:

[0026] When the current delay time does not conform to the preset delay time, the delay time of the control pin is determined to be abnormal, the abnormal delay time is taken as the current fault type, and fault information is generated according to the current fault type and the fault information is reported.

[0027] Optionally, after reading the initialization state data of the timing control chip, the method further includes:

[0028] When the initialization state data does not conform to the preset initialization state data, it is determined that the timing control chip power-on initialization is abnormal, and the initialization abnormality count is updated;

[0029] When the number of initialization exceptions exceeds the initialization exception count threshold, the chip initialization exception is taken as the current fault type, and fault information is generated and reported based on the current fault type.

[0030] Optionally, after determining that the timing control chip's power-on initialization is abnormal and updating the initialization abnormality count when the initialization state data does not conform to the preset initialization state data, the method further includes:

[0031] When the number of initialization exceptions is less than or equal to the initialization exception threshold, the timing control chip is reset and the timing control chip is re-initialized upon power-on. Then, the process returns to the step of configuring the safety parameters of the control pins in the timing control chip according to the preset power-on requirements when the timing control chip starts power-on initialization.

[0032] Optionally, after activating video transmission on the vehicle-mounted display screen, the method further includes:

[0033] After successfully initiating video transmission, the fault pin level of the timing control chip is monitored.

[0034] When the fault pin level of the timing control chip meets the preset fault level, the timing control chip is determined to be faulty, and the chip fault count is updated.

[0035] When the number of chip anomalies exceeds the chip anomaly threshold, the chip anomaly is identified as the current fault type, and fault information is generated and reported based on the current fault type.

[0036] Furthermore, to achieve the above objectives, the present invention also proposes a safe power-on initialization device, the safe power-on initialization device comprising:

[0037] The configuration module is used to configure the safety parameters of the control pins in the timing control chip according to preset power-on requirements when the timing control chip starts power-on initialization. The preset power-on requirements include preset default level, preset control level, preset delay time and preset power-on sequence. The safety parameters include default level, control level, delay time and power-on sequence.

[0038] The verification module is used to obtain the current safety parameters of the control pin, and verify each safety parameter of the control pin according to the preset power-on requirements and the current safety parameters to determine whether each safety parameter of the control pin is in a normal state.

[0039] The verification module is also used to determine that the timing control chip has completed power-on initialization and to read the initialization status data of the timing control chip when all safety parameters of the control pin are in normal condition.

[0040] The verification module is also used to determine that the timing control chip is powered on and initialized normally when the initialization status data matches the preset initialization status data, and to enable video transmission of the vehicle display screen.

[0041] Furthermore, to achieve the above objectives, the present invention also proposes a safe power-on initialization device, which includes: a memory, a processor, and a safe power-on initialization program stored in the memory and executable on the processor. The safe power-on initialization program is configured to implement the steps of the safe power-on initialization method as described above.

[0042] In addition, to achieve the above objectives, the present invention also proposes a storage medium storing a safe power-on initialization program, which, when executed by a processor, implements the steps of the safe power-on initialization method as described above.

[0043] In this invention, when the timing control chip begins power-on initialization, safety parameters of the control pins in the timing control chip are configured according to preset power-on requirements. Each safety parameter of the control pin is verified to determine if it is in a normal state. When all safety parameters of the control pins are in a normal state, the timing control chip is considered to have completed power-on initialization. The initialization status data of the timing control chip is read. If the initialization status data matches the preset initialization status data, the power-on initialization of the timing control chip is considered normal, and video transmission of the vehicle display screen is enabled. Compared to the traditional TCON chip fault detection mechanism, which does not perform safety verification on the power-on sequence and cannot identify abnormal faults occurring during power-on initialization, this invention performs safety verification on the default level, control level, delay time, and power-on sequence during the TCON chip's power-on initialization process. This ensures normal chip power-on and can identify potential faults during initialization, preventing abnormal phenomena such as yellow or black screens during display startup and ensuring functional safety. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the structure of the safe power-on initialization device for the hardware operating environment involved in the embodiments of the present invention;

[0045] Figure 2 This is a flowchart illustrating the first embodiment of the safe power-on initialization method of the present invention;

[0046] Figure 3 This is a schematic diagram of the parameter verification process of an embodiment of the safe power-on initialization method of the present invention;

[0047] Figure 4 This is a schematic diagram of the initialization state verification process of an embodiment of the safe power-on initialization method of the present invention;

[0048] Figure 5 This is a flowchart illustrating the second embodiment of the safe power-on initialization method of the present invention;

[0049] Figure 6This is a structural block diagram of the first embodiment of the safe power-on initialization device of the present invention.

[0050] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0051] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0052] Reference Figure 1 , Figure 1 This is a schematic diagram of the secure power-on initialization device structure for the hardware operating environment involved in the embodiments of the present invention.

[0053] like Figure 1 As shown, the safe power-on initialization device may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen or an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wireless-Fidelity (Wi-Fi) interface). The memory 1005 may be a high-speed random access memory (RAM) or a stable non-volatile memory (NVM), such as a disk drive. The memory 1005 may also optionally be a storage device independent of the aforementioned processor 1001.

[0054] Those skilled in the art will understand that Figure 1 The structure shown does not constitute a limitation on the safety power-on initialization device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0055] like Figure 1 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a network communication module, a user interface module, and a secure power-on initialization program.

[0056] exist Figure 1In the safety power-on initialization device shown, the network interface 1004 is mainly used for data communication with the network server; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and the memory 1005 in the safety power-on initialization device of the present invention can be set in the safety power-on initialization device, and the safety power-on initialization device calls the safety power-on initialization program stored in the memory 1005 through the processor 1001 and executes the safety power-on initialization method provided in the embodiment of the present invention.

[0057] This invention provides a safe power-on initialization method, referring to... Figure 2 , Figure 2 This is a flowchart illustrating the first embodiment of a safe power-on initialization method according to the present invention.

[0058] In this embodiment, the safe power-on initialization method includes the following steps:

[0059] Step S10: When the timing control chip starts power-on initialization, configure the safety parameters of the control pins in the timing control chip according to the preset power-on requirements. The preset power-on requirements include at least a preset default level, a preset control level, a preset delay time, and a preset power-on sequence. The safety parameters include at least a default level, a control level, a delay time, and a power-on sequence.

[0060] It should be noted that the execution subject in this embodiment is a safe power-on initialization device, which is equipped with a safe power-on initialization program. By running the safe power-on initialization program, the safe power-on initialization of the TCON chip is realized.

[0061] It is understood that the timing control chip described in this embodiment is the TCON chip, and the control pins refer to the control pins in the TCON chip. In this embodiment, the control pins are VDD, RESET, EVDD (positive voltage), and EVSS (negative voltage). The safety parameters refer to the parameters related to functional safety during the power-on initialization process of each control pin. In this embodiment, the safety parameters include the default level, control level, delay time, and power-on sequence. Other parameters can be added according to actual conditions, and this embodiment does not impose any restrictions on this. Among them, the power-on sequence and delay time of the chip have stricter requirements. Abnormal control will cause the chip initialization to fail, resulting in abnormal chip operation. Generally, the default level is 0, and the control level has two forms: high level (1) and low level (0). The delay time is in the millisecond range. The preset power-on requirements refer to the power-on requirements of the TCON chip, which can be considered as the setting of safety parameters, including preset default level, preset control level, preset delay time, and preset power-on sequence. The preset default level, preset control level, and preset delay time are the values ​​that the default level, control level, and delay time of each control pin need to maintain during the power-on initialization process. For example, the preset default level is 0, the preset control level is high level 1, and the preset delay time is 1ms. This embodiment does not impose any restrictions on this. The preset power-on sequence is the order of each control pin during the power-on initialization process. In this embodiment, the preset power-on sequence is VDD, RESET, EVDD, and EVSS.

[0062] In the specific implementation, according to the power-on requirements of the TCON chip, the default level, control level, delay time, and power-on sequence are configured for each control pin (VDD, RESET, EVDD, EVSS) in the chip.

[0063] Step S20: Obtain the current safety parameters of the control pin, and verify each safety parameter of the control pin according to the preset power-on requirements and the current safety parameters to determine whether each safety parameter of the control pin is in a normal state.

[0064] It should be understood that the current safety parameters refer to the actual safety parameters, including the current default level, current control level, current delay time, and current power-on sequence, i.e., the actual default level, actual control level, actual delay time, and actual power-on sequence. After configuring the safety parameters (default level, control level, delay time, and power-on sequence) for the control pins, the actual values ​​of the default level, control level, and delay time may not be the configured values ​​(preset default level, preset control level, and preset delay time), and the actual power-on sequence may also not be the preset power-on sequence. Therefore, this embodiment performs a safety check on these safety parameters after configuration to determine whether any abnormal situations have occurred.

[0065] It should be noted that the safety parameters of each control pin need to be checked for safety, and each safety parameter needs to be verified separately.

[0066] In practice, by comparing the actual security parameters with the configured security parameters, security checks are performed on each security parameter to confirm whether each security parameter is in a normal or abnormal state.

[0067] Further, step S20 includes:

[0068] Obtain the current default level of the control pin, compare the current default level with the preset default level, and determine that the default level of the control pin is in a normal state when the current default level matches the preset default level.

[0069] Understandably, when controlling the pin output level according to chip requirements, it is necessary to verify the chip's default level to prevent abnormal chip power-on timing due to cross-current between chips or other anomalies. The statement that the current default level conforms to the preset default level means that the current default level is the same as the preset default level.

[0070] It should be understood that, after obtaining the current default level of the control pin and comparing the current default level with the preset default level, the method further includes: when the current default level does not conform to the preset default level, determining that the default level of the control pin is abnormal, taking the default level abnormality as the current fault type, generating fault information according to the current fault type, and reporting the fault information.

[0071] It should be noted that the current fault type refers to the type of fault that is currently occurring. In this embodiment, if a default level abnormality occurs, the current fault type is considered to be a default level abnormality. The fault information refers to the feedback related to the fault, which includes at least the current fault type and may also include other relevant information / data. This embodiment does not impose any restrictions on this. The statement that the current default level does not conform to the preset default level means that the current default level is different from the preset default level.

[0072] In the specific implementation, the actual default level is compared with the preset default level. If the actual default level of each control pin is the same as the preset default level, the default level of the TCON chip is considered to be normal. Then, the power-on sequence is checked. If there is a pin among these control pins whose actual default level is different from the preset default level, the default level of that pin is abnormal, and the fault type is reported.

[0073] Obtain the current power-on sequence of the control pin, compare the current power-on sequence with the preset power-on sequence, and determine that the power-on sequence of the control pin is in a normal state when the current power-on sequence matches the preset power-on sequence.

[0074] It is understood that the current power-on sequence conforming to the preset power-on sequence means that the current power-on sequence is the same as the preset power-on sequence. In this embodiment, the power-on sequence of all control pins must be the same as the preset power-on sequence, namely VDD, RESET, EVDD, EVSS.

[0075] It should be understood that, after obtaining the current power-on sequence of the control pin and comparing the current power-on sequence with the preset power-on sequence, the method further includes: when the current power-on sequence does not conform to the preset power-on sequence, determining that the power-on sequence of the control pin is abnormal, taking the abnormal power-on sequence as the current fault type, generating fault information based on the current fault type, and reporting the fault information.

[0076] It should be noted that in this embodiment, if an abnormal power-on sequence occurs, the current fault type is considered to be an abnormal power-on sequence. The statement that the current power-on sequence does not conform to the preset power-on sequence means that the current power-on sequence is different from the preset power-on sequence.

[0077] In the specific implementation, the actual power-on sequence is compared with the preset power-on sequence. If the actual power-on sequence of each control pin is the same as the preset power-on sequence, the power-on sequence of the TCON chip is considered to be normal. Then, the control level is checked. If there is a pin among these control pins whose actual power-on sequence is different from the preset power-on sequence, the power-on sequence of that pin is abnormal, and the fault type is reported.

[0078] The current control level of the control pin is obtained, and the current control level is compared with the preset control level. When the current control level meets the preset control level, it is determined that the control level of the control pin is in a normal state.

[0079] It is understood that the current control level conforming to the preset control level means that the current control level is the same as the preset control level. Obtaining the current control level of the control pin includes: obtaining the configuration output count; when the configuration output count is less than or equal to a preset configuration count threshold, after a preset readback period, reading the current control level of the control pin and updating the configuration output count.

[0080] It should be understood that the configured output count refers to the number of times the level is output according to the preset control level, and the preset configuration count threshold refers to the set output count threshold, such as 5 times, which can be adjusted according to actual needs. This embodiment does not limit this. The preset readback period refers to the time period for reading back the level value after outputting the control level, such as 1ms, which can be adjusted according to actual needs. This embodiment does not limit this. Usually, the required preset readback period is determined by setting a readback timer. The readback timer is started at the same time as outputting the control level. When the readback timer exceeds the preset readback period, the current control level is compared with the preset control level, and the readback timer is turned off. After obtaining the configured output count, the method further includes: when the configured output count is greater than the preset configuration count threshold, the control level abnormality is taken as the current fault type, and fault information is generated according to the current fault type and the fault information is reported.

[0081] It should be noted that the output control level is configured according to the chip requirements, and a 1ms timer is started to read back and compare the configured output level (preset control level). If the configured output level (preset control level) is found to be inconsistent with the read-back level (current control level), the output is reconfigured. If the configured output is abnormal 5 times consecutively, the current fault type is considered to be a control level abnormality, and it is reported. In this embodiment, the preset control level, that is, the configured output level, is 1 (high level).

[0082] It is understood that, after obtaining the current control level of the control pin and comparing the current control level with the preset control level, the method further includes: when the current control level does not conform to the preset control level, determining that the control level of the control pin is abnormal, taking the abnormal control level as the current fault type, generating fault information based on the current fault type, and reporting the fault information.

[0083] It should be understood that, in this embodiment, if an abnormal control level occurs, the type of fault is considered to be an abnormal control level. The statement that the current control level does not conform to the preset control level means that the current control level is different from the preset control level.

[0084] In the specific implementation, the actual control level is compared with the preset control level. If the actual control level of each control pin is the same as the preset control level, the control level of the TCON chip is considered to be normal. Then, the delay time is checked. If there is a pin among these control pins whose actual control level is different from the preset control level, the control level of that pin is abnormal, and the fault type is reported.

[0085] The current delay time of the control pin is obtained, and the current delay time is compared with the preset delay time. When the current delay time meets the preset delay time, it is determined that the delay time of the control pin is in a normal state.

[0086] It should be noted that the current delay time conforming to the preset delay time means that the current control delay time is the same as the preset delay time. After obtaining the current delay time of the control pin and comparing it with the preset delay time, the process further includes: when the current delay time does not conform to the preset delay time, determining that the delay time of the control pin is abnormal, classifying the abnormal delay time as the current fault type, generating fault information based on the current fault type, and reporting the fault information.

[0087] It is understood that in this embodiment, if an abnormal delay time occurs, the current fault type is considered to be an abnormal delay time. The current delay time not conforming to the preset delay time means that the current delay time is different from the preset delay time. In this embodiment, the preset delay times between each control pin are: 20ms between VDD and RESET, 1.1ms between RESET and EVDD, and 7ms between EVSS and EVDD.

[0088] In the specific implementation, the actual delay time is compared with the preset delay time. If the actual delay time of each control pin is the same as the preset delay time, the delay time of the TCON chip is considered normal. If there is a pin among these control pins whose actual delay time is different from the preset delay time, the delay time of that pin is abnormal, and the fault type is reported.

[0089] like Figure 3 The parameter verification process diagram shown first confirms whether the default level is correct. If so, it then confirms whether the power-on sequence is correct; otherwise, it reports a fault. If the power-on sequence is correct, it then confirms whether the control level is correct; otherwise, it reports a fault type. When confirming whether the control level is correct, it configures the output control level and starts a 1ms timer to read back and compare the configured output level. If the configured output level is inconsistent with the read-back level, it is reconfigured. If the configured output is abnormal 5 times consecutively, a fault is reported. If the number of configured outputs does not exceed 5 times, the read-back comparison after configuration is performed again. If the set output is consistent with the read-back level, it then confirms whether the delay time is correct. If the delay time is correct, the power-on initialization is considered complete; otherwise, a fault is reported.

[0090] Step S30: When all safety parameters of the control pin are in normal condition, determine that the timing control chip has completed power-on initialization and read the initialization status data of the timing control chip.

[0091] It should be understood that if all safety parameters of all pins are normal, the power-on initialization is considered complete, and the next step can be taken to further assess the power-on initialization status.

[0092] It should be noted that the initialization status data refers to the value of the TCON chip initialization register, which is used to determine whether the power-on initialization was successful.

[0093] Step S40: When the initialization status data matches the preset initialization status data, determine that the timing control chip is powered on and initialized normally, and start the video transmission of the vehicle display screen.

[0094] It is understood that the preset initialization state data refers to the value of the initialization register when the power-on initialization is successful. By comparing the initialization state data with the preset initialization state data, it can be determined whether the initialization state data is the same as the preset initialization state data, that is, whether the initialization state data conforms to the preset initialization state data. For example, if the preset initialization state data is 1, it is considered that the initialization state data conforms to the preset initialization state data, and the chip power-on initialization is successful. If the initial state is not 1, it is considered that the initialization state data does not conform to the preset initialization state data, and the chip power-on initialization is unsuccessful, which is also known as an abnormality / fault.

[0095] Furthermore, after reading the initialization status data of the timing control chip, the method further includes: when the initialization status data does not conform to the preset initialization status data, determining that the timing control chip power-on initialization is abnormal, and updating the initialization abnormality count; when the initialization abnormality count is greater than the initialization abnormality count threshold, taking the chip initialization abnormality as the current fault type, generating fault information according to the current fault type, and reporting the fault information.

[0096] It should be understood that the initialization exception count refers to the number of times a power-on initialization exception is detected. Each time an exception is detected, the initialization exception count is incremented by 1. The initialization exception count threshold refers to the maximum set number of initialization exceptions, which can also be considered a threshold for the number of chip resets, for example, 5 times. This can be adjusted according to actual needs, and this embodiment does not impose any restrictions on it. When a power-on initialization exception occurs, it is possible that resetting and re-initializing the chip will succeed. Therefore, to ensure the accuracy of fault diagnosis, this embodiment sets an initialization exception count threshold. Only when the initialization exception count exceeds the threshold is the chip initialization process considered to have truly encountered an exception.

[0097] Furthermore, after determining that the timing control chip is abnormal during power-on initialization and updating the number of initialization errors when the initialization state data does not conform to the preset initialization state data, the method further includes: when the number of initialization errors is less than or equal to the threshold number of initialization errors, resetting the timing control chip and re-initializing the timing control chip during power-on, and returning to the step of configuring the safety parameters of the control pins in the timing control chip according to the preset power-on requirements when the timing control chip starts power-on initialization.

[0098] In the specific implementation, after the TCON chip is powered on and initialized, the initialization status of the chip is read back. If an initialization abnormality is found, the TCON chip is reset and re-initialized. If an initialization abnormality is detected 5 times in a row, the fault type is reported. At this time, the TCON chip is not working properly.

[0099] like Figure 4 The diagram shows the initialization status verification process. After the TCON chip is powered on and initialized, the initialization status of the chip is read back. If an initialization abnormality is found, the TCON chip is reset and re-initialized. If an initialization abnormality is detected 5 times in a row, the fault type is reported. At this time, the TCON chip is not working properly.

[0100] In this embodiment, when the timing control chip begins power-on initialization, the safety parameters of the control pins in the timing control chip are configured according to preset power-on requirements. Each safety parameter of the control pin is verified to determine if it is in a normal state. When all safety parameters of the control pin are in a normal state, the timing control chip is considered to have completed power-on initialization. The initialization status data of the timing control chip is read. If the initialization status data matches the preset initialization status data, the power-on initialization of the timing control chip is considered normal, and video transmission of the vehicle display screen is enabled. Compared to the traditional TCON chip fault detection mechanism, which does not perform safety verification on the power-on sequence and cannot identify abnormal faults occurring during power-on initialization, this embodiment performs safety verification on the default level, control level, delay time, and power-on sequence during the TCON chip's power-on initialization process. This ensures normal chip power-on and can identify potential faults during initialization, preventing abnormal phenomena such as yellow or black screens during display startup and ensuring functional safety.

[0101] Reference Figure 5 , Figure 5 This is a flowchart illustrating a second embodiment of a safe power-on initialization method according to the present invention.

[0102] Based on the above embodiments, in this embodiment, after step S40, the method further includes:

[0103] Step S501: After successfully starting video transmission, monitor the fault pin level of the timing control chip.

[0104] Step S502: When the fault pin level of the timing control chip meets the preset fault level, the timing control chip is determined to be abnormal, and the chip abnormality count is updated.

[0105] It should be noted that after the TCON chip successfully powers on and initializes, and the video is turned on, the system will monitor / monitor for faults in the vehicle display screen. Faults in the vehicle display screen may be due to video anomalies or chip malfunctions. Detecting the fault pin level of the TCON chip can determine whether the TCON chip has malfunctioned during operation. The vehicle display screen described in this embodiment is an OLED display screen.

[0106] It is understood that the preset fault level refers to the value of the fault pin level when the chip malfunctions. The fault pin level conforming to the preset fault level means that the fault pin level is the same as the preset fault level. When the fault pin level is the same as the preset fault level, the chip is considered to be malfunctioning. When the fault pin level is different from the preset fault level, the chip is considered to be working normally.

[0107] Step S503: When the number of chip malfunctions exceeds the chip malfunction threshold, the chip malfunction is taken as the current fault type, and fault information is generated and reported according to the current fault type.

[0108] It should be understood that the number of chip anomalies refers to the number of times the chip experiences an anomaly during operation, and the chip anomaly threshold refers to the maximum number of times the chip experiences an anomaly during operation, which can also be considered as the threshold for the number of chip resets, for example, 5 times. This can be adjusted according to actual needs, and this embodiment does not impose any restrictions on it.

[0109] It should be noted that, after determining that the timing control chip is abnormal and updating the chip abnormality count when the fault pin level of the timing control chip meets the preset fault level, the method further includes: resetting the timing control chip when the chip abnormality count is less than or equal to the chip abnormality count threshold.

[0110] It is understandable that when an abnormality occurs during chip operation, it may be able to work normally after a reset. Therefore, this embodiment sets an initialization abnormality count threshold. Only when the number of chip abnormalities exceeds the chip abnormality count threshold is it considered that an abnormality has actually occurred during chip operation.

[0111] In the specific implementation, after the TCON is successfully initialized and the video is turned on, the fault pin level of the TCON chip is detected. If the fault pin level is the same as the preset fault level, it is determined that the TCON chip is abnormal, and a reset operation is performed on the TCON chip. If the abnormal fault cannot be recovered after 5 consecutive resets, the fault type is reported.

[0112] In this embodiment, after successful video transmission, the fault pin level of the timing control chip is monitored. When the fault pin level of the timing control chip meets a preset fault level, the timing control chip is determined to be faulty, and the chip fault count is updated. When the chip fault count exceeds a chip fault count threshold, the chip fault is identified as the current fault type, and fault information is generated and reported based on the current fault type. This embodiment monitors front-end video faults and chip faults during operation after successful TCON initialization and video transmission, ensuring functional safety.

[0113] Furthermore, this embodiment of the invention also proposes a storage medium storing a safe power-on initialization program, which, when executed by a processor, implements the steps of the safe power-on initialization method described above.

[0114] Reference Figure 6 , Figure 6 This is a structural block diagram of the first embodiment of the safe power-on initialization device of the present invention.

[0115] like Figure 6 As shown, the safe power-on initialization device proposed in this embodiment of the invention includes:

[0116] Configuration module 10 is used to configure the safety parameters of the control pins in the timing control chip according to preset power-on requirements when the timing control chip starts power-on initialization. The preset power-on requirements include preset default level, preset control level, preset delay time and preset power-on sequence. The safety parameters include default level, control level, delay time and power-on sequence.

[0117] The verification module 20 is used to obtain the current safety parameters of the control pin, and verify each safety parameter of the control pin according to the preset power-on requirements and the current safety parameters to determine whether each safety parameter of the control pin is in a normal state.

[0118] The verification module 20 is also used to determine that the timing control chip has completed power-on initialization and read the initialization status data of the timing control chip when all safety parameters of the control pin are in normal state.

[0119] The verification module 20 is also used to determine that the timing control chip is powered on and initialized normally when the initialization status data matches the preset initialization status data, and to enable video transmission of the vehicle display screen.

[0120] In this embodiment, when the timing control chip begins power-on initialization, the safety parameters of the control pins in the timing control chip are configured according to preset power-on requirements. Each safety parameter of the control pin is verified to determine if it is in a normal state. When all safety parameters of the control pin are in a normal state, the timing control chip is considered to have completed power-on initialization. The initialization status data of the timing control chip is read. If the initialization status data matches the preset initialization status data, the power-on initialization of the timing control chip is considered normal, and video transmission of the vehicle display screen is enabled. Compared to the traditional TCON chip fault detection mechanism, which does not perform safety verification on the power-on sequence and cannot identify abnormal faults occurring during power-on initialization, this embodiment performs safety verification on the default level, control level, delay time, and power-on sequence during the TCON chip's power-on initialization process. This ensures normal chip power-on and can identify potential faults during initialization, preventing abnormal phenomena such as yellow or black screens during display startup and ensuring functional safety.

[0121] In one embodiment, the verification module 20 is further configured to obtain the current default level of the control pin, compare the current default level with the preset default level, and determine that the default level of the control pin is in a normal state when the current default level matches the preset default level.

[0122] Obtain the current power-on sequence of the control pin, compare the current power-on sequence with the preset power-on sequence, and determine that the power-on sequence of the control pin is in a normal state when the current power-on sequence matches the preset power-on sequence.

[0123] The current control level of the control pin is obtained, and the current control level is compared with the preset control level. When the current control level meets the preset control level, the control level of the control pin is determined to be in a normal state.

[0124] The current delay time of the control pin is obtained, and the current delay time is compared with the preset delay time. When the current delay time meets the preset delay time, it is determined that the delay time of the control pin is in a normal state.

[0125] In one embodiment, the verification module 20 is further configured to obtain the number of configuration outputs, and when the number of configuration outputs is less than or equal to a preset configuration output threshold, after a preset readback period, read the current control level of the control pin and update the number of configuration outputs;

[0126] When the number of configured outputs exceeds the preset configuration number threshold, an abnormal control level is identified as the current fault type, and fault information is generated and reported based on the current fault type.

[0127] In one embodiment, the verification module 20 is further configured to determine that the default level of the control pin is abnormal when the current default level does not conform to the preset default level, take the default level abnormality as the current fault type, generate fault information according to the current fault type, and report the fault information;

[0128] When the current power-on sequence does not conform to the preset power-on sequence, the power-on sequence of the control pin is determined to be abnormal, the abnormal power-on sequence is taken as the current fault type, and fault information is generated according to the current fault type and the fault information is reported.

[0129] When the current control level does not conform to the preset control level, the control level of the control pin is determined to be abnormal, the abnormal control level is taken as the current fault type, and fault information is generated and reported according to the current fault type.

[0130] When the current delay time does not conform to the preset delay time, the delay time of the control pin is determined to be abnormal, the abnormal delay time is taken as the current fault type, and fault information is generated according to the current fault type and the fault information is reported.

[0131] In one embodiment, the verification module 20 is further configured to determine that the timing control chip power-on initialization is abnormal when the initialization state data does not conform to the preset initialization state data, and update the number of initialization abnormalities;

[0132] When the number of initialization exceptions exceeds the initialization exception count threshold, the chip initialization exception is taken as the current fault type, and fault information is generated and reported based on the current fault type.

[0133] In one embodiment, the verification module 20 is further configured to reset the timing control chip and re-initialize the timing control chip when the number of initialization exceptions is less than or equal to the initialization exception number threshold, and return to the step of configuring the safety parameters of the control pins in the timing control chip according to the preset power-on requirements when the timing control chip starts power-on initialization.

[0134] In one embodiment, the safe power-on initialization device further includes a monitoring module 30, which is used to monitor the fault pin level of the timing control chip after successful video transmission.

[0135] When the fault pin level of the timing control chip meets the preset fault level, the timing control chip is determined to be faulty, and the chip fault count is updated.

[0136] When the number of chip anomalies exceeds the chip anomaly threshold, the chip anomaly is identified as the current fault type, and fault information is generated and reported based on the current fault type.

[0137] It should be understood that the above are merely illustrative examples and do not constitute any limitation on the technical solutions of the present invention. In specific applications, those skilled in the art can make settings as needed, and the present invention does not impose any restrictions on this.

[0138] It should be noted that the workflow described above is merely illustrative and does not limit the scope of protection of this invention. In practical applications, those skilled in the art can select some or all of the workflow to achieve the purpose of this embodiment according to actual needs, and no restrictions are imposed here.

[0139] In addition, for technical details not described in detail in this embodiment, please refer to the safe power-on initialization method provided in any embodiment of the present invention, which will not be repeated here.

[0140] Furthermore, it should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0141] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0142] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as read-only memory (ROM) / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0143] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A safe power-on initialization method, characterized in that, The safe power-on initialization method includes: When the timing control chip starts power-on initialization, the safety parameters of the control pins in the timing control chip are configured according to the preset power-on requirements. The preset power-on requirements include at least a preset default level, a preset control level, a preset delay time, and a preset power-on sequence. The safety parameters include at least a default level, a control level, a delay time, and a power-on sequence. Obtain the current default level of the control pin, compare the current default level with the preset default level, and determine that the default level of the control pin is in a normal state when the current default level matches the preset default level. Obtain the current power-on sequence of the control pin, compare the current power-on sequence with the preset power-on sequence, and determine that the power-on sequence of the control pin is in a normal state when the current power-on sequence matches the preset power-on sequence. The current control level of the control pin is obtained, and the current control level is compared with the preset control level. When the current control level meets the preset control level, the control level of the control pin is determined to be in a normal state. The current delay time of the control pin is obtained, and the current delay time is compared with the preset delay time. When the current delay time meets the preset delay time, it is determined that the delay time of the control pin is in a normal state. When all safety parameters of the control pin are in normal condition, it is determined that the timing control chip has completed power-on initialization, and the initialization status data of the timing control chip is read. When the initialization state data matches the preset initialization state data, it is determined that the timing control chip is powered on and initialized normally, and the video transmission of the vehicle display screen is started. The step of obtaining the current control level of the control pin includes: obtaining the number of configuration outputs; when the number of configuration outputs is less than or equal to a preset configuration output threshold, after a preset readback period, reading the current control level of the control pin and updating the number of configuration outputs; when the number of configuration outputs is greater than the preset configuration output threshold, taking the abnormal control level as the current fault type, generating fault information according to the current fault type, and reporting the fault information.

2. The method as described in claim 1, characterized in that, After obtaining the current default level of the control pin and comparing the current default level with the preset default level, the method further includes: When the current default level does not conform to the preset default level, the default level of the control pin is determined to be abnormal, the abnormal default level is taken as the current fault type, and fault information is generated according to the current fault type and the fault information is reported. After obtaining the current power-on sequence of the control pins and comparing the current power-on sequence with the preset power-on sequence, the method further includes: When the current power-on sequence does not conform to the preset power-on sequence, the power-on sequence of the control pin is determined to be abnormal, the abnormal power-on sequence is taken as the current fault type, and fault information is generated according to the current fault type and the fault information is reported. After obtaining the current control level of the control pin and comparing the current control level with the preset control level, the method further includes: When the current control level does not conform to the preset control level, the control level of the control pin is determined to be abnormal, the abnormal control level is taken as the current fault type, and fault information is generated and reported according to the current fault type. After obtaining the current delay time of the control pin and comparing the current delay time with the preset delay time, the method further includes: When the current delay time does not conform to the preset delay time, the delay time of the control pin is determined to be abnormal, the abnormal delay time is taken as the current fault type, and fault information is generated according to the current fault type and the fault information is reported.

3. The method as described in claim 1, characterized in that, After reading the initialization state data of the timing control chip, the method further includes: When the initialization state data does not conform to the preset initialization state data, it is determined that the timing control chip power-on initialization is abnormal, and the initialization abnormality count is updated; When the number of initialization exceptions exceeds the initialization exception count threshold, the chip initialization exception is taken as the current fault type, and fault information is generated and reported based on the current fault type.

4. The method as described in claim 3, characterized in that, After determining that the timing control chip power-on initialization is abnormal when the initialization state data does not conform to the preset initialization state data, and updating the initialization abnormality count, the method further includes: When the number of initialization exceptions is less than or equal to the initialization exception threshold, the timing control chip is reset and the timing control chip is re-initialized upon power-on. Then, the process returns to the step of configuring the safety parameters of the control pins in the timing control chip according to the preset power-on requirements when the timing control chip starts power-on initialization.

5. The method according to any one of claims 1 to 4, characterized in that, After activating video transmission on the vehicle-mounted display screen, the following is also included: After successfully initiating video transmission, the fault pin level of the timing control chip is monitored. When the fault pin level of the timing control chip meets the preset fault level, the timing control chip is determined to be faulty, and the chip fault count is updated. When the number of chip anomalies exceeds the chip anomaly threshold, the chip anomaly is identified as the current fault type, and fault information is generated and reported based on the current fault type.

6. A safe power-on initialization device, characterized in that, The safe power-on initialization device includes: The configuration module is used to configure the safety parameters of the control pins in the timing control chip according to preset power-on requirements when the timing control chip starts power-on initialization. The preset power-on requirements include preset default level, preset control level, preset delay time and preset power-on sequence. The safety parameters include default level, control level, delay time and power-on sequence. The verification module is used to obtain the current safety parameters of the control pin, and verify each safety parameter of the control pin according to the preset power-on requirements and the current safety parameters to determine whether each safety parameter of the control pin is in a normal state. The verification module is also used to determine that the timing control chip has completed power-on initialization and to read the initialization status data of the timing control chip when all safety parameters of the control pin are in normal condition. The verification module is also used to determine that the timing control chip is powered on and initialized normally when the initialization state data matches the preset initialization state data, and to enable video transmission of the vehicle display screen. The verification module is further configured to obtain the current default level of the control pin, compare the current default level with the preset default level, and determine that the default level of the control pin is in a normal state when the current default level matches the preset default level. Obtain the current power-on sequence of the control pin, compare the current power-on sequence with the preset power-on sequence, and determine that the power-on sequence of the control pin is in a normal state when the current power-on sequence matches the preset power-on sequence. The current control level of the control pin is obtained, and the current control level is compared with the preset control level. When the current control level meets the preset control level, the control level of the control pin is determined to be in a normal state. The current delay time of the control pin is obtained, and the current delay time is compared with the preset delay time. When the current delay time meets the preset delay time, it is determined that the delay time of the control pin is in a normal state. The verification module is also used to obtain the number of configuration outputs; When the number of configuration outputs is less than or equal to a preset configuration output threshold, after a preset readback period, the current control level of the control pin is read and the number of configuration outputs is updated. When the number of configured outputs exceeds the preset configuration number threshold, an abnormal control level is identified as the current fault type, and fault information is generated and reported based on the current fault type.

7. A safe power-on initialization device, characterized in that, The device includes: a memory, a processor, and a secure power-on initialization program stored in the memory and executable on the processor, the secure power-on initialization program being configured to implement the steps of the secure power-on initialization method as described in any one of claims 1 to 5.

8. A storage medium, characterized in that, The storage medium stores a safe power-on initialization program, which, when executed by the processor, implements the steps of the safe power-on initialization method as described in any one of claims 1 to 5.

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