Driving circuit and its operating method and backplane

Abstract

The present application provides a driving circuit, an operating method thereof, and a backplane. The driving circuit includes a light emitting element, a control circuit, a first driving transistor, and a second driving transistor. The control circuit distinguishes display data as first sub-display data and second sub-display data according to a set ratio. The control circuit generates a first data voltage according to the first sub-display data and a second data voltage according to the second sub-display data. The first driving transistor and the second driving transistor are coupled in parallel with each other. The first driving transistor generates a first driving current to the light emitting element according to the first data voltage. The second driving transistor generates a second driving current to the light emitting element according to the second data voltage.

Description

Technical Field

[0001] This invention relates to a display device and its operating method, and more particularly to a driving circuit with high grayscale accuracy, its operating method, and a backplate. Background Technology

[0002] Driving circuits used in display devices can be implemented, for example, using wafer fabrication chips or glass-based low-temperature polysilicon (LTPS) thin-film transistor (TFT) chips. Generally, the driving circuit divides the display data into multiple sub-display data based on the display device's specifications (e.g., 8-bit). These sub-display data correspond to different gray levels and driving currents. However, the driving circuit must accurately control each gray level to have a single gray level current, requiring the voltage value corresponding to each gray level to be precise to approximately 10 millivolts (mV), increasing the control complexity. Therefore, the driving circuit cannot effectively control the magnitude of the driving current, resulting in reduced gray level accuracy. Summary of the Invention

[0003] This invention provides a driving circuit that can improve the accuracy of grayscale.

[0004] The driving circuit of this invention includes a light-emitting element, a control circuit, a first driving transistor, and a second driving transistor. The control circuit receives a light-emitting signal and a write signal. The control circuit distinguishes displayed data into first sub-display data and second sub-display data according to a set ratio. The control circuit generates a first data voltage based on the first sub-display data and a second data voltage based on the second sub-display data. The first driving transistor and the second driving transistor are connected in parallel and coupled to each other, and are also coupled to the light-emitting element and the control circuit. The first driving transistor generates a first driving current to the light-emitting element based on the first data voltage. The second driving transistor generates a second driving current to the light-emitting element based on the second data voltage.

[0005] This invention also provides an operating method for a driving circuit. The operating method includes the following steps: A control circuit distinguishes displayed data into first sub-display data and second sub-display data according to a set ratio. The control circuit generates a first data voltage based on the first sub-display data and a second data voltage based on the second sub-display data. The control circuit receives a light-emitting signal and a write signal. A first driving transistor generates a first driving current to the light-emitting element based on the first data voltage. A second driving transistor generates a second driving current to the light-emitting element based on the second data voltage. The first driving transistor and the second driving transistor are connected in parallel and coupled to each other.

[0006] This invention also provides a backplane. The backplane includes a backlight panel and a printed circuit board. The backlight panel has a plurality of the aforementioned driving circuits. The printed circuit board is coupled to the backlight panel. The printed circuit board provides light emission signals and write signals to these driving circuits.

[0007] Based on the above, the driving circuit, its operation method, and the backplane of this embodiment of the invention distinguish the displayed data into first sub-display data and second sub-display data. The driving circuit can generate corresponding data voltages based on these different sub-display data, so that the parallel-coupled driving transistors output corresponding driving currents respectively. Therefore, the driving circuit can effectively control the driving current output to the light-emitting element to improve the accuracy of grayscale.

[0008] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a back panel according to an embodiment of the present invention.

[0010] Figure 2 Based on the present invention Figure 1 A block diagram of the driving circuit shown in the embodiment.

[0011] Figure 3 Based on the present invention Figure 2 A flowchart illustrating the operation method of the driving circuit in the embodiment.

[0012] Figure 4 Based on the present invention Figure 2 A schematic diagram of the operation of the drive circuit shown in the embodiment.

[0013] Figure 5 This is a circuit diagram of a driving circuit according to an embodiment of the present invention.

[0014] Figure 6 Based on the present invention Figure 5 A schematic diagram of the operation of the drive circuit shown in the embodiment.

[0015] Figures 7A to 7B Based on the present invention Figure 6 A schematic diagram of the operation of the drive circuit shown in the embodiment.

[0016] In the attached figures, the following labels are used:

[0017] 10: Back panel

[0018] 11: Backlight

[0019] 12: Printed Circuit Board

[0020] 100, 500: Drive circuit

[0021] 110: Integrated Circuits

[0022] 111, 511: Control circuit

[0023] 120, 520: Light-emitting elements

[0024] 121-124: Light Emitting Diode

[0025] 530: Reset Circuit

[0026] 611: First control circuit

[0027] 612: Second control circuit

[0028] 613: Bias element

[0029] C1~C2: Capacitors

[0030] D1, D2: Sub-display data

[0031] DataA[n], DataB[n]: Data voltage

[0032] deltaI1, deltaI2: Driving current difference

[0033] EM[n]: Emitted signal

[0034] Ids: Output drive current

[0035] L0~L255, L0~L15, L27, L251: Grayscale data

[0036] N1~N4: Nodes

[0037] P1~P2: Period

[0038] S301~S303: Steps

[0039] t1~t3: Time

[0040] T1~T9: Transistors

[0041] TD1, TD2: Driving transistors

[0042] VDD, VSS, VREF: Reference voltages

[0043] VGH, VGL: Voltage levels

[0044] WR[n]: Write signal Detailed Implementation

[0045] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description, when appearing in different drawings, are considered to be the same or similar components. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples within the scope of the present invention's patent application.

[0046] Figure 1 This is a schematic diagram of a back panel according to an embodiment of the present invention. Please refer to... Figure 1 The backplane 10 can be used in a liquid crystal display (LCD) display device. The backplane 10 may include a backlight panel 11, a printed circuit board 12, and multiple driving circuits 100. The backlight panel 11 is coupled to the printed circuit board 12. In this embodiment, these driving circuits 100 are arranged in an array and disposed on the backlight panel 11. For ease of explanation, in... Figure 1 The label indicates a single drive circuit 100.

[0047] In this embodiment, the printed circuit board 12 can be coupled to the backlight panel 11 via a chip-on-film (COF) package. The printed circuit board 12 can provide multiple control signals (e.g., for controlling the light emission operation) to control the light emission operation. Figure 2 The light emission signal EM[n] and the write signal WR[n] are sent to each driving circuit 100.

[0048] In this embodiment, each driving circuit 100 may include an integrated circuit 110 and a plurality of light-emitting diodes 121-124. The integrated circuit 110 is coupled to the light-emitting diodes 121-124. In this embodiment, the integrated circuit 110 can obtain multiple data voltages (e.g., based on measured current-voltage characteristic curves (IV curves) and target currents. Figure 2 The data voltages DataA[n] and DataB[n] shown are used to drive the light-emitting diodes 121 to 124 based on these data voltages and the aforementioned multiple control signals. In one embodiment, another integrated circuit (not shown) disposed in the printed circuit board 12 can generate the aforementioned multiple data voltages so that the integrated circuit 110 receives these data voltages and drives the light-emitting diodes 121 to 124 accordingly.

[0049] In this embodiment, integrated circuit 110 can be implemented, for example, as a chip using a glass-processed low-temperature polysilicon (LTPS) thin-film transistor (TFT) process. Integrated circuit 100 can be, for example, a system-on-a-chip (SOC) that includes processors such as microcontrollers, microprocessors, and digital signal processors, as well as memories such as read-only memory (ROM), random access memory (RAM), electronically erasable programmable read-only memory (EEPROM), and flash memory, and can run operating systems and applications.

[0050] In the top view of the back panel 10, for each drive circuit 100, the integrated circuit 110 is surrounded by adjacent light-emitting diodes 121 to 124. Figure 1 The number and configuration of the light-emitting diodes 121 to 124 in the embodiments are merely examples and are not intended to limit the scope of the embodiments.

[0051] Figure 2 Based on the present invention Figure 1 A block diagram of the driving circuit shown in the embodiment. (Refer to...) Figure 1 as well as Figure 2 The driving circuit 100 may include a control circuit 111, a first driving transistor TD1, a second driving transistor TD2, and a light-emitting element 120. In this embodiment, the control circuit 111, the first driving transistor TD1, and the second driving transistor TD2 may be integrated into an integrated circuit 110. The first driving transistor TD1 and the second driving transistor TD2 may be implemented, for example, as a p-type metal-oxide-semiconductor field-effect transistor (PMOSFET) or a p-type thin film transistor (PTFT). The first driving transistor TD1 and the second driving transistor TD2 are connected in parallel and coupled to the control circuit 111 and the light-emitting element 120.

[0052] In this embodiment, the control circuit 111 may include circuitry (not shown) for controlling (and calculating) display data, and for receiving data and / or signals (not shown) regarding control grayscale. The control circuit 111 may also include circuitry for controlling the light emission operation (e.g., [missing information]). Figure 5The control circuit 511 shown receives the light-emitting signal EM[n] and the write signal WR[n] regarding the driving light-emitting element 120. In this embodiment, the first terminal of the control circuit 111 is coupled to the control terminal (i.e., the gate terminal) of the first driving transistor TD1. The second terminal of the control circuit 111 is coupled to the first terminal (i.e., the source terminal) of the first driving transistor TD1 and the first terminal (i.e., the source terminal) of the second driving transistor TD2. The third terminal of the control circuit 111 is coupled to the control terminal (i.e., the gate terminal) of the second driving transistor TD2.

[0053] In this embodiment, the first terminal of the light-emitting element 120 can be coupled to the second terminal (i.e., the drain terminal) of the first driving transistor TD1 and the second terminal (i.e., the drain terminal) of the second driving transistor TD2. The second terminal of the light-emitting element 120 can receive a reference voltage VSS. In this embodiment, the light-emitting element 120 may include... Figure 1 The light-emitting diodes shown are 121 to 124.

[0054] Figure 3 Based on the present invention Figure 2 A flowchart illustrating the operation method of the driving circuit in the embodiment. (See reference) Figure 2 as well as Figure 3 The drive circuit 100 can perform the following steps S301 to S303 to execute the operation method.

[0055] In step S301, the control circuit 111 can distinguish between first sub-display data and second sub-display data according to a set ratio. In this embodiment, the control circuit 111 can also store the first sub-display data and the second sub-display data.

[0056] In this embodiment, the set ratio can be, for example, the ratio of the first bit to the second bit. The display data can be, for example, the maximum grayscale data that the display device can output. The first sub-display data can be, for example, a plurality of first valid bits of the display data. The second sub-display data can be, for example, a plurality of second valid bits of the display data.

[0057] In detail, the control circuit 111 divides the display data into first sub-display data based on the first bit number. The first sub-display data includes a plurality of first effective bits (i.e., first grayscale data) distinguished in the display data at every first bit number. Furthermore, the control circuit 111 divides the display data into second sub-display data based on the second bit number. The second sub-display data includes a plurality of second effective bits (i.e., second grayscale data) distinguished in the display data at every second bit number. In this way, the first grayscale data and the second grayscale data can be combined to form any output grayscale data.

[0058] In step S302, the control circuit 111 generates a first data voltage DataA[n] based on the first sub-display data and a second data voltage DataB[n] based on the second sub-display data. That is, the control circuit 111 can obtain the required first and second effective bits based on the output grayscale data. The control circuit 111 generates a driving voltage (i.e., the first data voltage DataA[n]) for displaying the first effective bit and a driving voltage (i.e., the second data voltage DataB[n]) for displaying the second effective bit. The control circuit 111 outputs these data voltages DataA[n] and DataB[n] to the control terminal (i.e., the gate terminal) of the first driving transistor TD1 and the control terminal (i.e., the gate terminal) of the second driving transistor TD2, respectively.

[0059] In step S303, the first driving transistor TD1 generates a first driving current to the light-emitting element 120 based on the first data voltage DataA[n], and the second driving transistor TD2 generates a second driving current to the light-emitting element 120 based on the second data voltage DataB[n]. In this embodiment, the light-emitting element 120 emits light according to the sum of the first driving current and the second driving current to display the output grayscale data.

[0060] It is worth mentioning that the control circuit 111 divides the maximum grayscale data into first sub-display data and second sub-display data with different bit spacings using a set ratio. Since the voltage difference between any two adjacent grayscale data in these sub-display data can be amplified, the control circuit 111 can precisely control the magnitudes of the data voltages DataA[n] and DataB[n], causing the driving transistors TD1 and TD2 to output corresponding driving currents. In this way, the driving circuit 100 can effectively control the magnitude of the driving current to improve the accuracy of the grayscale.

[0061] Figure 4 Based on the present invention Figure 2 The embodiment illustrates the operation of the drive circuit and provides an exemplary description. Figure 3 Implementation details regarding step S301 are provided in the reference. Figure 2 as well as Figure 4 The display device used in the driving circuit 100 can be, for example, an 8-bit display device. That is, the display data can be, for example, 8-bit metadata (i.e., 256 grayscale data). The driving circuit 100 can output a maximum driving current based on a voltage source (not shown) to display the display data. The voltage value of the voltage source can be, for example, 6 volts (V). The maximum driving current value can be, for example, 20 milliamperes (mA).

[0062] In this embodiment, the set ratio may be, for example, the ratio of the number of bits in the first sub-display data to the number of bits in the second sub-display data. More specifically, the set ratio may be, for example, the ratio of the number of bits in the first sub-display data to the number of bits in the second sub-display data, and for example, 4 bits: 4 bits. In one embodiment, the set ratio may be, for example, 2 bits: 6 bits or other ratios.

[0063] In this embodiment, the first sub-display data D1 consists of multiple most significant bits of the display data. Specifically, the control circuit 111 can set the second sub-display data D2 as grayscale data L0 and generate a second data voltage DataB[n] accordingly to turn off the second driving transistor TD2. At this time, the control circuit 111 can distinguish the first sub-display data D1 as multiple bits, and sequentially set multiple (e.g., 16) first grayscale data L0 to L255 corresponding to the first data voltage DataA[n]. That is, the control circuit 111 can sequentially set multiple (e.g., 16) data voltages DataA[n] corresponding to these grayscale data L0 to L255.

[0064] In this embodiment, the first sub-display data D1 includes multiple most significant bits (i.e., first grayscale data L0, L16, L32, ..., L255) distinguished in the display data at intervals of every first bit (e.g., 4 bits). The voltage source can then be evenly divided among these 16 most significant bits, such that the driving current difference deltaI1 between any two adjacent first grayscale data L0 to L255 for a single grayscale interval is 1.25 mA (i.e., 20 mA divided by 4 bits). In this embodiment, the voltage difference corresponding to the grayscale interval where the grayscale data L0 to L255 are most densely distributed in the IV curve can be, for example, 164.71 mV. Therefore, compared to conventional driving circuits, the voltage difference corresponding to the data voltage DataA[n] between each grayscale interval can be increased.

[0065] In this embodiment, the second sub-display data D2 consists of multiple least significant bits of the display data. Specifically, the control circuit 111 can set the first sub-display data D1 as grayscale data L0 and generate a first data voltage DataA[n] accordingly to turn off the first driving transistor TD1. At this time, the control circuit 111 can distinguish the second sub-display data D2 as multiple bits, and sequentially set multiple (e.g., 16) second grayscale data L0 to L15 corresponding to the second data voltage DataB[n]. That is, the control circuit 111 can sequentially set multiple (e.g., 16) data voltages DataB[n] corresponding to these grayscale data L0 to L15.

[0066] In this embodiment, the second sub-display data D2 includes multiple least significant bits (i.e., second grayscale data L0, L1, L2, ..., L15) distinguished in the display data at intervals of every second bit (e.g., 4 bits). The voltage source can then be evenly divided among these 16 least significant bits, such that the driving current difference deltaI2 between any two adjacent second grayscale data L0 to L15 for a single grayscale interval is 0.078125 mA (i.e., 1.25 mA divided by 4 bits). In this embodiment, the voltage difference corresponding to the grayscale interval where the grayscale data L0 to L15 are most densely distributed in the IV curve can be, for example, 117.65 mV. Therefore, compared to conventional driving circuits, the voltage difference corresponding to the data voltage DataB[n] between each grayscale interval can be increased.

[0067] It should be noted that since the voltage source is not directly divided into 8 bits (i.e., 256 effective bits), the voltage difference between any two adjacent grayscale data L0 to L255 or L0 to L15 can be increased to improve the accuracy of the modulation drive current and avoid grayscale reversal.

[0068] Taking the output grayscale data L27 as an example, the grayscale data L27 is the sum of the first grayscale data L16 in the first sub-display data D1 and the second grayscale data L11 in the second sub-display data D2. Therefore, the control circuit 111, based on the IV curve and the target output grayscale data L27, reverse-engineers the data voltages DataA[n] and DataB[n] of the first sub-display data D1 and the second sub-display data D2, respectively. The control circuit 111 generates the first data voltage DataA[n] based on the first grayscale data L16 in the first sub-display data D1, and generates the second data voltage DataB[n] based on the second grayscale data L11 in the second sub-display data D2.

[0069] Taking the output grayscale data L251 as an example, the grayscale data L251 is the sum of the first grayscale data L240 in the first sub-display data D1 and the second grayscale data L11 in the second sub-display data D2. Therefore, the control circuit 111, based on the IV curve and the target output grayscale data L251, reverse-engineers the data voltages DataA[n] and DataB[n] of the first sub-display data D1 and the second sub-display data D2, respectively. The control circuit 111 generates the first data voltage DataA[n] based on the first grayscale data L240 in the first sub-display data D1, and generates the second data voltage DataB[n] based on the second grayscale data L11 in the second sub-display data D2.

[0070] In this embodiment, to carry a larger first drive current, the size of the first drive transistor TD1 is larger than the size of the second drive transistor TD2. The size ratio between the first drive transistor TD1 and the second drive transistor TD2 can be, for example, 15:1. On the other hand, compared to conventional drive circuits, since the size of the second drive transistor TD2 is smaller than the size of the first drive transistor TD1, and the circuit elements used to drive the second drive transistor TD2 (e.g., Figure 5 The second control circuit 612 shown is also small in size, so the layout area of ​​the drive circuit 100 can remain unchanged.

[0071] Figure 5 This is a circuit diagram of a driving circuit according to an embodiment of the present invention. (See reference) Figure 5 The control circuit 511, the first driving transistor TD1, the second driving transistor TD2, and the light-emitting element 520 included in the driving circuit 500 can be referred to the relevant description of the driving circuit 100 and deduced by analogy, so they will not be repeated here.

[0072] In this embodiment, the control circuit 511 may include a first control circuit 611, a second control circuit 612, and a bias element 613. The first control circuit 611 may receive a first data voltage DataA[n], a light emission signal EM[n], a write signal WR[n], and a reference voltage VREF. One end of the first control circuit 611 is coupled to the bias element 613. The other end of the first control circuit 611 is coupled to the control terminal (i.e., the gate terminal) of the first driving transistor TD1 at the first node N1. In this embodiment, the first control circuit 611 may store the first data voltage DataA[n] according to the write signal WR[n]. The first control circuit 611 may provide the first data voltage DataA[n] to the first driving transistor TD1 according to the light emission signal EM[n].

[0073] In detail, the first control circuit 611 may include transistors T1 to T3 and capacitor C1. In this embodiment, transistors T1 to T3 may be implemented as control switches, for example, using PMOSFETs or P-TFTs, and may be implemented as multiple (e.g., two) PMOSFETs or P-TFTs connected in series. In one embodiment, transistors T1 to T3 may be implemented as single PMOSFETs or P-TFTs, for example. The control terminal (i.e., gate terminal) of transistor T1 receives a write signal WR[n]. The first terminal (i.e., source / drain terminal) of transistor T1 receives a reference voltage VREF. The second terminal (i.e., source / drain terminal) of transistor T1 is coupled to the control terminal (i.e., gate terminal) of the first driving transistor TD1 at the first node N1. The control terminal (i.e., gate terminal) of transistor T2 receives a write signal WR[n]. The first terminal (i.e., source / drain terminal) of transistor T2 receives a first data voltage DataA[n]. The second terminal (i.e., source / drain terminal) of transistor T2 is coupled to one end of capacitor C1. The other end of capacitor C1 is coupled to the first node N1. The control terminal (i.e., the gate terminal) of transistor T3 receives the light emission signal EM[n]. The first terminal (i.e., the source / drain terminal) of transistor T3 is coupled to one end of capacitor C1. The second terminal (i.e., the source / drain terminal) of transistor T3 is coupled to the first terminal (i.e., the source terminal) of each of the driving transistors TD1 and TD2 at the second node N2.

[0074] In this embodiment, the second control circuit 612 can receive a second data voltage DataB[n], a light emission signal EM[n], a write signal WR[n], and a reference voltage VREF. One end of the second control circuit 612 is coupled to a bias element 613. The other end of the second control circuit 612 is coupled to the control terminal (i.e., the gate terminal) of the second driving transistor TD2 at the third node N3. In this embodiment, the second control circuit 612 can store the second data voltage DataB[n] according to the write signal WR[n]. The second control circuit 612 can provide the second data voltage DataB[n] to the second driving transistor TD2 according to the light emission signal EM[n].

[0075] In detail, the second control circuit 612 may include transistors T4 to T6 and capacitor C2. In this embodiment, transistors T4 to T6 may be implemented as control switches and are either PMOSFETs or P-TFTs, and may be implemented as multiple (e.g., two) PMOSFETs or P-TFTs connected in series. In one embodiment, transistors T4 to T6 may be implemented as a single PMOSFET or P-TFT. The control terminal (i.e., gate terminal) of transistor T4 receives the write signal WR[n]. The first terminal (i.e., source / drain terminal) of transistor T4 receives the reference voltage VREF. The second terminal (i.e., source / drain terminal) of transistor T4 is coupled to the control terminal (i.e., gate terminal) of the second driving transistor TD2 at the third node N3. The control terminal (i.e., gate terminal) of transistor T5 receives the write signal WR[n]. The first terminal (i.e., source / drain terminal) of transistor T5 receives the second data voltage DataB[n]. The second terminal (i.e., source / drain terminal) of transistor T5 is coupled to one end of capacitor C2. The other end of capacitor C2 is coupled to the third node N3. The control terminal (i.e., the gate terminal) of transistor T6 receives the emitted light signal EM[n]. The first terminal (i.e., the source / drain terminal) of transistor T6 is coupled to one end of capacitor C2. The second terminal (i.e., the source / drain terminal) of transistor T6 is coupled to the second node N2.

[0076] In this embodiment, the bias element 613 can receive a reference voltage VDD and a light emission signal EM[n]. The bias element 613 is coupled to the first terminal (i.e., the source terminal) of each of the driving transistors TD1 and TD2 at the second node N2. In this embodiment, the bias element 613 can provide a reference voltage VDD to the driving transistors TD1 and TD2 according to the light emission signal EM[n].

[0077] Specifically, the bias element 613 may include transistor T7. In this embodiment, transistor T7 may be, for example, a control switch and implemented as a PMOSFET or P-TFT. The control terminal (i.e., the gate terminal) of transistor T7 receives the light emission signal EM[n]. The first terminal (i.e., the source / drain terminal) of transistor T7 receives the reference voltage VDD. The second terminal (i.e., the source / drain terminal) of transistor T7 is coupled to the second node N2.

[0078] In this embodiment, the light-emitting element 520 may include a plurality of light-emitting diodes connected in series. One end of these light-emitting diodes is coupled to the second terminal (i.e., the drain terminal) of each of the driving transistors TD1 and TD2 at the fourth node N4. The other end of these light-emitting diodes receives a reference voltage VSS.

[0079] In this embodiment, the driving circuit 500 further includes a reset circuit 530. The reset circuit 530 is coupled to the light-emitting element 520, the control circuit 511, the first driving transistor TD1, and the second driving transistor TD2. The reset circuit 530 can receive a reference voltage VREF and a write signal WR[n]. In this embodiment, the reset circuit 530 can provide the reference voltage VREF to the two terminals (i.e., the second node N2 and the fourth node N4) of the driving transistors TD1 and TD2 that are coupled in parallel according to the write signal WR[n].

[0080] Specifically, the reset circuit 530 may include transistors T8 to T9. In this embodiment, transistors T8 to T9 may be implemented as reset switches, for example, using PMOSFETs or P-TFTs, and may be implemented as multiple (e.g., two) PMOSFETs or P-TFTs connected in series. In one embodiment, transistors T8 to T9 may be implemented as single PMOSFETs or P-TFTs, for example. The control terminal (i.e., gate terminal) of transistor T8 receives a write signal WR[n]. The first terminal (i.e., source / drain terminal) of transistor T8 receives a reference voltage VREF. The second terminal (i.e., source / drain terminal) of transistor T8 is coupled to a second node N2. The control terminal (i.e., gate terminal) of transistor T9 receives a write signal WR[n]. The first terminal (i.e., source / drain terminal) of transistor T9 receives a reference voltage VREF. The second terminal (i.e., source / drain terminal) of transistor T9 is coupled to a fourth node N4.

[0081] In some embodiments, transistors T1 to T9 and driving transistors TD1 to TD2 may be implemented, for example, as n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs) or n-type thin-film transistors (NTFTs). In some embodiments, the signal is inverted compared to the corresponding signal in this embodiment.

[0082] Figure 6 Based on the present invention Figure 5 A schematic diagram of the operation of the drive circuit shown in the embodiment. Figures 7A to 7B Based on the present invention Figure 6 A schematic diagram of the operation of the drive circuit shown in the embodiment. Figure 6 In the diagram, the horizontal axis represents the operating time of the drive circuit 500, and the vertical axis represents the voltage or current value.

[0083] In this embodiment, the reference voltage VDD may be, for example, a high voltage source signal. The reference voltage VSS may be, for example, a low voltage source signal. The reference voltage VREF may be, for example, a ground signal. The first voltage level VGH may be higher than the reference voltage VDD, or may be, for example, a logic high level. The second voltage level VGL may be lower than the reference voltage VSS, or may be, for example, a logic low level.

[0084] For details regarding the operation of the drive circuit 500 during the writing phase in P1, please refer to [the relevant documentation / reference]. Figure 6 as well as Figure 7A At time t1, the write signal WR[n] generates a falling edge to be pulled from the first voltage level VGH to the second voltage level VGL, and the write phase begins. At time t2, the write phase ends.

[0085] Specifically, during the write phase P1 (i.e., time t1 to t2), the light emission signal EM[n] has a first voltage level VGH to turn off transistors T3, T6, and T7. The write signal WR[n] has a second voltage level VGL to turn on transistors T1, T2, T4, T5, T8, and T9. At this time, the voltage on the first node N1 is pulled to the reference voltage VREF via transistor T1, and the voltages on the second node N2 and the fourth node N4 are pulled to the reference voltage VREF via transistors T8 and T9, respectively, to reset the terminals of the first driving transistor TD1. The first driving transistor TD1 is turned off. On the other hand, the voltage on the third node N3 is pulled to the reference voltage VREF via transistor T4, so that the second driving transistor TD2 is also reset and turned off.

[0086] Continuing the above explanation, the voltage at one end of capacitor C1 is pulled up to the first data voltage DataA[n] via transistor T2. At this time, the voltage difference across capacitor C1 is the first data voltage DataA[n] minus the reference voltage VREF, so that the first data voltage DataA[n] is stored through capacitor C1. On the other hand, the voltage at one end of capacitor C2 is pulled up to the second data voltage DataB[n] via transistor T5. The voltage difference across capacitor C2 is the second data voltage DataB[n] minus the reference voltage VREF, so that the second data voltage DataB[n] is stored through capacitor C2.

[0087] For details regarding the operation of the driver circuit 500 during the light-emitting phase (P2), please refer to [the relevant documentation / reference]. Figure 6 as well as Figure 7B At time t2, the emission signal EM[n] generates a falling edge, pulling it from the first voltage level VGH to the second voltage level VGL, and the emission phase begins. At time t3, the emission phase ends.

[0088] Specifically, during the light-emitting phase P2 (i.e., time t2 to t3), the light-emitting signal EM[n] has a second voltage level VGL to turn on transistors T3, T6, and T7. The write signal WR[n] has a first voltage level VGH to turn off transistors T1, T2, T4, T5, T8, and T9. At this time, the voltage on the second node N2 is pulled to the reference voltage VDD via transistor T7. The voltage at one end of capacitor C1 is pulled to the reference voltage VDD via transistor T3. The voltage on the first node N1 is coupled via capacitor C1 to the reference voltage VDD minus the voltage difference between the first data voltage DataA[n] and the reference voltage VREF (i.e., VDD - (DataA[n] - VREF)). The first driving transistor TD1 is turned on to be driven according to the voltage difference between the first node N1 and the second node N2 (i.e., DataA[n] - VREF) to generate a first driving current.

[0089] On the other hand, the voltage at one end of capacitor C2 is pulled to the reference voltage VDD via transistor T6. The voltage at the third node N3 is coupled via capacitor C2 to the reference voltage VDD minus the voltage difference between the second data voltage DataB[n] and the reference voltage VREF (i.e., VDD - (DataB[n] - VREF)). The second driving transistor TD2 is turned on to be driven according to the voltage difference between the third node N3 and the second node N2 (i.e., DataB[n] - VREF) to generate a second driving current.

[0090] In this embodiment, the sum of the first driving current and the second driving current generated by driving transistors TD1 and TD2 is the output driving current Ids, which drives the light-emitting element 520. It should be noted that the first driving current and the second driving current are not affected by the voltage difference between the reference voltage VDD and the reference voltage VSS, and can compensate for the current-resistance voltage drop (IRDrop).

[0091] In summary, the driving circuit, its operation method, and the backplane of this invention distinguish display data into multiple most significant bits (i.e., first sub-display data) and multiple least significant bits (i.e., second sub-display data) by a set ratio, thereby increasing the voltage difference between any two adjacent grayscale data. Therefore, the driving circuit can output a first driving current and a second driving current respectively based on these different sub-display data to improve grayscale accuracy. In some embodiments, the multiple control switches used to operate the driving transistors have a small size, maintaining the layout area of ​​the driving circuit.

[0092] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended claims.

Claims

1. A driving circuit, characterized in that, include: A light-emitting element; A control circuit receives a light emission signal and a write signal, wherein the control circuit distinguishes display data into first sub-display data and second sub-display data according to a set ratio, generates a first data voltage based on the first sub-display data, and generates a second data voltage based on the second sub-display data; and A first driving transistor and a second driving transistor are connected in parallel and coupled to the light-emitting element and the control circuit. The first driving transistor generates a first driving current to the light-emitting element based on the first data voltage, and the second driving transistor generates a second driving current to the light-emitting element based on the second data voltage. The control circuit divides the display data into first sub-display data based on the first bit number. The first sub-display data includes a plurality of first valid bits, each separated by every first bit number, and each first valid bit is first grayscale data. The control circuit divides the display data into second sub-display data based on a second number of bits. The second sub-display data includes a plurality of second effective bits that are distinguished in the display data at intervals of the second number of bits. The second effective bits are second grayscale data.

2. The driving circuit as described in claim 1, characterized in that, The first sub-display data consists of multiple most significant bits of the display data, and the second sub-display data consists of multiple least significant bits of the display data.

3. The driving circuit as described in claim 1, characterized in that, The set ratio is the ratio of the number of bits in the first sub-display data to the number of bits in the second sub-display data.

4. The driving circuit as described in claim 1, characterized in that, The size of the first driving transistor is larger than the size of the second driving transistor.

5. The driving circuit as described in claim 1, characterized in that, The first driving transistor and the second driving transistor are respectively a P-type thin-film transistor and an N-type thin-film transistor.

6. The driving circuit as described in claim 1, characterized in that, The control circuit includes: A biasing element provides a first reference voltage to the first driving transistor and the second driving transistor according to the light emission signal; A first control circuit stores the first data voltage according to the write signal and provides the first data voltage to the first driving transistor according to the light emission signal; and A second control circuit stores the second data voltage according to the write signal and provides the second data voltage to the second driving transistor according to the light emission signal.

7. The driving circuit as described in claim 6, characterized in that, The first control circuit includes: A first transistor has a control terminal that receives the write signal, a first terminal of the first transistor that receives a second reference voltage, and a second terminal of the first transistor that is coupled to the control terminal of the first driving transistor at a first node. A first capacitor having a first terminal coupled to the first node; A second transistor having a control terminal for receiving the write signal, a first terminal for receiving the first data voltage, and a second terminal for being coupled to the second terminal of the first capacitor; and A third transistor has a control terminal for receiving the light emission signal, a first terminal of the third transistor is coupled to a second terminal of the first capacitor, and a second terminal of the third transistor is coupled to a first terminal of the first driving transistor and a first terminal of the second driving transistor at a second node.

8. The driving circuit as described in claim 7, characterized in that, The second control circuit includes: A fourth transistor has a control terminal that receives the write signal, a first terminal that receives the second reference voltage, and a second terminal that is coupled to the control terminal of the second drive transistor at a third node. A second capacitor having a first end coupled to the third node; A fifth transistor having a control terminal for receiving the write signal, a first terminal for receiving the second data voltage, and a second terminal for being coupled to the second terminal of the second capacitor; and A sixth transistor has a control terminal for receiving the light emission signal, a first terminal of the sixth transistor is coupled to the second terminal of the second capacitor, and the second terminal of the sixth transistor is coupled to the second node.

9. The driving circuit as described in claim 8, characterized in that, The biasing element includes: A seventh transistor has a control terminal that receives the light emission signal, a first terminal that receives the first reference voltage, and a second terminal that is coupled to the second node.

10. The driving circuit as described in claim 1, characterized in that, Also includes: A reset circuit is coupled to the light-emitting element, the control circuit, the first driving transistor, and the second driving transistor, wherein the reset circuit provides a second reference voltage to the two terminals of the first driving transistor and the second driving transistor that are coupled in parallel according to the write signal.

11. The driving circuit as described in claim 10, characterized in that, The reset circuit includes: An eighth transistor has a control terminal that receives the write signal, a first terminal that receives the second reference voltage, and a second terminal that is coupled at a second node to the first terminal of the first driving transistor and the first terminal of the second driving transistor; and A ninth transistor has a control terminal that receives the write signal, a first terminal that receives the second reference voltage, and a second terminal that is coupled to the second terminal of the first driving transistor and the second terminal of the second driving transistor at a fourth node.

12. A method for operating a driving circuit, characterized in that, include: A control circuit distinguishes the displayed data into first sub-display data and second sub-display data according to a set ratio. The control circuit generates a first data voltage based on the first sub-display data and a second data voltage based on the second sub-display data, wherein the control circuit receives a light emission signal and a write signal; and A first driving transistor generates a first driving current to a light-emitting element based on the first data voltage, and a second driving transistor generates a second driving current to the light-emitting element based on the second data voltage, wherein the first driving transistor and the second driving transistor are connected in parallel and coupled to each other; wherein, The control circuit divides the display data into first sub-display data based on the first bit number. The first sub-display data includes a plurality of first valid bits, each separated by every first bit number, and each first valid bit is first grayscale data. The control circuit divides the display data into second sub-display data based on a second number of bits. The second sub-display data includes a plurality of second effective bits that are distinguished in the display data at intervals of the second number of bits. The second effective bits are second grayscale data.

13. The operating method as described in claim 12, characterized in that, The first sub-display data consists of multiple most significant bits of the display data, and the second sub-display data consists of multiple least significant bits of the display data.

14. The operating method as described in claim 12, characterized in that, The set ratio is the ratio of the number of bits in the first sub-display data to the number of bits in the second sub-display data.

15. The operating method as described in claim 12, characterized in that, Also includes: During a write phase, the control circuit stores the first data voltage and the second data voltage according to the write signal. as well as During a light-emitting phase, the control circuit provides a first reference voltage to the first driving transistor and the second driving transistor according to the light-emitting signal, provides a first data voltage to the first driving transistor according to the light-emitting signal, and provides a second data voltage to the second driving transistor according to the light-emitting signal.

16. The operating method as described in claim 15, characterized in that, Also includes: During the write phase, a reset circuit provides a second reference voltage to the two terminals of the first driving transistor and the second driving transistor that are coupled in parallel, based on the write signal.

17. A backplate, characterized in that, include: A backlight panel is provided with multiple driving circuits as described in claim 1; as well as A printed circuit board, coupled to the backlight, is used to provide the light emission signal and the write signal to a plurality of the driving circuits.

18. The backplate as claimed in claim 17, characterized in that, Each of the control circuits, each of the first driving transistors, and each of the second driving transistors are integrated into an integrated circuit, wherein the integrated circuit is surrounded by a plurality of adjacent light-emitting diodes in each of the light-emitting elements.

Images