N77 band high-gain multistage low noise amplifier

Abstract

The application discloses a kind of N77 frequency band high gain multistage low noise amplifier, N77 frequency band is 3.3GHz-4.2GHz, it is related to radio frequency circuit design field.Gallium arsenide transistor ATF54143 three-stage cascade amplification structure is used, the design purpose of first stage is to obtain minimum noise, two three-stage is to obtain maximum gain and lower flatness, input-output matching uses series microstrip structure, π type microstrip structure is used at cascade, reduce circuit noise, improve overall gain, LC trap wave filter is added at the end to improve the gain uneven problem caused by multistage cascade.Finally, the gain of the low noise amplifier is greater than 34dB, the gain flatness is ±0.4dB, the noise figure is less than 1dB, the input and output return loss is less than-10dB, the input voltage standing wave ratio VSWR1 is less than 2, the output voltage standing wave ratio VSWR2 is less than 2, the output 1dB compression point is 12.5dBm, improve the performance of poor problems such as high noise, low gain and poor stability of N77 frequency band low noise amplifier at present stage.

Description

TECHNICAL FIELD

[0001] The application relates to the field of radio frequency circuit design, in particular to an N77 frequency band high-gain multistage low-noise amplifier. BACKGROUND

[0002] As the first stage of a radio frequency receiving module, a low-noise amplifier plays an important role in the whole radio frequency system, especially has the greatest influence on the noise of the system and the sensitivity of the receiver, so a low-noise amplifier with good performance has become a research hotspot at present. The low-noise amplifier not only needs to meet the noise requirement of the system in the receiving circuit, but also needs to sufficiently amplify the received signal, which requires the low-noise amplifier to simultaneously meet the indicators of good port matching, low noise coefficient, high gain, strong stability and low power consumption and the like.

[0003] The matching structure has a great influence on the performance indicators of the low-noise amplifier, the input matching network is restricted by the noise, and the output matching network is restricted by the output return loss, linearity and bandwidth, and a suitable matching structure can make each indicator reach a balance point of performance optimization, and finally achieve the purposes of reducing noise, improving gain and enhancing stability and the like. In the literature "Wideband noise figure low noise amplifier design for 3.5-4.5GHz", a low-noise amplifier working at 3.5GHz-4.5GHz is designed, the final gain is 20.317dB, the noise is 1.123dB, and the input voltage standing wave ratio is 1.473, and the performance can be further improved in part. SUMMARY

[0004] To solve the above problems, the application provides an N77 frequency band high-gain multistage low-noise amplifier, which improves the performance indicators such as gain, noise coefficient, gain flatness and stability of the N77 (3.3GHz-4.2GHz) frequency band low-noise amplifier.

[0005] To achieve the above object, the application adopts the following technical scheme, which comprises an input circuit, a cascade circuit, an output circuit, a bias circuit, a wave trap and a stabilized power supply.

[0006] The N77 frequency band high-gain multistage low-noise amplifier has a working frequency of 3.3GHz-4.2GHz, comprises input matching, a first-stage gallium arsenide transistor ATF54143, a first-stage bias circuit, a first-stage stabilized power supply, a first-stage interstage matching circuit, a second-stage gallium arsenide transistor ATF54143, a second-stage bias circuit, a second-stage stabilized power supply, a second-stage interstage matching circuit, a third-stage gallium arsenide transistor ATF54143, a third-stage bias circuit, a third-stage stabilized power supply, output matching and a wave trap, and the bias circuit is divided into a front-end bias circuit and a rear-end bias circuit.

[0007] The input matching circuit is connected with the first-stage front-end bias circuit and the gate of the first-stage gallium arsenide transistor ATF54143, the drain of the first-stage gallium arsenide transistor ATF54143 is connected with the first-stage back-end bias circuit and the first-stage inter-stage matching circuit, the first-stage back-end bias circuit is connected with the first-stage voltage stabilizer, the first-stage inter-stage matching circuit is connected with the second-stage front-end bias circuit and the gate of the second-stage gallium arsenide transistor ATF54143, the drain of the second-stage gallium arsenide transistor ATF54143 is connected with the second-stage back-end bias circuit and the second-stage inter-stage matching circuit, the second-stage back-end bias circuit is connected with the second-stage voltage stabilizer, the second-stage inter-stage matching circuit is connected with the third-stage front-end bias circuit and the gate of the third-stage gallium arsenide transistor ATF54143, the drain of the third-stage gallium arsenide transistor ATF54143 is connected with the third-stage back-end bias circuit and the output matching, the third-stage back-end bias circuit is connected with the third-stage voltage stabilizer, and the output matching is connected with the wave filter.

[0008] The input matching circuit is connected with the first-stage front-end bias circuit and the gate of the first-stage gallium arsenide transistor ATF54143, the drain of the first-stage gallium arsenide transistor ATF54143 is connected with the first-stage back-end bias circuit and the first-stage inter-stage matching circuit, the first-stage back-end bias circuit is connected with the first-stage voltage stabilizer, the first-stage inter-stage matching circuit is connected with the second-stage front-end bias circuit and the gate of the second-stage gallium arsenide transistor ATF54143, the drain of the second-stage gallium arsenide transistor ATF54143 is connected with the second-stage back-end bias circuit and the second-stage inter-stage matching circuit, the second-stage back-end bias circuit is connected with the second-stage voltage stabilizer, the second-stage inter-stage matching circuit is connected with the third-stage front-end bias circuit and the gate of the third-stage gallium arsenide transistor ATF54143, the drain of the third-stage gallium arsenide transistor ATF54143 is connected with the third-stage back-end bias circuit and the output matching, the third-stage back-end bias circuit is connected with the third-stage voltage stabilizer, and the output matching is connected with the wave filter.

[0009] The input matching circuit is connected with the first-stage front-end bias circuit and the gate of the first-stage gallium arsenide transistor ATF54143, the drain of the first-stage gallium arsenide transistor ATF54143 is connected with the first-stage back-end bias circuit and the first-stage inter-stage matching circuit, the first-stage back-end bias circuit is connected with the first-stage voltage stabilizer, the first-stage inter-stage matching circuit is connected with the second-stage front-end bias circuit and the gate of the second-stage gallium arsenide transistor ATF54143, the drain of the second-stage gallium arsenide transistor ATF54143 is connected with the second-stage back-end bias circuit and the second-stage inter-stage matching circuit, the second-stage back-end bias circuit is connected with the second-stage voltage stabilizer, the second-stage inter-stage matching circuit is connected with the third-stage front-end bias circuit and the gate of the third-stage gallium arsenide transistor ATF54143, the drain of the third-stage gallium arsenide transistor ATF54143 is connected with the third-stage back-end bias circuit and the output matching, the third-stage back-end bias circuit is connected with the third-stage voltage stabilizer, and the output matching is connected with the wave filter.

[0010] The first cascade matching circuit comprises a capacitor C4, a microstrip line TL5, a microstrip Tee Tee1, a microstrip line TL6, an inductor L3, a microstrip line TL7, a microstrip Tee Tee2, a microstrip line TL8, an inductor L4, a capacitor C5, and the capacitor C4, the microstrip line TL5, the microstrip Tee Tee1, the microstrip line TL7, the microstrip Tee Tee2, the microstrip line TL9 and one end of the capacitor C5 are sequentially connected, the other end of the capacitor C4 is connected with a drain electrode of the first stage gallium arsenide transistor ATF54143, the other end of the capacitor C5 is connected with a gate electrode of the second stage gallium arsenide transistor ATF54143, one end of the microstrip line TL6 is connected with a redundant connection of the microstrip Tee Tee1, the other end of the microstrip line TL6 is connected with one end of the inductor L3, the other end of the inductor L3 is grounded, one end of the microstrip line TL8 is connected with a redundant connection of the microstrip Tee Tee2, the other end of the microstrip line TL8 is connected with one end of the inductor L4, and the other end of the inductor L4 is grounded.

[0011] The second stage bias circuit has the same structure as the first stage bias circuit.

[0012] The second cascade matching circuit has the same structure as the first cascade matching circuit.

[0013] The third stage bias circuit has the same structure as the second stage bias circuit.

[0014] The output matching circuit comprises a microstrip line TL19, a microstrip line TL20 and a capacitor C12, one end of the microstrip line TL19, the microstrip line TL20 and one end of the capacitor C12 are sequentially connected, and the other end of the microstrip line TL19 is connected with a drain electrode of the third stage gallium arsenide transistor ATF54143.

[0015] The wave trap comprises a capacitor C13, a capacitor C14, a capacitor C15, an inductor L11, an inductor L12 and an inductor L13, one end of the capacitor C13 is connected with the other end of the capacitor C12, the other end of the capacitor C13 is connected with a radio frequency output port, the inductor L12 is connected with the capacitor C13 in parallel, one end of the inductor L11 is connected with a common connection point of the capacitor C12 and the capacitor C13, the other end of the inductor L11 is connected with one end of the capacitor C14, the other end of the capacitor C14 is grounded, one end of the inductor L13 is connected with a common connection point of the capacitor C13 and the inductor L12, the other end of the inductor L13 is connected with one end of the capacitor C15, and the other end of the capacitor C15 is grounded.

[0016] Among them, the source of the three-stage gallium arsenide transistor ATF54143 is uniformly added with a microstrip line, including microstrip line TL3, microstrip line TL4, microstrip line TL10, microstrip line TL11, microstrip line TL17, microstrip line TL18, which are connected with corresponding source respectively.

[0017] The beneficial results of the present application are:

[0018] Firstly, the present application provides a low noise amplifier with a three-stage cascade structure, which effectively improves the gain, noise coefficient, stability and return loss of the N77 frequency band low noise amplifier with a working frequency of 3.3GHz-4.2GHz.

[0019] Secondly, the present application provides an input matching network in the form of series microstrip, which is simple in structure and provides the best matching noise for the input end. The output matching network also adopts the form of series microstrip, and at the same time adopts conjugate matching to obtain the maximum gain index. The form of series microstrip is suitable for wideband network.

[0020] Thirdly, the present application effectively improves the problem of poor gain flatness caused by multi-stage cascade through the way of adding a wave trap at the end.

[0021] Fourthly, the present application finally obtains a three-stage cascade low noise amplifier with a gain greater than 34dB in the N77 frequency band, a gain flatness of ±0.4dB, a noise coefficient less than 1dB, an input and output return loss less than-10dB, an input voltage standing wave ratio VSWR1 less than 2, an output voltage standing wave ratio VSWR2 less than 2, and an output 1dB compression point of 12.5dBm, which is good in matching. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a circuit structure schematic diagram of the N77 frequency band high gain multi-stage low noise amplifier of the present application;

[0023] Figure 2 is an equal noise circle and an equal gain circle of the matching circuit when the center frequency is 3.75GHz.

[0024] Figure 3 is a noise coefficient nf(2) and a minimum noise coefficient NFmin curve diagram of the present application;

[0025] Figure 4 is a gain S21 curve diagram of the present application;

[0026] Figure 5 is an input and output return loss S11, S22 curve diagram of the present application;

[0027] Figure 6 is an input and output voltage standing wave ratio VSWR1, VSWR2 curve diagram of the present application;

[0028] Figure 7 is a curve chart of the stability factor Stabfact of the present application;

[0029] Figure 8 is a curve chart of the output 1dB compression point of the present application. DETAILED DESCRIPTION

[0030] The technical solutions of the present application are further described in detail below in combination with the drawings.

[0031] (1) Selecting appropriate transistors and DC working points

[0032] The low noise amplifier required by the present application works in the N77 frequency band, and the working frequency of the frequency band is 3.3GHz-4.2GHz, and it is required to have the characteristics of high gain and low noise. By comparing various transistors suitable for the frequency band, a pseudo-high electron mobility transistor ATF54143 with a gate width size of 800μm of gallium arsenide process of Avago Company is finally selected, and the minimum noise typical value of which is 0.7dB at 3.9GHz, and the gain is 13.53dB, which is suitable for the index requirements of the present application. Considering the factors of power consumption, noise, gain, etc., the DC working point V DS =3V, I DS =60mA is selected, which has good working performance at this time.

[0033] (2) Bias circuit and stability design

[0034] The present application all adopts TDK type capacitor inductor, and the bias circuit adopts resistance voltage division form. In order to simplify the circuit structure design, the three-stage circuit adopts the same static working point, so the same bias circuit is adopted, and 5V single power supply is used for power supply, and LC network is used to form a radio frequency choke circuit, which blocks high frequency signals from entering the DC path and transmits low frequency signals to the transistor. Stability is an important index of the amplifier, and K value is an index for judging whether the low noise amplifier works stably or not, which is defined as a stability factor, mainly including:

[0035]

[0036] Δ=S 11 S 22 -S 21 S 12 <1

[0037] Only by meeting the above conditions, a stable circuit can be obtained. Through the self-test of the transistor ATF54143 by ADS tool, it is found that the DC working point V DS =3V, I DS =60mA does not meet the stability condition, so a source negative feedback network is introduced, and a microstrip line structure is used to replace the inductor structure in order to improve the stability of the circuit.

[0038]

[0039] L represents the length of the microstrip line (unit inch), L represents the inductance value (unit nH), ε r represents the relative dielectric constant of the dielectric plate, and Z0 is the characteristic impedance of the microstrip line on the PCB. According to the index requirements, the selected microstrip line substrate is Rogers4350B, the dielectric constant is 3.66, and the plate thickness is 0.508 mm.

[0040] (3) Design of matching network

[0041] The first stage is to match the network to obtain the minimum noise figure, and the last two stages are to match the network to obtain the maximum gain and lower flatness. As shown in Figure 2 , the equal noise circle and the equal gain circle of the matching circuit at the center frequency point 3.75 GHz.

[0042] Γ s = Γ opt , the low noise amplifier has the minimum noise, Γ s is the reflection coefficient of the transistor looking at the source end, and Γ opt is the source reflection coefficient when the transistor has the minimum noise figure.

[0043] , the low noise amplifier has the maximum gain. Γ s is the reflection coefficient of the transistor looking at the source end, and Γ L is the reflection coefficient of the transistor looking at the load end, is the conjugate of the reflection coefficient of the transistor looking at the source end, is the conjugate of the reflection coefficient of the transistor looking at the load end.

[0044] The design process is realized by means of the Smith circle matching tool in ADS. The input matching network adopts a series microstrip form to match the 50Ω input impedance to the minimum noise point, the first stage inter-stage matching network is matched by using the conjugate complex of the second stage input impedance and the first stage output port impedance value, adopts a π type structure, the second stage inter-stage matching repeats the first stage inter-stage matching mode, the matching structure remains unchanged, and the output matching network also adopts a series microstrip form. The method of conjugate matching is used to obtain the maximum gain and good gain flatness. The three-stage circuit model matching index is not very ideal, and the optimization tool of ADS is used to set different optimization targets according to the index requirements of noise and gain, input and output return loss, and the final simulation result is obtained.

[0045] (4) Introduction of wave trap

[0046] The cascade can obtain higher gain and wider bandwidth, but the gain curve is not smooth and uneven, so the trap wave filter with LC structure at the end of the circuit can effectively improve the gain flatness, reduce the gain peak, and improve the input and output return loss, so as to achieve better performance effect.

[0047] The elements of the N77 frequency band high-gain multi-stage low-noise amplifier are:

[0048] The resistance R1=R4=R7=22Ω, R2=R5=R8=168Ω, R3=R6=R9=33Ω.

[0049] The inductance L1=L5=L9=160nH, L2=L6=L10=82nH, L3=L4=6.2nH, L7=L8=2.7nH, L11=L12=L13=56nH.

[0050] The capacitance C2=C6=C10=6pF, C3=C7=C11=22pF, C1=1pF, C4=1pF, C5=1pF, C8=3pF, C9=8pF, C12=47pF, C13=330pF, C14=C15=220pF.

[0051] As shown in Figure 3 The noise figure nf(2) and the minimum noise figure NFmin curve of the N77 frequency band high-gain multi-stage low-noise amplifier provided by the embodiment are provided, and both kinds of noise figures are less than 1dB.

[0052] As shown in Figure 4 The gain S21 curve of the N77 frequency band high-gain multi-stage low-noise amplifier provided by the embodiment is provided, the gain is greater than 34dB, and the gain flatness is ±0.4dB, and the performance is good.

[0053] As shown in Figure 5 The input and output return loss S11, S22 curve of the N77 frequency band high-gain multi-stage low-noise amplifier provided by the embodiment is provided, and both are less than-10dB, and the circuit reflection performance is good.

[0054] As shown in Figure 6 The input and output voltage standing wave ratio VSWR1, VSWR2 curve of the N77 frequency band high-gain multi-stage low-noise amplifier provided by the embodiment is provided, and both are less than 2, and the matching is good.

[0055] As shown in Figure 7 The stability factor Stabfact curve of the N77 frequency band high-gain multi-stage low-noise amplifier provided by the embodiment is provided, and both are greater than 1, and the stability is good.

[0056] As shown in Figure 8As shown, the N77 frequency band high gain multistage low noise amplifier provided by the embodiment has an output 1dB compression point curve of 12.5dBm, and has good linearity.

[0057] The application provides an N77 frequency band high gain multistage low noise amplifier to improve the noise, gain, stability and other problems of the N77 frequency band. A three-stage amplification structure is adopted to improve the gain and bandwidth, a resistor self-biasing structure and a single power supply form are adopted for the biasing circuit, a series microstrip form input / output matching structure and a π-type microstrip cascade structure are adopted to obtain a suitable matching point, a wave trap is added at the end of the circuit to improve the gain flatness and return loss of the overall circuit, and finally the three-stage cascade low noise amplifier has a gain greater than 34dB in the N77 frequency band, a gain flatness of ±0.4dB, a noise figure less than 1dB, an input / output return loss less than-10dB, an input voltage standing wave ratio VSWR1 less than 2, an output voltage standing wave ratio VSWR2 less than 2, and an output 1dB compression point of 12.5dBm. In summary, the application provides an N77 frequency band high gain multistage low noise amplifier with high gain, low noise, good stability, low loss and good amplification performance.

[0058] The above is only a preferred embodiment of the application, and does not limit the application in any form. According to the technical essence of the application, any simple modification, equivalent replacement and improvement of the above embodiment within the spirit and principle of the application are still within the protection scope of the technical scheme of the application.

Claims

1. An N77 band high-gain multi-stage low-noise amplifier, characterized in that, The N77 frequency band high gain multistage low noise amplifier working frequency is 3.3GHz-4.2GHz, including input matching, first stage gallium arsenide transistor ATF54143, first stage bias circuit, first stage voltage stabilizing power supply, first stage interstage matching circuit, second stage gallium arsenide transistor ATF54143, second stage bias circuit, second stage voltage stabilizing power supply, second stage interstage matching circuit, third stage gallium arsenide transistor ATF54143, third stage bias circuit, third stage voltage stabilizing power supply, output matching, wave trap, and the bias circuit is divided into front-end bias circuit and rear-end bias circuit; The input matching circuit is connected with the first stage front-end bias circuit and the gate of the first stage gallium arsenide transistor ATF54143, the drain of the first stage gallium arsenide transistor ATF54143 is connected with the first stage rear-end bias circuit and the first stage interstage matching circuit, the first stage rear-end bias circuit is connected with the first stage voltage stabilizing power supply, the first stage interstage matching circuit is connected with the second stage front-end bias circuit and the gate of the second stage gallium arsenide transistor ATF54143, the drain of the second stage gallium arsenide transistor ATF54143 is connected with the second stage rear-end bias circuit and the second stage interstage matching circuit, the second stage rear-end bias circuit is connected with the second stage voltage stabilizing power supply, the second stage interstage matching circuit is connected with the third stage front-end bias circuit and the gate of the third stage gallium arsenide transistor ATF54143, the drain of the third stage gallium arsenide transistor ATF54143 is connected with the third stage rear-end bias circuit and the output matching, the third stage rear-end bias circuit is connected with the third stage voltage stabilizing power supply, and the output matching is connected with the wave trap.

2. The low noise amplifier of claim 1, wherein, The input matching adopts a series microstrip cascade matching structure, including a blocking capacitor C1, a microstrip line TL1 and a microstrip line TL2, one end of the blocking capacitor C1 is connected with the microstrip line TL1 and the microstrip line TL2 in sequence, the other end of the blocking capacitor C1 is connected with a radio frequency input port, and the other end of the microstrip line TL2 is connected with the gate of the first stage gallium arsenide transistor ATF54143.

3. The low noise amplifier of claim 1, wherein, The first stage bias circuit includes resistance R1, resistance R2, resistance R3, inductance L1, inductance L2, capacitor C2, capacitor C3, +5V stabilized power supply, the resistance R1 one end, the resistance R2, the resistance R3 one end is connected in turn to realize the voltage division network, the resistance R1 other end is grounded, the inductance L1 one end is connected the common connection point of resistance R1 and resistance R2, the inductance L1 other end is connected the first stage gallium arsenide transistor ATF54143 gate, the capacitor C2 one end is connected the common connection point of resistance R1, resistance R2 and inductance L1, the capacitor C2 other end is grounded, the inductance L2 one end is connected the resistance R3 other end, the inductance L2 other end is connected the first stage gallium arsenide transistor ATF54143 drain, the capacitor C3 one end is connected the common connection point of resistance R3 and inductance L2, the capacitor C3 other end is grounded, the +5V stabilized power supply one end is connected the common connection point of resistance R2 and resistance R3, the +5V stabilized power supply other end is grounded.

4. The low noise amplifier of claim 1, wherein, The first stage intermatch circuit includes capacitor C4, microstrip line TL5, microstrip Tee1, microstrip line TL6, inductance L3, microstrip line TL7, microstrip Tee2, microstrip line TL8, inductance L4, microstrip line TL9, capacitor C5, the capacitor C4 one end, the microstrip line TL5, the microstrip Tee1, the microstrip line TL7, the microstrip Tee2, the microstrip line TL9 and the capacitor C5 one end are connected in turn, the capacitor C4 other end is connected with the first stage gallium arsenide transistor ATF54143 drain, the capacitor C5 other end is connected with the second stage gallium arsenide transistor ATF54143 gate, the microstrip line TL6 one end is connected with the microstrip Tee1 spare connection head, the microstrip line TL6 other end is connected with the inductance L3 one end, the inductance L3 other end is grounded, the microstrip line TL8 one end is connected with the microstrip Tee2 spare connection head, the microstrip line TL8 other end is connected with inductance L4 one end, the inductance L4 other end is grounded.

5. The low noise amplifier of claim 3, wherein, The second stage bias circuit is same with the first stage bias circuit structure.

6. The low noise amplifier of claim 4, wherein, The second stage intermatch circuit is same with the first stage intermatch circuit structure.

7. The low noise amplifier of claim 5, wherein, The third stage bias circuit is same with the second stage bias circuit structure.

8. The low noise amplifier of claim 1, wherein, The output matching circuit includes microstrip line TL19, microstrip line TL20, capacitor C12, the microstrip line TL19 one end, the microstrip line TL20 and the capacitor C12 one end are connected in turn, the microstrip line TL19 other end is connected with the third stage gallium arsenide transistor ATF54143 drain.

9. The low noise amplifier of claim 8, wherein, The trap wave filter comprises a capacitor C13, a capacitor C14, a capacitor C15, an inductor L11, an inductor L12 and an inductor L13, one end of the capacitor C13 is connected with the other end of the capacitor C12, the other end of the capacitor C13 is connected with a radio frequency output port, the inductor L12 is connected with the capacitor C13 in parallel, one end of the inductor L11 is connected with the common connection point of the capacitor C12 and the capacitor C13, the other end of the inductor L11 is connected with one end of the capacitor C14, the other end of the capacitor C14 is grounded, one end of the inductor L13 is connected with the common connection point of the capacitor C13 and the inductor L12, the other end of the inductor L13 is connected with one end of the capacitor C15, the other end of the capacitor C15 is grounded.

10. The low noise amplifier of claim 1, wherein, The source of the three-stage gallium arsenide transistor ATF54143 is connected with a microstrip line, which comprises a microstrip line TL3, a microstrip line TL4, a microstrip line TL10, a microstrip line TL11, a microstrip line TL17 and a microstrip line TL18, which are connected with corresponding sources respectively.

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