Digital predistortion processing methods, systems, devices, storage media, and software products

Abstract

This application discloses a digital predistortion processing method, system, device, storage medium, and program product, relating to the field of radio frequency communication technology. The method includes: receiving a first signal in a first frequency band; retrieving N principal coefficients and N first difference coefficients corresponding to the first signal from a target storage area based on the first frequency band; restoring N first digital predistortion (DPD) coefficients corresponding to the first signal based on the N principal coefficients and N first difference coefficients, where N is a positive integer; and performing digital predistortion processing on the first signal based on the N first DPD coefficients. According to the embodiments of this application, storage space can be saved to a certain extent, which is beneficial for reducing chip area and improving the efficiency of digital predistortion operations.

Description

Technical Field

[0001] This application belongs to the field of radio frequency communication technology, and in particular relates to a digital predistortion processing method, system, device, storage medium and program product. Background Technology

[0002] With the continuous development of radio frequency communication technology, the peak-to-average power ratio (PAPR) of the modulated transmitted signal is generally large. When a signal with a certain PAPR passes through a power amplifier, the nonlinearity of the power amplifier will cause the output signal of the power amplifier to be distorted, and at the same time, the efficiency of the power amplifier will also be reduced.

[0003] Currently, Digital Predistortion (DPD) is a promising technique for addressing the conflict between power amplifier linearity and efficiency. However, due to the complexity of power amplifier operations, digital predistortion is increasingly affecting the area and power consumption of communication front-end chips, hindering the improvement of digital predistortion operational efficiency. Summary of the Invention

[0004] This application provides a digital predistortion processing method, system, device, storage medium, and program product, which can save storage space to a certain extent, reduce chip area, and improve digital predistortion operation efficiency.

[0005] In a first aspect, embodiments of this application provide a digital predistortion processing method, which includes:

[0006] Receive the first signal of the first frequency band;

[0007] Based on the first frequency band, N main coefficients and N first difference coefficients corresponding to the first signal are retrieved from the target storage area; the N main coefficients and N first difference coefficients correspond one-to-one.

[0008] Based on N principal coefficients and N first difference coefficients, the N first digital predistortion (DPD) coefficients corresponding to the first signal are obtained, where N is a positive integer;

[0009] Based on N first DPD coefficients, digital predistortion processing is performed on the first signal;

[0010] The target storage area stores N main coefficients and L difference coefficient groups; each of the L difference coefficient groups includes N difference coefficients that correspond one-to-one with the N main coefficients; the L difference coefficient groups are matched one-to-one with L frequency bands, including the first frequency band, and the difference coefficient group matched with the first frequency band includes N first difference coefficients; L is a positive integer greater than or equal to 2.

[0011] According to one possible implementation of this application, the target principal coefficient is any one of the N principal coefficients; the target difference coefficient is the difference coefficient matched by any frequency band in the L frequency bands, and the target difference coefficient corresponds to the target principal coefficient; the number of bits of storage space occupied by the target difference coefficient is less than the number of bits of storage space occupied by the target DPD coefficient; the target DPD coefficient is obtained by restoring the target principal coefficient and the target difference coefficient.

[0012] According to one possible implementation of this application, the sum of the number of bits of storage space occupied by the N main coefficients is a first value; the sum of the number of bits of storage space occupied by each difference coefficient included in the L difference coefficient groups is a second value; and the sum of the number of bits of storage space occupied by each DPD coefficient included in the L DPD coefficient groups is a third value.

[0013] Among them, the L DPD coefficient groups correspond one-to-one with the L frequency bands; each of the L DPD coefficient groups includes N DPD coefficients; the N DPD coefficients in any DPD coefficient group are obtained by restoring the N main coefficients and the N difference coefficients under the corresponding frequency band.

[0014] The sum of the first and second values ​​is less than the third value.

[0015] According to one possible implementation of this application, the first target difference coefficient is matched with the target principal coefficient, and the first target difference coefficient is included among the N first difference coefficients;

[0016] Based on N principal coefficients and N first difference coefficients, N first DPD signals corresponding to the first signal are obtained, including:

[0017] Logical operations are performed on the target principal coefficient and the first target difference coefficient to restore the first target DPD coefficient; among the N first DPD coefficients, the first target DPD coefficient is included.

[0018] According to one possible implementation of this application, the number of bits of storage space occupied by the target primary coefficient is the same as the number of bits of storage space occupied by the target DPD coefficient;

[0019] The number of bits of storage space occupied by the target difference coefficient shall not exceed half the number of bits of storage space occupied by the target main coefficient.

[0020] According to one possible implementation of this application, the digital predistortion processing method further includes:

[0021] The same digital predistortion module is used to perform time-segmented digital predistortion processing on K signals in at least one of the L frequency bands; K is a positive integer;

[0022] The digital predistortion module includes multiple logic gate units; the operation speed of the digital predistortion module is L times the signal envelope speed, and the signal envelope speed is the transmission rate of any frequency band in the L frequency bands.

[0023] According to one possible implementation of this application, a first scheduler is communicatively connected to a digital predistortion module; the digital predistortion processing method further includes performing time-segmented digital predistortion processing on K signals of at least one of L frequency bands using the same digital predistortion module:

[0024] Receive K signals from at least one of L frequency bands;

[0025] The first scheduler transmits K signals to the digital predistortion module in time periods, so that the digital predistortion module can perform time-based digital predistortion processing on the K signals.

[0026] According to one possible implementation of this application, before retrieving N principal coefficients and N first difference coefficients corresponding to the first signal from the target storage area based on the first frequency band, the digital predistortion processing method further includes:

[0027] The first input signal and the first output signal of the power amplifier are acquired; the first input signal is a signal obtained by digital predistortion processing of a signal in the first frequency band; the first output signal is a signal obtained by amplifying the first input signal through the power amplifier.

[0028] Based on the first input signal and the first output signal, a first nonlinear model matching the first frequency band is calculated; the first nonlinear model includes N coefficient types.

[0029] Based on the first frequency band, N main coefficients and N first difference coefficients corresponding to the first signal are retrieved from the target storage area, including:

[0030] Based on the N coefficient types corresponding to the first frequency band, retrieve the N main coefficients corresponding one-to-one with the N coefficient types from the target storage area, as well as the first difference coefficients of the first frequency band corresponding one-to-one with the N coefficient types.

[0031] Based on N first DPD coefficients, digital predistortion processing is performed on the first signal, including:

[0032] Based on N first DPD coefficients and the first nonlinear model, digital predistortion processing is performed on the first signal.

[0033] According to one possible implementation of this application, the digital predistortion processing method further includes:

[0034] The same coefficient calculation module is used to process the second input signal and the second output signal to obtain a target nonlinear model that matches the target frequency band, which is then used for digital predistortion processing of the signal in the target frequency band. The target nonlinear model includes M coefficient types, where M is a positive integer.

[0035] Wherein, the target frequency band is any one of the L frequency bands; the second input signal is the signal obtained by digital predistortion processing of the signal of the target frequency band; the second output signal is the signal obtained by amplification of the second input signal by a power amplifier;

[0036] The coefficient operation module includes multiple logic gate units; the operation speed of the coefficient operation module is L times the signal envelope speed, and the signal envelope speed is the transmission rate of any frequency band in the L frequency bands.

[0037] According to one possible implementation of this application, before processing the second input signal and the second output signal using the same coefficient calculation module to obtain the target nonlinear model matching the target frequency band, the digital predistortion processing method further includes:

[0038] The second input signal and the second output signal are transmitted to the coefficient calculation module through the second scheduler, so that the coefficient calculation module can perform calculations on the second input signal and the second output signal.

[0039] According to one possible implementation of this application, after receiving the first signal of the first frequency band and before performing digital predistortion processing on the first signal, the digital predistortion processing method further includes:

[0040] From the L bandpass filters that correspond one-to-one with the L frequency bands, determine the first bandpass filter that matches the first frequency band;

[0041] The first signal is subjected to bandpass filtering through the first bandpass filter;

[0042] Based on N DPD coefficients, digital predistortion processing is performed on the first signal, including:

[0043] Based on N first DPD coefficients, digital predistortion processing is performed on the first signal after bandpass filtering.

[0044] According to one possible implementation of this application, after performing digital predistortion processing on the first signal based on N DPD coefficients, the digital predistortion processing method further includes:

[0045] The second signal is input into the power amplifier to obtain the third signal after amplification by the power amplifier; wherein, the second signal is: the signal obtained by digital predistortion processing of the first signal;

[0046] Based on the first and third signals, the power amplifier correction index of the power amplifier is calculated.

[0047] If the power amplifier calibration parameters do not meet the preset conditions, the N first difference coefficients corresponding to the first frequency band are updated.

[0048] Secondly, embodiments of this application provide a digital predistortion processing system, which includes:

[0049] An initial signal receiving module is used to receive the first signal of the first frequency band;

[0050] The coefficient retrieval module is used to retrieve N main coefficients and N first difference coefficients corresponding to the first signal from the target storage area based on the first frequency band; the N main coefficients and N first difference coefficients correspond one-to-one.

[0051] The DPD coefficient restoration module is used to restore the N first digital predistortion DPD coefficients corresponding to the first signal based on N main coefficients and N first difference coefficients, where N is a positive integer;

[0052] The digital predistortion processing module is used to perform digital predistortion processing on the first signal based on N first DPD coefficients;

[0053] The target storage area stores N main coefficients and L difference coefficient groups; each of the L difference coefficient groups includes N difference coefficients that correspond one-to-one with the N main coefficients; the L difference coefficient groups are matched one-to-one with L frequency bands, including the first frequency band, and the difference coefficient group matched with the first frequency band includes N first difference coefficients; L is a positive integer greater than or equal to 2.

[0054] Thirdly, embodiments of this application provide a digital predistortion processing apparatus, which includes:

[0055] Processor and memory storing computer program instructions;

[0056] When the processor executes the computer program instructions, it implements the digital predistortion processing method provided in any of the embodiments of this application described above.

[0057] Fourthly, embodiments of this application provide a computer storage medium storing computer program instructions, which, when executed by a processor, implement the digital predistortion processing method provided in any of the above embodiments of this application.

[0058] Fifthly, embodiments of this application provide a computer program product in which instructions, when executed by a processor of an electronic device, cause the electronic device to perform a digital predistortion processing method as provided in any of the embodiments of this application described above.

[0059] The digital predistortion processing method, system, device, storage medium, and program product of this application embodiment receive a first signal of a first frequency band, and then, based on the first frequency band, retrieve N principal coefficients corresponding to the first signal and N first difference coefficients corresponding one-to-one with the N principal coefficients from a target storage area; based on the N principal coefficients and N first difference coefficients, restore N first digital predistortion (DPD) coefficients corresponding to the first signal, where N is a positive integer; and perform digital predistortion processing on the first signal based on the N first DPD coefficients. The digital predistortion processing method, system, device, storage medium, and program product provided in this application embodiment, by splitting the DPD coefficients corresponding to multiple frequency bands into principal coefficients shared by multiple frequency bands and difference coefficients corresponding to multiple frequency bands and storing them in a target memory area, eliminates the need to store DPD coefficients corresponding to multiple frequency bands. When digital predistortion processing of a signal is required, only the corresponding principal coefficients and difference coefficients need to be retrieved to restore the DPD coefficients. This effectively saves storage space to a certain extent, helps reduce chip area, and improves the efficiency of digital predistortion operations. Attached Figure Description

[0060] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0061] Figure 1 This is a schematic flowchart of a digital predistortion processing method provided in an embodiment of this application.

[0062] Figure 2 This is a schematic flowchart of a digital predistortion processing method provided in an embodiment of this application;

[0063] Figure 3 This is a schematic flowchart of a scenario embodiment of the digital predistortion processing method provided in this application;

[0064] Figure 4 This is a schematic diagram of the structure of a digital predistortion processing system provided in an embodiment of this application;

[0065] Figure 5 This is a schematic diagram of the structure of a digital predistortion processing device provided in an embodiment of this application. Detailed Implementation

[0066] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0067] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0068] As described in the background section, the inventors of this application have discovered that digital predistortion is a relatively good technical means to resolve the contradiction between power amplifier linearity and power amplifier efficiency. However, due to the complexity of power amplifier operations at present, digital predistortion is constantly increasing in terms of the area and power consumption of communication front-end chips, which is not conducive to improving the efficiency of digital predistortion operations.

[0069] Please see Figure 1 , Figure 1 This is a schematic flowchart of a digital predistortion processing method according to an embodiment of this application. For power amplifiers with a wide bandwidth (hereinafter referred to as power amplifiers), the DPD coefficient varies at different frequencies, requiring frequency band processing. Figure 1 In the existing DPD scheme shown, 11 is the bandpass filter corresponding to the first frequency band, 12 is the coefficient calculation module for the first frequency band, 13 is the coefficient storage module for the first frequency band, and 14 is the predistortion calculation module for the first frequency band. 15 is the bandpass filter for the nth frequency band, 16 is the coefficient calculation module for the nth frequency band, 17 is the coefficient storage module for the nth frequency band, and 18 is the predistortion calculation module for the nth frequency band.

[0070] Here, 'n' represents the number of frequency bands the power amplifier supports. For example, a power amplifier with a 200MHz bandwidth (2.4GHz to 2.6GHz) might need to be divided into two 100MHz bands for processing, corresponding to 'n' equal to 2 in the diagram above. The coefficient calculation module can combine the power amplifier's input and output signals to predict the power amplifier's nonlinear model using an algorithm, thereby obtaining the coefficients of the nonlinear model. The DPD coefficients involved in the nonlinear model are stored in the coefficient storage module. The predistortion calculation module can use the DPD coefficients stored in the coefficient storage module to perform predistortion calculations on the input data before inputting it to the power amplifier.

[0071] However, further research by the inventors of this application revealed that the nonlinearity of the power amplifier is mainly caused by the active devices. Different types of power amplifiers, such as LDMOS (Laterally Diffused Metal Oxide Semiconductor), exhibit significant differences in nonlinearity due to the different active devices they employ. The DPD needs to support different types of power amplifiers simultaneously, as well as power amplifiers for different communication types and frequency bands. This significantly increases the complexity of the DPD's logic operations, leading to a substantial increase in the area and power consumption of the DPD in the communication front-end chip.

[0072] for Figure 1 The existing DPD technology solution shown here is configured with a coefficient calculation module, a coefficient storage module and a predistortion calculation module for each frequency band. The calculation speed of each module is matched with the signal envelope speed of each frequency band, which occupies a large chip area and reduces the actual DPD calculation and processing efficiency.

[0073] To address the aforementioned technical problems, embodiments of this application provide a digital predistortion processing method, system, device, storage medium, and program product, which can solve the problem in related technologies where the area and power consumption of digital predistortion in communication front-end chips are constantly increasing, which is not conducive to improving the efficiency of digital predistortion operations.

[0074] It should be noted that the embodiments provided in this application are not intended to limit the scope of this application.

[0075] The technical concept of this application is as follows: The inventors of this application considered that although there are differences between the DPD coefficients corresponding to the high-frequency and low-frequency parts of a power amplifier, the actual differences are not significant; for example, the gain difference will not exceed 1dB. Configuring coefficient storage units for each frequency band would also waste chip area. A typical DPD has hundreds of coefficients, and each coefficient requires multiple bits of storage. Based on this, the DPD coefficients corresponding to multiple frequency bands can be split into two parts for storage: main coefficients shared by multiple frequency bands and difference coefficients corresponding to each frequency band, thereby reducing the space occupied by coefficient storage.

[0076] The digital predistortion processing method provided in the embodiments of this application will be introduced below.

[0077] Figure 2 A schematic flowchart of a digital predistortion processing method according to an embodiment of this application is shown. This digital predistortion processing method is applied to an electronic device, which may include a server or a terminal, etc. Figure 2 As shown, the digital predistortion processing method includes the following steps:

[0078] This application provides a digital predistortion processing method, which includes:

[0079] S210, receives the first signal of the first frequency band;

[0080] S220, based on the first frequency band, retrieves N main coefficients and N first difference coefficients corresponding to the first signal from the target storage area; the N main coefficients and N first difference coefficients correspond one-to-one;

[0081] S230, based on N principal coefficients and N first difference coefficients, restore the N first digital predistortion (DPD) coefficients corresponding to the first signal, where N is a positive integer;

[0082] S240 performs digital predistortion processing on the first signal based on N first DPD coefficients.

[0083] The target storage area stores N main coefficients and L difference coefficient groups; each of the L difference coefficient groups can include N difference coefficients that correspond one-to-one with the N main coefficients; the L difference coefficient groups are matched one-to-one with L frequency bands, and the L frequency bands can include the first frequency band. The difference coefficient group matched with the first frequency band can include N first difference coefficients; L is a positive integer greater than or equal to 2.

[0084] The target principal coefficient is any one of the N principal coefficients; the target difference coefficient is the difference coefficient matched by any frequency band in the L frequency bands, and the target difference coefficient corresponds to the target principal coefficient; the number of bits of storage space occupied by the target difference coefficient is less than the number of bits of storage space occupied by the target DPD coefficient; the target DPD coefficient is obtained by restoring the target principal coefficient and the target difference coefficient.

[0085] The digital predistortion processing method of this application embodiment receives a first signal in a first frequency band, and then, based on the first frequency band, retrieves N principal coefficients corresponding to the first signal and N first difference coefficients corresponding one-to-one with the N principal coefficients from a target storage area; based on the N principal coefficients and the N first difference coefficients, restores N first digital predistortion (DPD) coefficients corresponding to the first signal, where N is a positive integer; and performs digital predistortion processing on the first signal based on the N first DPD coefficients.

[0086] As described above, the digital predistortion processing method provided in this application splits the DPD coefficients corresponding to multiple frequency bands into a main coefficient shared by multiple frequency bands and a difference coefficient corresponding to each frequency band, and stores them in a target memory area. In this way, it is not necessary to store the DPD coefficients corresponding to multiple frequency bands. When digital predistortion processing is required for the signal, it is only necessary to retrieve the corresponding main coefficient and difference coefficient to restore the DPD coefficients. This can effectively save storage space to a certain extent, reduce chip area, and improve the efficiency of digital predistortion operation.

[0087] In S210, in a specific implementation, a first signal of the first frequency band is received. The first signal can be a digital signal. The bandwidth of the first frequency band can be determined according to the actual power amplifier communication requirements. This application does not make specific limitations on this.

[0088] In S220, specifically, based on the first frequency band, N main coefficients and N first difference coefficients corresponding to the first signal are retrieved from the target storage area. The N main coefficients and N first difference coefficients correspond one-to-one.

[0089] The target storage area stores N main coefficients and L difference coefficient groups. Each of the L difference coefficient groups can include N difference coefficients that correspond one-to-one with the N main coefficients. The L difference coefficient groups are matched one-to-one with L frequency bands, and the L frequency bands can include a first frequency band. The difference coefficient group matched with the first frequency band includes the aforementioned N first difference coefficients. L is a positive integer greater than or equal to 2.

[0090] To facilitate understanding, a specific example is provided below. If N=3, L=3, and the target storage area stores three principal coefficients: 100, 200, and 300. The difference coefficient group for the first frequency band includes three difference coefficients corresponding one-to-one with the aforementioned three principal coefficients: 1, 2, and 3; the difference coefficient group for the second frequency band includes three difference coefficients corresponding one-to-one with the aforementioned three principal coefficients: 2, 3, and 4; and the difference coefficient group for the third frequency band includes three difference coefficients corresponding one-to-one with the aforementioned three principal coefficients: 3, 4, and 5.

[0091] After receiving the first signal of the first frequency band, the aforementioned N principal coefficients and N first difference coefficients are retrieved from the target storage area. For example, the N principal coefficients are 100, 200, and 300. The N first difference coefficients corresponding one-to-one with the N principal coefficients are 1, 2, and 3.

[0092] It should be understood that, in this embodiment, decimal data is used for illustration for readability, but in actual chip memory data storage, the aforementioned principal coefficients, difference coefficients and DPD coefficients can all be binary data, and this application does not impose specific restrictions on this.

[0093] In S230, in specific implementation, based on N main coefficients and N first difference coefficients, N first digital predistortion (DPD) coefficients corresponding to the first signal are restored, where N is a positive integer.

[0094] According to some embodiments of this application, optionally, in order to more reasonably realize the restoration of DPD coefficients, the first target difference coefficient is matched with the target principal coefficient, and the first target difference coefficient may be included among the N first difference coefficients;

[0095] Based on N principal coefficients and N first difference coefficients, the N first DPD signals corresponding to the first signal are reconstructed, which may include:

[0096] Logical operations are performed on the target principal coefficient and the first target difference coefficient to restore the first target DPD coefficient; among the N first DPD coefficients, the first target DPD coefficient can be included.

[0097] In this embodiment, the logical operation can be logical addition, logical subtraction, or logical multiplication, etc., and this application does not impose strict limitations. Considering that both the principal coefficient and the difference coefficient are obtained by splitting and storing the original DPD coefficient, the logical operation method adopted during restoration can be determined according to the splitting method of the original DPD coefficient.

[0098] To further illustrate the restoration process, consider the following example: If the N principal coefficients are 100, 200, and 300, and the N corresponding first difference coefficients are 1, 2, and 3, and the target principal coefficient is 100, then the corresponding first target difference coefficient is 1. This target principal coefficient and the first target difference coefficient are obtained by splitting and storing the original DPD coefficient 101. Therefore, when restoring the DPD coefficient, the first target DPD coefficient 101 can be obtained by performing a logical addition operation on the target principal coefficient 100 and the first target difference coefficient 1. Alternatively, using binary data as an example, if the target principal coefficient is 11110000 and the first target difference coefficient is 0001, the first target DPD coefficient obtained after logical addition is 11110001.

[0099] It should be added that, considering that actual chip data is often read bit by bit, a complete DPD coefficient can also be obtained by controlling the data reading order of the main coefficient and the difference coefficient.

[0100] For example, the original DPD coefficient 11110001 is split into the target main coefficient 1111 and the first target difference coefficient 0001. By controlling the reading order of the target main coefficient and the first target difference coefficient, the first target PDD coefficient, i.e. the original DPD coefficient 11110001, is obtained by reading and restoring.

[0101] Based on the above examples, this application does not strictly limit the specific implementation details of how to process the master coefficients and difference coefficients to restore the original DPD coefficients.

[0102] According to some embodiments of this application, optionally, in order to ensure the reduction of storage space occupation, thereby effectively reducing chip area and improving digital predistortion efficiency, the target principal coefficient is any one of N principal coefficients; the target difference coefficient is the difference coefficient matched by any frequency band in L frequency bands, and the target difference coefficient corresponds to the target principal coefficient; the number of bits of storage space occupied by the target difference coefficient is less than the number of bits of storage space occupied by the target DPD coefficient; the target DPD coefficient is obtained based on the target principal coefficient and the target difference coefficient.

[0103] Referring to the example, assume that the target storage area in this embodiment stores three main coefficients: 11110000, 11010000, and 10010000. The difference coefficient group of the first frequency band includes three difference coefficients that correspond one-to-one with the aforementioned three main coefficients: 0001, 0010, and 0011; the difference coefficient group of the second frequency band includes three difference coefficients that correspond one-to-one with the aforementioned three main coefficients: 0010, 0011, and 0100; and the difference coefficient group of the third frequency band includes three difference coefficients that correspond one-to-one with the aforementioned three main coefficients: 0011, 0100, and 0110. The DPD coefficients for each frequency band obtained after restoration are as follows: First frequency band: 11110001, 11010010, 10010011; Second frequency band: 11110010, 11010010, 10010011; Third frequency band: 10010011, 10010100, 10010110.

[0104] If the target primary coefficient is 10010000, the target difference coefficient can correspond to: 0011 in the first frequency band, or 0100 in the second frequency band, or 0110 in the third frequency band. If the target difference coefficient is 10010011, the restored target DPD coefficient is 10010011; if the target difference coefficient corresponds to 0100 in the second frequency band, the target DPD coefficient is 10010100; if the target difference coefficient is 0110 in the third frequency band, the target DPD coefficient is 10010110. In this example, the target difference coefficient occupies 4 bits of storage space, and the target DPD coefficient occupies 8 bits of storage space.

[0105] In this embodiment, by limiting the number of bits in the storage space occupied by the target difference coefficient to be less than the number of bits in the storage space occupied by the target DPD coefficient—that is, the number of bits in the storage space occupied by the difference coefficient under any frequency band is less than the number of bits in its corresponding DPD coefficient—it is possible to avoid storing multi-bit DPD coefficients corresponding to multiple frequency bands during DPD calculation. Instead, only the common principal coefficient shared by multiple frequency bands and the smaller-bit difference coefficients corresponding to each frequency band need to be stored. By adopting this scheme, after splitting the DPD coefficients into principal coefficients and difference coefficients for storage, storage space can be effectively saved to a certain extent, which is beneficial for reducing chip area and improving the efficiency of digital predistortion calculation.

[0106] According to some embodiments of this application, optionally, and further, in order to more fully ensure the reduction of the storage space occupied by the coefficients, the sum of the number of bits of the storage space occupied by the above N main coefficients is a first value; the sum of the number of bits of the storage space occupied by each difference coefficient that can be included in the L difference coefficient groups is a second value; and the sum of the number of bits of the storage space occupied by each DPD coefficient that can be included in the L DPD coefficient groups is a third value.

[0107] Among them, the L DPD coefficient groups correspond one-to-one with the L frequency bands; each DPD coefficient group in the L DPD coefficient groups can include N DPD coefficients; the N DPD coefficients in any DPD coefficient group are obtained by restoring the N main coefficients and the N difference coefficients under the corresponding frequency band.

[0108] The sum of the first and second values ​​is less than the third value.

[0109] The following example illustrates this: the target storage area stores three primary coefficients: 11110000, 11010000, and 10010000. The difference coefficient group for the first frequency band includes three difference coefficients corresponding to the aforementioned three primary coefficients: 0001, 0010, and 0011; the difference coefficient group for the second frequency band includes three difference coefficients corresponding to the aforementioned three primary coefficients: 0010, 0011, and 0100; and the difference coefficient group for the third frequency band includes three difference coefficients corresponding to the aforementioned three primary coefficients: 0011, 0100, and 0110.

[0110] Furthermore, the DPD coefficients included in the DPD coefficient group corresponding to the first frequency band are: 11110001, 11010010, 10010011; the DPD coefficients included in the DPD coefficient group corresponding to the second frequency band are: 11110010, 11010010, 10010011; and the DPD coefficients included in the DPD coefficient group corresponding to the third frequency band are: 10010011, 10010100, 10010110.

[0111] The three principal coefficients mentioned above are all 8 bits of data, representing the sum of the number of bits of storage space occupied by the N principal coefficients. The first value is 24. The second value is the sum of the number of bits of storage space occupied by each difference coefficient in the L difference coefficient groups. In the example above, the second value is 3*3*4 = 36. The third value is the sum of the number of bits of storage space occupied by each DPD coefficient in the L DPD coefficient groups. In the example above, the third value is 3*3*8 = 72. The sum of the first and second values ​​is less than the third value.

[0112] In other words, what would normally require storing 72 bits of DPD coefficients for each frequency band can be reduced to only 24 + 36 = 60 bits of storage space after the DPD coefficients are split into main coefficients and difference coefficients corresponding to each frequency band. This reduces the storage space required for coefficient storage and helps to reduce chip area. Furthermore, the digital predistortion processing scheme provided in this application demonstrates a more significant reduction in storage space as the number of frequency bands supported by the power amplifier increases.

[0113] In S240, in a specific implementation, the first signal is digitally predistorted based on N first DPD coefficients.

[0114] According to some embodiments of this application, optionally, compared to the prior art scheme of configuring multiple corresponding digital predistortion modules for multiple frequency bands to perform logic operations, since the logic gate units in each digital predistortion module occupy memory, in order to further reduce the chip area, the digital predistortion processing method may further include:

[0115] The same digital predistortion module is used to perform time-segmented digital predistortion processing on K signals in at least one of the L frequency bands; K is a positive integer;

[0116] The digital predistortion module may include multiple logic gate units; the operation speed of the digital predistortion module is L times the signal envelope speed, and the signal envelope speed is the transmission rate of any frequency band in the L frequency bands.

[0117] In this embodiment, the same high-speed digital predistortion module is used for time-segmented digital predistortion processing for signals in all frequency bands, thereby reducing the number of logic gates and thus reducing chip area. Furthermore, the logic algorithm for digital predistortion processing is the same for all frequency bands. By increasing the clock frequency, the operation speed of the digital predistortion module reaches L times the signal envelope speed, saving redundant logic operations and reducing chip memory consumption without affecting the efficiency of digital predistortion processing.

[0118] According to some embodiments of this application, optionally, in order to more reasonably realize the sharing of the logical operations of the digital predistortion module for signals of multiple frequency bands, the first scheduler is communicatively connected to the digital predistortion module; when using the same digital predistortion module to perform time-segmented digital predistortion processing on K signals of at least one of L frequency bands, the digital predistortion processing method may further include:

[0119] Receive K signals from at least one of L frequency bands;

[0120] The first scheduler transmits K signals to the digital predistortion module in time periods, so that the digital predistortion module can perform time-based digital predistortion processing on the K signals.

[0121] Thus, by introducing the first scheduler before the digital predistortion module, multiple signals can be sequentially and time-divisionally transmitted to the digital predistortion module for logical operations according to the relevant scheduling mechanism at the same time, which is beneficial to maintaining the orderliness of the signal DPD.

[0122] According to some embodiments of this application, optionally, and more specifically, in order to further reduce the content space occupied by the coefficient storage, the number of bits of the storage space occupied by the target main coefficient is the same as the number of bits of the storage space occupied by the target DPD coefficient.

[0123] The number of bits of storage space occupied by the target difference coefficient shall not exceed half the number of bits of storage space occupied by the target main coefficient.

[0124] According to some embodiments of this application, optionally, in order to more reasonably implement the digital predistortion processing operation of the signal, before retrieving the N main coefficients and N first difference coefficients corresponding to the first signal from the target storage area based on the first frequency band, the digital predistortion processing method may further include:

[0125] The first input signal and the first output signal of the power amplifier are acquired; the first input signal is a signal obtained by digital predistortion processing of a signal in the first frequency band; the first output signal is a signal obtained by amplifying the first input signal through the power amplifier.

[0126] Based on the first input signal and the first output signal, a first nonlinear model matching the first frequency band is calculated; the first nonlinear model may include N coefficient types.

[0127] Based on the first frequency band, retrieving N main coefficients and N first difference coefficients corresponding to the first signal from the target storage area may include:

[0128] Based on the N coefficient types corresponding to the first frequency band, retrieve the N main coefficients corresponding one-to-one with the N coefficient types from the target storage area, as well as the first difference coefficients of the first frequency band corresponding one-to-one with the N coefficient types.

[0129] Digital predistortion processing of the first signal based on N first DPD coefficients can include:

[0130] Based on N first DPD coefficients and the first nonlinear model, digital predistortion processing is performed on the first signal.

[0131] To facilitate understanding of the above scheme, specific examples will be provided below.

[0132] The first nonlinear model described above can be understood as an operational rule that integrates various operational laws and mathematical relationships. In a simple case, the above nonlinear model can specifically be a nonlinear relation, such as: Ax 2 +Bx+C. In this formula, the coefficient A of the quadratic term, the coefficient B of the linear term, and the coefficient C of the constant term can be regarded as these three coefficient types.

[0133] The target storage area stores three principal coefficients corresponding to three coefficient types: quadratic coefficient A, linear coefficient B, and constant coefficient C: 100, 200, and 300. The difference coefficient group for the first frequency band includes three difference coefficients corresponding to the aforementioned three principal coefficients (i.e., the three coefficient types): 1, 2, and 3; the difference coefficient group for the second frequency band includes three difference coefficients corresponding to the aforementioned three principal coefficients (i.e., the three coefficient types): 2, 3, and 4; and the difference coefficient group for the third frequency band includes three difference coefficients corresponding to the aforementioned three principal coefficients (i.e., the three coefficient types): 3, 4, and 5.

[0134] After receiving the first signal of the first frequency band, the coefficient type corresponding to the first frequency band is determined. The N principal coefficients, each corresponding to one of the N coefficient types, and the N first difference coefficients, each corresponding to one of the N coefficient types, are retrieved from the target storage area. After reconstructing the N first DPD coefficients based on the N principal coefficients and the N first difference coefficients, digital predistortion processing is performed on the first signal according to the N first DPD coefficients and the first nonlinear model.

[0135] It should be noted that the coefficient types for different frequency bands may not be the same. For example, the coefficient types for the first frequency band may include A, B, and C, while the coefficient types for the second frequency band may include A, B, C, and D.

[0136] Furthermore, the target memory area may also store other main coefficients corresponding to coefficient types other than the above N coefficient types, as well as the difference coefficients corresponding to other main coefficients, i.e. other coefficient types, under each frequency band. This application does not make specific limitations on this, and the specific settings can be made according to the actual DPD operation and processing requirements.

[0137] According to some embodiments of this application, optionally, similarly, in order to further reduce the chip area and effectively improve DPD efficiency, the digital predistortion processing method may further include:

[0138] The same coefficient calculation module is used to process the second input signal and the second output signal to obtain a target nonlinear model that matches the target frequency band, which can be used to perform digital predistortion processing on the signal of the target frequency band; the target nonlinear model can include M coefficient types, where M is a positive integer;

[0139] Wherein, the target frequency band is any one of the L frequency bands; the second input signal is the signal obtained by digital predistortion processing of the signal of the target frequency band; the second output signal is the signal obtained by amplification of the second input signal by a power amplifier;

[0140] The coefficient operation module may include multiple logic gate units; the operation speed of the coefficient operation module is L times the signal envelope speed, and the signal envelope speed is the transmission rate of any frequency band in the L frequency bands.

[0141] In this embodiment, for the input and output signals corresponding to each frequency band, the same high-speed coefficient calculation module is used to perform time-segmented nonlinear model calculations and coefficient calculations, thereby reducing the chip area by reducing the number of logic gate units.

[0142] Furthermore, when sharing the same coefficient calculation module for multi-band signals, the clock frequency is increased to make the calculation speed of the coefficient calculation module reach L times the signal envelope speed. This saves on repetitive logic operations and chip memory consumption without affecting the coefficient calculation efficiency.

[0143] According to some embodiments of this application, optionally, in order to more reasonably realize the sharing of logical operations of multiple frequency bands for the above-mentioned coefficient calculation module, before using the same coefficient calculation module to process the second input signal and the second output signal to obtain the target nonlinear model matching the target frequency band, the digital predistortion processing method may further include:

[0144] The second scheduler transmits the second input signal and the second output signal to the coefficient calculation module, so that the coefficient calculation module can perform calculations on the second input signal and the second output signal. The second scheduler is communicatively connected to the coefficient calculation module.

[0145] Thus, by introducing the second scheduler before the coefficient calculation module, multiple signals can be sequentially and time-divisionally transmitted to the coefficient calculation module for logical operations in accordance with the relevant scheduling mechanism at the same time, which helps to maintain the orderliness and stability of signal coefficient calculation.

[0146] According to some embodiments of this application, optionally, and more specifically, before performing predistortion processing on the signal, it is often necessary to perform bandpass filtering on the signal to improve the accuracy of subsequent DPD and power amplifier. After receiving the first signal of the first frequency band, and before performing digital predistortion processing on the first signal, the digital predistortion processing method may further include:

[0147] From the L bandpass filters that correspond one-to-one with the L frequency bands, determine the first bandpass filter that matches the first frequency band;

[0148] The first signal is subjected to bandpass filtering through the first bandpass filter;

[0149] Digital predistortion processing of the first signal based on N DPD coefficients can include:

[0150] Based on N first DPD coefficients, digital predistortion processing is performed on the first signal after bandpass filtering.

[0151] According to some embodiments of this application, optionally, considering that the actual DPD processing framework is often a normally open closed-loop system, when the tracking power amplifier changes due to environmental changes, it is necessary to update the DPD coefficients stored inside the chip in a timely manner to meet the DPD processing requirements. Based on this, after performing digital predistortion processing on the first signal based on N DPD coefficients as described above, the digital predistortion processing method may further include:

[0152] The second signal is input into the power amplifier to obtain the third signal after amplification by the power amplifier; wherein, the second signal is: the signal obtained by digital predistortion processing of the first signal;

[0153] Based on the first and third signals, the power amplifier correction index of the power amplifier is calculated.

[0154] If the power amplifier calibration parameters do not meet the preset conditions, the N first difference coefficients corresponding to the first frequency band are updated.

[0155] It should be noted that the aforementioned power amplifier correction parameters can be, for example, ACPR (Adjacent Channel Power Ratio), and this application does not impose specific limitations on them. The aforementioned preset conditions can be set based on actual DPD operation and processing parameters, etc., and are not strictly limited here.

[0156] To facilitate understanding of the digital predistortion processing method provided in the above embodiments, the following describes the method using a specific scenario embodiment. Figure 3 This is a schematic flowchart of a scenario embodiment of the digital predistortion processing method provided in this application.

[0157] like Figure 3In the illustrated scenario, 1 is the bandpass filter 1 corresponding to the first frequency band, i.e., the first bandpass filter mentioned above, and 101 is the bandpass filter n corresponding to the nth frequency band. 2 is the aforementioned second scheduler. 3 is the high-speed coefficient calculation module. 4 is the DPD coefficient storage module. In this DPD coefficient storage module 4, 401 is the storage unit for the main part of the DPD coefficients (main coefficients), 402 is the storage unit for the difference part of the DPD coefficients in the first frequency band (difference coefficients), 403 is the storage unit for the difference part of the DPD coefficients in the nth frequency band (difference coefficients), 5 is the aforementioned first scheduler, and 6 is the high-speed digital predistortion module.

[0158] In this embodiment, on the one hand, by using a high-speed coefficient calculation module and a digital predistortion module to process signals from multiple frequency bands, the logical operations of the shared coefficient calculation module and digital predistortion module can be time-division multiplexed under the coordination of the corresponding scheduler.

[0159] Compared to the existing technology that configures a coefficient calculation module and a digital predistortion module for each frequency band, this embodiment uses the same coefficient calculation module and the same digital predistortion module. The logic algorithm of DPD for each frequency band is exactly the same. The speed improvement is achieved by increasing the clock frequency, so that the speed of the coefficient calculation module and the digital predistortion module is n times the speed of the envelope signal, where n is the number of bandpass filters (i.e., the number of frequency bands L mentioned above). This saves on repetitive logic operations, thereby effectively reducing the number of logic gate units in the chip and thus achieving the goal of reducing the chip area.

[0160] On the other hand, in this embodiment, multi-digit DPD coefficients are split into two parts for storage: primary coefficients and minor difference coefficients, to reduce the space occupied by coefficients and storage. For example, each DPD coefficient typically requires a 12-bit binary signal description, and there are hundreds of DPD coefficients. For different frequency bands, each DPD coefficient differs by only a minimum of 4 bits. Based on this, this embodiment uses 12 bits to store the primary part (primary coefficient) of each DPD coefficient, and allocates 4 bits for the difference part (difference coefficient) for each coefficient type under each frequency band, to significantly reduce the space occupied by storage units.

[0161] Thus, for a two-band scenario, 16% of coefficient storage units can be saved, and for a three-band scenario, 33% of coefficient storage units can be saved. The number of bits for the difference coefficients stored corresponding to the aforementioned DPD coefficients will not exceed half the number of bits of the original DPD coefficients. Therefore, even in the worst-case scenario, storage space can be saved in a two-band scenario, which is beneficial for reducing chip area and improving digital predistortion efficiency.

[0162] Based on the digital predistortion processing method provided in the above embodiments, this application also provides a digital predistortion processing system corresponding to the above digital predistortion processing method. The following describes... Figure 4 A detailed introduction to the digital predistortion processing system is provided.

[0163] Figure 4 A schematic diagram of the structure of a digital predistortion processing system provided in an embodiment of this application is shown. Figure 4 The digital predistortion processing system 400 shown includes:

[0164] Initial signal receiving module 410 is used to receive the first signal of the first frequency band;

[0165] The coefficient retrieval module 420 is used to retrieve N main coefficients and N first difference coefficients corresponding to the first signal from the target storage area based on the first frequency band; the N main coefficients and N first difference coefficients correspond one-to-one.

[0166] The DPD coefficient restoration module 430 is used to restore the N first digital predistortion (DPD) coefficients corresponding to the first signal based on the N main coefficients and the N first difference coefficients, where N is a positive integer;

[0167] The digital predistortion processing module 440 is used to perform digital predistortion processing on the first signal based on N first DPD coefficients;

[0168] The target storage area stores N main coefficients and L difference coefficient groups; each of the L difference coefficient groups includes N difference coefficients that correspond one-to-one with the N main coefficients; the L difference coefficient groups are matched one-to-one with L frequency bands, including the first frequency band, and the difference coefficient group matched with the first frequency band includes N first difference coefficients; L is a positive integer greater than or equal to 2.

[0169] Among them, the target principal coefficient is any one of the N principal coefficients; the target difference coefficient is the difference coefficient matched by any frequency band in the L frequency bands, and the target difference coefficient corresponds to the target principal coefficient; the number of bits of storage space occupied by the target difference coefficient is less than the number of bits of storage space occupied by the target DPD coefficient; the target DPD coefficient is obtained by restoring the target principal coefficient and the target difference coefficient.

[0170] The digital predistortion processing system of this application embodiment includes a module for receiving a first signal in a first frequency band, retrieving N principal coefficients corresponding to the first signal and N first difference coefficients corresponding one-to-one with the N principal coefficients from a target storage area based on the first frequency band; restoring N first digital predistortion (DPD) coefficients corresponding to the first signal based on the N principal coefficients and the N first difference coefficients, where N is a positive integer; and performing digital predistortion processing on the first signal based on the N first DPD coefficients.

[0171] As described above, the digital predistortion processing system provided in this application splits the DPD coefficients corresponding to multiple frequency bands into a main coefficient shared by multiple frequency bands and a difference coefficient corresponding to each frequency band, and stores them in a target memory area. In this way, it is not necessary to store the DPD coefficients corresponding to multiple frequency bands. When digital predistortion processing of the signal is required, it is only necessary to retrieve the corresponding main coefficient and difference coefficient to restore the DPD coefficients. This can effectively save storage space to a certain extent, reduce chip area, and improve the efficiency of digital predistortion operation.

[0172] According to one possible implementation of this application, optionally, the target principal coefficient is any one of the N principal coefficients; the target difference coefficient is the difference coefficient matched by any frequency band in the L frequency bands, and the target difference coefficient corresponds to the target principal coefficient; the number of bits of storage space occupied by the target difference coefficient is less than the number of bits of storage space occupied by the target DPD coefficient; the target DPD coefficient is obtained by restoring the target principal coefficient and the target difference coefficient.

[0173] According to some embodiments of this application, optionally, the sum of the number of bits of storage space occupied by N main coefficients is a first value; the sum of the number of bits of storage space occupied by each difference coefficient that can be included in L difference coefficient groups is a second value; and the sum of the number of bits of storage space occupied by each DPD coefficient that can be included in L DPD coefficient groups is a third value.

[0174] Among them, the L DPD coefficient groups correspond one-to-one with the L frequency bands; each of the L DPD coefficient groups can include N DPD coefficients; the N DPD coefficients in any DPD coefficient group are obtained by restoring the N main coefficients and the N difference coefficients under the corresponding frequency band.

[0175] The sum of the first and second values ​​is less than the third value.

[0176] According to some embodiments of this application, optionally, the first target difference coefficient is matched with the target principal coefficient, and the first target difference coefficient may be included among the N first difference coefficients;

[0177] The DPD coefficient restoration module 430, based on N main coefficients and N first difference coefficients, restores N first DPD signals corresponding to the first signal, specifically including:

[0178] Logical operations are performed on the target principal coefficient and the first target difference coefficient to restore the first target DPD coefficient; among the N first DPD coefficients, the first target DPD coefficient can be included.

[0179] According to some embodiments of this application, optionally, the number of bits of storage space occupied by the target primary coefficient is the same as the number of bits of storage space occupied by the target DPD coefficient;

[0180] The number of bits of storage space occupied by the target difference coefficient shall not exceed half the number of bits of storage space occupied by the target main coefficient.

[0181] According to some embodiments of this application, optionally, the digital predistortion processing system may further include:

[0182] The first processing module can be used to perform time-segmented digital predistortion processing on K signals from at least one of the L frequency bands using the same digital predistortion module; where K is a positive integer.

[0183] The digital predistortion module may include multiple logic gate units; the operation speed of the digital predistortion module is L times the signal envelope speed, and the signal envelope speed is the transmission rate of any frequency band in the L frequency bands.

[0184] According to some embodiments of this application, optionally, the first scheduler is communicatively connected to the digital predistortion module; the digital predistortion processing system, which uses the same digital predistortion module to perform time-segmented digital predistortion processing on K signals of at least one of L frequency bands, may further include:

[0185] The first receiving module can be used to receive K signals from at least one of the L frequency bands;

[0186] The first scheduling module can be used to transmit K signals to the digital predistortion module in time periods through the first scheduler, so that the digital predistortion module can perform time-period digital predistortion processing on the K signals.

[0187] According to some embodiments of this application, optionally, before retrieving N principal coefficients and N first difference coefficients corresponding to the first signal from the target storage area based on the first frequency band, the digital predistortion processing system may further include:

[0188] The first acquisition module can be used to acquire the first input signal and the first output signal of the power amplifier; the first input signal is a signal obtained by digital predistortion processing of a signal in the first frequency band; the first output signal is a signal obtained by amplification of the first input signal by the power amplifier.

[0189] The first arithmetic module can be used to calculate a first nonlinear model that matches the first frequency band based on the first input signal and the first output signal; the first nonlinear model can include N coefficient types.

[0190] The coefficient retrieval module 420 described above, based on the first frequency band, retrieves N main coefficients and N first difference coefficients corresponding to the first signal from the target storage area, which may include:

[0191] The first retrieval submodule can be used to retrieve, based on the N coefficient types corresponding to the first frequency band, N main coefficients corresponding to the N coefficient types one by one from the target storage area, and the first difference coefficients corresponding to the N coefficient types of the first frequency band one by one.

[0192] The aforementioned digital predistortion processing module 440, based on N first DPD coefficients, performs digital predistortion processing on the first signal, and may include:

[0193] Based on N first DPD coefficients and the first nonlinear model, digital predistortion processing is performed on the first signal.

[0194] According to some embodiments of this application, optionally, the digital predistortion processing system may further include:

[0195] The second processing module can be used to process the second input signal and the second output signal using the same coefficient calculation module to obtain a target nonlinear model that matches the target frequency band, which can be used to perform digital predistortion processing on the signal of the target frequency band; the target nonlinear model can include M coefficient types, where M is a positive integer;

[0196] Wherein, the target frequency band is any one of the L frequency bands; the second input signal is the signal obtained by digital predistortion processing of the signal of the target frequency band; the second output signal is the signal obtained by amplification of the second input signal by a power amplifier;

[0197] The coefficient calculation module mentioned above may include multiple logic gate units; the calculation speed of the coefficient calculation module is L times the signal envelope speed, and the signal envelope speed is the transmission rate of any frequency band in the L frequency bands.

[0198] According to some embodiments of this application, optionally, before processing the second input signal and the second output signal using the same coefficient calculation module to obtain the target nonlinear model matching the target frequency band, the digital predistortion processing system may further include:

[0199] The second scheduling module can be used to transmit the second input signal and the second output signal to the coefficient calculation module through the second scheduler, so that the coefficient calculation module can perform calculations on the second input signal and the second output signal.

[0200] According to some embodiments of this application, optionally, after receiving the first signal of the first frequency band and before performing digital predistortion processing on the first signal, the digital predistortion processing system may further include:

[0201] The first determining module can be used to determine the first bandpass filter that matches the first frequency band from L bandpass filters that correspond one-to-one with L frequency bands;

[0202] The filtering module can be used to perform bandpass filtering on the first signal through the first bandpass filter;

[0203] The aforementioned digital predistortion processing module 440, based on N DPD coefficients, performs digital predistortion processing on the first signal, and may include:

[0204] Based on N first DPD coefficients, digital predistortion processing is performed on the first signal after bandpass filtering.

[0205] According to some embodiments of this application, optionally, after performing digital predistortion processing on the first signal based on N DPD coefficients, the digital predistortion processing system may further include:

[0206] The power amplifier processing module can be used to input the second signal into the power amplifier to obtain a third signal after amplification by the power amplifier; wherein, the second signal is: the signal obtained after digital predistortion processing of the first signal;

[0207] The index calculation module can be used to calculate the power amplifier correction index of the power amplifier based on the first signal and the third signal.

[0208] The coefficient update module can be used to update the N first difference coefficients corresponding to the first frequency band when the power amplifier correction index does not meet the preset conditions.

[0209] Based on the digital predistortion processing method provided in the above embodiments of this application, a digital predistortion processing device provided in this application is described below. Please refer to... Figure 5 , Figure 5 This is a schematic diagram of the structure of a digital predistortion processing device provided in an embodiment of this application.

[0210] The digital predistortion processing device may include a processor 501 and a memory 502 storing computer program instructions.

[0211] Specifically, the processor 501 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0212] Memory 502 may include mass storage for data or instructions. For example, and not limitingly, memory 502 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 502 may include removable or non-removable (or fixed) media. Where appropriate, memory 502 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 502 is non-volatile solid-state memory.

[0213] Memory may include read-only memory (ROM), random access memory (RAM), disk storage media devices, optical storage media devices, flash memory devices, and electrical, optical, or other physical / tangible memory storage devices. Therefore, typically, memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the methods according to one aspect of this disclosure.

[0214] The processor 501 reads and executes computer program instructions stored in the memory 502 to implement any of the digital predistortion processing methods in the above embodiments.

[0215] In one example, the data digital predistortion processing device may further include a communication interface 503 and a bus 510. Wherein, as Figure 5 As shown, the processor 501, memory 502, and communication interface 503 are connected through bus 510 and complete communication with each other.

[0216] The communication interface 503 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0217] Bus 510 includes hardware, software, or both, that couples components of a digital predistortion processing device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 510 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, any suitable bus or interconnect is contemplated herein.

[0218] The digital predistortion processing device executes the digital predistortion processing method in the embodiments of this application, thereby achieving Figure 2 The described digital predistortion processing method.

[0219] Furthermore, in conjunction with the digital predistortion processing methods in the above embodiments, this application embodiment can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the digital predistortion processing methods in the above embodiments.

[0220] Based on the digital predistortion processing method in the above embodiments, this application provides a computer program product. When the instructions in the computer program product are executed by the processor of an electronic device, the electronic device performs the digital predistortion processing method provided in any of the above embodiments of this application.

[0221] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0222] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0223] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0224] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0225] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A digital predistortion processing method, characterized in that, include: Receive the first signal of the first frequency band; Based on the first frequency band, N principal coefficients and N first difference coefficients corresponding to the first signal are retrieved from the target storage area; the N principal coefficients and the N first difference coefficients correspond one-to-one. Based on the N principal coefficients and the N first difference coefficients, the N first digital predistortion (DPD) coefficients corresponding to the first signal are restored, where N is a positive integer; Based on the N first DPD coefficients, the first signal is subjected to digital predistortion processing; The target storage area stores the N main coefficients and L difference coefficient groups; each of the L difference coefficient groups includes N difference coefficients that correspond one-to-one with the N main coefficients; the L difference coefficient groups are matched one-to-one with L frequency bands, including the first frequency band, and the difference coefficient group matched with the first frequency band includes the N first difference coefficients; L is a positive integer greater than or equal to 2.

2. The method according to claim 1, characterized in that, The target principal coefficient is any one of the N principal coefficients; the target difference coefficient is the difference coefficient matched in any one of the L frequency bands, and the target difference coefficient corresponds to the target principal coefficient; the number of bits of storage space occupied by the target difference coefficient is less than the number of bits of storage space occupied by the target DPD coefficient; The target DPD coefficient is obtained by restoring the target principal coefficient and the target difference coefficient.

3. The method according to claim 1 or 2, characterized in that, The sum of the number of bits of storage space occupied by the N main coefficients is the first value; the sum of the number of bits of storage space occupied by each difference coefficient included in the L difference coefficient groups is the second value; the sum of the number of bits of storage space occupied by each DPD coefficient included in the L DPD coefficient groups is the third value. Wherein, the L DPD coefficient groups correspond one-to-one with the L frequency bands; each of the L DPD coefficient groups includes N DPD coefficients; the N DPD coefficients in any DPD coefficient group are obtained by restoring the N main coefficients and the N difference coefficients under the corresponding frequency band; The sum of the first value and the second value is less than the third value.

4. The method according to claim 2, characterized in that, The first target difference coefficient matches the target principal coefficient, and the first target difference coefficient is included among the N first difference coefficients; The process of reconstructing the N first DPD coefficients corresponding to the first signal based on the N principal coefficients and the N first difference coefficients includes: Logical operations are performed on the target principal coefficient and the first target difference coefficient to restore the first target DPD coefficient; wherein the first target DPD coefficient is included among the N first DPD coefficients.

5. The method according to claim 2, characterized in that, The number of bits of storage space occupied by the target primary coefficient is the same as the number of bits of storage space occupied by the target DPD coefficient; The number of bits of storage space occupied by the target difference coefficient shall not exceed half the number of bits of storage space occupied by the target main coefficient.

6. The method according to claim 1, characterized in that, The method further includes: The same digital predistortion module is used to perform time-segmented digital predistortion processing on K signals in at least one of the L frequency bands; K is a positive integer; The digital predistortion module includes multiple logic gate units; the operation speed of the digital predistortion module is L times the signal envelope speed, where the signal envelope speed is the transmission rate of any frequency band among the L frequency bands.

7. The method according to claim 6, characterized in that, The first scheduler is communicatively connected to the digital predistortion module; before performing time-segmented digital predistortion processing on K signals of at least one of the L frequency bands using the same digital predistortion module, the method further includes: Receive K signals from at least one of the L frequency bands; The first scheduler transmits the K signals to the digital predistortion module in time periods, so that the digital predistortion module can perform time-based digital predistortion processing on the K signals.

8. The method according to claim 1, characterized in that, Before retrieving the N principal coefficients and N first difference coefficients corresponding to the first signal from the target storage area based on the first frequency band, the method further includes: The first input signal and the first output signal of the power amplifier are acquired; the first input signal is: the signal of the first frequency band obtained after digital predistortion processing; the first output signal is the signal obtained by amplifying the first input signal through the power amplifier. Based on the first input signal and the first output signal, a first nonlinear model matching the first frequency band is calculated; the first nonlinear model includes N coefficient types. The step of retrieving N principal coefficients and N first difference coefficients corresponding to the first signal from the target storage area based on the first frequency band includes: Based on the N coefficient types corresponding to the first frequency band, retrieve the N main coefficients corresponding one-to-one with the N coefficient types from the target storage area, as well as the first difference coefficients of the first frequency band corresponding one-to-one with the N coefficient types; The digital predistortion processing of the first signal based on the N first DPD coefficients includes: Based on the N first DPD coefficients and the first nonlinear model, the first signal is subjected to digital predistortion processing.

9. The method according to claim 8, characterized in that, The method further includes: The same coefficient calculation module is used to process the second input signal and the second output signal to obtain a target nonlinear model that matches the target frequency band, which is then used to perform digital predistortion processing on the signal of the target frequency band; the target nonlinear model includes M coefficient types, where M is a positive integer; Wherein, the target frequency band is any one of the L frequency bands; the second input signal is the signal obtained by digital predistortion processing of the signal of the target frequency band; the second output signal is the signal obtained by amplification of the second input signal by the power amplifier; The coefficient calculation module includes multiple logic gate units; the calculation speed of the coefficient calculation module is L times the signal envelope speed, and the signal envelope speed is the transmission rate of the signal in any of the L frequency bands.

10. The method according to claim 9, characterized in that, Before processing the second input signal and the second output signal using the same coefficient calculation module to obtain the target nonlinear model matching the target frequency band, the method further includes: The second input signal and the second output signal are transmitted to the coefficient calculation module through the second scheduler, so that the coefficient calculation module can perform calculations on the second input signal and the second output signal.

11. The method according to claim 1, characterized in that, After receiving the first signal of the first frequency band, and before performing digital predistortion processing on the first signal, the method further includes: From the L bandpass filters that correspond one-to-one with the L frequency bands, determine the first bandpass filter that matches the first frequency band; The first signal is subjected to bandpass filtering through the first bandpass filter; The digital predistortion processing of the first signal based on the N first DPD coefficients includes: Based on the N first DPD coefficients, the first signal after bandpass filtering is subjected to digital predistortion processing.

12. The method according to claim 1, characterized in that, After performing digital predistortion processing on the first signal based on the N first DPD coefficients, the method further includes: The second signal is input into the power amplifier to obtain the third signal after amplification by the power amplifier; wherein, the second signal is: the signal obtained after digital predistortion processing of the first signal; Based on the first signal and the third signal, the power amplifier correction index of the power amplifier is calculated. If the power amplifier correction index does not meet the preset conditions, the N first difference coefficients corresponding to the first frequency band are updated.

13. A digital predistortion processing system, characterized in that, The digital predistortion processing system includes: An initial signal receiving module is used to receive the first signal of the first frequency band; The coefficient retrieval module is used to retrieve N main coefficients and N first difference coefficients corresponding to the first signal from the target storage area based on the first frequency band; the N main coefficients and the N first difference coefficients correspond one-to-one. The DPD coefficient restoration module is used to restore the N first digital predistortion (DPD) coefficients corresponding to the first signal based on the N main coefficients and the N first difference coefficients, where N is a positive integer; A digital predistortion processing module is used to perform digital predistortion processing on the first signal based on the N first DPD coefficients; The target storage area stores the N main coefficients and L difference coefficient groups; each of the L difference coefficient groups includes N difference coefficients that correspond one-to-one with the N main coefficients; the L difference coefficient groups are matched one-to-one with L frequency bands, including the first frequency band, and the difference coefficient group matched with the first frequency band includes the N first difference coefficients; L is a positive integer greater than or equal to 2.

14. A digital predistortion processing device, characterized in that, The device includes: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, it implements the digital predistortion processing method as described in any one of claims 1-12.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions, which, when executed by a processor, implement the digital predistortion processing method as described in any one of claims 1-12.

16. A computer program product, characterized in that, When the instructions in the computer program product are executed by the processor of the electronic device, the electronic device performs the digital predistortion processing method as described in any one of claims 1-12.

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