A memory and a manufacturing method thereof
By simultaneously forming the bottom electrode of the memory array region and the top contact of the logic region on the upper surface of the bottom circuit layer, combined with the use of a hard mask layer, the problems of cumbersome and costly memory manufacturing processes are solved, achieving the effects of simplified processes and reduced costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG HIKSTOR TECHOGY CO LTD
- Filing Date
- 2022-03-04
- Publication Date
- 2026-07-14
AI Technical Summary
In existing technologies, the manufacturing process of memory is complicated and costly, and traditional copper electroplating is difficult to meet the preparation requirements of high aspect ratio top contacts, which poses electrical and reliability risks.
The bottom electrode of the memory array region and the first top contact of the logic region are formed simultaneously on the upper surface of the bottom circuit layer, and the hard mask layer and the second top contact are formed simultaneously in the through-hole of the patterned dielectric layer. The two are connected in contact, which simplifies the manufacturing process and reduces the use of photomasks.
It simplifies the manufacturing process of memory, reduces costs, and improves product reliability and electrical performance.
Smart Images
Figure CN116761435B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the semiconductor field, and in particular to a memory and a method for manufacturing the same. Background Technology
[0002] Resistive random access memory (MRAM), resistive random access memory (RRAM), and other resistive memories can be divided into a memory array region for implementing storage functions and a logic region for implementing logic functions and other functions. The bottom electrode in the memory array region needs to have a high aspect ratio to reduce backsplashing during the etching of the memory cell layer, ensure sufficient cleaning after the main etching, and prevent metal contamination caused by over-etching of the memory cell layer.
[0003] Currently, when forming the top contact of the logic area, after the memory cell layer of the memory array area is etched and the medium is backfilled, at least one separate photomask is needed to perform photomask work on the medium layer of the logic area and to perform separate etching to form vias. That is, the top contact of the logic area needs to be made by operating the logic area separately, which makes the memory manufacturing process complicated and costly.
[0004] Furthermore, as technology nodes continue to shrink and storage density continues to increase, more cleaning and over-etching are required after the main etching of the storage cells to ensure that the device performance does not degrade. This means that the bottom electrode needs to be taller, and the corresponding top contact will also become taller. In addition, the top contact will also decrease in size as technology nodes shrink. Both of these factors greatly limit the filling of vias during the fabrication of the top contact. Traditional copper plating cannot meet the fabrication requirements of the high aspect ratio top contact, posing electrical and reliability risks.
[0005] Therefore, how to solve the above-mentioned technical problems should be a key focus for those skilled in the art. Summary of the Invention
[0006] The purpose of this application is to provide a memory and a method for manufacturing the same, so as to simplify the manufacturing process of the memory and reduce costs.
[0007] To address the aforementioned technical problems, this application provides a method for manufacturing a memory, comprising:
[0008] The bottom electrode of the memory array region and the first top contact of the logic region are formed simultaneously on the upper surface of the bottom circuit layer;
[0009] A patterned medium layer is formed on the upper surface of the storage cell layer to be processed in the storage array area and the logic area;
[0010] A hard mask layer and a second top contact are simultaneously formed in the via of the patterned dielectric layer; the hard mask layer corresponds to the bottom electrode, and the second top contact is in contact with and connected to the first top contact;
[0011] The memory cell layer is etched to form a memory cell layer, thus obtaining the memory.
[0012] Optionally, before etching the storage cell layer to be processed to form the storage cell layer, after removing the patterned medium layer above the plane of the upper surface of the storage cell layer in the storage array region and the logic region, the method further includes:
[0013] A dielectric layer is deposited in the storage array area and the logic area.
[0014] Optionally, when forming the patterned medium layer, the width of the through hole corresponding to the second top contact body is smaller than the width of the first top contact body.
[0015] Optionally, after etching the storage cell layer to be processed to form the storage cell layer, the method further includes:
[0016] A protective layer is deposited in the storage array area and the logic area.
[0017] Optionally, the formation process of the storage cell layer to be processed in the storage array region includes:
[0018] The storage cell layer to be processed, the dielectric hard mask layer, and the photoresist layer are formed in sequence in both the storage array area and the logic area;
[0019] Remove the photoresist layer located in the logic region;
[0020] Remove the dielectric hard mask layer located in the logic region and the photoresist layer located in the memory array region;
[0021] Remove the storage cell layer to be processed located in the logical area, and retain the storage cell layer to be processed located in the storage array area.
[0022] Optionally, removing the storage cell layer to be processed located in the logical area includes:
[0023] The memory cell layer to be processed, located in the logic region, is removed by a dual etching method of reactive ion etching and ion beam etching.
[0024] Optionally, removing the storage cell layer to be processed located in the logical area includes:
[0025] The memory cell layer to be processed, located in the logic region, is removed using reactive ion etching.
[0026] Optionally, the bottom electrode, the first top contact, the hard mask layer, and the second top contact are all made of tungsten or cobalt.
[0027] Optionally, the simultaneous formation of the bottom electrode of the memory array region and the first top contact of the logic region on the upper surface of the bottom circuit layer includes:
[0028] The bottom electrode and the first top contact are simultaneously formed on the upper surface of the bottom circuit layer using a chemical vapor deposition method.
[0029] This application also provides a memory, which is manufactured using any of the memory manufacturing methods described above.
[0030] This application provides a memory fabrication method comprising: simultaneously forming a bottom electrode of a memory array region and a first top contact of a logic region on the upper surface of a bottom circuit layer; forming a patterned dielectric layer on the upper surface of the memory cell layer to be processed in the memory array region and the logic region; simultaneously forming a hard mask layer and a second top contact in a via of the patterned dielectric layer; the hard mask layer corresponding to the bottom electrode, and the second top contact being in contact with the first top contact; etching the memory cell layer to be processed to form a memory cell layer, thereby obtaining a memory.
[0031] As can be seen, in this application, when fabricating the memory, the first top contact of the logic region is formed at the same time as the bottom electrode of the memory array region, and the second top contact of the logic region is formed at the same time as the hard mask layer of the memory array region. The second top contact and the first top contact are in contact and connected, and the two together form the top contact of the logic region. That is, the top contact of the logic region is fabricated in two stages, and each fabrication is completed simultaneously with the structure in the memory array region. There is no need to separately illuminate and etch the logic region to form vias, which simplifies the fabrication process of the memory, reduces the use of photomasks, and lowers costs.
[0032] In addition, this application also provides a memory that has the above-mentioned advantages. Attached Figure Description
[0033] To more clearly illustrate the technical solutions of the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 A flowchart illustrating a memory fabrication method provided in an embodiment of this application;
[0035] Figures 2 to 15 This is a process flow diagram of a memory fabrication method provided in an embodiment of this application. Detailed Implementation
[0036] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0037] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.
[0038] As described in the background section, the current method of forming the top contact of the logic area requires separate operation of the logic area. After the memory cell layer of the memory array area is etched, the medium is backfilled, and then light irradiation, etching and electroplating of metal are performed, which makes the manufacturing process of the memory cumbersome and costly.
[0039] In view of this, this application provides a method for manufacturing a memory, please refer to... Figure 1 ,include:
[0040] Step S101: Simultaneously form the bottom electrode of the memory array region and the first top contact of the logic region on the upper surface of the bottom circuit layer.
[0041] The formation process of the bottom electrode and the first top contact includes:
[0042] Step S1011: A silicon nitride barrier layer 2, a silicon oxide dielectric layer 3, and a photoresist layer are sequentially formed on the bottom circuit layer 1 of the memory array region and the logic region, and the photoresist is patterned to form a patterned photoresist layer 4, such as... Figure 2 As shown;
[0043] Step S1012: Using the patterned photoresist layer 4 as a mask, etch the silicon oxide dielectric layer 3 and the silicon nitride barrier layer 2 to form the vias of the bottom electrode and the first top contact, remove the patterned photoresist and clean, as shown. Figure 3 As shown;
[0044] Step S1013: Simultaneously fill the through holes of the bottom electrode and the first top contact body with metal, and perform planarization treatment to form the bottom electrode 5 and the first top contact body 6, as shown. Figure 4As shown. The planarization process can be achieved using chemical mechanical polishing.
[0045] It should be noted that the materials of the bottom electrode and the first top contact are not limited in this application, as long as they are conductive materials. For example, the materials of the bottom electrode and the first top contact can be tantalum, tantalum nitride, tungsten, or cobalt. Preferably, the materials of the bottom electrode and the first top contact are both tungsten or cobalt, in order to reduce backsplashing caused during the etching of the memory cell layer to be processed, improve the filling effect, eliminate the risk of electron migration, and increase product reliability.
[0046] When the materials of the bottom electrode and the first top contact are both tungsten or cobalt, the simultaneous formation of the bottom electrode of the storage array region and the first top contact of the logic region on the upper surface of the bottom circuit layer includes: simultaneously forming the bottom electrode and the first top contact on the upper surface of the bottom circuit layer using a chemical vapor deposition method.
[0047] Due to the presence of the memory cell layer and bottom electrode in the memory array area, the top contact depth of the logic area (the sum of the depths of the first and second top contacts) is relatively large, making it difficult to fabricate by electroplating. This limits the possibility of increasing the height of the bottom electrode and also makes it difficult to reduce the size of the logic area interconnects. However, chemical vapor deposition can reduce the fabrication difficulty of the top contacts of the logic area and further increase the height of the bottom electrode.
[0048] Step S102: A patterned medium layer is formed on the upper surface of the storage cell layer to be processed in the storage array area and the logic area.
[0049] It should be noted that in the actual manufacturing process, after step S101 and before step S102, the process also includes: forming a layer of storage cells to be processed in the storage array area. The process of forming the storage cell layer includes:
[0050] Step S201: The memory cell layer 7 to be processed, the dielectric hard mask layer 8, and the photoresist layer 9 are formed sequentially in both the memory array region and the logic region, as follows: Figure 5 As shown.
[0051] Step S202: Remove the photoresist layer 9 located in the logic region, such as... Figure 6 As shown.
[0052] Step S203: Remove the dielectric hard mask layer 8 located in the logic region and the photoresist layer 9 located in the memory array region, such as... Figure 7 As shown.
[0053] In this step, when removing the dielectric hard mask layer of the logic area, reactive ion etching can be used to remove it.
[0054] Step S204: Remove the storage cell layer 7 to be processed located in the logical area, and retain the storage cell layer 7 to be processed located in the storage array area, such as... Figure 8 As shown.
[0055] Optionally, as one possible implementation, removing the memory cell layer to be processed located in the logic region includes: using a dual etching method of reactive ion etching and ion beam etching to remove the memory cell layer to be processed located in the logic region. However, this application does not specifically limit this. As another possible implementation, reactive ion etching can also be used to remove the memory cell layer to be processed located in the logic region; or ion beam etching can be used to remove the memory cell layer to be processed located in the logic region.
[0056] It is important to emphasize that in this step, the memory cell layer to be processed in the logic area must be completely removed, the silicon oxide dielectric layer around the first top contact will also be partially etched, and part of the dielectric hard mask layer in the memory array area will also be etched away.
[0057] In the above process, a lower-cost photomask can be used when etching away the logic area storage cell layer, thereby further reducing the manufacturing cost.
[0058] The process of forming a patterned medium layer on the upper surface of the storage cell layer to be processed in the storage array area and the logic area includes:
[0059] Step S1021: A silicon oxide dielectric layer is formed by backfilling the dielectric in the memory array area and the logic area. Chemical mechanical planarization is then used to make the logic area and the memory array area have the same height. A patterned photoresist layer 4 is then formed on the silicon oxide dielectric layer, such as... Figure 9 As shown;
[0060] It should be noted that the photomask used in this step can be the same as the photomask used in step S1011, in order to reduce manufacturing costs.
[0061] Step S1022: Using the patterned photoresist layer 4 as a mask, the silicon oxide dielectric layer 3 of the memory array region and logic region is etched to form a patterned dielectric layer, and the patterned photoresist layer is removed and cleaned, as follows. Figure 10 As shown.
[0062] Preferably, when forming the patterned dielectric layer, the width D1 of the via corresponding to the second top contact is smaller than the width D2 of the first top contact, so as to control the etching stop and avoid process fluctuations caused by nesting accuracy deviation.
[0063] Step S103: A hard mask layer and a second top contact are simultaneously formed in the through-hole of the patterned dielectric layer; the hard mask layer corresponds to the bottom electrode, and the second top contact is in contact with the first top contact.
[0064] Please refer to the following steps. Figure 11 After forming a hard mask layer 10 and a second top contact 11 simultaneously in the via of the patterned dielectric layer, a chemical mechanical planarization process is required.
[0065] It should be noted that the materials of the hard mask layer and the second top contact are not limited in this application, as long as they are conductive materials. For example, the materials of the hard mask layer and the second top contact can be tantalum, tantalum nitride, tungsten, or cobalt. Preferably, both the hard mask layer and the second top contact are made of tungsten or cobalt to reduce backsplashing during the etching of the memory cell layer to be processed, improve the filling effect, eliminate the risk of electron migration, and increase product reliability.
[0066] When both the hard mask layer and the second top contact are made of tungsten or cobalt, simultaneously forming the hard mask layer and the second top contact in the via of the patterned dielectric layer includes:
[0067] A hard mask layer and a second top contact are simultaneously formed in the vias of the patterned dielectric layer using a chemical vapor deposition method.
[0068] Furthermore, after forming the hard mask layer and the second top contact, it is also necessary to remove the patterned dielectric layer above the plane of the upper surface of the memory cell layer to be processed in the memory array area and logic area, such as... Figure 12 As shown.
[0069] Step S104: Etch the storage cell layer to be processed to form a storage cell layer, thereby obtaining the memory.
[0070] During the etching of the memory cell layer to be processed, the first and second top contacts of the logic area are also etched. The first top contact is in the shape of an inverted T, such as... Figure 13 As shown.
[0071] Preferably, in one embodiment of this application, after etching the memory cell layer to be processed to form the memory cell layer, the method further includes:
[0072] A protective layer 12 is deposited in the storage array area and the logic area, such as... Figure 14 As shown.
[0073] After forming the memory cell layer or depositing the protective layer, it is necessary to backfill the medium in the memory array area and logic area, and then fabricate the top circuit layer 13, resulting in a memory such as Figure 15 As shown.
[0074] In this application, during the fabrication of the memory, the first top contact of the logic region is formed simultaneously with the bottom electrode of the memory array region, and the second top contact of the logic region is formed simultaneously with the hard mask layer of the memory array region. The second top contact and the first top contact are in contact and connected, and together they form the top contact of the logic region. That is, the top contact of the logic region is fabricated in two stages, and each fabrication is completed simultaneously with the structure in the memory array region. There is no need to separately illuminate and etch the logic region to form vias, which simplifies the fabrication process of the memory, reduces the use of photomasks, and lowers costs.
[0075] Based on the above embodiments, in one embodiment of this application, before etching the storage cell layer to be processed to form the storage cell layer, after removing the patterned medium layer above the plane of the upper surface of the storage cell layer in the storage array region and the logic region, the method further includes:
[0076] A dielectric layer is deposited in the memory array region and the logic region to reduce backsplashing during the etching process of the memory cell layer to be processed.
[0077] The materials of the dielectric layer include, but are not limited to, SiN, SiO2, and SiON.
[0078] This application also provides a memory, which is manufactured using the memory manufacturing method described in any of the above embodiments.
[0079] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0080] The memory and its manufacturing method provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.
Claims
1. A method for manufacturing a memory, characterized in that, include: The bottom electrode of the memory array region and the first top contact of the logic region are formed simultaneously on the upper surface of the bottom circuit layer; A patterned medium layer is formed on the upper surface of the storage cell layer to be processed in the storage array area and the logic area; A hard mask layer and a second top contact are simultaneously formed in the via of the patterned dielectric layer; the hard mask layer corresponds to the bottom electrode, and the second top contact is in contact with and connected to the first top contact; The memory cell layer is etched to form a memory cell layer, thus obtaining the memory.
2. The memory fabrication method as described in claim 1, characterized in that, Before etching the storage cell layer to be processed to form the storage cell layer, after removing the patterned medium layer above the plane of the upper surface of the storage cell layer in the storage array region and the logic region, the process further includes: A dielectric layer is deposited in the storage array area and the logic area.
3. The memory fabrication method as described in claim 1, characterized in that, When forming the patterned medium layer, the width of the through hole corresponding to the second top contact is smaller than the width of the first top contact.
4. The memory fabrication method as described in claim 1, characterized in that, After etching the storage cell layer to be processed to form the storage cell layer, the process further includes: A protective layer is deposited in the storage array area and the logic area.
5. The memory fabrication method as described in claim 1, characterized in that, The formation process of the storage cell layer to be processed in the storage array region includes: The storage cell layer to be processed, the dielectric hard mask layer, and the photoresist layer are formed in sequence in both the storage array area and the logic area; Remove the photoresist layer located in the logic region; Remove the dielectric hard mask layer located in the logic region and the photoresist layer located in the memory array region; Remove the storage cell layer to be processed located in the logical area, and retain the storage cell layer to be processed located in the storage array area.
6. The memory fabrication method as described in claim 5, characterized in that, The removal of the unprocessed storage unit layer located in the logical area includes: The memory cell layer to be processed, located in the logic region, is removed by a dual etching method of reactive ion etching and ion beam etching.
7. The memory fabrication method as described in claim 5, characterized in that, The removal of the unprocessed storage unit layer located in the logical area includes: The memory cell layer to be processed, located in the logic region, is removed using reactive ion etching.
8. The method for manufacturing a memory according to any one of claims 1 to 7, characterized in that, The bottom electrode, the first top contact, the hard mask layer, and the second top contact are all made of tungsten or cobalt.
9. The memory fabrication method as described in claim 8, characterized in that, The first top contact of the storage array region and the logic region simultaneously formed on the upper surface of the bottom circuit layer includes: The bottom electrode and the first top contact are simultaneously formed on the upper surface of the bottom circuit layer using a chemical vapor deposition method.
10. A memory, characterized in that, The memory is manufactured using the memory manufacturing method as described in any one of claims 1 to 9.