An air conditioning system

Abstract

An embodiment of the present invention provides an air-conditioning system, which relates to the field of electrical appliance technology. The air-conditioning system reduces costs by disassembling the functions of a communication chip into a main control chip and an additional circuit. The air-conditioning system includes: a first bus, a second bus, and a controller, the controller being electrically connected to a load; the controller including a communication circuit; the communication circuit including: a main control chip, an AC coupling circuit on the signal receiving side, and an AC coupling circuit on the signal sending side. The main control chip includes a signal parsing module, and the main control chip is configured to parse a received first communication signal and complete reception if the first communication signal is a normal signal, and to parse a generated second communication signal and complete transmission if the second communication signal is a normal signal.

Description

Technical Field

[0001] The present invention relates to the technical field of electrical appliances, and in particular to an air-conditioning system. Background Art

[0002] With the development of science and technology, the application of air conditioners has become more and more common, and the daily lives of more and more people are closely related to air conditioners.

[0003] Currently, central air conditioning systems commonly use a home bus communication method for communication between indoor and outdoor units, between wired controllers and indoor units, and between outdoor units. This communication circuit utilizes a communication chip, typically an 1192 protocol conversion chip. Because each indoor unit, outdoor unit, or wired controller in a central air conditioning system requires communication, this chip is used in significant quantities and is expensive per unit, hindering the further adoption of air conditioning. Summary of the Invention

[0004] An embodiment of the present invention provides an air-conditioning system, which reduces costs by separating the functions of a communication chip into a main control chip and an additional circuit.

[0005] The above-mentioned air conditioning system includes: a first bus, a second bus and a controller, the controller is electrically connected to the load; the controller includes a communication circuit; the communication circuit includes: a main control chip, a signal receiving side AC coupling circuit and a signal sending side AC coupling circuit.

[0006] The two first ports of the main control chip are respectively electrically connected to the two first ports of the signal receiving side AC coupling circuit, the two second ports of the main control chip are respectively electrically connected to the two first ports of the signal sending side AC coupling circuit, the two second ports of the signal receiving side AC coupling circuit are respectively electrically connected to the first bus and the second bus, and the two second ports of the signal sending side AC coupling circuit are respectively electrically connected to the first bus and the second bus.

[0007] Among them, the main control chip includes a signal analysis module, and the main control chip is configured to analyze the received first communication signal and complete the reception when the first communication signal is a normal signal, and to analyze the generated second communication signal and complete the sending when the second communication signal is a normal signal.

[0008] Based on the above technical solution, some embodiments of the present application provide an air conditioning system that separates the functions of a communication chip into a main control chip and additional circuits added to the communication loop. In other words, a portion of the communication chip's parsing function is integrated into the main control chip, allowing the main control chip to perform the communication chip's parsing function. Meanwhile, another portion of the communication chip's functions is implemented by adding additional circuits to the communication loop, thereby replacing the communication chip's functions. This reduces the cost of the air conditioning system and promotes the further development of the air conditioning industry. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the technical solution of the present invention and do not constitute a limitation to the technical solution of the present invention.

[0010] Figure 1 A schematic diagram of the composition of an air conditioning system provided by an embodiment of the present invention;

[0011] Figure 2 A schematic diagram of the composition of an air conditioning system provided in the prior art;

[0012] Figure 3 A circuit diagram of a communication loop provided by an embodiment of the present invention;

[0013] Figure 4 A circuit diagram of an analysis module provided in an embodiment of the present invention;

[0014] Figure 5 A circuit diagram of a communication circuit receiving a signal provided by an embodiment of the present invention;

[0015] Figure 6 A circuit diagram of a communication circuit for sending signals provided by an embodiment of the present invention;

[0016] Figure 7 A circuit diagram of a communication circuit for receiving and sending signals provided in an embodiment of the present invention;

[0017] Figure 8 A circuit diagram of another communication circuit for receiving and sending signals provided by an embodiment of the present invention;

[0018] Figure 9 A circuit diagram of adding a clamping circuit to a communication circuit provided by an embodiment of the present invention;

[0019] Figure 10 A specific structural circuit diagram of a clamping circuit provided by an embodiment of the present invention;

[0020] Figure 11 A circuit diagram of a communication circuit provided by an embodiment of the present invention with an anti-reverse circuit and a balancing circuit added;

[0021] Figure 12 A specific structural circuit diagram of an anti-reverse circuit provided by an embodiment of the present invention;

[0022] Figure 13 A specific structural circuit diagram of a balancing circuit provided by an embodiment of the present invention;

[0023] Figure 14 A circuit diagram of a communication circuit provided by an embodiment of the present invention with a bus drive circuit and a negative pressure protection circuit added;

[0024] Figure 15 A circuit diagram of a communication circuit provided by an embodiment of the present invention that receives signals after adding other circuits;

[0025] Figure 16 A circuit diagram for sending signals after adding other circuits to a communication circuit provided by an embodiment of the present invention;

[0026] Figure 17 A circuit diagram for receiving and sending signals after adding other circuits to a communication circuit provided by an embodiment of the present invention;

[0027] Figure 18 A circuit diagram of another communication circuit provided by an embodiment of the present invention that receives and sends signals after adding other circuits;

[0028] Figure 19 A circuit diagram of adding a terminal resistor and an overvoltage protection circuit to a communication circuit provided by an embodiment of the present invention;

[0029] Figure 20 A circuit diagram for adding a fuse to a communication circuit provided by an embodiment of the present invention;

[0030] Figure 21 A circuit diagram of another communication circuit with a fuse added according to an embodiment of the present invention;

[0031] Figure 22 A circuit diagram of adding a fuse to another communication circuit provided by an embodiment of the present invention;

[0032] Figure 23 A flow chart of sending signals through a communication loop provided by an embodiment of the present invention;

[0033] Figure 24 A flow chart of a communication loop receiving a signal provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] As described in the background, current air conditioning systems generally use a home bus communication method for communication between indoor and outdoor units, between wired controllers and indoor units, and between outdoor units. This communication circuit utilizes a communication chip, a protocol conversion chip, exemplified by an 1192 communication chip. This chip, developed by Japan's Mitsumi Corporation, requires communication with every indoor unit, outdoor unit, and wired controller in a central air conditioning system. Consequently, this chip is used in significant quantities and is expensive per unit, increasing the cost of air conditioning systems and hindering their further adoption.

[0035] like Figure 2 As shown, Figure 2 The invention relates to an air conditioning system in the prior art, wherein the air conditioning system comprises a communication circuit, and the communication circuit comprises a communication chip. Figure 2 The communication chip is located in the outdoor unit, the main control chip is electrically connected to the communication chip, and the communication chip is connected to other air-conditioning devices via the first bus and the second bus. The other air-conditioning devices here include: outdoor units, indoor units and wired controllers.

[0036] That is, the outdoor units are connected to each other in communication, the outdoor units are connected to the indoor units in communication, and the outdoor units are connected to the wired controller in communication. It should be noted that the communication chip can also be located in the indoor unit or the wired controller, thereby achieving communication between two air-conditioning devices.

[0037] Based on this, an embodiment of the present application provides an air conditioning system. This air conditioning system divides the existing communication chip into two parts. First, a portion of the communication chip's parsing functions are integrated into the main control chip. Then, the remaining portion of the communication chip's functions is implemented by adding multiple circuits to the communication loop. This allows the communication loop to still perform communication functions even without the communication chip.

[0038] Among them, parsing can be understood as the interpretation of signals, converting one form of communication protocol into another, similar to human translation.

[0039] Figure 1 The present invention provides a schematic diagram of the composition of an air conditioning system. The air conditioning system includes at least two air conditioning devices and a communication bus. It should be noted that the air conditioning system involved in the present invention can be a common air conditioning system consisting of one indoor unit and one outdoor unit, or a multi-split air conditioning system commonly known as a one-to-many system. For ease of description, different types of air conditioning systems are described as follows: Figure 1 The structural diagram of the air conditioning system shown in FIG. 1 is used as an example for explanation.

[0040] like Figure 1As shown, the air conditioning system 1000 includes a first bus A, a second bus B, and a controller 500. The air conditioning system 1000 includes at least one indoor unit 100, at least one outdoor unit 200, and at least one wired controller 300. The controller 500 is communicatively connected via the first bus A and the second bus B. The first bus A and the second bus B are referred to as the home bus in the air conditioning system.

[0041] The Home Bus System (HBS) consists of a coaxial cable and four pairs of twisted-pair cables. The former is used to transmit image information, and the latter is used to transmit voice, data and control signals.

[0042] like Figure 3 As shown, the controller 500 includes a communication circuit 50 , which includes a main control chip 1 , a signal receiving side AC coupling circuit 2 and a signal sending side AC coupling circuit 3 .

[0043] The first bus A is electrically connected to one end of the load 600 , and the second bus B is electrically connected to the other end of the load 600 .

[0044] The main control chip 1 includes two first ports 101 and two second ports 102 ; the signal receiving side AC coupling circuit 2 includes two first ports 201 and two second ports 202 ; the signal sending side AC coupling circuit 3 includes two first ports 301 and two second ports 302 .

[0045] The two first ports 101 of the main control chip 1 are electrically connected to the two first ports 201 of the signal receiving side AC coupling circuit 2, respectively. The two second ports 102 of the main control chip 1 are electrically connected to the two first ports 301 of the signal sending side AC coupling circuit 3, respectively. The two second ports 202 of the signal receiving side AC coupling circuit 2 are electrically connected to the first bus A and the second bus B, respectively. The two second ports 302 of the signal sending side AC coupling circuit 3 are electrically connected to the first bus A and the second bus B, respectively.

[0046] In some embodiments, the signal receiving side AC coupling circuit and the signal transmitting side AC coupling circuit may be separate capacitors, capacitors and resistors connected in series, or capacitors and resistors connected in parallel.

[0047] like Figure 4 As shown, the main control chip 1 further includes a signal analysis module 11, and the main control chip 1 is configured to analyze the received first communication signal, complete the reception when the first communication signal is a normal signal, and, as shown in FIG. Figure 5 As shown, the generated second communication signal is parsed, and the sending is completed when the second communication signal is a normal signal.

[0048] like Figure 4 As shown, the analysis module 11 includes: a first output module 10 and a second output module 20 ; the first output module 10 is electrically connected to the first pin 51 , and the second output module 20 is electrically connected to the second pin 52 .

[0049] At least one of the first output module 10 and the second output module 20 includes a logic control module 30 and a level conversion circuit 40 .

[0050] That is to say, referring to Figure 4 , only the logic control module 30 and the level conversion circuit 40, the second output module 20 does not include: the logic control module 30 and the level conversion circuit 40; or, refer to Figure 5 , only the second output module 20 includes: a logic control module 30 and a level conversion circuit 40, and the first output module 10 does not include: a logic control module 30 and a level conversion circuit 40; or, not only the first output module 10 includes: a logic control module 30 and a level conversion circuit 40, but the second output module 20 also includes: a logic control module 30 and a level conversion circuit 40.

[0051] In some embodiments, the first output module 10 acts on the first pin 51, and the second output module 20 does not act on the second pin 52; alternatively, the second output module 20 acts on the first pin 51, and the first output module 10 does not act on the second pin 52; alternatively, the first output module 10 acts on the first pin 51, and the second output module 20 acts on the second pin 52.

[0052] The logic control module 30 includes a first control terminal K1 , a second control terminal K2 and a third control terminal K3 .

[0053] The level conversion circuit 40 includes a first transistor Q1 , a second transistor Q2 , a third transistor Q3 , a first resistor R1 , and a second resistor R2 .

[0054] The control electrode of the first transistor Q1 is electrically connected to the first control terminal K1, the first electrode of the first transistor Q1 is electrically connected to the second end of the first resistor R1, the second electrode of the first transistor Q1 is electrically connected to the output terminal OUT, and the first end of the first resistor R1 is electrically connected to the first voltage terminal VCC;

[0055] The control electrode of the second transistor Q2 is electrically connected to the second control terminal K2 , the first electrode of the second transistor Q2 is electrically connected to the output terminal OUT, and the second electrode of the second transistor Q2 is electrically connected to the second voltage terminal GND.

[0056] The control electrode of the third transistor is electrically connected to the third control terminal K3, the first electrode of the third transistor is electrically connected to the second end of the second resistor R2, the second electrode of the third transistor is electrically connected to the second voltage terminal GND, and the first end of the second resistor R2 is electrically connected to the output terminal OUT.

[0057] In some embodiments, the transistor is an NPN-type triode, the first control signal having an on-level is a high level, and the second control signal having an off-level is a low level.

[0058] In some embodiments, the transistor is a PNP transistor, the first control signal with an on-level is a low level, and the second control signal with an off-level is a high level.

[0059] Among them, Figure 4 As shown, taking an NPN transistor as an example, if the NPN transistor is turned on, for example, the first transistor Q1 is turned on, then the first voltage terminal VCC and the output terminal OUT can be considered as a wire; if the second transistor Q2 is turned on, then the second voltage terminal GND and the output terminal OUT can be considered as a wire. If the first transistor Q1 is turned on and the second transistor Q2 is turned off, the output terminal outputs the voltage of the first voltage terminal VCC; if the first transistor Q1 is turned off and the second transistor Q2 is turned on, the output terminal outputs the voltage of the second voltage terminal GND; if the first transistor Q1 is turned on and the second transistor Q2 is also turned on, the circuit is short-circuited and no voltage can be output.

[0060] When the logic control module 30 is configured to output a first control signal and a third control signal with an on-level, and a second control signal with an off-level, the first control signal controls the first transistor Q1 to turn on, the third control signal controls the third transistor Q3 to turn on, and the second control signal controls the second transistor Q2 to turn off; the first transistor Q1 and the third transistor Q3 are both connected, and the voltage across the second resistor R2 is transmitted to the output terminal OUT.

[0061] For example, the voltage of the first voltage terminal VCC is 5V, the voltage of the second voltage terminal GND is 0V, the resistance value of the first resistor R1 is the same as the resistance value of the second resistor R2, and because the voltage at the output terminal is the voltage across the second resistor R2, the voltage output at the output terminal is 2.5V; if the ratio of the resistance value of the first resistor R1 to the resistance value of the second resistor R2 is 4:1, the voltage output at the output terminal is 1V.

[0062] In order to facilitate the description of subsequent solutions, the transistors in the second output module 20 are: a fourth transistor Q4, a fifth transistor Q5 and a sixth transistor Q6, which correspond one-to-one to the first transistor Q1, the second transistor Q2 and the third transistor Q3 in the first output module 10; the resistors in the second output module 20 are: a third resistor R3 and a fourth resistor R4, which correspond one-to-one to the first resistor R1 and the second resistor R2 in the first output module 10.

[0063] The voltage outputted by the output terminal is the voltage across the second resistor R2, and the voltage across the second resistor R2 is related to the ratio of the resistance value of the first resistor R1 to the resistance value of the second resistor R2. Therefore, if the ratio of the resistance value of the first resistor R1 to the resistance value of the second resistor R2 can be changed, the voltage outputted by the output terminal can be adjusted arbitrarily.

[0064] In some embodiments, any one or more of the first resistor R1 , the second resistor R2 , the third resistor R3 , and the fourth resistor R4 are adjustable resistors.

[0065] in, Figure 5 This means that the main control chip receives the first communication signal sent by the load 600. The first communication signal is transmitted to the two second ports 202 of the signal receiving side AC coupling circuit 2 via the first bus A and the second bus B. The signal receiving side AC coupling circuit 2 receives the first communication signal and transmits the useful AC signal via the two first ports 201 of the signal receiving side AC coupling circuit 2 to the two first ports 101 of the main control chip 1. The main control chip 1 then analyzes the first communication signal.

[0066] Figure 6 This refers to the transmission of the second communication signal from the main control chip to the load 600. The main control chip 1 parses and calibrates the second communication signal. The second communication signal is transmitted via the main control chip 1 and transmitted through the two second ports 102 of the main control chip 1 to the two first ports 301 of the signal-sending-side AC coupling circuit 3. The signal-sending-side AC coupling circuit 3 receives the second communication signal and transmits the useful AC signal to the first bus A and the second bus B via the two second ports 302 of the signal-sending-side AC coupling circuit 2. The second communication signal is then transmitted to the load 600, completing the communication with the load 600.

[0067] In some embodiments, as Figure 6 and Figure 7 As shown, the port of the first bus A electrically connected to the signal receiving side AC coupling circuit 2 is the first sub-port 2021 of the two second ports 202 of the signal receiving side AC coupling circuit 2; the port of the second bus B electrically connected to the signal receiving side AC coupling circuit 2 is the second sub-port 2022 of the two second ports 202 of the signal receiving side AC coupling circuit 2; Figure 7 Of the two first ports 201 of the AC coupling circuit 2 at the middle signal receiving side, the upper one is the first sub-port 2011 , and the lower one is the second sub-port 2012 .

[0068] Correspondingly, the two first ports 101 of the main control chip 1 include: a first sub-port 1011 and a second sub-port 1012; the two second ports 102 of the main control chip 1 include: a first sub-port 1021 and a second sub-port 1022; the two first ports 301 of the signal sending side AC coupling circuit 3 include: a first sub-port 3011 and a second sub-port 3012; the two second ports 302 of the signal sending side AC coupling circuit 3 include: a first sub-port 3021 and a second sub-port 3022.

[0069] The first communication signal is transmitted via the first bus A to the first sub-port 2021 of the two second ports 202 of the signal receiving side AC coupling circuit 2. The signal receiving side AC coupling circuit 2 receives the first communication signal and transmits the useful AC signal via the first sub-port 2011 of the two first ports 201 of the signal receiving side AC coupling circuit 2 to the first sub-port 1011 of the two first ports 101 of the main control chip 1, thereby transmitting the useful AC signal to the main control chip 1. The main control chip 1 parses the first communication signal.

[0070] The main control chip 1 transmits a second communication signal. The first subport 1021 of the two second ports 102 of the main control chip 1 transmits the second communication signal and transmits the second communication signal to the second subport 3012 of the two first ports 301 of the signal-sending-side AC coupling circuit 3. The signal-sending-side AC coupling circuit 3 receives the second communication signal and transmits the useful AC signal to the second bus B via the second subport 3022 of the two second ports 302 of the signal-sending-side AC coupling circuit 2. The second communication signal is transmitted to the load 600 via the second bus B, thereby completing communication with the load 600.

[0071] In some embodiments, as Figure 6 and Figure 8 As shown, the first communication signal is transmitted to the second sub-port 2022 of the two second ports 202 of the signal receiving side AC coupling circuit 2 via the second bus B. The signal receiving side AC coupling circuit 2 receives the first communication signal and transmits the useful AC signal to the second sub-port 1012 of the two first ports 101 of the main control chip 1 via the second sub-port 2012 of the two first ports 201 of the signal receiving side AC coupling circuit 2, thereby transmitting the useful AC signal to the main control chip 1. The main control chip 1 parses the first communication signal.

[0072] The main control chip 1 transmits a second communication signal. The second sub-port 1022 of the two second ports 102 of the main control chip 1 transmits the second communication signal and transmits the second communication signal to the first sub-port 3011 of the two first ports 301 of the signal-transmitting-side AC coupling circuit 3. The signal-transmitting-side AC coupling circuit 3 receives the second communication signal and transmits the useful AC signal to the first bus A via the first sub-port 3021 of the two second ports 302 of the signal-transmitting-side AC coupling circuit 2. The second communication signal is transmitted to the load 600 via the first bus A, thereby completing communication with the load 600.

[0073] In summary, some embodiments of the present application provide an air conditioning system that separates the functionality of a communication chip into a main control chip and additional circuits added to the communication loop. In other words, a portion of the communication chip's parsing functionality is integrated into the main control chip, allowing the main control chip to perform the communication chip's parsing functionality. Meanwhile, another portion of the communication chip's functionality is implemented by adding additional circuits to the communication loop, thereby replacing the functionality of the communication chip. This reduces the cost of the air conditioning system and promotes the further development of the air conditioning industry.

[0074] In some embodiments, as Figure 9 As shown, the communication circuit 50 further includes: a first clamping circuit 4 and a second clamping circuit 5 .

[0075] The first clamp circuit 4 includes two first ports 401 and two second ports 402. The two first ports 401 of the first clamp circuit 4 include a first sub-port 4011 and a second sub-port 4012; the two second ports 402 of the first clamp circuit 4 include a first sub-port 4021 and a second sub-port 4022 (see Figure 5 and Figure 6 ).

[0076] The second clamp circuit 5 includes two first ports 501 and two second ports 502. The two first ports 501 of the second clamp circuit 5 include a first sub-port 5011 and a second sub-port 5012; the two second ports 502 of the second clamp circuit 5 include a first sub-port 5021 and a second sub-port 5022 (see Figure 5 and Figure 6 ).

[0077] The two first ports 401 of the first clamping circuit 4 are electrically connected to the two first ports of the main control chip 1 respectively; the two second ports 402 of the first clamping circuit 4 are electrically connected to the two first ports 201 of the signal receiving side AC coupling circuit 2 respectively; the two first ports 501 of the second clamping circuit 5 are electrically connected to the two second ports 102 of the main control chip 1 respectively; the two second ports 502 of the second clamping circuit 5 are electrically connected to the two first ports 301 of the signal sending side AC coupling circuit 3 respectively.

[0078] The first clamping circuit 4 is configured to clamp the voltage of the signals at the two first ports 101 of the main control chip 1 within a specified range. The second clamping circuit 5 is configured to clamp the voltage of the signals at the two second ports 102 of the main control chip 1 within a specified range.

[0079] In some embodiments, the first clamping circuit 4 and the second clamping circuit 5 may be Schottky diodes or ordinary switching diodes.

[0080] The internal structure of the first clamping circuit 4 is specifically described by taking the first clamping circuit 4 as an example.

[0081] like Figure 10 As shown, the first clamping circuit 4 includes a third diode D3 and a fourth diode D4.

[0082] The cathode of the third diode D3 is electrically connected to the first signal line C, the anode of the third diode D3 and the anode of the fourth diode D4 are electrically connected to the ground terminal GND, and the cathode of the fourth diode D4 is electrically connected to the second signal line D.

[0083] For example, if the voltage of the load 600 is lower than the voltage of the ground terminal GND, the third diode D3 is turned on and the voltage of the load 600 is clamped at about -0.3V, thereby ensuring that the port of the main control chip 1 does not have an excessively low voltage.

[0084] Similarly, if the voltage of the load 600 is lower than the voltage of the ground terminal GND, the fourth diode D4 is turned on, and the voltage of the load 600 is clamped at about -0.3V, thereby ensuring that the port of the main control chip 1 does not have an excessively low voltage. The above-mentioned low voltage refers to a voltage below zero.

[0085] That is to say, when the above-mentioned load 600 is at an abnormally low voltage, the first clamping circuit 4 can clamp the voltage across the load 600 to about -0.3V based on the unidirectional conductivity of the third diode D3 and the fourth diode D4 and the voltage drop of the diode when the diode is turned on, thereby protecting the port of the main control chip and making the main control chip operate better.

[0086] In some embodiments, the port of the main control chip is a pin of the main control chip.

[0087] It should be noted that abnormally low voltage refers to a negative voltage that is lower than the allowable range. For example, -3V is an abnormally low voltage; -0.2V is not an abnormally low voltage. Whether it is an abnormal negative voltage can be determined based on the ability of the main control chip pin to withstand negative pressure.

[0088] like Figure 11 As shown, the communication circuit 50 further includes an anti-reverse circuit 6 and a balancing circuit 7 .

[0089] The anti-reverse circuit 6 includes two first ports 601 and two second ports 602. The two first ports 601 of the anti-reverse circuit 6 include a first sub-port 6011 and a second sub-port 6012; the two second ports 602 of the anti-reverse circuit 6 include a first sub-port 6021 and a second sub-port 6022 (see Figure 5 and Figure 6 ).

[0090] The balancing circuit 7 includes two first ports 701 and two second ports 702. The two first ports 701 of the balancing circuit 7 include a first sub-port 7011 and a second sub-port 7012; the two second ports 702 of the balancing circuit 7 include a first sub-port 7021 and a second sub-port 7022 (see Figure 5 and Figure 6 ).

[0091] The two first ports 601 of the anti-reverse circuit 6 are electrically connected to the two second ports 102 of the main control chip 1 respectively; the two second ports 602 of the anti-reverse circuit 6 are electrically connected to the two first ports 701 of the balancing circuit 7 respectively; the two second ports 702 of the balancing circuit 7 are electrically connected to the two first ports 501 of the second clamping circuit 5 respectively.

[0092] The anti-reverse circuit 6 is configured to prevent the signals on the first bus A and the second bus B from being transmitted to the main control chip 1 through the signal sending side AC coupling circuit 3. The balancing circuit 7 is configured to stabilize the voltage in the communication circuit 50 when there is no signal transmission in the communication circuit 50.

[0093] like Figure 12 As shown, the anti-reverse circuit 6 includes a first diode D1 and a second diode D2.

[0094] Reference Figure 11, wherein the anode of the first diode D1 is electrically connected to the first sub-port 6011 of the two first ports 601 of the anti-backward circuit 6, and the cathode of the first diode D1 is electrically connected to the first sub-port 6021 of the two second ports 602 of the anti-backward circuit 6; the anode of the second diode D2 is electrically connected to the second sub-port 6012 of the two first ports 601 of the anti-backward circuit 6, and the cathode of the second diode D2 is electrically connected to the second sub-port 6022 of the two second ports 602 of the anti-backward circuit 6.

[0095] For example, if the voltage at the first end of the load 600 is greater than the voltage of the second sub-port 1022 of the two second ports 102 of the main control chip 1, due to the unidirectional conductivity of the first diode D1, the voltage of the load 600 cannot reach the main control chip 1, thereby protecting the second sub-port 1022 of the main control chip 1.

[0096] Similarly, if the voltage at the second end of the load 600 is greater than the voltage at the first sub-port 1021 of the two second ports 102 of the main control chip 1, due to the unidirectional conductivity of the second diode D2, the voltage of the load 600 cannot reach the main control chip 1, thereby protecting the first sub-port 1021 of the main control chip 1.

[0097] That is, when the load 600 is at an abnormally high voltage, the abnormally high voltage refers to the voltage across the load 600 being greater than the voltage across the two second ports 102 of the main control chip. The anti-reverse circuit 6 can protect the pins of the main control chip based on the unidirectional conductivity of the first diode D1 and the second diode D2, thereby ensuring better operation of the main control chip.

[0098] In some embodiments, the first diode D1 and the second diode D2 are Schottky diodes. The first diode D1 and the second diode D2 may also be common switching diodes.

[0099] It should be noted that both types of diodes can conduct electricity in one direction and can be used in rectification applications. The difference is that ordinary switching diodes can be made to withstand higher voltages, while Schottky diodes have a faster recovery speed and can be used in high-frequency applications.

[0100] like Figure 13 As shown, the balancing circuit 7 includes: a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4.

[0101] A first end of the first resistor R1 is electrically connected to the power supply terminal VCC, a second end of the first resistor R1 is electrically connected to a first end of the second resistor R2 and also electrically connected to the first signal line C; a second end of the second resistor R2 is electrically connected to the ground terminal GND.

[0102] A first end of the third resistor R3 is electrically connected to the power supply terminal VCC, a second end of the third resistor R3 is electrically connected to a first end of the fourth resistor R4 and also electrically connected to the second signal line D; a second end of the fourth resistor R4 is electrically connected to the ground terminal GND.

[0103] The first signal line C and the second signal line D are connecting lines between two circuit modules.

[0104] In some embodiments, if the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are the same, the level on the first signal line C is VCC / 2, and the level on the second signal line A is also VCC / 2, that is, the levels on the first signal line C and the second signal line D are both the first level VCC / 2. At this time, the level on the first signal line C and the level on the second signal line D are differentiated to obtain a level of 0. Since 0 is a stable state, it can be ensured that the differential signal on the first signal line C and the second signal line D is at a stable low level when idle, thereby improving communication quality.

[0105] It should be noted that the differential calculation method is the level of the first signal line C minus the level of the second signal line D, for example: (VCC / 2-VCC / 2) = 0. It is sufficient to ensure that the level of the first signal line C and the level of the second signal line D are clamped at the same voltage.

[0106] In summary, when no signal is transmitted on the first signal line C and the second signal line D, the voltage levels on the first signal line C and the second signal line D are both clamped to the first voltage level, and the voltage levels are then differentiated to be zero. In other words, the resistance ratio of the third resistor R3 to the fourth resistor R4 is equal to the resistance ratio of the first resistor R1 to the second resistor R2.

[0107] For example, if the resistance of the first resistor R1 is 10kΩ and the resistance of the second resistor R2 is 30kΩ, the voltage level of the first signal line C is VCC / 4. If the resistance of the third resistor R3 is 20kΩ and the resistance of the fourth resistor R4 is 60kΩ, the voltage level of the second signal line D is also VCC / 4. In this case, the ratio of the resistance values ​​of the third resistor R3 and the fourth resistor R4 is equal to the ratio of the resistance values ​​of the first resistor R1 and the second resistor R2. At the same time, the voltage level of the first signal line C and the voltage level of the second signal line D are both clamped at VCC / 4, meeting the differential requirement.

[0108] In some embodiments, the resistance values ​​of the first resistor R1 , the second resistor R2 , the third resistor R3 and the fourth resistor R4 are all in the kΩ level.

[0109] like Figure 14 As shown, the communication circuit 50 further includes: a negative pressure protection circuit 8 and a bus driving circuit 9.

[0110] The negative voltage protection circuit 8 includes two first ports 801 . The two first ports 801 of the negative voltage protection circuit 8 include a first sub-port 8011 and a second sub-port 8012 .

[0111] The bus driving circuit 9 includes: two first ports 901, two second ports 902 and two third ports 903. The two first ports 901 of the bus driving circuit 9 include: a first sub-port 9011 and a second sub-port 9012; the two second ports 902 of the bus driving circuit 9 include: a first sub-port 9021 and a second sub-port 9022; the two third ports 903 of the bus driving circuit 9 include: a first sub-port 9031 and a second sub-port 9032 (see Figure 5 and Figure 6 ).

[0112] The main control chip 1 further includes: two third ports 103, the two third ports 103 of the main control chip 1 include: a first sub-port 1031 and a second sub-port 1032 (refer to Figure 5 and Figure 6 ).

[0113] The two first ports 801 of the negative voltage protection circuit 8 are electrically connected to the two second ports 902 of the bus drive circuit 9, respectively; and the two first ports 801 of the negative voltage protection circuit 8 are also electrically connected to the two first ports 301 of the signal sending side AC coupling circuit 3, respectively; the two first ports 901 of the bus drive circuit 9 are electrically connected to the two second ports 502 of the second clamping circuit 5, respectively; the two second ports 902 of the bus drive circuit 9 are electrically connected to the two first ports 301 of the signal sending side AC coupling circuit 3, respectively; the two third ports 903 of the bus drive circuit 9 are electrically connected to the two third ports 103 of the main control chip 1, respectively.

[0114] The negative voltage protection circuit 8 is configured to prevent abnormal negative voltage shocks on the first bus A and the second bus B. The bus driving circuit 9 is configured to improve the driving capability of the communication circuit 50 when the communication circuit 50 is at a low level.

[0115] It should be noted that Figure 14 The two main control chips in the figure are the same main control chip. The figure is to better show the ports of the main control chip and the connection method with other circuits.

[0116] It should be noted that if the communication circuit is in a low voltage state, the bus drive circuit 9 plays a role in the communication circuit to improve the driving capability of the communication circuit; if the communication circuit is in a non-low voltage state, the bus drive circuit 9 does not play a role in the communication circuit, and the bus drive circuit 9 can be regarded as a wire.

[0117] In some embodiments, the negative voltage protection circuit 8 may be a Schottky diode or a common switching diode.

[0118] In some embodiments, the bus driving circuit 9 may be a transistor.

[0119] In summary, the specific process of receiving and sending communication signals by the communication circuit in this application is as follows (refer to Figures 15 to 18 ):

[0120] It should be noted that when describing the ports of a circuit below, the two first ports or the two second ports are directly described. The two first ports and the two second ports already include the sub-ports in the port, and the sub-ports therein will not be directly described. Figures 11 to 14 For example, 101 is the upper label of the two first ports of the main control chip 1 and the upper label of the first sub-port 1011 and the second sub-port 1012 of the two first ports of the main control chip 1 .

[0121] like Figure 15 As shown, Figure 15 This refers to the master control chip receiving a first communication signal sent by the load 600. The first communication signal is transmitted via the first bus A and the second bus B to the two second ports (2021, 2022) of the signal receiving side AC coupling circuit 2. The signal receiving side AC coupling circuit 2 receives the first communication signal and transmits the useful AC signal via the two first ports (2011, 2012) of the signal receiving side AC coupling circuit 2 to the two second ports (4021, 4022) of the first clamping circuit 4. The first clamping circuit 4 receives the first communication signal and transmits it to the two first ports (1011, 1012) of the master control chip 1 via the two first ports (4011, 4012) of the first clamping circuit 4. Simultaneously, the first clamping circuit 4 clamps the voltages of the two first ports (1011, 1012) of the master control chip 1 to within a specified range. This transmits the first communication signal to the master control chip 1, which then analyzes the first communication signal.

[0122] like Figure 16 As shown, Figure 16 It refers to the second communication signal sent by the main control chip being transmitted to the load 600 .

[0123] If the voltage in the communication circuit 50 is not a low voltage, the process of transmitting the second communication signal from the main control chip to the load 600 is as follows: the main control chip 1 analyzes and calibrates the second communication signal. The second communication signal is then transmitted via the main control chip 1 and transmitted to the two first ports (6011, 6012) of the anti-reverse circuit 6 via the two second ports (6021, 6022) of the main control chip 1. The anti-reverse circuit 6 receives the second communication signal and transmits it to the two first ports (7011, 7012) of the balancing circuit 7 via the two second ports (7021, 7022) of the anti-reverse circuit 6. The balancing circuit 7 receives the second communication signal and transmits it to the two first ports (5011, 5012) of the second clamping circuit 5 via the two second ports (7021, 7022) of the balancing circuit 7. The second clamping circuit 5 receives the second communication signal and transmits the second communication signal to the two first ports (3011, 3012) of the signal-sending-side AC coupling circuit 3 via the two second ports (5021, 5022) of the second clamping circuit 5. The signal-sending-side AC coupling circuit 3 receives the second communication signal and transmits the useful AC signal to the first bus A and the second bus B via the two second ports (3021, 3022) of the signal-sending-side AC coupling circuit 2. Thus, the second communication signal is transmitted to the load 600, completing the communication work with the load 600.

[0124] If the voltage in the communication circuit 50 is low, the process of transmitting the second communication signal from the main control chip to the load 600 is as follows: the main control chip 1 analyzes and calibrates the second communication signal. The second communication signal is then transmitted via the main control chip 1 and transmitted to the two first ports (6011, 6012) of the anti-reverse circuit 6 via the two second ports (6021, 6022) of the main control chip 1. The anti-reverse circuit 6 receives the second communication signal and transmits it to the two first ports (7011, 7012) of the balancing circuit 7 via the two second ports (7021, 7022) of the anti-reverse circuit 6. The balancing circuit 7 receives the second communication signal and transmits it to the two first ports (5011, 5012) of the second clamping circuit 5 via the two second ports (7021, 7022) of the balancing circuit 7. The second clamping circuit 5 receives the second communication signal and transmits the second communication signal to the two first ports (9011, 9012) of the bus driving circuit 9 via the two second ports (9021, 9022) of the second clamping circuit 5. The bus driving circuit 9 receives the second communication signal and transmits it to the two first ports (3011, 3012) of the signal transmitting-side AC coupling circuit 3 via the two second ports (9021, 9022) of the bus driving circuit 9. The signal transmitting-side AC coupling circuit 3 receives the second communication signal and transmits the useful AC signal to the first bus A and the second bus B via the two second ports (3021, 3022) of the signal transmitting-side AC coupling circuit 2. The second communication signal is thereby transmitted to the load 600, completing communication with the load 600.

[0125] like Figure 17 As shown, if the voltage in the communication circuit 50 is low, the first communication signal is transmitted via the first bus A to the first sub-port 2021 of the two second ports (2021, 2022) of the signal receiving-side AC coupling circuit 2. The signal receiving-side AC coupling circuit 2 receives the first communication signal and transmits the useful AC signal via the first sub-port 2011 of the two first ports (2011, 2012) of the signal receiving-side AC coupling circuit 2 to the first sub-port 4021 of the two second ports (4021, 4022) of the first clamping circuit 4. The first clamping circuit 4 receives the first communication signal and transmits the first communication signal via the first sub-port 4011 of the two first ports (4011, 4012) of the first clamping circuit 4 to the first sub-port 1011 of the two first ports (1011, 1012) of the main control chip 1. The main control chip 1 then parses the first communication signal.

[0126] The process of transmitting the second communication signal sent by the main control chip to the load 600 is as follows: the main control chip 1 analyzes and calibrates the second communication signal. The second communication signal is sent by the main control chip 1 and transmitted through the first sub-port 1021 of the two second ports (1021, 1022) of the main control chip 1 to the second sub-port 6012 of the two first ports (6011, 6012) of the anti-backlash circuit 6. The anti-backlash circuit 6 receives the second communication signal and transmits the second communication signal to the second sub-port 7012 of the two first ports (7011, 7012) of the balancing circuit 7 through the second sub-port 7022 of the two second ports (7021, 7022) of the balancing circuit 7. The balancing circuit 7 receives the second communication signal and transmits the second communication signal to the second sub-port 5012 of the two first ports (5011, 5012) of the second clamping circuit 5 through the second sub-port 7022 of the two second ports (7021, 7022) of the balancing circuit 7. The second clamping circuit 5 receives the second communication signal and transmits the second communication signal to the second subport 9012 of the two first ports (9011, 9012) of the bus driving circuit 9 via the second subport 9022 of the two second ports (9021, 9022) of the second clamping circuit 5. The bus driving circuit 9 receives the second communication signal and transmits the second communication signal to the second subport 3012 of the two first ports (3011, 3012) of the signal transmitting-side AC coupling circuit 3 via the second subport 9022 of the two second ports (9021, 9022) of the bus driving circuit 9. The signal transmitting-side AC coupling circuit 3 receives the second communication signal and transmits the useful AC signal to the second bus B via the second subport 3022 of the two second ports (3021, 3022) of the signal transmitting-side AC coupling circuit 2. The second communication signal is thereby transmitted to the load 600, completing communication with the load 600.

[0127] like Figure 17As shown, if the voltage in the communication circuit 50 is not a low voltage, the first communication signal is transmitted via the first bus A to the first subport 2021 of the two second ports (2021, 2022) of the signal receiving-side AC coupling circuit 2. The signal receiving-side AC coupling circuit 2 receives the first communication signal and transmits the useful AC signal via the first subport 2011 of the two first ports (2011, 2012) of the signal receiving-side AC coupling circuit 2 to the first subport 4021 of the two second ports (4021, 4022) of the first clamping circuit 4. The first clamping circuit 4 receives the first communication signal and transmits the first communication signal via the first subport 4011 of the two first ports (4011, 4012) of the first clamping circuit 4 to the first subport 1011 of the two first ports (1011, 1012) of the main control chip 1. The main control chip 1 then parses the first communication signal.

[0128] The process of transmitting the second communication signal sent by the main control chip to the load 600 is as follows: the main control chip 1 analyzes and calibrates the second communication signal. The second communication signal is sent by the main control chip 1 and transmitted through the first sub-port 1021 of the two second ports (1021, 1022) of the main control chip 1 to the second sub-port 6012 of the two first ports (6011, 6012) of the anti-backlash circuit 6. The anti-backlash circuit 6 receives the second communication signal and transmits the second communication signal to the second sub-port 7012 of the two first ports (7011, 7012) of the balancing circuit 7 through the second sub-port 7022 of the two second ports (7021, 7022) of the balancing circuit 7. The balancing circuit 7 receives the second communication signal and transmits the second communication signal to the second sub-port 5012 of the two first ports (5011, 5012) of the second clamping circuit 5 through the second sub-port 7022 of the two second ports (7021, 7022) of the balancing circuit 7. The second clamping circuit 5 receives the second communication signal and transmits the second communication signal to the second sub-port 3012 of the two first ports (3011, 3012) of the signal-sending-side AC coupling circuit 3 via the second sub-port 5022 of the two second ports (5021, 5022) of the second clamping circuit 5. The signal-sending-side AC coupling circuit 3 receives the second communication signal and transmits the useful AC signal to the second bus B via the second sub-port 3022 of the two second ports (3021, 3022) of the signal-sending-side AC coupling circuit 2. The second communication signal is thereby transmitted to the load 600, completing the communication with the load 600.

[0129] like Figure 18As shown, if the voltage in the communication circuit 50 is low, the first communication signal is transmitted via the second bus B to the second subport 2022 of the two second ports (2021, 2022) of the signal receiving-side AC coupling circuit 2. The signal receiving-side AC coupling circuit 2 receives the first communication signal and transmits the useful AC signal via the second subport 2012 of the two first ports (2011, 2012) of the signal receiving-side AC coupling circuit 2 to the second subport 4022 of the two second ports (4021, 4022) of the first clamping circuit 4. The first clamping circuit 4 receives the first communication signal and transmits the first communication signal via the second subport 4012 of the two first ports (4011, 4012) of the first clamping circuit 4 to the second subport 1012 of the two first ports (1011, 1012) of the main control chip 1. The main control chip 1 then parses the first communication signal.

[0130] The process of transmitting the second communication signal sent by the main control chip to the load 600 is as follows: the main control chip 1 analyzes and calibrates the second communication signal. The second communication signal is sent by the main control chip 1 and transmitted to the first sub-port 6011 of the two first ports (6011, 6012) of the anti-backlash circuit 6 through the second sub-port 1022 of the two second ports (1021, 1022) of the main control chip 1. The anti-backlash circuit 6 receives the second communication signal and transmits the second communication signal to the first sub-port 7011 of the two first ports (7011, 7012) of the balancing circuit 7 through the first sub-port 7021 of the two second ports (7021, 7022) of the balancing circuit 7. The balancing circuit 7 receives the second communication signal and transmits the second communication signal to the first sub-port 5011 of the two first ports (5011, 5012) of the second clamping circuit 5 through the first sub-port 7021 of the two second ports (7021, 7022) of the balancing circuit 7. The second clamping circuit 5 receives the second communication signal and transmits the second communication signal to the first subport 9011 of the two first ports (9011, 9012) of the bus driving circuit 9 via the first subport 5021 of the two second ports (5021, 5022) of the second clamping circuit 5. The bus driving circuit 9 receives the second communication signal and transmits the second communication signal to the first subport 3011 of the two first ports (3011, 3012) of the signal transmitting-side AC coupling circuit 3 via the first subport 9021 of the two second ports (9021, 9022) of the bus driving circuit 9. The signal transmitting-side AC coupling circuit 3 receives the second communication signal and transmits the useful AC signal to the first bus A via the first subport 3021 of the two second ports (3021, 3022) of the signal transmitting-side AC coupling circuit 2. Thus, the second communication signal is transmitted to the load 600, completing the communication with the load 600.

[0131] like Figure 18 As shown, if the voltage in the communication circuit 50 is not a low voltage, the first communication signal is transmitted via the second bus B to the second subport 2022 of the two second ports (2021, 2022) of the signal receiving-side AC coupling circuit 2. The signal receiving-side AC coupling circuit 2 receives the first communication signal and transmits the useful AC signal via the second subport 2012 of the two first ports (2011, 2012) of the signal receiving-side AC coupling circuit 2 to the second subport 4022 of the two second ports (4021, 4022) of the first clamping circuit 4. The first clamping circuit 4 receives the first communication signal and transmits the first communication signal via the second subport 4012 of the two first ports (4011, 4012) of the first clamping circuit 4 to the second subport 1012 of the two first ports (1011, 1012) of the main control chip 1. The main control chip 1 then parses the first communication signal.

[0132] The process of transmitting the second communication signal sent by the main control chip to the load 600 is as follows: the main control chip 1 analyzes and calibrates the second communication signal. The second communication signal is sent by the main control chip 1 and transmitted to the first sub-port 6011 of the two first ports (6011, 6012) of the anti-backlash circuit 6 through the second sub-port 1022 of the two second ports (1021, 1022) of the main control chip 1. The anti-backlash circuit 6 receives the second communication signal and transmits the second communication signal to the first sub-port 7011 of the two first ports (7011, 7012) of the balancing circuit 7 through the first sub-port 7021 of the two second ports (7021, 7022) of the balancing circuit 7. The balancing circuit 7 receives the second communication signal and transmits the second communication signal to the first sub-port 5011 of the two first ports (5011, 5012) of the second clamping circuit 5 through the first sub-port 7021 of the two second ports (7021, 7022) of the balancing circuit 7. The second clamping circuit 5 receives the second communication signal and transmits the second communication signal to the first sub-port 3011 of the two first ports (3011, 3012) of the signal-sending-side AC coupling circuit 3 via the first sub-port 5021 of the two second ports (5021, 5022) of the second clamping circuit 5. The signal-sending-side AC coupling circuit 3 receives the second communication signal and transmits the useful AC signal to the first bus A via the first sub-port 3021 of the two second ports (3021, 3022) of the signal-sending-side AC coupling circuit 2. As a result, the second communication signal is transmitted to the load 600, completing the communication with the load 600.

[0133] It should be noted that for Figure 17 and Figure 18The way of receiving and sending signals requires a different anti-reverse circuit than other methods, so the anti-reverse circuit needs to be modified. ( Figure 17 and Figure 18 not described in the ).

[0134] In some embodiments, as Figure 19 As shown, the communication circuit in this application also includes: a terminal resistor 12 and an overvoltage protection circuit 13.

[0135] The first end of the terminal resistor 12 is electrically connected to the first bus A, and the second end of the terminal resistor 12 is electrically connected to the second bus B; the first end of the overvoltage protection circuit 13 is electrically connected to the first bus A, and the second end of the overvoltage protection circuit 13 is electrically connected to the second bus B.

[0136] The terminal resistor 12 is configured to reduce the transmission delay of the communication waveform in the communication loop. The overvoltage protection circuit 13 is configured to filter out abnormal peak voltages on the first bus A or the second bus B.

[0137] In some embodiments, the overvoltage protection circuit 13 may be a varistor, or a varistor and a diode connected in series.

[0138] like Figures 20 to 22 As shown, the communication circuit in the present application further includes: a first fuse 14 and / or a second fuse 15 .

[0139] like Figure 20 As shown, the communication circuit in the present application includes: a first fuse 14; a first end of the first fuse 14 is electrically connected to a first end of the overvoltage protection circuit 13, and a second end of the first fuse 14 is connected to the first bus A.

[0140] like Figure 21 As shown, the communication circuit in the present application includes: a second fuse 15; a first end of the second fuse 15 is electrically connected to the second end of the overvoltage protection circuit 13, and a second end of the second fuse 15 is connected to the second bus B.

[0141] like Figure 22 As shown, the communication circuit in the present application includes: a first fuse 14 and a second fuse 15; the first end of the first fuse 14 is electrically connected to the first end of the overvoltage protection circuit 13, and the second end of the first fuse 14 is connected to the first bus A; the first end of the second fuse 15 is electrically connected to the second end of the overvoltage protection circuit 13, and the second end of the second fuse 15 is connected to the second bus B.

[0142] To facilitate understanding of the solution of the present application, the following flowchart specifically describes the process of sending and receiving signals in the communication circuit.

[0143] like Figure 23As shown, the process of sending signals in the communication circuit is as follows (refer to Figures 16 to 20 ):

[0144] S101: The main control chip sends a signal, which is a second communication signal.

[0145] S102: The main control chip analyzes the signal.

[0146] S103: The main control chip performs self-transmission and self-reception calibration on the signal.

[0147] S104: Determine whether the signal is a normal signal. If the signal is a normal signal, proceed to the next step; if the signal is an abnormal signal, return to step S101 and continue the above steps.

[0148] S105: The signal passes through the anti-reverse circuit. The signal is sent to the anti-reverse circuit via the main control chip.

[0149] S106: The signal passes through the balancing circuit and is sent to the balancing circuit via the anti-reverse circuit.

[0150] S107: The signal passes through the second clamping circuit. The signal is sent to the second clamping circuit via the balancing circuit.

[0151] S108: The signal passes through the negative voltage protection circuit. The signal is sent from the second clamping circuit and passes through the negative voltage protection circuit.

[0152] S109: The signal passes through the AC coupling circuit on the signal sending side. The signal is transmitted to the AC coupling circuit on the signal sending side.

[0153] S110, the signal passes through the terminal resistor.

[0154] S111, the signal passes through the overvoltage protection circuit.

[0155] S112, the signal passes through the fuse.

[0156] S113: The signal is transmitted to the first bus and / or the second bus. The signal is sent to the load via the first bus and / or the second bus.

[0157] like Figure 24 As shown, the process of receiving signals in the communication circuit is as follows (refer to Figure 15 、 Figure 17 、 Figure 18 、 Figure 19 and Figure 20 ):

[0158] S201, bus sends signal: The load sends a signal to the communication loop via the first bus and / or the second bus.

[0159] S202: The signal passes through the fuse and overvoltage protection circuit.

[0160] S203: Passing through the terminal resistor: The signal passes through the terminal resistor.

[0161] S204: The signal passes through the AC coupling circuit on the signal receiving side. The signal is transmitted to the AC coupling circuit on the signal receiving side.

[0162] S205: The signal passes through the first clamping circuit. The signal is sent to the first clamping circuit via the signal receiving side AC coupling circuit.

[0163] S206: Signal analysis: The signal is sent to the main control chip via the first clamping circuit, and the main control chip analyzes the signal.

[0164] S207: Determine whether the signal is a normal signal. If the signal is a normal signal, proceed to the next step; if the signal is an abnormal signal, return to step S201 and continue the above steps.

[0165] S208, complete reception and reply: The signal transmitted by the load is analyzed and received by the main control chip, and the main control chip sends a new signal to the load to reply the signal.

[0166] In some embodiments, the load of the air-conditioning system may be an air-conditioning indoor unit or outdoor unit, a wired controller, a centralized controller, or other devices including differential communication.

Claims

1. An air conditioning system, characterized in that: include: a first bus and a second bus; A controller, the controller including a communication circuit; the controller is electrically connected to the load; The communication circuit includes: a main control chip, a signal receiving side AC coupling circuit and a signal sending side AC coupling circuit; The two first ports of the main control chip are respectively electrically connected to the two first ports of the signal receiving side AC coupling circuit, the two second ports of the main control chip are respectively electrically connected to the two first ports of the signal sending side AC coupling circuit, the two second ports of the signal receiving side AC coupling circuit are respectively electrically connected to the first bus and the second bus, and the two second ports of the signal sending side AC coupling circuit are respectively electrically connected to the first bus and the second bus; Among them, the main control chip includes a signal analysis module, and the main control chip is configured to analyze the received first communication signal and complete the reception when the first communication signal is a normal signal, and to analyze the generated second communication signal and complete the sending when the second communication signal is a normal signal.

2. The air conditioning system according to claim 1, characterized in that The communication circuit further includes: a first clamping circuit; The two first ports of the first clamping circuit are electrically connected to the two first ports of the main control chip respectively; the two second ports of the first clamping circuit are electrically connected to the two first ports of the signal receiving side AC coupling circuit respectively; The first clamping circuit is configured to clamp the voltages of signals at the two first ports of the main control chip to within a specified range.

3. The air conditioning system according to claim 2, characterized in that The communication circuit further includes: a second clamping circuit; The two first ports of the second clamping circuit are electrically connected to the two second ports of the main control chip respectively; the two second ports of the second clamping circuit are electrically connected to the two first ports of the signal sending side AC coupling circuit respectively; The second clamping circuit is configured to clamp the voltages of signals at the two second ports of the main control chip to within a specified range.

4. The air conditioning system according to claim 3, characterized in that The communication circuit further includes: an anti-reverse circuit; The two first ports of the anti-reverse circuit are electrically connected to the two second ports of the main control chip respectively; the two second ports of the anti-reverse circuit are electrically connected to the two first ports of the second clamping circuit respectively; The anti-reverse circuit is configured to prevent signals on the first bus and the second bus from being transmitted to the main control chip through the signal sending side AC coupling circuit.

5. The air conditioning system according to claim 4, characterized in that The communication circuit further includes: a balancing circuit; The two first ports of the balancing circuit are electrically connected to the two second ports of the anti-reverse circuit respectively; the two second ports of the balancing circuit are electrically connected to the two first ports of the second clamping circuit respectively; The balancing circuit is configured to stabilize the voltage in the communication loop when there is no signal transmission in the communication loop.

6. The air conditioning system according to claim 5, characterized in that The communication circuit also includes: a negative pressure protection circuit; The two first ports of the negative voltage protection circuit are electrically connected to the two second ports of the second clamp respectively; and the two first ports of the negative voltage protection circuit are also electrically connected to the two first ports of the signal sending side AC coupling circuit respectively; The negative voltage protection circuit is configured to prevent abnormal negative voltage shocks on the first bus and the second bus.

7. The air conditioning system according to claim 6, characterized in that The communication circuit also includes: a bus drive circuit; The two first ports of the bus drive circuit are respectively electrically connected to the two second ports of the second clamping circuit; the two second ports of the bus drive circuit are respectively electrically connected to the two first ports of the signal sending side AC coupling circuit; and the two third ports of the bus drive circuit are respectively electrically connected to the two third ports of the main control chip.

8. The air conditioning system according to any one of claims 1 to 7, characterized in that: The communication circuit further includes: a terminal resistor; A first end of the terminal resistor is electrically connected to the first bus, and a second end of the terminal resistor is electrically connected to the second bus; The terminal resistor is configured to reduce a transmission delay of a communication waveform in a communication loop.

9. The air conditioning system according to claim 8, characterized in that The communication circuit also includes: an overvoltage protection circuit; A first end of the overvoltage protection circuit is electrically connected to the first bus, and a second end of the overvoltage protection circuit is electrically connected to the second bus; The overvoltage protection circuit is configured to filter out abnormal spike voltage on the first bus or the second bus.

10. The air conditioning system according to claim 9, characterized in that The communication circuit further includes: a first fuse and / or a second fuse; A first end of the first fuse is electrically connected to a first end of the overvoltage protection circuit, and a second end of the first fuse is connected to the first bus; The first end of the second fuse is electrically connected to the second end of the overvoltage protection circuit, and the second end of the second fuse is connected to the second bus.

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