Driving circuit, driving method, pixel circuit, display panel, and display device

Abstract

The application provides a driving circuit, a driving method, a pixel circuit, a display panel and a display device. The driving circuit comprises a first switch circuit and a scanning signal generation circuit. The first switch circuit controls writing of a data signal provided by a data output end into the scanning signal generation circuit under control of a first gating control signal. The scanning signal generation circuit is configured to generate a scanning signal according to the data signal and output the scanning signal through a scanning signal output end. The application can control the scanning signal on a scanning line in at least part of a blank time period between two frame display times, so as to control, according to the scanning signal, whether to refresh a data voltage of a corresponding pixel circuit by controlling the transistor on the scanning line to be turned on or turned off in a next frame display time, and realize updating of a local picture on a screen.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a driving circuit, a driving method, a pixel circuit, a display panel and a display device. BACKGROUND

[0002] OLED (Organic Light Emitting Diode) display technology has the advantages of high contrast, fast response, low power consumption, etc. In order to further reduce power consumption, LTPO (Low Temperature Polycrystalline Oxide) display technology realized by combining LTPS (Low Temperature Polycrystalline Silicon) and IGZO (Indium Gallium Zinc Oxide) can realize low frame rate display, and reduce driving power consumption by reducing the repeated refreshing of static pictures. However, the existing OLED display still needs to initialize and write all pixel voltages within a frame when updating the picture. Under some special pictures, most of the pixel voltages on the whole screen do not need to be updated, that is, they can be maintained at the original display brightness by the low leakage LTPO TFT (Thin Film Transistor), and the repeated writing of these pixels causes waste of data line power consumption. SUMMARY

[0003] The main purpose of the present application is to provide a driving circuit, a driving method, a pixel circuit, a display panel and a display device, which solves the problem that the screen local picture update cannot be realized in the prior art.

[0004] The driving circuit provided by the embodiment of the present application comprises a first switch circuit and a scan signal generation circuit.

[0005] The first switch circuit is electrically connected with a first gate control line, a data output end of a source driver and the scan signal generation circuit, and is used for controlling the writing of a data signal provided by the data output end into the scan signal generation circuit under the control of a first gate control signal provided by the first gate control line.

[0006] The scan signal generation circuit is used for generating a scan signal according to the data signal, and outputting the scan signal through a scan signal output end.

[0007] Optionally, the driving circuit provided by at least one embodiment of the present application further comprises a second switch circuit.

[0008] The second switch circuit is respectively electrically connected with a second gate control line, the data output end and a data line included in a display panel, and is used for controlling the communication or disconnection between the data output end and the data line under the control of a second gate control signal provided by the second gate control line.

[0009] The first gate control line and the second gate control line are the same gate control line, or the first gate control line and the second gate control line are different.

[0010] Optionally, the first switch circuit comprises a first transistor and a first capacitor; the first switch circuit provides the data signal to the scan signal generation circuit through a control node;

[0011] a gate of the first transistor is electrically connected with the first gate control line, a first pole of the first transistor is electrically connected with the data output terminal, and a second pole of the first transistor is electrically connected with the control node;

[0012] a first end of the first capacitor is electrically connected with the control node, and a second end of the first capacitor is electrically connected with a direct current voltage terminal.

[0013] Optionally, the second switch circuit comprises a second transistor;

[0014] a gate of the second transistor is electrically connected with the second gate control line, a first pole of the second transistor is electrically connected with the data output terminal, and a second pole of the second transistor is electrically connected with the data line.

[0015] Optionally, the scan signal generation circuit comprises an output control circuit and an output circuit; the first switch circuit provides the data signal to the scan signal generation circuit through a control node;

[0016] the output control circuit is electrically connected with the control node, a first voltage terminal, a second voltage terminal, an output control terminal and a scan output terminal respectively, and is configured to control the output control terminal to be connected or disconnected with the first voltage terminal under the control of the potential of the control node, and control the output control terminal to be connected or disconnected with the second voltage terminal under the control of the signal provided by the scan output terminal;

[0017] the output circuit is electrically connected with a control terminal, the scan output terminal, the output control terminal, the first voltage terminal and the second voltage terminal respectively, and is configured to control the scan output terminal to be connected or disconnected with the first voltage terminal under the control of the control signal provided by the control terminal, and control the scan output terminal to be connected or disconnected with the second voltage terminal under the control of the potential of the output control terminal.

[0018] Optionally, the scan output terminal is the scan signal output terminal; or,

[0019] the scan signal generation circuit further comprises an inverting circuit; an input terminal of the inverting circuit is electrically connected with the scan output terminal, an output terminal of the inverting circuit is electrically connected with the scan signal output terminal, and the inverting circuit is configured to invert the voltage signal inputted by the input terminal to obtain an inverted voltage signal, and output the inverted voltage signal through the output terminal.

[0020] Optionally, the output control circuit comprises a third transistor and a fourth transistor;

[0021] The gate of the third transistor is electrically connected with the control node, the first pole of the third transistor is electrically connected with the first voltage terminal, and the second pole of the third transistor is electrically connected with the output control terminal.

[0022] The gate of the fourth transistor is electrically connected with the scan output terminal, the first pole of the fourth transistor is electrically connected with the output control terminal, and the second pole of the fourth transistor is electrically connected with the second voltage terminal.

[0023] The output circuit comprises a fifth transistor, a sixth transistor and a second capacitor.

[0024] The gate of the fifth transistor is electrically connected with the control terminal, the first pole of the fifth transistor is electrically connected with the first voltage terminal, and the second pole of the fifth transistor is electrically connected with the scan output terminal.

[0025] The gate of the sixth transistor is electrically connected with the output control terminal, the first pole of the sixth transistor is electrically connected with the scan output terminal, and the second pole of the sixth transistor is electrically connected with the second voltage terminal.

[0026] The first terminal of the second capacitor is electrically connected with the control terminal, and the second terminal of the second capacitor is electrically connected with the second voltage terminal.

[0027] The embodiment of the present application provides a driving method applied to the driving circuit, and the driving method comprises the following steps:

[0028] The first switch circuit controls the data signal provided by the data output terminal of the source driver to be written into the scan signal generation circuit under the control of the first gate control signal.

[0029] The scan signal generation circuit generates the scan signal according to the data signal, and outputs the scan signal to the corresponding column scan line of the display panel through the scan signal output terminal.

[0030] Optionally, the driving circuit further comprises a second switch circuit, and the driving method further comprises the following steps:

[0031] The second switch circuit controls the data output terminal of the source driver to be communicated with the corresponding column data line of the display panel under the control of the second gate control signal in the data writing period in one frame display time.

[0032] The embodiment of the present application provides a pixel circuit, which comprises a light emitting element, a light emitting driving circuit and a control circuit.

[0033] The light-emitting driving circuit is electrically connected with the first node and the first electrode of the light-emitting element respectively, and is used for generating a driving current for driving the light-emitting element under the control of the potential of the first node; and the second electrode of the light-emitting element is electrically connected with the third voltage terminal.

[0034] The control circuit is electrically connected with the first gate line, the scan line, the first node and the first electrode of the light-emitting element respectively, and is used for controlling the first node and the first electrode of the light-emitting element to be connected or disconnected under the control of the first gate driving signal provided by the first gate line and the scan signal provided by the scan line.

[0035] Optionally, the control circuit includes a first control circuit and a second control circuit; the first end of the light-emitting driving circuit is electrically connected with the second node, and the second end of the light-emitting driving circuit is electrically connected with the third node and the first electrode of the light-emitting element respectively.

[0036] The first control circuit is electrically connected with the first gate line, the first node and the intermediate node respectively, and is used for controlling the first node and the intermediate node to be connected or disconnected under the control of the first gate driving signal provided by the first gate line.

[0037] The second control circuit is electrically connected with the scan line, the intermediate node and the third node respectively, and is used for controlling the intermediate node and the third node to be connected or disconnected under the control of the scan signal provided by the scan line.

[0038] Optionally, the control circuit includes a first control circuit and a second control circuit; the first end of the light-emitting driving circuit is electrically connected with the second node, and the second end of the light-emitting driving circuit is electrically connected with the third node and the first electrode of the light-emitting element respectively.

[0039] The first control circuit is electrically connected with the first gate line, the third node and the intermediate node respectively, and is used for controlling the third node and the intermediate node to be connected or disconnected under the control of the first gate driving signal provided by the first gate line.

[0040] The second control circuit is electrically connected with the scan line, the intermediate node and the first node respectively, and is used for controlling the intermediate node and the first node to be connected or disconnected under the control of the scan signal provided by the scan line.

[0041] Optionally, the pixel circuit further includes a first initialization circuit; the first end of the light-emitting driving circuit is electrically connected with the second node, and the second end of the light-emitting driving circuit is electrically connected with the third node and the first electrode of the light-emitting element respectively.

[0042] The first initialization circuit is electrically connected with the first initial control end, the first initial voltage end and the second node respectively, and is configured to write the first initial voltage provided by the first initial voltage end into the second node under the control of a first initial control signal provided by the first initial control end.

[0043] Optionally, the pixel circuit further comprises a second initialization circuit, a first end of the light-emitting driving circuit is electrically connected with the second node, and a second end of the light-emitting driving circuit is electrically connected with the third node and the first electrode of the light-emitting element respectively.

[0044] The second initialization circuit is electrically connected with the second initial control end, the second initial voltage end and the third node respectively, and is configured to write the second initial voltage provided by the second initial voltage end into the third node under the control of a second initial control signal provided by the second initial control end.

[0045] Optionally, the pixel circuit further comprises a data writing circuit, a first light-emitting control circuit, a second light-emitting control circuit and an energy storage circuit, a first end of the light-emitting driving circuit is electrically connected with the second node, and a second end of the light-emitting driving circuit is electrically connected with the third node and the first electrode of the light-emitting element respectively.

[0046] The data writing circuit is electrically connected with the second gate line, the data line and the second node respectively, and is configured to write a data voltage provided by the data line into the second node under the control of a second gate driving signal provided by the second gate line.

[0047] The first light-emitting control circuit is electrically connected with the light-emitting control line, the power voltage end and the second node respectively, and is configured to control the power voltage end to be connected or disconnected with the second node under the control of a light-emitting control signal provided by the light-emitting control line.

[0048] The second light-emitting control circuit is electrically connected with the light-emitting control line, the third node and the first electrode of the light-emitting element respectively, and is configured to control the third node to be electrically connected with the first electrode of the light-emitting element under the control of the light-emitting control signal.

[0049] The energy storage circuit is electrically connected with the first node, and is configured to store electric energy.

[0050] Optionally, the pixel circuit further comprises a third initialization circuit.

[0051] The third initialization circuit is electrically connected with the first initial control end, the third initial voltage end and the first pole of the light emitting element respectively, and is configured to write the third initial voltage provided by the third initial voltage end into the first pole of the light emitting element under the control of a first initial control signal provided by the first initial control end.

[0052] Optionally, the first control circuit comprises a first control transistor, and the second control circuit comprises a second control transistor.

[0053] The gate of the first control transistor is electrically connected with the first gate line, the first pole of the first control transistor is electrically connected with the first node, and the second pole of the first control transistor is electrically connected with the intermediate node.

[0054] The gate of the second control transistor is electrically connected with the scan line, the first pole of the second control transistor is electrically connected with the intermediate node, and the second pole of the second control transistor is electrically connected with the third node.

[0055] Optionally, the first control circuit comprises a first control transistor, and the second control circuit comprises a second control transistor.

[0056] The gate of the first control transistor is electrically connected with the first gate line, the first pole of the first control transistor is electrically connected with the intermediate node, and the second pole of the first control transistor is electrically connected with the third node.

[0057] The gate of the second control transistor is electrically connected with the scan line, the first pole of the second control transistor is electrically connected with the first node, and the second pole of the second control transistor is electrically connected with the intermediate node.

[0058] Optionally, the first initialization circuit comprises a first initialization transistor.

[0059] The gate of the first initialization transistor is electrically connected with the first initial control end, the first pole of the first initialization transistor is electrically connected with the first initial voltage end, and the second pole of the first initialization transistor is electrically connected with the second node.

[0060] Optionally, the second initialization circuit comprises a second initialization transistor.

[0061] The gate of the second initialization transistor is electrically connected with the second initial control end, the first pole of the second initialization transistor is electrically connected with the second initial voltage end, and the second pole of the second initialization transistor is electrically connected with the third node.

[0062] Optionally, the data writing circuit comprises a writing transistor, the first light emitting control circuit comprises a first light emitting control transistor, the second light emitting control circuit comprises a second light emitting control transistor, the light emitting driving circuit comprises a driving transistor, and the energy storage circuit comprises a storage capacitor.

[0063] The gate of the writing transistor is electrically connected with the second gate line, the first electrode of the writing transistor is electrically connected with the data line, and the second electrode of the writing transistor is electrically connected with the second node.

[0064] The gate of the first light emitting control transistor is electrically connected with the light emitting control line, the first electrode of the first light emitting control transistor is electrically connected with the power voltage terminal, and the second electrode of the first light emitting control transistor is electrically connected with the second node.

[0065] The gate of the second light emitting control transistor is electrically connected with the light emitting control line, the first electrode of the second light emitting control transistor is electrically connected with the third node, and the second electrode of the second light emitting control transistor is electrically connected with the first electrode of the light emitting element.

[0066] The gate of the driving transistor is electrically connected with the first node, the first electrode of the driving transistor is electrically connected with the second node, and the second electrode of the driving transistor is electrically connected with the third node.

[0067] The first terminal of the storage capacitor is electrically connected with the first node, and the second terminal of the storage capacitor is electrically connected with the power voltage terminal.

[0068] Optionally, the third initialization circuit comprises a third initialization transistor.

[0069] The gate of the third initialization transistor is electrically connected with the first initial control terminal, the first electrode of the third initialization transistor is electrically connected with the third initial voltage terminal, and the second electrode of the third initialization transistor is electrically connected with the first electrode of the light emitting element.

[0070] The embodiment of the present application provides a pixel driving method applied to the pixel circuit, and the pixel driving method comprises the following steps.

[0071] The light emitting driving circuit generates a driving current for driving the light emitting element under the control of the potential of the first node.

[0072] The control circuit controls the communication or disconnection between the first node and the first electrode of the light emitting element under the control of the first gate driving signal and the scanning signal.

[0073] Optionally, the pixel circuit comprises a first initialization circuit, a first end of a light-emitting driving circuit is electrically connected with the second node, a second end of the light-emitting driving circuit is electrically connected with the third node and a first electrode of the light-emitting element respectively; the display period comprises a first initialization time period and a second initialization time period arranged in sequence; and the pixel driving method comprises:

[0074] In the first initialization time period, the control circuit controls the first node and the third node to be in communication under the control of the first gate driving signal and the scanning signal; the first initialization circuit writes the first initial voltage into the second node under the control of a first initial control signal; and the light-emitting driving circuit controls the second node and the third node to be in communication under the control of the potential of the first node.

[0075] In the second initialization time period, the control circuit controls the first node and the third node to be disconnected under the control of the first gate driving signal and the scanning signal; the first initialization circuit writes the first initial voltage into the second node under the control of the first initial control signal; and the light-emitting driving circuit controls the second node and the third node to be in communication under the control of the potential of the first node.

[0076] The display panel provided by the embodiment of the present application comprises a source driver and the above-mentioned driving circuit.

[0077] The source driver comprises a data output end.

[0078] Optionally, the display panel provided by the embodiment of the present application comprises a plurality of scanning lines.

[0079] The scanning signal output end in the scanning signal generation circuit in the driving circuit is electrically connected with the scanning lines.

[0080] Optionally, the display panel comprises a plurality of data lines.

[0081] The data output end is directly electrically connected with the data lines; or the driving circuit comprises a second switch circuit, the second switch circuit controls the data output end and the data lines to be in communication or disconnected under the control of a second gating control signal.

[0082] Optionally, the source driver is arranged at a first side edge of the display panel, and the driving circuit is arranged at the first side edge of the display panel; or

[0083] The source driver is arranged at a first side edge of the display panel, and the driving circuit is arranged at a second side edge of the display panel, the first side edge and the second side edge being opposite side edges.

[0084] Optionally, the display panel according to at least one of the embodiments of the present application further comprises the pixel circuit.

[0085] The embodiment of the present application further provides a display device comprising the display panel.

[0086] The embodiment of the present application can control the scanning signal on the scanning line in at least part of the blank time period between two display time periods, so as to control the transistor controlled by the scanning line to be turned on or turned off according to the scanning signal, and control whether the data voltage refresh is performed on the corresponding pixel circuit, so as to realize the update of the local picture on the screen, and the rest of the picture does not need to be charged and discharged for multiple times, thereby further reducing the power consumption of the OLED (Organic Light Emitting Diode) display, and realizing the ultra-low power consumption through the local update of the display picture. BRIEF DESCRIPTION OF DRAWINGS

[0087] Figure 1 is a structural diagram of the driving circuit according to at least one of the embodiments of the present application;

[0088] Figure 2 is a circuit diagram of the driving circuit according to at least one of the embodiments of the present application;

[0089] Figure 3 is a circuit diagram of the driving circuit according to at least one of the embodiments of the present application;

[0090] Figure 4 is a circuit diagram of the driving circuit according to at least one of the embodiments of the present application;

[0091] Figure 5 is a circuit diagram of the driving circuit according to at least one of the embodiments of the present application;

[0092] Figure 6A is a circuit diagram of the driving circuit according to at least one of the embodiments of the present application;

[0093] Figure 6B is a circuit diagram of the driving circuit according to at least one of the embodiments of the present application;

[0094] Figure 7 is a circuit diagram of the driving circuit according to at least one of the embodiments of the present application;

[0095] Figure 8 is a circuit diagram of the driving circuit according to at least one of the embodiments of the present application;

[0096] Figure 9 is a structural diagram of the driving circuit according to at least one of the embodiments of the present application;

[0097] Figure 10 is a structural diagram of the driving circuit according to at least one of the embodiments of the present application;

[0098] Figure 11 is a circuit diagram of the driving circuit according to at least one embodiment of the present application;

[0099] Figure 12 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 11

[0100] Figure 13 is a circuit diagram of the driving circuit according to at least one embodiment of the present application;

[0101] Figure 14 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 13

[0102] Figure 15 is a structure diagram of the pixel circuit according to at least one embodiment of the present application;

[0103] Figure 16 is a structure diagram of the pixel circuit according to at least one embodiment of the present application;

[0104] Figure 17 is a structure diagram of the pixel circuit according to at least one embodiment of the present application;

[0105] Figure 18 is a structure diagram of the pixel circuit according to at least one embodiment of the present application;

[0106] Figure 19 is a structure diagram of the pixel circuit according to at least one embodiment of the present application;

[0107] Figure 20 is a circuit diagram of the pixel circuit according to at least one embodiment of the present application;

[0108] Figure 21A is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 20

[0109] is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 21B Figure 20 is a circuit diagram of the pixel circuit according to at least one embodiment of the present application;

[0110] Figure 22 is a circuit diagram of the pixel circuit according to at least one embodiment of the present application;

[0111] Figure 23 is a circuit diagram of the pixel circuit according to at least one embodiment of the present application;

[0112] Figure 24 is a circuit diagram of the pixel circuit according to at least one embodiment of the present application;

[0113] Figure 25 ​​​is a structural diagram of the display panel according to at least one embodiment of the present application;

[0114] Figure 26 is a structural diagram of the display panel according to at least one embodiment of the present application;

[0115] Figure 27 is a structural diagram of the display panel according to at least one embodiment of the present application. DETAILED DESCRIPTION

[0116] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0117] The transistors used in all the embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one pole is called the first pole and the other pole is called the second pole.

[0118] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0119] The driving circuit according to the embodiments of the present application comprises a first switch circuit and a scan signal generation circuit.

[0120] The first switch circuit is electrically connected with a first gate control line, a data output end of a source driver and the scan signal generation circuit, and is used for controlling writing of a data signal provided by the data output end into the scan signal generation circuit under control of a first gate control signal provided by the first gate control line.

[0121] The scan signal generation circuit is used for generating a scan signal according to the data signal and outputting the scan signal through a scan signal output end.

[0122] In this embodiment of the invention, the driving circuit may include a first switching circuit and a scanning signal generation circuit. During at least a portion of the blank time period between two display frames, the first switching circuit, under the control of a first gating control signal, controls the data signal provided by the data output terminal to be written into the scanning signal generation circuit. The scanning signal generation circuit generates a scanning signal based on the data signal and provides the scanning signal to a column of scanning lines included in the display panel. Based on the scanning signal, the transistors controlled by the column of scanning lines are turned on or off during the next frame display time.

[0123] In practical implementation, when the transistor controlled by the scan line of the next frame is turned off during the display time of the next frame, the pixel circuit where the transistor is located does not write data voltage. The original display brightness can be maintained by the low leakage current transistor, avoiding the waste of some power caused by repeated writing of the pixel circuit.

[0124] When the transistor controlled by the scan line of the next frame is turned on during the display time, the pixel circuit where the transistor is located writes data voltage and refreshes the screen normally.

[0125] When updating an OLED (Organic Light Emitting Diode) display, all pixel circuits need to be initialized and data voltages written within one frame of display time. However, in certain special scenes (such as AOD (Always On Display), static scenes, or scenes with infrequent updates), the data voltages of most pixel circuits on the entire screen do not need to be updated. The original display brightness can be maintained by the low-leakage LTPO (Low Temperature Polycrystalline Oxide) TFT (Thin Film Transistor). Repeatedly writing data to these pixel circuits results in wasted power consumption on the data lines.

[0126] Based on this, embodiments of the present invention design a driving circuit that can control the scanning signal on a scanning line during at least a portion of the blank time period between two display frames. According to the scanning signal, the transistor controlled by the scanning line is turned on or off during the next display frame, thereby controlling whether to refresh the data voltage of the corresponding pixel circuit. This achieves the updating of a partial screen image, while the remaining images do not require multiple charging and discharging cycles, thus further reducing the power consumption of the OLED display, or achieving ultra-low power consumption through partial updating of the display image.

[0127] like Figure 1 As shown, the driving circuit described in this embodiment of the invention includes a first switching circuit 11 and a scanning signal generation circuit SD;

[0128] The first switching circuit 11 is electrically connected to the first gating control line SW1, the data output terminal S0 of the source driver, and the scan signal generation circuit SD, and is used to control the data signal provided by the data output terminal S0 to be written into the scan signal generation circuit SD under the control of the first gating control signal provided by the first gating control line SW1.

[0129] The scan signal generation circuit SD is used to generate a scan signal based on the data signal, and outputs the scan signal through the scan signal output terminal CG.

[0130] In at least one embodiment of the present invention, the first switching circuit 11 may be electrically connected to a data output terminal of the source driver.

[0131] Optionally, the first switching circuit includes a first transistor and a first capacitor; the first switching circuit provides the data signal to the scan signal generation circuit through a control node;

[0132] The gate of the first transistor is electrically connected to the first gating control line, the first terminal of the first transistor is electrically connected to the data output terminal, and the second terminal of the first transistor is electrically connected to the control node.

[0133] The first terminal of the first capacitor is electrically connected to the control node, and the second terminal of the first capacitor is electrically connected to the DC voltage terminal.

[0134] In at least one embodiment of the present invention, the data output terminal can be directly electrically connected to the data line, and the scan signal output terminal can be electrically connected to the scan line, but is not limited thereto.

[0135] like Figure 2 As shown, the pixel circuit labeled P11 is the first row and first column, the pixel circuit labeled P21 is the second row and first column, the pixel circuit labeled P31 is the third row and first column, and the pixel circuit labeled P41 is the fourth row and first column.

[0136] The lines labeled DL are data lines, the lines labeled CG are scan lines, the lines labeled NG1 are the first line of the first row, the lines labeled NG2 are the first line of the first row, the lines labeled NG3 are the first line of the third row, and the lines labeled NG4 are the first line of the fourth row.

[0137] The driving circuit described in at least one embodiment of the present invention includes a first switching circuit and a scanning signal generation circuit SD;

[0138] The first switching circuit includes a first transistor T1;

[0139] The gate of the first transistor T1 is electrically connected with the first gate control line SW1, the source of the first transistor T1 is connected with the data line DL, and the second electrode of the first transistor is electrically connected with the scan signal generation circuit SD.

[0140] The data output terminal S0 of the source driver is electrically connected with the data line DL.

[0141] The scan signal generation circuit SD is used for generating a scan signal according to a data signal provided by the data output terminal S0, and providing the scan signal to the scan line CGL.

[0142] In Figure 2 In at least one embodiment shown, T1 is a p-type transistor, and SW1 provides a low voltage signal to make T1 open between two frame display times.

[0143] Figure 3 At least one embodiment shown is different from Figure 2 In at least one embodiment shown, T1 is an n-type transistor, and SW1 provides a high voltage signal to make T1 open between two frame display times.

[0144] The driving circuit in at least one embodiment of the present application further comprises a second switch circuit.

[0145] The second switch circuit is electrically connected with a second gate control line, the data output terminal and the data line included in the display panel, respectively, and is used for controlling the data output terminal and the data line to be connected or disconnected under the control of a second gate control signal provided by the second gate control line.

[0146] The first gate control line and the second gate control line are the same gate control line, or the first gate control line and the second gate control line are different.

[0147] In the specific implementation, the driving circuit can further comprise a second switch circuit, and the second switch circuit controls the data output terminal and the data line to be connected or disconnected under the control of a second gate control signal.

[0148] Optionally, the second switch circuit comprises a second transistor.

[0149] The gate of the second transistor is electrically connected with the second gate control line, the first electrode of the second transistor is electrically connected with the data output terminal, and the second electrode of the second transistor is electrically connected with the data line.

[0150] As Figure 4As shown, P11 is a first row first column pixel circuit, P21 is a second row first column pixel circuit, P31 is a third row first column pixel circuit, and P41 is a fourth row first column pixel circuit;

[0151] DL is a data line, CG is a scan line, NG1 is a first row first gate line, NG2 is a second row first gate line, NG3 is a third row first gate line, and NG4 is a fourth row first gate line;

[0152] The driving circuit in at least one embodiment of the present application comprises a first switch circuit, a second switch circuit and a scan signal generation circuit SD;

[0153] The first switch circuit can comprise a first transistor T1;

[0154] The gate of T1 is electrically connected with a first gate control line SW1, the source of T1 is electrically connected with a data output terminal S0 of a source driver, and the drain of T1 is electrically connected with the scan signal generation circuit SD;

[0155] The second switch circuit 13 comprises a second transistor T2;

[0156] The gate of T2 is electrically connected with the first gate control line SW1, the source of T2 is electrically connected with a data line DL, and the drain of T2 is electrically connected with the data output terminal S0 of the source driver;

[0157] The scan signal generation circuit SD is configured to generate a scan signal according to a data signal provided by the data output terminal S0 and provide the scan signal to a scan line CGL.

[0158] In at least one embodiment as shown, Figure 4 In at least one embodiment as shown, T1 is a p-type transistor and T2 is an n-type transistor.

[0159] As shown in at least one embodiment of the present application, Figure 4 In at least one embodiment as shown, during at least part of the blank time period between two display times, SW1 provides a low voltage signal and T1 is turned on to write a data signal provided by the data output terminal S0 into the scan signal generation circuit SD, and the scan signal generation circuit SD is configured to generate a scan signal according to the data signal provided by the data output terminal S0 and provide the scan signal to the scan line CGL.

[0160] During one display time, SW1 provides a high voltage signal and T2 is turned on to control the communication between the data output terminal S0 and the data line DL.

[0161] Figure 5 In at least one embodiment as shown, the driving circuit is applied to a display panel comprising a plurality of pixel circuits arranged in a plurality of rows and a plurality of columns, Figure 4The difference between at least one embodiment shown is that T1 is an n-type transistor and T2 is a p-type transistor.

[0162] The application as Figure 5 At least one embodiment shown works as follows: during at least part of the blank time period between two display time periods, SW1 provides a high voltage signal and T1 is turned on to write the data signal provided by the data output terminal S0 to the scan signal generation circuit SD, which is used to generate a scan signal according to the data signal provided by the data output terminal S0 and provide the scan signal to the first column scan line CG1.

[0163] During one display time period, SW1 provides a low voltage signal and T2 is turned on to control the communication between the data output terminal S0 and the data line DL.

[0164] In Figure 4 , Figure 5 In at least one embodiment shown, the first gate control line and the second gate control line are the same gate control line.

[0165] As Figure 6A shown, P11 is the first row first column pixel circuit, P21 is the second row first column pixel circuit, P31 is the third row first column pixel circuit, and P41 is the fourth row first column pixel circuit.

[0166] DL is the data line, CG is the scan line, NG1 is the first row first gate line, NG2 is the first row first gate line, NG3 is the third row first gate line, and NG4 is the fourth row first gate line.

[0167] The driving circuit in at least one embodiment of the application comprises a first switch circuit, a second switch circuit and a scan signal generation circuit SD.

[0168] The first switch circuit can comprise a first transistor T1.

[0169] The gate of T1 is electrically connected to the first gate control line SW1, the source of T1 is electrically connected to the data line DL, and the drain of T1 is electrically connected to the scan signal generation circuit SD.

[0170] The second switch circuit 13 comprises a second transistor T2.

[0171] The gate of T2 is electrically connected to the second gate control line SW2, the source of T2 is electrically connected to the data line DL, and the drain of T2 is electrically connected to the data output terminal S0 of the source driver.

[0172] The scan signal generation circuit SD is configured to generate a scan signal according to a data signal provided by the data output terminal S0, and provide the scan signal to the scan line CGL.

[0173] In Figure 6A In at least one embodiment shown, the first gate control line and the second gate control line are different gate control lines.

[0174] In Figure 6A In at least one embodiment shown, T1 is a p-type transistor, and T2 is a p-type transistor.

[0175] In Figure 6A In at least one embodiment shown, during at least part of the blank time period between two display time periods, SW1 provides a low voltage signal, SW2 provides a high voltage signal, and T1 is turned on to write a data signal provided by the data output terminal S0 into the scan signal generation circuit SD, which is configured to generate a scan signal according to the data signal provided by the data output terminal S0, and provide the scan signal to the scan line CGL.

[0176] During a display time period, SW2 provides a low voltage signal, SW1 provides a high voltage signal, and T2 is turned on to control the communication between the data output terminal S0 and the data line DL.

[0177] Figure 6B In at least one embodiment shown, the difference between the at least one embodiment shown and Figure 6A In at least one embodiment shown, T1 is an n-type transistor, and T2 is an n-type transistor.

[0178] In Figure 6B In at least one embodiment shown, during at least part of the blank time period between two display time periods, SW1 provides a high voltage signal, SW2 provides a low voltage signal, and T1 is turned on to write a data signal provided by the data output terminal S0 into the scan signal generation circuit SD, which is configured to generate a scan signal according to the data signal provided by the data output terminal S0, and provide the scan signal to the scan line CGL.

[0179] During a display time period, SW2 provides a high voltage signal, SW1 provides a low voltage signal, and T2 is turned on to control the communication between the data output terminal S0 and the data line DL.

[0180] In Figure 2 to Figure 6B In at least one embodiment shown, the scan signal generation circuit and the source driver are arranged on the same side of the display panel. In actual operation, the scan signal generation circuit and the source driver can be arranged on opposite sides of the display panel.

[0181] Figure 7 At least one embodiment shown in the specification is different from Figure 2 At least one embodiment shown in the specification is different from

[0182] Figure 8 At least one embodiment shown in the specification is different from Figure 3 At least one embodiment shown in the specification is different from

[0183] In at least one embodiment of the application, the scan signal generation circuit comprises an output control circuit and an output circuit; the first switch circuit provides the data signal to the scan signal generation circuit through a control node;

[0184] The output control circuit is electrically connected with the control node, the first voltage terminal, the second voltage terminal, the output control terminal and the scan output terminal respectively, and is used for controlling the output control terminal to be connected or disconnected with the first voltage terminal under the control of the potential of the control node, and controlling the output control terminal to be connected or disconnected with the second voltage terminal under the control of the signal provided by the scan output terminal;

[0185] The output circuit is electrically connected with the control terminal, the scan output terminal, the output control terminal, the first voltage terminal and the second voltage terminal respectively, and is used for controlling the scan output terminal to be connected or disconnected with the first voltage terminal under the control of the control signal provided by the control terminal, and controlling the scan output terminal to be connected or disconnected with the second voltage terminal under the control of the potential of the output control terminal.

[0186] In the specific implementation, the scan signal generation circuit can comprise an output control circuit and an output circuit, the output control circuit controls the output control terminal to be connected or disconnected with the first voltage terminal under the control of the potential of the control node, and controls the output control terminal to be connected or disconnected with the second voltage terminal under the control of the signal provided by the scan output terminal; the output circuit controls the scan output terminal to be connected or disconnected with the first voltage terminal under the control of the control signal provided by the control terminal, and controls the scan output terminal to be connected or disconnected with the second voltage terminal under the control of the potential of the output control terminal.

[0187] Optionally, the scan output terminal is the scan signal output terminal; or,

[0188] The scan signal generation circuit further comprises an inverting circuit; an input end of the inverting circuit is electrically connected with the scan output end, and an output end of the inverting circuit is electrically connected with the scan signal output end; the inverting circuit is used for inverting a voltage signal inputted at the input end to obtain an inverted voltage signal, and outputting the inverted voltage signal through the output end.

[0189] As shown in Figure 9 The first switch circuit 11 is electrically connected with the first gate control line SW1, the data output end S0 of the source driver and the control node NC respectively, and is used for controlling the data output end S0 and the control node NC to be connected or disconnected under the control of the first gate control signal provided by the first gate control line SW1.

[0190] The scan signal generation circuit comprises an output control circuit 71 and an output circuit 72.

[0191] The output control circuit 71 is electrically connected with the control node NC, a first voltage end V1, a second voltage end V2, an output control end OE and a scan signal output end CG respectively, and is used for controlling the output control end OE and the first voltage end V1 to be connected or disconnected under the control of the potential of the control node NC, and controlling the output control end OE and the second voltage end V2 to be connected or disconnected under the control of the signal provided by the scan signal output end CG.

[0192] The output circuit 72 is electrically connected with a control end VHRD, the output control end OE, the scan signal output end CG, the first voltage end V1 and the second voltage end V2 respectively, and is used for controlling the scan signal output end CG and the first voltage end V1 to be connected or disconnected under the control of the potential of the control signal provided by the control end VHRD, and controlling the scan signal output end CG and the second voltage end V2 to be connected or disconnected under the control of the potential of the output control end OE.

[0193] In Figure 9 In at least one embodiment of the scan signal generation circuit shown in the figure, the scan output end can be a scan signal output end CG, the first voltage end can be a high voltage end, and the second voltage end can be a low voltage end, but is not limited thereto.

[0194] As shown in Figure 10 The first switch circuit 11 is electrically connected with the first gate control line SW1, the data output end S0 of the source driver and the control node NC respectively, and is used for controlling the data output end S0 and the control node NC to be connected or disconnected under the control of the first gate control signal provided by the first gate control line SW1.

[0195] The scan signal generation circuit comprises an output control circuit 71 and an output circuit 72;

[0196] The output control circuit 71 is electrically connected with the control node NC, the first voltage terminal V1, the second voltage terminal V2, the output control terminal OE and the scan output terminal OP respectively, and is configured to control the output control terminal OE to be connected or disconnected with the first voltage terminal V1 under the control of the potential of the control node NC1, and control the output control terminal OE to be connected or disconnected with the second voltage terminal V2 under the control of the signal provided by the scan output terminal OP.

[0197] The output circuit 72 is electrically connected with the control terminal VHRD, the scan output terminal OP, the output control terminal OE, the first voltage terminal V1 and the second voltage terminal V2 respectively, and is configured to control the scan output terminal OP to be connected or disconnected with the first voltage terminal V1 under the control of the potential of the control terminal VHRD, and control the scan output terminal OP to be connected or disconnected with the second voltage terminal V2 under the control of the potential of the output control terminal OE.

[0198] The scan signal generation circuit further comprises an inverting circuit 73.

[0199] The input end of the inverting circuit 73 is electrically connected with the scan output terminal OP, and the output end of the inverting circuit 73 is electrically connected with the scan signal output terminal CG, and the inverting circuit 73 is configured to invert the voltage signal inputted by the input end to obtain an inverted voltage signal, and output the inverted voltage signal through the output end of the inverting circuit 73.

[0200] Optionally, the output control circuit comprises a third transistor and a fourth transistor.

[0201] The gate of the third transistor is electrically connected with the control node, the first pole of the third transistor is electrically connected with the first voltage terminal, and the second pole of the third transistor is electrically connected with the output control terminal.

[0202] The gate of the fourth transistor is electrically connected with the scan output terminal, the first pole of the fourth transistor is electrically connected with the output control terminal, and the second pole of the fourth transistor is electrically connected with the second voltage terminal.

[0203] The output circuit comprises a fifth transistor, a sixth transistor and a second capacitor.

[0204] The gate of the fifth transistor is electrically connected with the control terminal, the first pole of the fifth transistor is electrically connected with the first voltage terminal, and the second pole of the fifth transistor is electrically connected with the scan output terminal.

[0205] A gate of the sixth transistor is electrically connected with the output control end, a first pole of the sixth transistor is electrically connected with the scan output end, and a second pole of the sixth transistor is electrically connected with the second voltage end.

[0206] A first end of the second capacitor is electrically connected with the control end, and a second end of the second capacitor is electrically connected with the second voltage end.

[0207] As shown in Figure 11 As shown in Figure 9 Based on at least one embodiment shown in the drawings,

[0208] The first switch circuit comprises a first transistor T1 and a first capacitor C1.

[0209] A gate of the first transistor T1 is electrically connected with the first gating control line SW1, a source of the first transistor is electrically connected with the data output end S0, and a drain of the first transistor T1 is electrically connected with the control node NC.

[0210] A first end of the first capacitor C1 is electrically connected with the control node NC, and a second end of the first capacitor C1 is electrically connected with the low voltage end VGL.

[0211] The output control circuit comprises a third transistor T3 and a fourth transistor T4.

[0212] A gate of the third transistor T3 is electrically connected with the control node NC, a source of the third transistor T3 is electrically connected with the high voltage end VGH, and a drain of the third transistor T3 is electrically connected with the output control end OE.

[0213] A gate of the fourth transistor T4 is electrically connected with the scan signal output end CG, a source of the fourth transistor T4 is electrically connected with the output control end OE, and a drain of the fourth transistor T4 is electrically connected with the low voltage end VGL.

[0214] The output circuit comprises a fifth transistor T5, a sixth transistor T6 and a second capacitor C2.

[0215] A gate of the fifth transistor T5 is electrically connected with the control end VHRD, a source of the fifth transistor T5 is electrically connected with the high voltage end VGH, and a drain of the fifth transistor T5 is electrically connected with the scan signal output end CG.

[0216] A gate of the sixth transistor T6 is electrically connected with the output control end OE, a source of the sixth transistor T6 is electrically connected with the scan signal output end CG, and a drain of the sixth transistor T6 is electrically connected with the low voltage end VGL.

[0217] The first end of the second capacitor C2 is electrically connected with the control end VHRD, and the second end of the second capacitor C2 is electrically connected with the low voltage end VGL.

[0218] In Figure 11 In at least one embodiment of the scan signal generation circuit shown, the control voltage end is a second voltage end, the first voltage end is a high voltage end, and the second voltage end is a low voltage end, but the application is not limited thereto.

[0219] In Figure 11 In at least one embodiment of the scan signal generation circuit shown, S0 can be electrically connected with the corresponding column data line DL.

[0220] In Figure 11 In at least one embodiment shown, T1 is a p-type transistor, T3 is a p-type transistor, T4 is an n-type transistor, T5 is a p-type transistor, and T6 is an n-type transistor.

[0221] In Figure 11 In at least one embodiment shown, the control end VHRD is used for a 3V voltage signal, the high voltage end VGH can be used to provide an 8V voltage signal, and the low voltage end VGL can be used to provide a -8V voltage signal.

[0222] In at least one embodiment of the application, the voltage value of the control signal provided by the control end VHRD can be greater than or equal to 3V and less than or equal to 4V, the voltage value of the high voltage signal provided by the high voltage end VGH can be greater than or equal to 7V and less than or equal to 9V, and the voltage value of the low voltage signal provided by the low voltage end VGL can be greater than or equal to -9V and less than or equal to -7V, but the application is not limited thereto.

[0223] As Figure 12 shown, Figure 11 In at least one embodiment shown, TB1 is a first blank time period, TB2 is a second control time period, TX1 is a first data write time period, and TX2 is a second data write time period.

[0224] In part of the first blank time period TB1, SW1 provides a low voltage signal, T1 is turned on, S0 provides a high voltage signal, the data line DL is connected to the high voltage signal, the potential of NC is a high voltage, T5 is turned on, CG is connected to VGH, the potential of CG is a high voltage, T4 is turned on to connect OE to VGL, and OE outputs a low voltage signal;

[0225] In the first data write time period TX1, the potential of CG is maintained as a high voltage.

[0226] In part of the time in the second blank time period TB2, SW1 provides a low voltage signal, T1 is open, S0 provides a low voltage signal, DL accesses a low voltage signal, the potential of NC is a low voltage, T3 is open, OE is communicated with VGH, the potential of OE is a high voltage, T6 is open, and CG outputs a low voltage signal;

[0227] In the second data writing time period TX2, the potential of CG is maintained as a low voltage.

[0228] Figure 11 In part of the time in the first blank time period TB1, the voltage value of the high voltage signal accessed by DL can be 7V in at least one of the embodiments shown.

[0229] In part of the time in the second blank time period TB2, the voltage value of the low voltage signal accessed by DL can be 0V.

[0230] But it is not limited thereto.

[0231] The present application Figure 11 In part of the time in the second blank time period TB2, the opening degree of T6 is higher than that of T5, so that CG outputs a low voltage signal in at least one of the embodiments shown.

[0232] As Figure 13 shown, Figure 10 on the basis of at least one of the embodiments shown,

[0233] The first switch circuit comprises a first transistor T1 and a first capacitor C1.

[0234] The gate of the first transistor T1 is electrically connected with the first gate control line SW1, the source of the first transistor is electrically connected with the data output end S0, and the drain of the first transistor T1 is electrically connected with the control node NC.

[0235] The first end of the first capacitor C1 is electrically connected with the control node NC, and the second end of the first capacitor C1 is electrically connected with the low voltage end VGL.

[0236] The output control circuit comprises a third transistor T3 and a fourth transistor T4.

[0237] The gate of the third transistor T3 is electrically connected with the control node NC, the source of the third transistor T3 is electrically connected with the high voltage end VGH, and the drain of the third transistor T3 is electrically connected with the output control end OE.

[0238] The gate of the fourth transistor T4 is electrically connected with the control node NC, the source of the fourth transistor T4 is electrically connected with the output control end OE, and the drain of the fourth transistor T4 is electrically connected with the low voltage end VGL.

[0239] The output circuit comprises a fifth transistor T5 and a sixth transistor T6.

[0240] The gate of the fifth transistor T5 is electrically connected with the control end VHRD, the source of the fifth transistor T5 is electrically connected with the high voltage end VGH, and the drain of the fifth transistor T5 is electrically connected with the scan output end OP.

[0241] The gate of the sixth transistor T6 is electrically connected with the output control end OE, the source of the sixth transistor T6 is electrically connected with the scan output end OP, and the drain of the sixth transistor T6 is electrically connected with the low voltage end VGL.

[0242] The inverting circuit comprises an inverter IV.

[0243] The input end of the inverter IV is electrically connected with the scan output end OP, the output end of the inverter IV is electrically connected with the scan signal output end CG, the inverter IV is used for inverting the voltage signal inputted by the input end to obtain an inverted voltage signal, and the inverted voltage signal is outputted through the output end of the inverter IV.

[0244] In at least one embodiment of the scan signal generation circuit shown in Figure 13 In at least one embodiment of the scan signal generation circuit shown in the drawings, the first voltage end is a high voltage end, and the second voltage end is a low voltage end, but the present application is not limited thereto.

[0245] In at least one embodiment of the scan signal generation circuit shown in Figure 13 In at least one embodiment of the scan signal generation circuit shown in the drawings, S0 can be electrically connected with the data line DL.

[0246] In at least one embodiment of the scan signal generation circuit shown in Figure 13 In at least one embodiment of the scan signal generation circuit shown in the drawings, the control end VHRD is used for a 3V voltage signal, the high voltage end VGH can be used for providing an 8V voltage signal, and the low voltage end VGL can be used for providing a -8V voltage signal.

[0247] Figure 13 In at least one embodiment of the scan signal generation circuit shown in the drawings, the first blank time period, the first data writing time period, the second blank time period and the second data writing time period can be sequentially set.

[0248] At least part of the time in the first blank time period, SW1 provides a low voltage signal, T1 is open, S0 provides a high voltage signal, DL accesses a high voltage signal, the potential of NC is high voltage, T5 is open, OP is communicated between VGH, the potential of OP is high voltage, T4 is open, so that OE is communicated between VGL, OE outputs a low voltage signal; CG outputs a low voltage signal;

[0249] In the first data write time period, the potential of CG is maintained as a low voltage;

[0250] At least part of the time in the second blank time period, SW1 provides a low voltage signal, T1 is open, S0 provides a low voltage signal, DL accesses a low voltage signal, the potential of NC is low voltage, T3 is open, OE is communicated between VGH, the potential of OE is high voltage, T6 is open, OP outputs a low voltage signal; CG outputs a high voltage signal;

[0251] In the second data write time period, the potential of CG is maintained as a high voltage.

[0252] Figure 13 At least one embodiment shown in operation, in the first blank time period, the voltage value of the high voltage signal accessed by DL can be 7V;

[0253] In the second blank time period TB2, the voltage value of the low voltage signal accessed by DL can be 0V;

[0254] But not limited to this.

[0255] The application Figure 13 At least one embodiment shown in operation, in the second blank time period, the opening degree of T6 is higher than that of T5, so that OP outputs a low voltage signal.

[0256] Figure 14 The Figure 13 The simulation working timing diagram of at least one embodiment of the scan signal generation circuit.

[0257] The driving method described in the embodiment of the application is applied to the driving circuit described above, and the driving method comprises the following steps:

[0258] The first switch circuit controls writing of a data signal provided by a data output end of a source driver into the scan signal generation circuit under control of a first gate control signal;

[0259] The scan signal generation circuit generates a scan signal according to the data signal and outputs the scan signal to a corresponding column scan line of a display panel through a scan signal output end.

[0260] In the driving method, at least part of the blank time between two display times, the first switch circuit controls the writing of the data signal provided by the data output terminal of the source driver into the scan signal generation circuit under the control of the first gate control signal; the scan signal generation circuit generates a scan signal according to the data signal provided by the data output terminal, and outputs the scan signal to the corresponding column scan line of the display panel through the scan signal output terminal.

[0261] In at least one embodiment of the present application, the driving circuit further comprises a second switch circuit; and the driving method further comprises:

[0262] In the data writing time period in a display time, the second switch circuit controls the communication between the data output terminal of the source driver and the corresponding column data line of the display panel under the control of the second gate control signal.

[0263] In specific implementation, the driving circuit can further comprise a second switch circuit, and in the data writing time period in a display time, the second switch circuit controls the communication between the data output terminal and the corresponding column data line of the display panel under the control of the second gate control signal, so as to provide the data voltage to the data line.

[0264] The pixel circuit in the embodiment of the present application comprises a light emitting element, a light emitting driving circuit and a control circuit.

[0265] The light emitting driving circuit is electrically connected with the first node and the first electrode of the light emitting element respectively, and is used for generating a driving current for driving the light emitting element under the control of the potential of the first node; the second electrode of the light emitting element is electrically connected with the third voltage terminal.

[0266] The control circuit is electrically connected with the first gate line, the scan line, the first node and the first electrode of the light emitting element respectively, and is used for controlling the communication or disconnection between the first node and the first electrode of the light emitting element under the control of the first gate driving signal provided by the first gate line and the scan signal provided by the scan line.

[0267] In specific implementation, the pixel circuit can comprise a control circuit and a light emitting driving circuit, the light emitting driving circuit generates a driving current under the control of the potential of the first node, and the control circuit controls the communication or disconnection between the first node and the first electrode of the light emitting element under the control of the first gate driving signal provided by the first gate line and the scan signal provided by the scan line; the driving current can be a current for driving the light emitting element to emit light.

[0268] In at least one embodiment of the present application, the third voltage terminal can be a low voltage terminal, but is not limited thereto.

[0269] Optionally, the light emitting element is an organic light emitting diode, the first electrode of the light emitting element is an anode, and the second electrode of the light emitting element is a cathode.

[0270] As shown in Figure 15 the pixel circuit can include a light emitting element E0, a control circuit 201, and a light emitting driving circuit 230;

[0271] The light emitting driving circuit 230 is electrically connected with the first node N1 and the first electrode of the light emitting element E0 respectively, for generating a driving current for driving the light emitting element E0 under the control of the potential of the first node N1; the second electrode of the light emitting element E0 is electrically connected with a third voltage terminal V3.

[0272] The control circuit 201 is electrically connected with a first gate line NG, a scan line CGL, the first node N1, and the first electrode of the light emitting element E0 respectively, for controlling the communication or disconnection between the first node N1 and the first electrode of the light emitting element E0 under the control of a first gate driving signal provided by the first gate line NG and a scan signal provided by the scan line CGL.

[0273] In at least one embodiment of the present application, the control circuit includes a first control circuit and a second control circuit; a first end of the light emitting driving circuit is electrically connected with a second node, and a second end of the light emitting driving circuit is electrically connected with a third node and the first electrode of the light emitting element respectively;

[0274] The first control circuit is electrically connected with the first gate line, the first node, and an intermediate node respectively, and the first control circuit is used for controlling the communication or disconnection between the first node and the intermediate node under the control of a first gate driving signal provided by the first gate line;

[0275] The second control circuit is electrically connected with a scan line, the intermediate node, and the third node respectively, and the second control circuit is used for controlling the communication or disconnection between the intermediate node and the third node under the control of a scan signal provided by the scan line.

[0276] In specific implementation, the control circuit can include a first control circuit and a second control circuit, the first control circuit controls the communication or disconnection between the first node and the intermediate node under the control of a first gate driving signal provided by the first gate line, and the second control circuit controls the communication or disconnection between the intermediate node and the third node under the control of a scan signal provided by the scan line.

[0277] As shown in Figure 16 in Figure 15The control circuit includes a first control circuit 241 and a second control circuit 242 based on at least one embodiment of the pixel circuit shown; a first end of the light-emitting driving circuit 230 is electrically connected to the second node N2, and a second end of the light-emitting driving circuit 230 is electrically connected to the third node N3 and the first electrode of the light-emitting element E0, respectively;

[0278] The first control circuit 241 is electrically connected to the first gate line NG, the first node N1, and an intermediate node NZ, respectively, for controlling the communication or disconnection between the first node N1 and the intermediate node NZ under the control of a first gate driving signal provided by the first gate line NG;

[0279] The second control circuit 242 is electrically connected to the scan line CGL, the intermediate node NZ, and the third node N3, respectively, for controlling the communication or disconnection between the intermediate node NZ and the third node N3 under the control of a scan signal provided by the scan line CGL.

[0280] In at least one embodiment of the present application, the control circuit includes a first control circuit and a second control circuit; a first end of the light-emitting driving circuit is electrically connected to a second node, and a second end of the light-emitting driving circuit is electrically connected to a third node and a first electrode of the light-emitting element, respectively;

[0281] The first control circuit is electrically connected to the first gate line, the third node, and an intermediate node, respectively, for controlling the communication or disconnection between the third node and the intermediate node under the control of a first gate driving signal provided by the first gate line;

[0282] The second control circuit is electrically connected to the scan line, the intermediate node, and the first node, respectively, for controlling the communication or disconnection between the intermediate node and the first node under the control of a scan signal provided by the scan line.

[0283] In specific implementation, the control circuit can include a first control circuit and a second control circuit, the first control circuit controls the communication or disconnection between the third node and the intermediate node under the control of a first gate driving signal provided by the first gate line; and the second control circuit controls the communication or disconnection between the intermediate node and the first node under the control of a scan signal provided by the scan line.

[0284] As shown in Figure 17 the control circuit can include a first control circuit and a second control circuit, the first control circuit controls the communication or disconnection between the third node and the intermediate node under the control of a first gate driving signal provided by the first gate line; and the second control circuit controls the communication or disconnection between the intermediate node and the first node under the control of a scan signal provided by the scan line. Figure 15The control circuit includes a first control circuit 241 and a second control circuit 242 based on at least one embodiment of the pixel circuit shown, a first end of the light-emitting driving circuit 230 is electrically connected with the second node N2, and a second end of the light-emitting driving circuit 230 is respectively electrically connected with the third node N3 and the first electrode of the light-emitting element E0;

[0285] The first control circuit 241 is electrically connected with the first gate line NG, the third node N3 and an intermediate node NZ respectively, and is used for controlling the third node N3 and the intermediate node NZ to be connected or disconnected under the control of a first gate driving signal provided by the first gate line NG.

[0286] The second control circuit 242 is electrically connected with the scan line CGL, the intermediate node NZ and the first node N1 respectively, and is used for controlling the intermediate node NZ and the first node N1 to be connected or disconnected under the control of a scan signal provided by the scan line CGL.

[0287] The pixel circuit in at least one embodiment of the present application further includes a first initialization circuit; a first end of the light-emitting driving circuit is electrically connected with a second node, and a second end of the light-emitting driving circuit is respectively electrically connected with a third node and a first electrode of the light-emitting element.

[0288] The first initialization circuit is electrically connected with a first initial control end, a first initial voltage end and the second node respectively, and is used for writing a first initial voltage provided by the first initial voltage end into the second node under the control of a first initial control signal provided by the first initial control end.

[0289] In specific implementation, the display period can include a first initialization time period and a second initialization time period arranged in sequence.

[0290] In the first initialization time period, the control circuit controls the first node and the third node to be connected under the control of the first gate driving signal and the scan signal; the first initialization circuit writes the first initial voltage into the second node under the control of the first initial control signal; and the light-emitting driving circuit controls the second node and the third node to be connected under the control of the potential of the first node.

[0291] In the second initialization time period, the control circuit controls the first node and the third node to be disconnected under the control of the first gate driving signal and the scan signal; the first initialization circuit writes the first initial voltage into the second node under the control of the first initial control signal; and the light-emitting driving circuit controls the second node and the third node to be connected under the control of the potential of the first node.

[0292] The pixel circuit in at least one embodiment of the present application is used in work, and in a first initialization time period, the potentials of the first node, the second node and the third node are initialized before data writing, so as to reduce subsequent charging difference. In a second initialization time period, the first initialization circuit writes the first initial voltage to the second node, and the light-emitting driving circuit controls the communication between the second node and the third node, so that the driving transistor included in the light-emitting driving circuit is in a bias state, and the hysteresis phenomenon can be improved.

[0293] The pixel circuit in at least one embodiment of the present application further comprises a second initialization circuit; the first end of the light-emitting driving circuit is electrically connected with the second node, and the second end of the light-emitting driving circuit is electrically connected with the third node and the first electrode of the light-emitting element respectively.

[0294] The second initialization circuit is electrically connected with the second initial control end, the second initial voltage end and the third node respectively, and is used for writing the second initial voltage provided by the second initial voltage end to the third node under the control of the second initial control signal provided by the second initial control end.

[0295] In specific implementation, the pixel circuit can further comprise a second initialization circuit.

[0296] In a third initialization time period arranged between the first initialization time period and the second initialization time period, before the data writing time period, the second initialization circuit writes the second initial voltage to the third node under the control of the second initial control signal, so that the driving transistor included in the light-emitting driving circuit can be turned on at the beginning of the data writing time period, and data voltage writing and threshold voltage compensation are facilitated.

[0297] In at least one embodiment of the present application, the pixel circuit further comprises a data writing circuit, a first light-emitting control circuit, a second light-emitting control circuit and an energy storage circuit; the first end of the light-emitting driving circuit is electrically connected with the second node, and the second end of the light-emitting driving circuit is electrically connected with the third node and the first electrode of the light-emitting element respectively.

[0298] The data writing circuit is electrically connected with the second gate line, the data line and the second node respectively, and is used for writing the data voltage provided by the data line to the second node under the control of the second gate driving signal provided by the second gate line.

[0299] The first light-emitting control circuit is electrically connected with the light-emitting control line, the power voltage end and the second node respectively, and is used for controlling the communication or disconnection between the power voltage end and the second node under the control of the light-emitting control signal provided by the light-emitting control line.

[0300] The second light-emitting control circuit is electrically connected with the light-emitting control line, the third node and the first electrode of the light-emitting element respectively, and is used for controlling the third node to be electrically connected with the first electrode of the light-emitting element under the control of the light-emitting control signal.

[0301] The energy storage circuit is electrically connected with the first node, and is used for storing electric energy.

[0302] In a specific implementation, the pixel circuit can further include a data writing circuit, a first light-emitting control circuit, a second light-emitting control circuit and an energy storage circuit; the data writing circuit is used for writing a data voltage into the second node; the first light-emitting control circuit and the second light-emitting control circuit are used for controlling a light-emitting path to be turned on; and the energy storage circuit is used for storing electric energy.

[0303] The pixel circuit according to at least one embodiment of the present application further includes a third initialization circuit.

[0304] The third initialization circuit is electrically connected with a first initial control end, a third initial voltage end and the first electrode of the light-emitting element respectively, and is used for writing a third initial voltage provided by the third initial voltage end into the first electrode of the light-emitting element under the control of a first initial control signal provided by the first initial control end.

[0305] In a specific implementation, the pixel circuit can further include a third initialization circuit, which writes a third initial voltage into the first electrode of the light-emitting element under the control of a first initial control signal, so as to control the light-emitting element not to emit light and clear residual charges in the first electrode of the light-emitting element.

[0306] As shown in Figure 18 As shown in Figure 16 On the basis of at least one embodiment of the pixel circuit shown in the figure, the pixel circuit according to at least one embodiment of the present application can further include a first initialization circuit 231, a second initialization circuit 232, a data writing circuit 233, a first light-emitting control circuit 234, a second light-emitting control circuit 235, an energy storage circuit 236 and a third initialization circuit 237; the second electrode of the light-emitting element E0 is electrically connected with a low-level end ELVSS.

[0307] The first initialization circuit 231 is electrically connected with a first initial control end HR, a first initial voltage end I1 and the second node N2 respectively, and is used for writing a first initial voltage Vinit1 provided by the first initial voltage end I1 into the second node N2 under the control of a first initial control signal provided by the first initial control end HR.

[0308] The second initialization circuit 232 is electrically connected with the second initial control end PR, the second initial voltage end I2 and the third node N3 respectively, and is configured to write the second initial voltage Vinit2 provided by the second initial voltage end I2 into the third node N3 under the control of the second initial control signal provided by the second initial control end PR;

[0309] The data writing circuit 233 is electrically connected with the second gate line PG, the data line DT and the second node N2 respectively, and is configured to write the data voltage Vdata provided by the data line DT into the second node N2 under the control of the second gate driving signal provided by the second gate line PG;

[0310] The first light-emitting control circuit 234 is electrically connected with the light-emitting control line E1, the power voltage end ELVDD and the second node N2 respectively, and is configured to control the power voltage end ELVDD and the second node N2 to be connected or disconnected under the control of the light-emitting control signal provided by the light-emitting control line E1;

[0311] The second light-emitting control circuit 235 is electrically connected with the light-emitting control line E1, the third node N3 and the first electrode of the light-emitting element E0 respectively, and is configured to control the third node N3 and the first electrode of the light-emitting element E0 to be electrically connected under the control of the light-emitting control signal, and the second electrode of the light-emitting element E0 is electrically connected with the third voltage end V3;

[0312] The energy storage circuit 236 is electrically connected with the first node N1, and is configured to store electric energy;

[0313] The third initialization circuit 237 is electrically connected with the first initial control end HR, the third initial voltage end I3 and the first electrode of the light-emitting element E0 respectively, and is configured to write the third initial voltage Vinit3 provided by the third initial voltage end I3 into the first electrode of the light-emitting element E0 under the control of the first initial control signal provided by the first initial control end HR.

[0314] In at least one embodiment of the pixel circuit shown in the figure, the third voltage end is a low voltage end ELVSS. Figure 18 As shown in the figure, in at least one embodiment of the pixel circuit, the first initial control end HR is electrically connected with the first initial voltage end I1.

[0315] Figure 19 As shown in the figure, in at least one embodiment of the pixel circuit, the second initial control end PR is electrically connected with the second initial voltage end I2. Figure 17 Based on at least one embodiment of the pixel circuit shown in the figure, the pixel circuit in at least one embodiment of the present application can further include a first initialization circuit 231, a second initialization circuit 232, a data writing circuit 233, a first light-emitting control circuit 234, a second light-emitting control circuit 235, an energy storage circuit 236 and a third initialization circuit 237; and the second electrode of the light-emitting element E0 is electrically connected with a low voltage end ELVSS. ​

[0316] The first initialization circuit 231 is electrically connected to the first initial control terminal HR, the first initial voltage terminal I1 and the second node N2 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second node N2 under the control of the first initial control signal provided by the first initial control terminal HR.

[0317] The second initialization circuit 232 is electrically connected to the second initial control terminal PR, the second initial voltage terminal I2 and the third node N3 respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the third node N3 under the control of the second initial control signal provided by the second initial control terminal PR.

[0318] The data writing circuit 233 is electrically connected to the second gate line PG, the data line DT and the second node N2 respectively, and is used to write the data voltage Vdata provided by the data line DT into the second node N2 under the control of the second gate drive signal provided by the second gate line PG.

[0319] The first light-emitting control circuit 234 is electrically connected to the light-emitting control line E1, the power supply voltage terminal ELVDD and the second node N2 respectively, and is used to control the connection or disconnection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light-emitting control signal provided by the light-emitting control line E1.

[0320] The second light-emitting control circuit 235 is electrically connected to the light-emitting control line E1, the third node N3 and the first pole of the light-emitting element E0, respectively, and is used to control the third node N3 to be electrically connected to the first pole of the light-emitting element E0 under the control of the light-emitting control signal, and the second pole of the light-emitting element E0 to be electrically connected to the third voltage terminal V3.

[0321] The energy storage circuit 236 is electrically connected to the first node N1 and is used to store electrical energy.

[0322] The third initialization circuit 237 is electrically connected to the first initial control terminal HR, the third initial voltage terminal I3, and the first electrode of the light-emitting element E0, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E0 under the control of the first initial control signal provided by the first initial control terminal HR.

[0323] exist Figure 19 In at least one embodiment of the pixel circuit shown, the third voltage terminal is a low-level terminal ELVSS.

[0324] Optionally, the first control circuit comprises a first control transistor, and the second control circuit comprises a second control transistor;

[0325] The gate of the first control transistor is electrically connected with the first gate line, the first pole of the first control transistor is electrically connected with the first node, and the second pole of the first control transistor is electrically connected with the intermediate node;

[0326] The gate of the second control transistor is electrically connected with the scan line, the first pole of the second control transistor is electrically connected with the intermediate node, and the second pole of the second control transistor is electrically connected with the third node.

[0327] Optionally, the first control circuit comprises a first control transistor, and the second control circuit comprises a second control transistor;

[0328] The gate of the first control transistor is electrically connected with the first gate line, the first pole of the first control transistor is electrically connected with the intermediate node, and the second pole of the first control transistor is electrically connected with the third node.

[0329] The gate of the second control transistor is electrically connected with the scan line, the first pole of the second control transistor is electrically connected with the first node, and the second pole of the second control transistor is electrically connected with the intermediate node.

[0330] Optionally, the first initialization circuit comprises a first initialization transistor;

[0331] The gate of the first initialization transistor is electrically connected with the first initial control end, the first pole of the first initialization transistor is electrically connected with the first initial voltage end, and the second pole of the first initialization transistor is electrically connected with the second node.

[0332] Optionally, the second initialization circuit comprises a second initialization transistor;

[0333] The gate of the second initialization transistor is electrically connected with the second initial control end, the first pole of the second initialization transistor is electrically connected with the second initial voltage end, and the second pole of the second initialization transistor is electrically connected with the third node.

[0334] Optionally, the data writing circuit comprises a writing transistor, the first light-emitting control circuit comprises a first light-emitting control transistor, the second light-emitting control circuit comprises a second light-emitting control transistor, the light-emitting driving circuit comprises a driving transistor, and the energy storage circuit comprises a storage capacitor;

[0335] A gate of the write transistor is electrically connected with the second gate line, a first electrode of the write transistor is electrically connected with the data line, and a second electrode of the write transistor is electrically connected with the second node;

[0336] A gate of the first light-emitting control transistor is electrically connected with the light-emitting control line, a first electrode of the first light-emitting control transistor is electrically connected with the power voltage terminal, and a second electrode of the first light-emitting control transistor is electrically connected with the second node;

[0337] A gate of the second light-emitting control transistor is electrically connected with the light-emitting control line, a first electrode of the second light-emitting control transistor is electrically connected with the third node, and a second electrode of the second light-emitting control transistor is electrically connected with the first electrode of the light-emitting element;

[0338] A gate of the drive transistor is electrically connected with the first node, a first electrode of the drive transistor is electrically connected with the second node, and a second electrode of the drive transistor is electrically connected with the third node;

[0339] A first terminal of the storage capacitor is electrically connected with the first node, and a second terminal of the storage capacitor is electrically connected with the power voltage terminal.

[0340] Optionally, the third initialization circuit comprises a third initialization transistor;

[0341] A gate of the third initialization transistor is electrically connected with the first initial control terminal, a first electrode of the third initialization transistor is electrically connected with the third initial voltage terminal, and a second electrode of the third initialization transistor is electrically connected with the first electrode of the light-emitting element.

[0342] As shown in Figure 20 At least one embodiment of the pixel circuit is shown in Figure 18 On the basis of the at least one embodiment of the pixel circuit, the first control circuit comprises a first control transistor M1, the second control circuit comprises a second control transistor M2, and the light-emitting drive circuit comprises a drive transistor M0;

[0343] A gate of the first control transistor M1 is electrically connected with the first gate line NG, a source of the first control transistor M1 is electrically connected with the first node N1, and a second electrode of the first control transistor M1 is electrically connected with an intermediate node NZ;

[0344] A gate of the second control transistor M2 is electrically connected with the scan line CGL, a source of the second control transistor M2 is electrically connected with the intermediate node NZ, and a drain of the second control transistor M2 is electrically connected with the third node N3;

[0345] A gate of the driving transistor M0 is electrically connected with the first node N1, a source of the driving transistor M0 is electrically connected with the second node N2, and a drain of the driving transistor M0 is electrically connected with the third node N3;

[0346] The first initialization circuit comprises a first initialization transistor M3;

[0347] A gate of the first initialization transistor M3 is electrically connected with the first initial control end HR, a source of the first initialization transistor M3 is electrically connected with the first initial voltage end I1, and a drain of the first initialization transistor M3 is electrically connected with the second node N2; the first initial voltage end I1 is used for providing a first initial voltage Vinit1;

[0348] The second initialization circuit comprises a second initialization transistor M4;

[0349] A gate of the second initialization transistor M4 is electrically connected with the second initial control end PR, a source of the second initialization transistor M4 is electrically connected with the second initial voltage end I2, and a drain of the second initialization transistor M4 is electrically connected with the third node N3; the second initial voltage end I2 is used for providing a second initial voltage Vinit2;

[0350] The data writing circuit comprises a writing transistor M5, the first light-emitting control circuit comprises a first light-emitting control transistor M6, the second light-emitting control circuit comprises a second light-emitting control transistor M7, the energy storage circuit comprises a storage capacitor Cst, and the light-emitting element is an organic light-emitting diode O1;

[0351] A gate of the writing transistor M5 is electrically connected with the second gate line PG, a source of the writing transistor M5 is electrically connected with the data line DT, and a drain of the writing transistor M5 is electrically connected with the second node N2;

[0352] A gate of the first light-emitting control transistor M6 is electrically connected with the light-emitting control line E1, a source of the first light-emitting control transistor M6 is electrically connected with the power voltage end ELVDD, and a drain of the first light-emitting control transistor M6 is electrically connected with the second node N2;

[0353] A gate of the second light-emitting control transistor M7 is electrically connected with the light-emitting control line E1, a source of the second light-emitting control transistor M7 is electrically connected with the third node N3, and a drain of the second light-emitting control transistor M7 is electrically connected with an anode of the organic light-emitting diode O1;

[0354] A first end of the storage capacitor Cst is electrically connected with the first node N1, and a second end of the storage capacitor Cst is electrically connected with the power voltage end ELVDD;

[0355] The third initialization circuit includes a third initialization transistor M8;

[0356] The gate of the third initialization transistor M8 is electrically connected to the first initial control terminal HR, the source of the third initialization transistor M8 is electrically connected to the third initial voltage terminal I3, and the drain of the third initialization transistor M8 is electrically connected to the anode of the organic light-emitting diode O1.

[0357] The cathode of the organic light-emitting diode O1 is electrically connected to the low-level terminal ELVSS.

[0358] exist Figure 20 In at least one embodiment of the pixel circuit shown, M1 and M2 are n-type transistors, and the other transistors are p-type transistors, but this is not a limitation.

[0359] like Figure 21A As shown, the present invention Figure 20 When at least one embodiment of the pixel circuit shown is in operation, a frame display time may include a first initialization time period TI1, a third initialization time period TI3, a data writing time period TX, a second initialization time period TI2, and a light emission time period TF, which are set sequentially; during the frame display time, CG may output a high voltage signal to control M2 to be turned on.

[0360] During the first initialization period TI1, the third initialization period TI3, and the data writing period TX, NG outputs a high voltage signal to control M1 to conduct.

[0361] During the first initialization period TI1, the third initialization period TI3, the data writing period TX, and the second initialization period TI2, E1 provides a high voltage signal, and M6 and M7 are turned off.

[0362] During the second initialization period TI2 and the emission period TF, NG outputs a low voltage signal to control M1 to turn off;

[0363] During the first initialization period TI1, HR outputs a low voltage signal, PR and PG both output high voltage signals, M3 is turned on to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second node N2, M0 is turned on to control the connection between N2 and N3, M1 and M2 are turned on to control the connection between N1 and N3, so as to initialize the potential of the first node N1, the potential of the second node N2 and the potential of the third node N3, in order to reduce the difference in subsequent charging.

[0364] In the third initialization time period TI3, the PR outputs a low voltage signal, the HR and the PG both output high voltage signals, and the M4 is turned on to write the second initial voltage Vinit2 provided by the I2 into the third node N3, so that the M0 can be turned on at the beginning of the data writing time period TX;

[0365] In the data writing time period TX, the HR and the PR both output high voltage signals, the PG outputs a low voltage signal, and the M5 is turned on to provide the data voltage Vdata to the N2 by the DT;

[0366] At the beginning of the data writing time period TX, the M0 is turned on, and the Vdata charges the Cst until the potential of the first node N1 becomes Vdata+Vth, and the M0 is turned off; wherein, the Vth is the threshold voltage of the M0.

[0367] In the second initialization time period TI2, the HR outputs a low voltage signal, the PR and the PG both output high voltage signals, and the M3 is turned on to write the Vinit1 into the second node N2, and the M0 is turned on to make the N2 and the N3 communicate, at this time, the potential of the N1 is a smaller positive voltage, the potential of the N2 and the potential of the N3 are higher positive voltages, the M0 is in a bias state, and all the driving transistors included in the display panel are in a bias state, so that the hysteresis phenomenon can be improved.

[0368] In at least one embodiment of the present application, the voltage value of the Vinit1 can be a positive value, for example, the voltage value of the Vinit1 can be greater than or equal to 4V and less than or equal to 7V.

[0369] The voltage value of the Vinit2 and the voltage value of the Vinit3 can be negative values, for example, the voltage value of the Vinit2 and the voltage value of the Vinit3 can be greater than or equal to-5V and less than or equal to-3V.

[0370] But not limited to this.

[0371] The present application Figure 20 At least one embodiment of the pixel circuit shown in the present application works as follows: in the first initialization time period, the potential of the N1, the potential of the N2 and the potential of the N3 are all set to a reference voltage, so that in the data writing time period, the data voltage of the previous frame display time will not affect the writing of the data voltage of the current frame.

[0372] Figure 20 At least one embodiment of the pixel circuit shown in the present application works as follows: when the data voltage refresh of the pixel circuit is not needed, the CG needs to output a low voltage signal in at least part of the blank time period between two frame display times, and the CG needs to continuously output a low voltage signal in the following frame display time to control the M2 to be turned off, so that the data voltage writing will not be performed, the display picture is maintained, and the picture is not refreshed.

[0373] When data voltage refresh of the pixel circuit is needed, the CG is controlled to output a high voltage signal at least in part of the blank time period between two frame display times, and the CG continuously outputs the high voltage signal in the next frame display time to control the M2 to be turned on to perform data voltage writing in the data writing time period to refresh the picture.

[0374] In Figure 21A In the working timing diagram shown, a frame display time can be a refresh frame.

[0375] As Figure 21B shown, the present application Figure 20 At least one embodiment of the pixel circuit shown in operation, the holding frame can include a holding initial time period TBC and a holding light-emitting time period TBF arranged in sequence;

[0376] In the holding initial time period TBC, the HR outputs a low voltage signal, the NG outputs a low voltage signal, the PR and the PG both output a high voltage signal, the E1 provides a high voltage signal, the M1 is turned off to control the N1 and the N3 to be disconnected, the M6 and the M7 are turned off, the M5 is turned off; the M3 and the M8 are turned on, the I1 provides a first initial voltage Vinit1 to the second node N2, the driving transistor M0 is turned on to control the N2 and the N3 to be connected, the potential of the second node N2 and the potential of the third node N3 are initialized to improve the hysteresis phenomenon; the I3 provides a third initial voltage Vinit3 to the third node N3, and the potential of the anode of the O1 is initialized to control the O1 not to emit light and clear the residual charge of the anode of the O1;

[0377] In the holding light-emitting time period TBF, the E1 provides a low voltage signal, the HR provides a high voltage signal, the NG outputs a low voltage signal, the PR and the PG both output a high voltage signal, the M1, the M2, the M3, the M4, the M5 and the M8 are all turned off, the M6 and the M7 are turned on, and the M0 drives the O1 to emit light.

[0378] Figure 22 At least one embodiment of the pixel circuit shown in the difference with Figure 20 At least one embodiment of the pixel circuit shown in the difference with

[0379] Figure 22 At least one embodiment of the pixel circuit shown in operation, when data voltage refresh of the pixel circuit is not needed, the CG is controlled to output a high voltage signal at least in part of the blank time period between two frame display times, and the CG continuously outputs a low voltage signal in the next frame display time to control the M2 to be turned off so that data voltage writing is not performed to maintain the display picture and not refresh the picture;

[0380] When it is needed to refresh the data voltage of the pixel circuit, at least part of the time in the blank time period between two frame display times, the CG is controlled to output a low voltage signal, and in the following frame display time, the CG continuously outputs a high voltage signal to control the M2 to be turned on to write the data voltage in the data writing time period to refresh the picture.

[0381] Figure 23 At least one embodiment of the pixel circuit shown in the figure is different from Figure 20 At least one embodiment of the pixel circuit shown in the figure is different from

[0382] The gate of the first control transistor M1 is electrically connected with the first gate line NG, the source of the first control transistor M1 is electrically connected with the intermediate node NZ, and the drain of the first control transistor M1 is electrically connected with the third node N3.

[0383] The gate of the second control transistor M2 is electrically connected with the scan line CGL, the source of the second control transistor M2 is electrically connected with the first node N1, and the drain of the second control transistor M2 is electrically connected with the intermediate node NZ.

[0384] In Figure 23 In at least one embodiment of the pixel circuit shown in the figure, M1 and M2 are both n-type transistors.

[0385] Figure 23 At least one embodiment of the pixel circuit shown in the figure is different from

[0386] When it is needed to refresh the data voltage of the pixel circuit, at least part of the time in the blank time period between two frame display times, the CG is controlled to output a low voltage signal, and in the following frame display time, the CG continuously outputs a high voltage signal to control the M2 to be turned on to write the data voltage in the data writing time period to refresh the picture.

[0387] Figure 24 At least one embodiment of the pixel circuit shown in the figure is different from Figure 23 At least one embodiment of the pixel circuit shown in the figure is different from

[0388] Figure 24At least one embodiment of the pixel circuit is configured to, when the pixel circuit needs to be refreshed, control the CG to output a low voltage signal during at least part of a blank time period between two frame display times, and control the CG to continuously output a high voltage signal during a next frame display time, so as to control the M2 to be turned on, and to perform data voltage writing during a data writing time period, so as to refresh the picture.

[0389] At least one embodiment of the pixel circuit is configured to, when the pixel circuit needs to be refreshed, control the CG to output a low voltage signal during at least part of a blank time period between two frame display times, and control the CG to continuously output a high voltage signal during a next frame display time, so as to control the M2 to be turned on, and to perform data voltage writing during a data writing time period, so as to refresh the picture.

[0390] The pixel driving method according to an embodiment of the present application is applied to the pixel circuit described above, and the pixel driving method comprises the following steps.

[0391] The light emitting driving circuit generates a driving current for driving the light emitting element under the control of the potential of the first node.

[0392] The control circuit controls the first node to be connected or disconnected with the first electrode of the light emitting element under the control of the first gate driving signal and the scanning signal.

[0393] In at least one embodiment of the present application, the pixel circuit comprises a first initialization circuit, a first end of the light emitting driving circuit is electrically connected with a second node, and a second end of the light emitting driving circuit is electrically connected with a third node and a first electrode of the light emitting element respectively; a display period comprises a first initialization time period and a second initialization time period arranged in sequence; and the pixel driving method comprises the following steps.

[0394] During the first initialization time period, the control circuit controls the first node to be connected with the third node under the control of the first gate driving signal and the scanning signal; the first initialization circuit writes a first initial voltage into the second node under the control of a first initial control signal; and the light emitting driving circuit controls the second node to be connected with the third node under the control of the potential of the first node.

[0395] During the second initialization time period, the control circuit controls the first node to be disconnected with the third node under the control of the first gate driving signal and the scanning signal; the first initialization circuit writes the first initial voltage into the second node under the control of the first initial control signal; and the light emitting driving circuit controls the second node to be connected with the third node under the control of the potential of the first node.

[0396] The display panel in at least one embodiment of the present application comprises a source driver and the above-mentioned driving circuit.

[0397] The source driver comprises a data output end.

[0398] The display panel in at least one embodiment of the present application comprises a plurality of scanning lines.

[0399] The scanning signal output end in the scanning signal generation circuit in the driving circuit is electrically connected with the scanning lines.

[0400] In a specific implementation, the display panel can comprise a plurality of scanning lines, and the scanning signal output end is electrically connected with the scanning lines to provide scanning signals to the scanning lines.

[0401] Optionally, the display panel comprises a plurality of data lines.

[0402] The data output end is directly electrically connected with the data lines; or,

[0403] The driving circuit comprises a second switch circuit, which controls the communication or disconnection between the data output end and the data lines under the control of a second gate control signal.

[0404] In at least one embodiment of the present application, the source driver is arranged at a first side edge of the display panel, and the driving circuit is arranged at the first side edge of the display panel; or,

[0405] The source driver is arranged at a first side edge of the display panel, and the driving circuit is arranged at a second side edge of the display panel, and the first side edge and the second side edge are opposite side edges.

[0406] For example, the first side edge can be a lower side edge, and the second side edge can be an upper side edge, but the present application is not limited thereto.

[0407] As shown in FIG. 1, A0 represents a display area of the display panel. Figure 25 DL1 represents a first column of data lines, CG1 represents a first column of scanning lines, DL2 represents a second column of data lines, CG2 represents a second column of scanning lines, DL3 represents a third column of data lines, CG3 represents a third column of scanning lines, DL4 represents a fourth column of data lines, and CG4 represents a fourth column of scanning lines; DLm represents an mth column of data lines, and CGm represents an mth column of scanning lines; DLM represents an Mth column of data lines, and CGM represents an Mth column of scanning lines.

[0408] m and M are both positive integers; SI represents a source driver.

[0409] ​

[0410] The first data output terminal of the source driver SI is labeled as S1, the second data output terminal of the source driver SI is labeled as S2, the third data output terminal of the source driver SI is labeled as S3, the fourth data output terminal of the source driver SI is labeled as S4, the mth data output terminal is labeled as Sm, the Mth data output terminal is labeled as SM, the first first-gate control line is labeled as SW11, and the second first-gate control line is labeled as SW21.

[0411] The source driver SI is electrically connected with the SW11 and the SW21, for providing the first first-gate control signal to the SW11 and the second first-gate control signal to the SW21.

[0412] In Figure 25 , the first gate unit is labeled as X1, the second gate unit is labeled as X2, the third gate unit is labeled as X3, the fourth gate unit is labeled as X4, the mth gate unit is labeled as Xm, and the Mth gate unit is labeled as XM.

[0413] Each gate unit comprises a first switch circuit and a scan signal generation circuit; or, each gate unit comprises a first switch circuit, a second switch circuit, and a scan signal generation circuit.

[0414] As Figure 25 shown, the first gate unit X1 is electrically connected with the DL1 and the CG1 respectively, the second gate unit X2 is electrically connected with the DL2 and the CG2 respectively, the third gate unit X3 is electrically connected with the DL3 and the CG3 respectively, the fourth gate unit X4 is electrically connected with the DL4 and the CG4 respectively, the mth gate unit Xm is electrically connected with the DL and the CGm respectively, and the Mth gate unit XM is electrically connected with the DLM and the CGM respectively.

[0415] The source driver SI is disposed below the A0, and the first gate unit X1, the second gate unit X2, the third gate unit X3, the fourth gate unit X4, the mth gate unit Xm, and the Mth gate unit XM are disposed below the A0.

[0416] Figure 26 At least one embodiment of the display panel shown in Figure 25 differs from at least one embodiment of the display panel shown in

[0417] Figure 27 At least one embodiment of the display panel shown in Figure 26 differs from at least one embodiment of the display panel shown in

[0418] The data output terminals of the source driver SI are concentrated in the middle of the display panel to realize a narrow bottom frame, Figure 27 At least one embodiment of the display panel shown combines a FIP (Fanout In Pixel) embodiment. The display panel described in at least one embodiment of the application can also include a plurality of rows and columns of the pixel circuit described above.

[0419] In Figure 25 At least one embodiment of the display panel shown combines a FIP (Fanout In Pixel) embodiment. The display panel described in at least one embodiment of the application can also include a plurality of rows and columns of the pixel circuit described above. Figure 27 In at least one embodiment of the display panel shown, each gate-on unit can be the driving circuit described in at least one embodiment of the application.

[0420] In at least one embodiment of the application, two columns of pixel circuits can be electrically connected to the same column of scan lines.

[0421] The embodiment of the application provides a driving scheme applied to an OLED display. The local refresh pixel circuit cooperates with the source driving circuit and the driving scheme, so that the screen local picture update can be realized through an HCT control signal (the HCT control signal can be a data signal provided by the data output terminal of the source driver in a blank time period), and the rest of the picture does not need to be charged and discharged multiple times, so that the power consumption of the OLED display is further reduced, or the local update of the display picture is realized to achieve ultra-low power consumption.

[0422] In at least one embodiment of the application, for a display device, when it is necessary to update part of the picture, such as only the date and time part needs to be updated. In the row direction, it can be controlled whether the gate driving circuit outputs: in the row where the picture needs to be updated, the first gate driving signal is normally output, the first control transistor in the pixel circuit in the display area is normally opened, and data update is performed; in the row where the picture does not need to be updated, the potential of the first gate driving signal is always maintained to close the first control transistor, so as to ensure that the pixel brightness does not change, thereby realizing local refresh in the row direction. In the column direction, it can be realized by controlling whether the column scan line opens the second control transistor in the pixel circuit: in the blank time period between two display times, the source driver outputs an HCT pulse, and different scan signals are written into the column scan line. If the current column needs to be updated, the column scan line needs to ensure that the second control transistor is always opened, and the current column can be normally refreshed; if some columns do not need to be updated, the column scan line needs to ensure that the second control transistor in the pixel circuit of these columns is always closed.

[0423] The display panel described in at least one embodiment of the application also includes the pixel circuit described above.

[0424] The display device described in the embodiment of the application includes the display panel described above.

[0425] The above describes the preferred embodiments of the present application. It should be noted that, for those skilled in the art, several improvements and refinements can be made without departing from the principles of the present application, and these improvements and refinements should also be considered as falling within the scope of the present application.

Claims

1. A drive circuit characterized by comprising: The first switch circuit and a scan signal generation circuit are included. The first switch circuit is electrically connected with a first gate control line, a data output terminal of a source driver and the scan signal generation circuit, and is used for controlling writing of a data signal provided by the data output terminal into the scan signal generation circuit under control of a first gate control signal provided by the first gate control line; The scan signal generation circuit is used for generating a scan signal according to the data signal and outputting the scan signal through a scan signal output terminal; The first switch circuit is used for controlling writing of the data signal into the scan signal generation circuit under control of the first gate control signal in at least part of a blank time period between two frame display times; The scan signal generation circuit is used for generating a scan signal according to the data signal and outputting the scan signal to a corresponding column scan line of a display panel through the scan signal output terminal in at least part of the blank time period between the two frame display times; In at least part of the blank time period between the two frame display times, the scan signal on a column scan line is controlled to control, according to the scan signal, whether a transistor controlled by the column scan line is turned on or turned off in the next frame display time to control whether a corresponding pixel circuit is refreshed with a data voltage.

2. The drive circuit of claim 1, wherein A second switch circuit is further included. The second switch circuit is electrically connected with a second gate control line, the data output terminal and a data line included in the display panel respectively, and is used for controlling communication or disconnection between the data output terminal and the data line under control of a second gate control signal provided by the second gate control line; The first gate control line and the second gate control line are the same gate control line, or the first gate control line and the second gate control line are different.

3. The drive circuit of claim 1, wherein The first switch circuit includes a first transistor and a first capacitor, and the first switch circuit provides the data signal to the scan signal generation circuit through a control node; The gate of the first transistor is electrically connected with the first gate control line, the first pole of the first transistor is electrically connected with the data output terminal, and the second pole of the first transistor is electrically connected with the control node; The first end of the first capacitor is electrically connected with the control node, and the second end of the first capacitor is electrically connected with a direct current voltage terminal.

4. The drive circuit of claim 2, wherein The second switch circuit includes a second transistor; The gate of the second transistor is electrically connected with the second gate control line, the first pole of the second transistor is electrically connected with the data output terminal, and the second pole of the second transistor is electrically connected with the data line.

5. The drive circuit of claim 1, wherein, The scan signal generation circuit includes an output control circuit and an output circuit, and the first switch circuit provides the data signal to the scan signal generation circuit through the control node; The output control circuit is electrically connected with the control node, the first voltage terminal, the second voltage terminal, the output control terminal and the scan output terminal respectively, and is configured to control the output control terminal to be connected or disconnected with the first voltage terminal under the control of the potential of the control node, and control the output control terminal to be connected or disconnected with the second voltage terminal under the control of the signal provided by the scan output terminal. The output circuit is electrically connected with the control terminal, the scan output terminal, the output control terminal, the first voltage terminal and the second voltage terminal respectively, and is configured to control the scan output terminal to be connected or disconnected with the first voltage terminal under the control of the control signal provided by the control terminal, and control the scan output terminal to be connected or disconnected with the second voltage terminal under the control of the potential of the output control terminal.

6. The drive circuit of claim 5, wherein, The scan output terminal is the scan signal output terminal; or The scan signal generation circuit further comprises an inverting circuit; an input terminal of the inverting circuit is electrically connected with the scan output terminal, an output terminal of the inverting circuit is electrically connected with the scan signal output terminal, and the inverting circuit is configured to invert the voltage signal inputted by the input terminal to obtain an inverted voltage signal, and output the inverted voltage signal through the output terminal.

7. The drive circuit of claim 5, wherein, The output control circuit comprises a third transistor and a fourth transistor; a gate of the third transistor is electrically connected with the control node, a first pole of the third transistor is electrically connected with the first voltage terminal, and a second pole of the third transistor is electrically connected with the output control terminal; a gate of the fourth transistor is electrically connected with the scan output terminal, a first pole of the fourth transistor is electrically connected with the output control terminal, and a second pole of the fourth transistor is electrically connected with the second voltage terminal; The output circuit comprises a fifth transistor, a sixth transistor and a second capacitor; a gate of the fifth transistor is electrically connected with the control terminal, a first pole of the fifth transistor is electrically connected with the first voltage terminal, and a second pole of the fifth transistor is electrically connected with the scan output terminal; a gate of the sixth transistor is electrically connected with the output control terminal, a first pole of the sixth transistor is electrically connected with the scan output terminal, and a second pole of the sixth transistor is electrically connected with the second voltage terminal; a first terminal of the second capacitor is electrically connected with the control terminal, and a second terminal of the second capacitor is electrically connected with the second voltage terminal.

8. A driving method applied to the driving circuit according to any one of claims 1 to 7, characterized by, The driving method comprises: in at least part of the blank time period between two frames of display time, The first switch circuit controls the writing of the data signal provided by the data output terminal of the source driver into the scan signal generation circuit under the control of the first gating control signal; The scan signal generation circuit generates the scan signal according to the data signal, and outputs the scan signal to the corresponding column scan line of the display panel through the scan signal output terminal; The driving method comprises: in at least part of the blank time period between two frames of display time, The first switch circuit controls the writing of the data signal provided by the data output terminal of the source driver into the scan signal generation circuit under the control of the first gating control signal; The scan signal generation circuit generates the scan signal according to the data signal, and outputs the scan signal to the corresponding column scan line of the display panel through the scan signal output terminal; At least part of the time in the blank time period between two frame display times, a scanning signal on a column of scanning lines is controlled to control, according to the scanning signal, whether the transistor controlled by the scanning line is turned on or turned off to control whether the corresponding pixel circuit is refreshed with a data voltage in the next frame display time.

9. The driving method according to claim 8, wherein The driving circuit further comprises a second switch circuit; and the driving method further comprises: During a data writing time period in a frame display time, the second switch circuit controls the data output terminal of the source driver to be in communication with the corresponding column data line of the display panel under the control of a second gate control signal.

10. A display panel, characterized by, The source driver and the driving circuit according to any one of claims 1 to 7 are included. The source driver comprises a data output terminal. The display panel further comprises a pixel circuit, which comprises a light emitting element, a light emitting driving circuit and a control circuit. The light emitting driving circuit is electrically connected to the first node and a first electrode of the light emitting element respectively, and is configured to generate a driving current for driving the light emitting element under the control of the potential of the first node; and a second electrode of the light emitting element is electrically connected to a third voltage terminal. The control circuit is electrically connected to the first gate line, the scanning line, the first node and the first electrode of the light emitting element respectively, and is configured to control the first node and the first electrode of the light emitting element to be in communication or disconnected under the control of a first gate driving signal provided by the first gate line and a scanning signal provided by the scanning line.

11. The display panel of claim 10, wherein, The display panel comprises a plurality of column scanning lines. The scanning signal output terminal in the scanning signal generation circuit in the driving circuit is electrically connected to the scanning line.

12. The display panel of claim 10, wherein, The display panel comprises a plurality of column data lines. The data output terminal is directly electrically connected to the data line; or the driving circuit comprises a second switch circuit, which controls the data output terminal and the data line to be in communication or disconnected under the control of a second gate control signal.

13. The display panel of any of claims 10 to 12, wherein, The source driver is arranged at a first side edge of the display panel, and the driving circuit is arranged at the first side edge of the display panel; or The source driver is arranged at a first side edge of the display panel, and the driving circuit is arranged at a second side edge of the display panel, the first side edge and the second side edge being opposite side edges.

14. The display panel of claim 10, wherein, The control circuit comprises a first control circuit and a second control circuit; a first end of the light emitting driving circuit is electrically connected to a second node, and a second end of the light emitting driving circuit is electrically connected to a third node and a first electrode of the light emitting element respectively; The first control circuit is electrically connected to the first gate line, the first node and an intermediate node respectively, and is configured to control the first node and the intermediate node to be in communication or disconnected under the control of a first gate driving signal provided by the first gate line; The second control circuit is electrically connected to the scanning line, the intermediate node and the third node respectively, and is configured to control the intermediate node and the third node to be in communication or disconnected under the control of a scanning signal provided by the scanning line.

15. The display panel of claim 10, wherein, The control circuit comprises a first control circuit and a second control circuit; a first end of the light-emitting driving circuit is electrically connected with a second node, and a second end of the light-emitting driving circuit is electrically connected with a third node and a first electrode of the light-emitting element respectively; The first control circuit is electrically connected with the first gate line, the third node and an intermediate node respectively, and is used for controlling the third node and the intermediate node to be connected or disconnected under the control of a first gate driving signal provided by the first gate line; The second control circuit is electrically connected with the scan line, the intermediate node and the first node respectively, and is used for controlling the intermediate node and the first node to be connected or disconnected under the control of a scan signal provided by the scan line.

16. The display panel of claim 10, wherein, The first initialization circuit is electrically connected with a first initial control end, a first initial voltage end and the second node respectively, and is used for writing a first initial voltage provided by the first initial voltage end into the second node under the control of a first initial control signal provided by the first initial control end. The second initialization circuit is electrically connected with a second initial control end, a second initial voltage end and the third node respectively, and is used for writing a second initial voltage provided by the second initial voltage end into the third node under the control of a second initial control signal provided by the second initial control end.

17. The display panel of claim 10, wherein, The data writing circuit is electrically connected with a second gate line, a data line and the second node respectively, and is used for writing a data voltage provided by the data line into the second node under the control of a second gate driving signal provided by the second gate line. The first light-emitting control circuit is electrically connected with a light-emitting control line, a power voltage end and the second node respectively, and is used for controlling the power voltage end and the second node to be connected or disconnected under the control of a light-emitting control signal provided by the light-emitting control line.

18. The display panel of claim 10, wherein, The second light-emitting control circuit is electrically connected with the light-emitting control line, the third node and the first electrode of the light-emitting element respectively, and is used for controlling the third node and the first electrode of the light-emitting element to be electrically connected under the control of the light-emitting control signal. The energy storage circuit is electrically connected with the first node, and is used for storing electric energy. The third initialization circuit is electrically connected with the first node, and is used for writing a third initial voltage provided by a third initial voltage end into the first node under the control of a third initial control signal provided by a third initial control end. ​ ​ 19. The display panel of claim 18, wherein, ​ The third initialization circuit is electrically connected with the first initial control end, the third initial voltage end and the first electrode of the light emitting element, respectively, for writing the third initial voltage provided by the third initial voltage end into the first electrode of the light emitting element under the control of the first initial control signal provided by the first initial control end.

20. The display panel of claim 14, wherein, The first control circuit comprises a first control transistor, and the second control circuit comprises a second control transistor; The gate of the first control transistor is electrically connected with the first gate line, the first electrode of the first control transistor is electrically connected with the intermediate node, and the second electrode of the first control transistor is electrically connected with the third node; The gate of the second control transistor is electrically connected with the scan line, the first electrode of the second control transistor is electrically connected with the intermediate node, and the second electrode of the second control transistor is electrically connected with the third node.

21. The display panel of claim 15, wherein, The first control circuit comprises a first control transistor, and the second control circuit comprises a second control transistor; The gate of the first control transistor is electrically connected with the first gate line, the first electrode of the first control transistor is electrically connected with the intermediate node, and the second electrode of the first control transistor is electrically connected with the third node; The gate of the second control transistor is electrically connected with the scan line, the first electrode of the second control transistor is electrically connected with the first node, and the second electrode of the second control transistor is electrically connected with the intermediate node.

22. The display panel of claim 16, wherein, The first initialization circuit comprises a first initialization transistor; The gate of the first initialization transistor is electrically connected with the first initial control end, the first electrode of the first initialization transistor is electrically connected with the first initial voltage end, and the second electrode of the first initialization transistor is electrically connected with the second node.

23. The display panel of claim 17, wherein, The second initialization circuit comprises a second initialization transistor; The gate of the second initialization transistor is electrically connected with the second initial control end, the first electrode of the second initialization transistor is electrically connected with the second initial voltage end, and the second electrode of the second initialization transistor is electrically connected with the third node.

24. The display panel of claim 18, wherein, The data writing circuit comprises a writing transistor, the first light emitting control circuit comprises a first light emitting control transistor, the second light emitting control circuit comprises a second light emitting control transistor, the light emitting driving circuit comprises a driving transistor, and the energy storage circuit comprises a storage capacitor; The gate of the writing transistor is electrically connected with the second gate line, the first electrode of the writing transistor is electrically connected with the data line, and the second electrode of the writing transistor is electrically connected with the second node; The gate of the first light emitting control transistor is electrically connected with the light emitting control line, the first electrode of the first light emitting control transistor is electrically connected with the power voltage end, and the second electrode of the first light emitting control transistor is electrically connected with the second node; The gate of the second light emitting control transistor is electrically connected with the light emitting control line, the first electrode of the second light emitting control transistor is electrically connected with the third node, and the second electrode of the second light emitting control transistor is electrically connected with the first electrode of the light emitting element; A gate of the driving transistor is electrically connected with the first node, a first electrode of the driving transistor is electrically connected with the second node, and a second electrode of the driving transistor is electrically connected with the third node. A first end of the storage capacitor is electrically connected with the first node, and a second end of the storage capacitor is electrically connected with a power voltage terminal.

25. The display panel of claim 19, wherein, The third initialization circuit includes a third initialization transistor. A gate of the third initialization transistor is electrically connected with the first initial control terminal, a first electrode of the third initialization transistor is electrically connected with the third initial voltage terminal, and a second electrode of the third initialization transistor is electrically connected with the first electrode of the light emitting element. 26.The pixel driving method applied to the pixel circuit in the display panel of any one of claims 10 to 25, characterized in that, The pixel driving method includes: The light emitting driving circuit generates a driving current for driving the light emitting element under the control of the potential of the first node. The control circuit controls the first node and the first electrode of the light emitting element to be connected or disconnected under the control of the first gate driving signal and the scanning signal.

27. The pixel driving method according to claim 26, wherein The pixel circuit includes a first initialization circuit, a first end of the light emitting driving circuit is electrically connected with the second node, and a second end of the light emitting driving circuit is respectively electrically connected with the third node and the first electrode of the light emitting element; the display period includes a first initialization time period and a second initialization time period arranged in sequence; and the pixel driving method includes: In the first initialization time period, the control circuit controls the first node and the third node to be connected under the control of the first gate driving signal and the scanning signal; the first initialization circuit writes the first initial voltage into the second node under the control of the first initial control signal; and the light emitting driving circuit controls the second node and the third node to be connected under the control of the potential of the first node. In the second initialization time period, the control circuit controls the first node and the third node to be disconnected under the control of the first gate driving signal and the scanning signal; the first initialization circuit writes the first initial voltage into the second node under the control of the first initial control signal; and the light emitting driving circuit controls the second node and the third node to be connected under the control of the potential of the first node.

28. A display device comprising: The display panel includes the pixel circuit as claimed in any one of claims 10 to 25.

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