Semiconductor memory device

Abstract

The present application provides a semiconductor storage device capable of properly adjusting the potential of a source line layer. The semiconductor storage device (2) includes: a taking circuit that takes the potential of a source line layer (320); and a first adjustment circuit that adjusts the potential of the source line layer (320) to a prescribed target potential. A dummy pillar (DP) is included in the taking circuit, the dummy pillar (DP) penetrates a plurality of wiring layers (332), is a pillar-shaped body having an end connected to the source line layer (320), and a portion intersecting the wiring layers (332) functions as a transistor.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2022-034959 (filed on March 8, 2022). This application incorporates the entire contents of this basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to semiconductor memory devices. Background Technology

[0004] For example, a semiconductor memory device such as NAND flash memory has multiple memory cell transistors for storing data. The memory cell transistors are formed as memory pillars arranged along multiple word line layers. The ends of the memory pillars are connected to the source line layer. Summary of the Invention

[0005] According to the disclosed embodiments, a semiconductor memory device capable of appropriately adjusting the potential of the source line layer is provided.

[0006] The semiconductor memory device of the embodiment includes: a plurality of word line layers stacked at intervals; a memory pillar, which is a pillar-shaped body penetrating the plurality of word line layers, the portion of which intersects with the word line layers functions as a memory cell transistor; a source line layer connected to the end of the memory pillar; an acquisition circuit for acquiring the potential of the source line layer; and a first adjustment circuit for adjusting the potential of the source line layer to a predetermined target potential. The acquisition circuit includes a dummy pillar, which penetrates the plurality of word line layers, is a pillar-shaped body with its end connected to the source line layer, and the portion of which intersects with the word line layers functions as a transistor. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a structural example of a storage system according to an implementation method.

[0008] Figure 2 This is a block diagram illustrating the structure of a semiconductor memory device according to an implementation method.

[0009] Figure 3 It is an equivalent circuit diagram representing the structure of a memory cell array.

[0010] Figure 4 It is a cross-sectional view showing the structure of the memory cell array.

[0011] Figure 5 This is a diagram showing the circuit structure of the readout amplifier unit.

[0012] Figure 6 This is a diagram illustrating an example of the threshold distribution of a memory cell transistor.

[0013] Figure 7It is a graph showing the potential changes of each wire during a write operation.

[0014] Figure 8 It is a diagram showing the potential changes of each wiring during the readout operation.

[0015] Figure 9 It is a diagram that represents the configuration of multiple blocks, etc.

[0016] Figure 10 It is a cross-sectional view showing the connected area and the structure in its vicinity.

[0017] Figure 11 This is a diagram used to illustrate the potential adjustment of the source line layer.

[0018] Figure 12 This is a diagram illustrating the potential adjustment of the source line layer in a comparative example semiconductor memory device. Detailed Implementation

[0019] Hereinafter, this embodiment will be described with reference to the accompanying drawings. To facilitate understanding, the same reference numerals will be used as much as possible to refer to the same constituent elements in each drawing, and repeated descriptions will be omitted.

[0020] The semiconductor storage device 2 in this embodiment is a non-volatile storage device configured as NAND flash memory. Figure 1 The diagram illustrates a structural example of a memory system including a semiconductor memory device 2. This memory system includes a memory controller 1 and a semiconductor memory device 2. Furthermore, the semiconductor memory device 2... Figure 1 The storage system actually has multiple [systems], but [there are] more [systems] installed. Figure 1 Only one of them is shown in the diagram. The specific structure of semiconductor memory device 2 will be described later. This memory system can be connected to a host device (not shown). The host device is, for example, a personal computer, a mobile terminal, or other electronic device.

[0021] The storage controller 1 controls the writing of data to the semiconductor storage device 2 according to write requests from the host. Additionally, the storage controller 1 controls the reading of data from the semiconductor storage device 2 according to read requests from the host.

[0022] Between the storage controller 1 and the semiconductor storage device 2, the following signals are transmitted and received: chip enable signal / CE, ready-busy signal R / B, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal / RE, RE, write protection signal / WP, data signal DQ<7:0>, data strobe signal DQS, and / DQS.

[0023] The chip enable signal / CE is used to enable the semiconductor memory device 2. The ready / busy signal R / B is used to indicate whether the semiconductor memory device 2 is in a ready or busy state. "Ready state" means accepting instructions from external sources. "Busy state" means not accepting instructions from external sources. The instruction latch enable signal indicates that the signal DQ<7:0> represents an instruction. The address latch enable signal ALE indicates that the signal DQ<7:0> represents an address. The write enable signal / WE is used to fetch received signals into the semiconductor memory device 2, and is asserted whenever instructions, addresses, and data are received through the memory controller 1. The memory controller 1 instructs the semiconductor memory device 2 to fetch the signal DQ<7:0> while the signal / WE is at the "L (Low)" level.

[0024] The read enable signal / RE is used to enable the memory controller 1 to read data from the semiconductor memory device 2. Signal RE is the complementary signal to signal / RE. These are used, for example, to control the timing of the operation of the semiconductor memory device 2 when the output signal DQ<7:0> is displayed. The write protect signal / WP is used to instruct the semiconductor memory device 2 to disable data writing and erasing. Signals DQ<7:0> are the entities of data transmitted and received between the semiconductor memory device 2 and the memory controller 1, including instructions, addresses, and data. The data strobe signal DQS is used to control the timing of the input and output of signal DQ<7:0>. Signal / DQS is the complementary signal to signal DQS.

[0025] The storage controller 1 includes RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15. RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are connected to each other via an internal bus 16.

[0026] The host interface 13 outputs requests received from the host, user data (write data), etc., to the internal bus 16. Additionally, the host interface 13 sends user data read from the semiconductor storage device 2, responses from the processor 12, etc., to the host.

[0027] The memory interface 15 controls the processes of writing user data, etc., to the semiconductor storage device 2 and reading user data, etc., from the semiconductor storage device 2 based on the instructions of the processor 12.

[0028] Processor 12 provides unified control over memory controller 1. Processor 12 may be, for example, a CPU, MPU, etc. When processor 12 receives a request from the host via host interface 13, it performs control according to that request. For example, processor 12, according to a request from the host, instructs memory interface 15 to write user data and parity data to semiconductor memory device 2. Additionally, processor 12, according to a request from the host, instructs memory interface 15 to read user data and parity data from semiconductor memory device 2.

[0029] Processor 12 determines the storage area (memory region) on semiconductor storage device 2 for user data stored in RAM 11. User data is stored in RAM 11 via internal bus 16. Processor 12 determines the memory region for data in page units (page data) written as units. Hereinafter, the user data stored in one page of semiconductor storage device 2 is also referred to as "cell data". Cell data is generally encoded and stored in semiconductor storage device 2 as codewords. In this embodiment, encoding is not necessary. Storage controller 1 may also store cell data in semiconductor storage device 2 without encoding, but... Figure 1 The diagram illustrates an encoding structure as an example. When the storage controller 1 does not perform encoding, the page data is identical to the cell data. Furthermore, a codeword can be generated based on a single cell of data, or it can be generated based on segmented data obtained by dividing the cell data. Alternatively, a codeword can be generated using multiple cells of data.

[0030] For each data unit, processor 12 determines the memory region of the semiconductor storage device 2 to be written to. It allocates a physical address to the memory region of the semiconductor storage device 2. Processor 12 manages the memory region to be written to the destination of the data unit using the physical address. Processor 12 specifies the determined memory region (physical address) and instructs memory interface 15 to write user data to semiconductor storage device 2. Processor 12 manages the mapping between the logical address (the logical address managed by the host) of user data and the physical address. Upon receiving a read request, including a logical address from the host, processor 12 determines the physical address corresponding to the logical address, specifies the physical address, and instructs memory interface 15 to read the user data.

[0031] ECC circuit 14 encodes user data stored in RAM 11 to generate codewords. Furthermore, ECC circuit 14 decodes codewords read from semiconductor memory device 2. ECC circuit 14 performs error detection and correction in the data, for example, by utilizing a checksum assigned to the user data.

[0032] RAM 11 temporarily stores user data received from the host before it is stored in the semiconductor storage device 2, or temporarily stores data read from the semiconductor storage device 2 before it is sent to the host. RAM 11 is, for example, a general-purpose memory such as SRAM or DRAM.

[0033] exist Figure 1 The diagram shows a structural example of a memory controller 1 comprising an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 may also be integrated into the memory interface 15. Alternatively, the ECC circuit 14 may also be integrated into the semiconductor memory device 2. Figure 1 The specific structure and configuration of the elements shown are not particularly limited.

[0034] In the event that a write request is received from the host Figure 1 The storage system operates as follows: The processor 12 temporarily stores the data to be written in RAM 11. The processor 12 reads the data stored in RAM 11 and inputs it to ECC circuit 14. ECC circuit 14 encodes the input data and inputs the codeword to memory interface 15. Memory interface 15 writes the input codeword to semiconductor storage device 2.

[0035] In the event that a read request is received from the host Figure 1 The storage system operates as follows: The memory interface 15 inputs the codewords read from the semiconductor storage device 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codewords and stores the decoded data in the RAM 11. The processor 12 sends the data stored in the RAM 11 to the host via the host interface 13.

[0036] The structure of semiconductor memory device 2 will be described. For example... Figure 2 As shown, the semiconductor memory device 2 includes a memory cell array 110, a sense amplifier 120, a line decoder 130, an input / output circuit 21, a logic control circuit 22, a sequence generator 41, a register 42, a voltage generation circuit 43, an input / output pad group 31, a logic control pad group 32, and a power input terminal group 33.

[0037] Storage cell array 110 is the part that stores data. Figure 3 In the diagram, the structure of the memory cell array 110 is represented as an equivalent circuit diagram. The memory cell array 110 consists of multiple blocks BLK, but... Figure 3 The diagram only shows one block BLK. The composition of the other block BLKs in the storage cell array 110 is also similar. Figure 3 The same as shown.

[0038] like Figure 3As shown, block BLK includes, for example, four serial units SU (SU0 to SU3). Each serial unit SU includes multiple NAND strings NS. Each NAND string NS includes, for example, eight memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST2.

[0039] Furthermore, the number of memory cell transistors MT is not limited to 8; for example, it can be 32, 48, 64, or 96. For instance, to improve cutoff characteristics, select transistors ST1 and ST2 can each be composed of multiple transistors instead of a single transistor. Moreover, dummy cell transistors can be placed between the memory cell transistor MT and the select transistors ST1 and ST2.

[0040] The memory cell transistor MT is configured to be connected in series between the select transistor ST1 and the select transistor ST2. The memory cell transistor MT7 on one side is connected to the source of the select transistor ST1, and the memory cell transistor MT0 on the other side is connected to the drain of the select transistor ST2.

[0041] The gates of the selection transistors ST1 for each of the serial cells SU0 to SU3 are shared by the selection gate lines SGD0 to SGD3. The gates of the selection transistors ST2 are shared by multiple serial cells SU within the same block BLK via the same selection gate line SGS. The control gates of the memory cell transistors MT0 to MT7 within the same block BLK are shared by the word lines WL0 to WL7. That is, the word lines WL0 to WL7 and the selection gate line SGS are shared by multiple serial cells SU0 to SU3 within the same block BLK. In contrast, the selection gate line SGD is set individually for each serial cell SU0 to SU3, even within the same block BLK.

[0042] The memory cell array 110 has m bit lines BL (BL0, BL1, ..., BL(m-1)). The "m" mentioned above is an integer representing the number of NAND strings NS included in one string cell SU. The drain of the select transistor ST1 in each NAND string NS is connected to the corresponding bit line BL. The source of the select transistor ST2 is connected to the source line SL. The source lines SL are collectively connected to the sources of the multiple select transistors ST2 in block BLK.

[0043] Data stored in multiple memory cell transistors MT within the same block BLK is erased simultaneously. Conversely, data is read from and written to multiple memory cell transistors MT connected to one word line WL and belonging to one string cell SU simultaneously. Each memory cell can hold 3 bits of data consisting of the upper bit, middle bit, and lower bit.

[0044] That is, in this embodiment, the semiconductor memory device 2 uses a TLC method, which stores 3 bits of data in one memory cell transistor MT, as a way to write data to the memory cell transistor MT. Alternatively, other methods for writing data to the memory cell transistor MT include an MLC method, which stores 2 bits of data in one memory cell transistor MT, and an SLC method, which stores 1 bit of data in one memory cell transistor MT.

[0045] Furthermore, in the following explanation, the collection of 1-bit data stored by multiple memory cell transistors MT connected to one word line WL and belonging to one string unit SU is called a "page". Figure 3 In the figure, one of the sets consisting of multiple memory cell transistors MT as described above is labeled with the reference numeral "MG".

[0046] As in this embodiment, when 3 bits of data are stored in one memory cell transistor MT, a set of multiple memory cell transistors MT connected to a common word line WL within one string cell SU can store 3 pages of data.

[0047] exist Figure 4 The figure schematically depicts a cross-section of the memory cell array 110 when it is cut along the direction of the bit line BL. As shown in the figure, multiple NAND strings NS are formed above the source line layer 320 in the memory cell array 110. The source line layer 320 is also referred to as the buried source line (BSL), which is equivalent to... Figure 3 The source line SL. The source line layer 320 is formed, for example, from polysilicon.

[0048] Above the source line layer 320, multiple wiring layers 333 functioning as select gate lines (SGS), multiple wiring layers 332 functioning as word lines (WL), and multiple wiring layers 331 functioning as select gate lines (SGD) are stacked. They are all stacked vertically with intervals between each other. An insulating layer (not shown) is disposed between each of the stacked wiring layers 333, 332, and 331. In this embodiment, the multiple word lines (WL) are each formed as layered wiring layers 332 as described above. The wiring layers 332 correspond to the "word line layers" in this embodiment.

[0049] Multiple storage vias 334 are formed in the storage cell array 110. Each storage via 334 is a hole that penetrates the wiring layers 333, 332, and 331, as well as the insulating layer (not shown) located between them, and reaches the source line layer 320 in the vertical direction. On the side of each storage via 334, a barrier insulating film 335, a charge storage layer 336, and a gate insulating film 337 are formed sequentially, and a conductive pillar 338 is embedded inside it. The conductive pillar 338 is made of, for example, polysilicon and functions as a region forming a channel when the storage cell transistors MT and select transistors ST1 and ST2 included in the NAND string NS are operated. Thus, a pillar-shaped structure composed of the barrier insulating film 335, the charge storage layer 336, the gate insulating film 337, and the conductive pillar 338 is formed inside the storage via 334. Hereinafter, this pillar-shaped structure will also be referred to as the "storage pillar MP". The storage column MP is connected to the top and bottom wiring layers 333, 332, and 331, and its lower end is connected to the source line layer 320.

[0050] The portions of the memory pillars MP formed inside the memory holes 334 that intersect with the stacked wiring layers 333, 332, and 331 function as transistors. The transistor located at the portion intersecting with wiring layer 331 functions as a select transistor ST1. The transistor located at the portion intersecting with wiring layer 332 functions as memory cell transistors MT (MT0 to MT7). The transistor located at the portion intersecting with wiring layer 333 functions as a select transistor ST2. With this structure, the memory pillars MP formed inside each memory hole 334 serve as references... Figure 3 The NAND string NS is explained to perform its function. The conductive pillar 338 located inside the storage pillar MP is the part that functions as a channel for the storage cell transistor MT, the selection transistors ST1 and ST2.

[0051] A wiring layer, functioning as a bit line BL, is formed above the conductive post 338. A contact plug 339, connecting the conductive post 338 to the bit line BL, is formed at the upper end of the conductive post 338. Each bit line BL is in a direction that intersects with the stacking direction of multiple wiring layers 332, etc. (in...) Figure 4 The conductor extending in the left-right direction (as described above) is connected to the end of the storage column MP opposite to the source line layer 320 via the contact plug 339.

[0052] and Figure 4 The structure shown is the same as the structure along Figure 4 There are multiple [items] arranged along the depth direction of the paper. By following... Figure 4 A collection of multiple NAND strings NS arranged in a row along the depth direction of the paper forms a single string unit SU.

[0053] Figure 4 The multiple storage columns (MPs) shown belong to the same block (BLK). Other block (BLK) included in storage cell array 110 are configured in... Figure 4 The left and right sides of the block BLK shown, but... Figure 4 The diagram is omitted. For configuration of multiple block BLKs, please refer to [reference needed]. Figure 9 More details will follow.

[0054] Conductors LI are arranged between adjacent blocks BLK. Conductors LI are formed along... Figure 4 A flat conductor LI extends in the depth direction of the paper and is configured to separate blocks BLK. The lower end of conductor LI is connected to source line layer 320. The upper end of conductor LI is connected to a wiring layer (not shown).

[0055] In the semiconductor memory device 2 of this embodiment, a peripheral circuit PER is provided at a position between the source line layer 320 and the semiconductor substrate 300, that is, at a position opposite to the memory pillar MP across the source line layer 320. The peripheral circuit PER is a circuit used to control the operation of the memory cell transistor MT, and realizes the writing, reading and erasing operations of data in the memory cell array 110. Figure 2 The readout amplifier 120, line decoder 130, and voltage generation circuit 43 shown are part of the peripheral circuitry (PER). The PER includes various transistors, RC circuits, etc. Figure 4 In the example shown, the transistor TR formed on the semiconductor substrate 300 is electrically connected to the bit line BL located on the upper side of the memory cell array 110 via a contact 924.

[0056] Alternatively, instead of this structure, a structure can be adopted in which the memory cell array 110 is directly disposed on the semiconductor substrate 300. In this case, the p-type well region of the semiconductor substrate 300 functions as the source line SL, i.e., the source line layer. Furthermore, the peripheral circuitry PER is disposed along the surface of the semiconductor substrate 300 adjacent to the memory cell array 110.

[0057] return Figure 2 Continuing with the explanation, the sense amplifier 120 is a circuit used to adjust the voltage applied to the bit line BL, or to read the voltage of the bit line BL and convert it into data. When reading data, the sense amplifier 120 obtains the read data from the memory cell transistor MT to the bit line BL and transmits the obtained read data to the input / output circuit 21. When writing data, the sense amplifier 120 transmits the write data written via the bit line BL to the memory cell transistor MT. The operation of the sense amplifier 120 is controlled by the sequence generator 41, described later.

[0058] The sense amplifier 120 includes multiple sense amplifier units SAUs, each corresponding to a plurality of bit lines BL. One sense amplifier unit SAU is connected to each bit line BL. That is, the sense amplifier unit SAU can be considered a circuit connected to the memory cell transistor MT of the serial cell SU via the bit line BL. Figure 5 The detailed circuit configuration of a single readout amplifier unit (SAU) is extracted and represented.

[0059] like Figure 5 As shown, the sense amplifier unit SAU includes a sense amplifier section SA, latch circuits SDL, ADL, BDL, CDL, and XDL. The sense amplifier section SA, latch circuits SDL, ADL, BDL, CDL, and XDL are connected via a bus in a manner that enables them to send and receive data with each other.

[0060] The sense amplifier unit SA, for example, reads the data read to the corresponding bit line BL during the sense operation and determines whether the read data is "0" or "1". The sense amplifier unit SA includes, for example, a transistor TR1 as a p-channel MOS transistor, transistors TR2 to TR9 as n-channel MOS transistors, and a capacitor C10.

[0061] Transistor TR1 is connected to the power supply line at one end and to transistor TR2 at the other end. The gate of transistor TR1 is connected to node INV_S within the latch circuit SDL. Transistor TR2 is connected to transistor TR1 at one end and to node COM at the other end. A signal BLX is input to the gate of transistor TR2. Transistor TR3 is connected to node COM at one end and to transistor TR4 at the other end. A signal BLC is input to the gate of transistor TR3. Transistor TR4 is a high-voltage MOS transistor. One end of transistor TR4 is connected to transistor TR3. The other end of transistor TR4 is connected to the corresponding bit line BL. A signal BLS is input to the gate of transistor TR4.

[0062] Transistor TR5 is connected at one end to node COM and at the other end to node SRC. The gate of transistor TR5 is connected to node INV_S. Transistor TR6 is connected at one end between transistors TR1 and TR2, and at the other end to node SEN. A signal HLL is input to the gate of transistor TR6. Transistor TR7 is connected at one end to node SEN and at the other end to node COM. A signal XXL is input to the gate of transistor TR7.

[0063] One end of transistor TR8 is grounded, and the other end is connected to transistor TR9. The gate of transistor TR8 is connected to node SEN. One end of transistor TR9 is connected to transistor TR8, and the other end is connected to the bus BUS. A signal STB is input to the gate of transistor TR9. One end of capacitor C10 is connected to node SEN. The clock signal CLK is input to the other end of capacitor C10.

[0064] Signals SW, BLX, BLC, BLS, HLL, XXL, and STB are generated, for example, by sequence generator 41. Additionally, a voltage Vdd, for example, the internal power supply voltage of the semiconductor memory device 2, is applied to the power line connected to one end of transistor TR1, and a voltage Vss, for example, the ground voltage of the semiconductor memory device 2, is applied to node SRC.

[0065] The latch circuits SDL, ADL, BDL, CDL, and XDL temporarily hold the read or written data. The latch circuit XDL is connected to the input / output circuit 21 and is used to read the input and output of data between the amplifier unit SAU and the input / output circuit 21.

[0066] The latch circuit SDL includes, for example, inverters IV11 and IV12, and transistors TR13 and TR14 as n-channel MOS transistors. The input node of inverter IV11 is connected to node LAT_S. The output node of inverter IV11 is connected to node INV_S. The input node of inverter IV12 is connected to node INV_S. The output node of inverter IV12 is connected to node LAT_S. One end of transistor TR13 is connected to node INV_S, and the other end is connected to the bus. A signal STI_S is input to the gate of transistor TR13. One end of transistor TR13 is connected to node LAT_S, and the other end of transistor TR14 is connected to the bus. A signal STL_S is input to the gate of transistor TR14. For example, the data held in node LAT_S is equivalent to the data held by the latch circuit SDL. Furthermore, the data held in node INV_S is equivalent to the inverted data of the data held in node LAT_S. The circuit structures of latch circuits ADL, BDL, CDL, and XDL are the same as those of latch circuit SDL, so their descriptions are omitted.

[0067] return Figure 2Continuing the explanation, the line decoder 130 is a circuit consisting of a group of switches (not shown) used to apply voltages to the word lines WL. The line decoder 130 receives the block address and row address from register 42, selects the corresponding block BLK based on the block address, and selects the corresponding word line WL based on the row address. The line decoder 130 switches the switch group on and off to apply the voltage from the voltage generation circuit 43 to the selected word line WL. The operation of the line decoder 130 is controlled by the sequence generator 41.

[0068] The input / output circuit 21 transmits and receives signals DQ<7:0> and data strobe signals DQS and / DQS with the memory controller 1. The input / output circuit 21 transfers the instruction and address contained in the signal DQ<7:0> to register 42. Additionally, the input / output circuit 21 transmits and receives write and read data with the sense amplifier 120.

[0069] The logic control circuit 22 receives the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protection signal / WP from the memory controller 1. Additionally, the logic control circuit 22 transmits the ready-to-work signal R / B to the memory controller 1, notifying the external system of the status of the semiconductor memory device 2.

[0070] The sequence generator 41 controls the operation of each part of the memory cell array 110 based on the control signals input from the memory controller 1 to the interface circuit 20. The sequence generator 41 functions as a "control circuit" that oversees the overall operation of the semiconductor memory device 10.

[0071] Register 42 is the part that temporarily holds instructions and addresses. Register 42 stores instructions that indicate write operations, read operations, and erase operations. After the instruction is input from the memory controller 1 to the input / output circuit 21, it is transferred from the input / output circuit 21 to register 42 and held.

[0072] In addition, register 42 also holds the address corresponding to the aforementioned instruction. This address is transferred from the memory controller 1 to the input / output circuit 21 and then from the input / output circuit 21 to register 42 and held thereafter.

[0073] Furthermore, register 42 also holds status information representing the operating state of semiconductor memory device 2. This status information is updated by sequence generator 41 each time based on the operating state of memory cell array 110, etc. Upon request from memory controller 1, the status information is output as a status signal from input / output circuit 21 to memory controller 1.

[0074] The voltage generation circuit 43 generates the voltages required for the write, read, and erase operations of data in the memory cell array 110. These voltages include, for example, the voltages applied to each word line WL and each bit line BL. The operation of the voltage generation circuit 43 is controlled by the sequence generator 41.

[0075] The input / output pad group 31 is a part that has multiple terminals (pads) for transmitting and receiving various signals between the storage controller 1 and the input / output circuit 21. Each terminal is independently configured with respect to the signals DQ<7:0> and the data strobe signals DQS and / DQS.

[0076] The logic control pad group 32 is a portion provided with multiple terminals (pads) for transmitting and receiving various signals between the memory controller 1 and the logic control circuit 22. Each terminal is independently configured corresponding to the chip enable signal / CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, write protect signal / WP, and ready busy signal R / B.

[0077] The power input terminal block 33 is a portion provided with multiple terminals for receiving the applied voltages required for the operation of the semiconductor memory device 2. The voltages applied to each terminal include the power supply voltages Vcc, VccQ, Vpp, and the ground voltage Vss.

[0078] The power supply voltage Vcc is the circuit power supply voltage provided externally as the operating power source, for example, a voltage of approximately 3.3V. The power supply voltage VccQ is, for example, a voltage of 1.2V. The power supply voltage VccQ is the voltage used when transmitting and receiving signals between the memory controller 1 and the semiconductor memory device 2. The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, for example, a voltage of 12V.

[0079] When writing or erasing data to the memory cell array 110, a high voltage of approximately 20V is required. In this case, boosting the approximately 12V power supply voltage Vpp is more efficient in generating the desired voltage with high speed and low power consumption compared to boosting the approximately 3.3V power supply voltage Vcc using the voltage generation circuit 43. On the other hand, if the semiconductor memory device 2 is used in an environment where a high voltage cannot be supplied, the power supply voltage Vpp may not need to be supplied. Even without the power supply voltage Vpp being supplied, the semiconductor memory device 2 can perform various operations as long as the power supply voltage Vcc is supplied. That is, the power supply voltage Vcc is the standard power supply supplied to the semiconductor memory device 2, while the power supply voltage Vpp is, for example, an additional, arbitrary power supply supplied depending on the usage environment.

[0080] Figure 6 This is a schematic diagram illustrating the threshold distribution, etc., of the memory cell transistor MT. In Figure 6 The middle section of the graph shows the relationship between the threshold voltage of the memory cell transistor MT (horizontal axis) and the number of memory cell transistors MT (vertical axis).

[0081] In the case of using the TLC method as described in this embodiment, such as Figure 6 As shown in the middle section, multiple memory cell transistors MT form eight threshold distributions. These eight threshold distributions (write levels) are named sequentially from the lowest threshold voltage as "ER" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level.

[0082] Figure 6 The table above corresponds to each of the threshold voltage levels, representing examples of the data assigned. As shown in the table, different 3-bit data are assigned to the “ER” level, “A” level, “B” level, “C” level, “D” level, “E” level, “F” level, and “G” level, as shown below.

[0083] "ER" level: "111" ("lower bit / middle bit / higher bit")

[0084] "A" level: "011"

[0085] "B" level: "001"

[0086] "C" level: "000"

[0087] "D" level: "010"

[0088] "E" level: 110

[0089] "F" level: 100

[0090] "G" level: 101

[0091] Between each pair of adjacent threshold distributions, a verification voltage is set for use during the write operation. Specifically, verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set corresponding to the "A", "B", "C", "D", "E", "F", and "G" levels, respectively.

[0092] The verification voltage VfyA is set between the maximum threshold voltage at the "ER" level and the minimum threshold voltage at the "A" level. When the verification voltage VfyA is applied to the word line WL, the memory cell transistors MT connected to the word line WL whose threshold voltage is at the "ER" level are turned on, and the memory cell transistors MT whose threshold voltage is above the "A" level are turned off.

[0093] The other verification voltages VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set in the same way as the verification voltage VfyA. Verification voltage VfyB is set between the "A" level and the "B" level, verification voltage VfyC is set between the "B" level and the "C" level, verification voltage VfyD is set between the "C" level and the "D" level, verification voltage VfyE is set between the "D" level and the "E" level, verification voltage VfyF is set between the "E" level and the "F" level, and verification voltage VfyG is set between the "F" level and the "G" level.

[0094] For example, the verification voltage VfyA is set to 0.8V, VfyB to 1.6V, VfyC to 2.4V, VfyD to 3.1V, VfyE to 3.8V, VfyF to 4.6V, and VfyG to 5.6V. However, this is not a limitation; the verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG can be appropriately set in stages within the range of 0V to 7.0V.

[0095] Furthermore, read voltages used in the read operation are set between adjacent threshold distributions. "Read voltage" refers to the voltage applied to the word line WL, i.e., the select word line, connected to the memory cell transistor MT that is being read, during the read operation. During the read operation, data is determined based on whether the threshold voltage of the memory cell transistor MT that is being read is higher than the applied read voltage.

[0096] like Figure 6 As schematically shown in the lower section of the diagram, specifically, the read voltage VrA, which determines whether the threshold voltage of the memory cell transistor MT is at or above the "ER" level, is set between the maximum threshold voltage at the "ER" level and the minimum threshold voltage at the "A" level.

[0097] The other readout voltages VrB, VrC, VrD, VrE, VrF, and VrG are set in the same way as the readout voltage VrA. Readout voltage VrB is set between the "A" and "B" levels, readout voltage VrC is set between the "B" and "C" levels, readout voltage VrD is set between the "C" and "D" levels, readout voltage VrE is set between the "D" and "E" levels, readout voltage VrF is set between the "E" and "F" levels, and readout voltage VrG is set between the "F" and "G" levels.

[0098] Then, the read path voltage VPASS_READ is set to a voltage higher than the maximum threshold voltage of the highest threshold distribution (e.g., "G" level). The memory cell transistor MT, to which the read path voltage VPASS_READ is applied to the gate, becomes on regardless of the data stored.

[0099] Furthermore, the verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are, for example, set to be higher than the readout voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG, respectively. That is, the verification voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set near the lower edge of the threshold distributions of the "A," "B," "C," "D," "E," "F," and "G" levels, respectively.

[0100] When the data allocation described above is applied, the lower-level bit page data (lower page data) can be determined during the read operation using the read results of read voltages VrA and VrE. The middle-level bit page data (middle page data) can be determined using the read results of read voltages VrB, VrD, and VrF. The upper-level bit page data (upper page data) can be determined using the read results of read voltages VrC and VrG. Thus, the lower-level page data, middle-level page data, and upper-level page data are determined by 2, 3, and 2 read operations respectively. Therefore, the data allocation described above is called a "2-3-2 code".

[0101] Furthermore, the data allocation described above is merely an example, and actual data allocation is not limited to this. For example, 2 bits or more of data can be stored in a single memory cell transistor MT. Additionally, the number of threshold distributions for data allocation can be 7 or less, or 9 or more. For example, "1-3-3 code" or "1-2-4 code" can be used instead of "2-3-2 code". Furthermore, the allocation of lower-level bits / middle-level bits / higher-level bits can be changed, for example. More specifically, for example, in "2-3-2 code", data can be allocated by determining the lower-level page data using the readout results of readout voltages VrC and VrB, determining the middle-level page data based on the readout results of readout voltages VrB, VrD, and VrF, and determining the higher-level page data based on the readout results of readout voltages VrA and VrE. That is, for example, the allocation of lower-level bits and higher-level bits can be interchanged. In this case, data is allocated according to each level of the threshold voltage as follows.

[0102] "ER" level: "111" ("lower bit / middle bit / higher bit")

[0103] Level "A": 110

[0104] "B" level: 100

[0105] "C" level: "000"

[0106] "D" level: "010"

[0107] "E" level: "011"

[0108] "F" level: "001"

[0109] "G" level: 101

[0110] The write operation performed in the semiconductor memory device 2 will be described. The write operation includes a programming operation and a verification operation. The "programming operation" refers to the action of injecting electrons into the charge accumulation layer 336 of a portion of the memory cell transistor MT, thereby changing the threshold voltage of that memory cell transistor MT. The "verification operation" refers to the action of reading data after the programming operation to determine whether the threshold voltage of the memory cell transistor MT has reached the target level and to verify this. Once the threshold voltage of the memory cell transistor MT has reached the target level, writing to it is disabled.

[0111] During the write operation, the above programming and verification actions are repeatedly executed. As a result, the threshold voltage of the memory cell transistor MT rises to the target level.

[0112] Hereinafter, the word line WL connected to the memory cell transistor MT that is the object of a write operation (i.e., the object that causes a change in the threshold voltage) will also be referred to as the "select word line". In addition, the word line WL connected to the memory cell transistor MT that is not the object of a write operation will also be referred to as the "non-select word line".

[0113] Hereinafter, the string unit SU that becomes the object of the write operation will be referred to as the "selected string unit". In addition, the string unit SU that is not the object of the write operation will be referred to as the "non-selected string unit".

[0114] Explain the programming actions. Figure 7 This indicates the potential changes of each wiring during the programming operation. During programming, the readout amplifier 120 changes the potential of each bit line BL in accordance with the programming data. For the bit line BL connected to the memory cell transistor MT that is being programmed (which should raise the threshold voltage), a voltage such as ground Vss (0V) is applied as an "L" level. For the bit line BL connected to a memory cell transistor MT that is not being programmed (which should maintain the threshold voltage), a voltage such as 2.5V is applied as an "H" level. The former bit line BL... Figure 7 The latter is marked as "BL(0)". The bit line BL in the latter... Figure 7 The Chinese character is marked as "BL(1)".

[0115] The line decoder 130 selects any block BLK as the target of the write operation, and then selects any serial cell SU. More specifically, the voltage generation circuit 43 applies, for example, 5V to the select gate line SGD (select gate line SGDsel) in the selected serial cell SU via the line decoder 130. This turns on the select transistor ST1. On the other hand, the voltage generation circuit 43 applies, for example, a voltage Vss to the select gate line SGS via the line decoder 130. This turns on the select transistor ST2.

[0116] Additionally, a voltage of, for example, 5V is applied from the voltage generation circuit 43 to the selection gate line SGD (non-selection selection gate line SGDusel) of the non-selection string unit SU in the selection block BLK via the line decoder 130. This turns on the selection transistor ST1. Furthermore, in the string units SU included in each block BLK, the selection gate line SGS is connected to a common ground. Therefore, in the non-selection string unit SU, the selection transistor ST2 is also turned off.

[0117] Furthermore, voltage Vss is applied, for example, to the select gate line SGD and select gate line SGS in the non-selection block BLK via the voltage generation circuit 43 and the line decoder 130. As a result, select transistors ST1 and ST2 are turned off.

[0118] The source line SL is set to a potential higher than that of the select gate line SGS. This potential is, for example, 1V.

[0119] Then, the potential of the select gate line SGDsel in the select block BLK is set to, for example, 2.5V. This potential is the voltage that turns on the select transistor ST1 corresponding to the bit line BL(0), which was given 0V in the above example, but turns off the select transistor ST1 corresponding to the bit line BL(1), which was given 2.5V. Thus, in the select string unit SU, the select transistor ST1 corresponding to the bit line BL(0) is turned on, and the select transistor ST1 corresponding to the bit line BL(1), which was given 2.5V, is turned off. On the other hand, the potential of the non-select gate line SGDusel is set to, for example, voltage Vss. Thus, in the non-select string unit SU, the select transistor ST1 is turned off regardless of the potentials of the bit lines BL(0) and BL(1).

[0120] Furthermore, the line decoder 130 selects any word line WL as the target for a write operation within the selection block BLK. A voltage, for example, VPGM is applied from the voltage generation circuit 43 to the word line WL (selected word line WLsel) that is the target for the write operation via the line decoder 130. On the other hand, a voltage, for example, VPASS_PGM is applied from the voltage generation circuit 43 to other word lines WL (non-selected word lines WLusel) via the line decoder 130. The voltage VPGM is a high voltage used to inject electrons into the charge storage layer 336 through tunneling. The voltage VPASS_PGM is a voltage that turns on the memory cell transistor MT connected to the word line WL, while maintaining a critical constant voltage. VPGM is a voltage higher than VPASS_PGM.

[0121] In the NAND string NS corresponding to the bit line BL(0) of the programming object, the selection transistor ST1 becomes on. Therefore, the channel potential of the memory cell transistor MT connected to the selection word line WLsel becomes 0V. The potential difference between the control gate and the channel increases, resulting in electrons being injected into the charge accumulation layer 336, thus raising the threshold voltage of the memory cell transistor MT.

[0122] In the NAND string NS corresponding to the bit line BL(1) which is not the programming object, the selection transistor ST1 becomes off. Therefore, the channel of the memory cell transistor MT connected to the selection word line WLsel is electrically floated, and the channel potential rises to near the voltage VPGM through capacitive coupling with word lines WL, etc. The potential difference between the control gate and the channel decreases, resulting in no electron injection into the charge accumulation layer 336, thus maintaining the threshold voltage of the memory cell transistor MT. More precisely, the higher the threshold voltage distribution level, the less it fluctuates.

[0123] The readout action is explained below. Furthermore, the verification action performed after the programming action is the same as the readout action described below. Figure 8 This indicates the potential changes of each wiring during a read operation. During a read operation, the NAND string NS, including the memory cell transistor MT that is the target of the read operation, is selected. Alternatively, the string cell SU, including the page that is the target of the read operation, is selected.

[0124] First, a voltage of, for example, 5V is applied from the voltage generation circuit 43 to the select gate line SGDsel, the non-select select gate line SGDusel, and the select gate line SGS via the row decoder 130. This turns on the select transistors ST1 and ST2 included in the select block BLK. Additionally, a read path voltage VPASS_READ is applied from the voltage generation circuit 43 to the select word line WLsel and the non-select word line via the row decoder 130. The read path voltage VPASS_READ is a voltage that turns on the memory cell transistor MT regardless of its threshold voltage and prevents the threshold voltage from changing. Therefore, regardless of whether it is a select string cell SU or a non-select string cell SU, the bit line BL is connected to the source line layer 320 in all NAND strings NS included in the select block BLK.

[0125] Next, for the word line WL (select word line WLsel) connected to the memory cell transistor MT that is the object of the read operation, a read voltage Vr, such as VrA, is applied from the voltage generation circuit 43 via the line decoder 130. For other word lines (non-select word lines WLusel), a read path voltage VPASS_READ is applied.

[0126] Additionally, while maintaining the voltage applied to the select gate line SGDsel and the select gate line SGS, a voltage, for example Vss, is applied from the voltage generation circuit 43 to the non-select select gate line SGDusel via the line decoder 130. As a result, the select transistor ST1 included in the select string unit SU remains in the on state, but the select transistor ST1 included in the non-select string unit SU becomes in the off state. Furthermore, regardless of whether it is the select string unit SU or the non-select string unit SU, the select transistor ST2 included in the select block BLK becomes in the on state.

[0127] Therefore, the NAND string NS included in the non-selection string cell SU will at least have the selection transistor ST1 turned off, thus not forming a current path. On the other hand, the NAND string NS included in the selection string cell SU will form or not form a current path depending on the relationship between the read voltage Vr applied to the select word line WLsel and the threshold voltage of the memory cell transistor MT.

[0128] The sense amplifier 120 applies a voltage, for example, 1.5V, to the bit line BL connected to the selected NAND string NS. Additionally, the potential of the source line SL is, for example, 0.5V at this time.

[0129] In this state, the sense amplifier 120 reads data based on the value of the current flowing through the bit line BL. Specifically, it determines whether the threshold voltage of the memory cell transistor MT, which is the target of the read operation, is higher than the read voltage applied to the memory cell transistor MT. Alternatively, data readout may be based not on the value of the current flowing in the bit line BL, but on the time-varying potential in the bit line BL. In the latter case, the bit line BL is pre-charged to a predetermined potential.

[0130] The verification operation described earlier is performed in the same way as the read-out operation described above. In the verification operation, for example, a verification voltage such as VfyA is applied from the voltage generation circuit 43 to the word line WL connected to the memory cell transistor MT that is being verified via the line decoder 130.

[0131] Additionally, the action of applying a 5V voltage to the select gate line SGDsel and the non-select gate line SGDusel in the initial stage of the previously described programming operation is sometimes omitted. Similarly, the action of applying a 5V voltage to the non-select gate line SGDusel and applying the read path voltage VPASS_READ to the select word line WLsel in the initial stage of the previously described read operation (verification operation) is sometimes omitted.

[0132] The erase operation is explained below. During the erase operation, all data in the memory cell transistors MT included in the block BLK that will be the target area is erased together.

[0133] During the erase operation, the potentials of both the bit line BL and the source line SL are set to VERA. "VERA" is the potential required to erase the data in the memory cell transistor MT, for example, 20V.

[0134] The gate lines SGD and SGS are each selected at a potential lower than VERA, for example, set to 13V. In each of the selector transistors ST1 and ST2, GIDL is generated based on the potential difference between each gate line and VERA, and the generated holes charge the channels of each NAND string NS. As a result, the potential of the channels of the NAND string NS rises to VERA.

[0135] At this point, the potential of each word line WL is set to a sufficiently low potential compared to the aforementioned VERA (e.g., ground potential). In each memory cell transistor MT, the threshold voltage decreases due to the potential difference between the outer word line WL and the inner channel, thereby erasing the data.

[0136] However, in both the programming and reading operations, the potential of the source line SL, i.e., the potential of the source line layer 320, must be maintained at the specified target potential as described above. For example, in Figure 8 In the readout operation shown, when the potential of the source line layer 320 is higher than the target potential (0.5V in this example), it is impossible to properly determine the threshold voltage of the memory cell transistor MT, making it difficult to accurately read the data.

[0137] However, in the source line layer 320, local potential fluctuations sometimes occur as current flows in from the multiple memory pillars MP. In particular, as in this embodiment, when the source line layer 320 is formed of polysilicon with relatively high resistance, local potential fluctuations in the source line layer 320 are prone to occur.

[0138] Therefore, the semiconductor memory device 2 of this embodiment includes a circuit for adjusting the potential of the source line layer 320. Before describing this circuit, the specific structure of the memory cell array 110 will be described first.

[0139] Figure 9 This is a top-down schematic diagram illustrating the configuration of multiple blocks BLK of the memory cell array 110. As shown in the diagram, the multiple blocks BLK are configured to extend along the direction of the bit line BL (in... Figure 9 There are multiple blocks arranged in a vertical direction (as described above). Conductors LI are configured between adjacent blocks BLK.

[0140] like Figure 9 As shown, only one source line layer 320 is provided in the entire memory cell array 110, and it is formed in a top view within a range that can include all blocks BLK. That is, in this embodiment, a single source line layer 320 is shared in all blocks BLK.

[0141] Each bit line (BL) extends in a manner that intersects with each block (BLK), with one end connected to... Figure 2 The sense amplifier 120 is connected. The bit line BL is connected along... Figure 9 The elements are arranged at equal intervals in the left and right directions. However, in the central part in the left and right directions, specifically in the area marked with reference numeral "302", the bit line BL is not provided. This area will also be referred to as "connection area 302" below.

[0142] In the connection area 302 of each block BLK, neither bit lines (BL) nor storage pillars (MP) are set. The area outside the connection area 302 in the block BLK, i.e., the area with storage pillars (MP), is also referred to as "cell area 301". The aforementioned connection area 302 becomes the area connecting the two cell areas 301 located on the left and right sides.

[0143] exist Figure 10 In the diagram, the connecting region 302 and the structure in its vicinity are shown as a cross-sectional view. Figure 10 The cross section shown is the cross section when the memory cell array 110 is cut perpendicularly to the direction in which the bit line BL extends.

[0144] In cell region 301, wiring layers 333, 332, and 331 are stacked at intervals, with an insulating layer 350 formed between them. Additionally, an insulating layer 352 is formed around the bit line BL and contact plug 339 disposed on the upper side of cell region 301. Figure 10 The part marked with the reference numeral "360" on the lower side is an insulating layer formed between the source line layer 320 and the semiconductor substrate 300, which is the insulating layer covering the periphery circuit PER.

[0145] In such Figure 9 When viewed from above, the storage columns MP are distributed in a lattice pattern, resulting in... Figure 9 , Figure 10 There are multiple storage columns arranged in a left-right direction. A dummy column DP is positioned further outwards from the storage column MP located at the very end of this arrangement. Figure 10 In the cross section, two dummy columns DP are arranged near the end of the unit region 301 that becomes the connection region 302.

[0146] A dummy pillar DP is a pillar with the same structure as a memory pillar MP, formed simultaneously during the formation of the memory pillar MP. Similar to the memory pillar MP, the dummy pillar DP extends through wiring layers 333, 332, and 331 in the vertical direction, with its lower end connected to the source line layer 320. Therefore, the portions of the dummy pillar DP that intersect with each wiring layer function as transistors. However, the dummy pillar DP is not used for data storage.

[0147] In this way, among the multiple pillars formed in cell region 301, the pillars formed at the ends are not used as storage pillars (MP) for storing data, but become dummy pillars (DP). That is, only the pillars located in the inner region of the multiple pillars arranged in a grid pattern are used as storage pillars (MP). By excluding the pillars at the ends that are prone to deviating from a uniform shape from the storage pillars (MP), data writing and reading can be performed with high precision.

[0148] A dummy bit line DBL is provided on the upper side of the dummy post DP. The dummy bit line DBL is a conductor that extends parallel to the bit line BL and is connected to the end of the dummy post DP opposite to the source line layer 320 via a contact plug 340. The shape (e.g., width dimension) of the dummy bit line DBL may be the same as or different from that of the bit line BL.

[0149] like Figure 9 as well as Figure 10 As shown, in unit region 301, a dummy post DP is provided not only near the end that becomes the connection region 302, but also near the end that becomes the opposite side of the connection region 302, and a dummy bit line DBL connected thereto is also provided.

[0150] In connection area 302, each wiring layer 333, 332, and 331 connects to... Figure 10 The unit region 301 located on the left side is led out in a stepped manner. That is, each wiring layer 333, 332, 331 is formed to extend longer towards the inside of the connection region 302 the closer to the lower layer.

[0151] In the connection area 302, a portion of each wiring layer 333, 332, and 331 is exposed upwards, and the lower end of a contact 341 extending from above connects to each exposed portion. The contact 341 is, for example, a columnar component formed of a conductive material such as tungsten. The upper end of the contact 341 is connected to the wiring 370 via a contact 342. The wiring 370 is used to apply voltage to the wiring layers 333, 332, and 331. Furthermore, the contact 342 and the wiring 370 are independently provided corresponding to each contact 341, but... Figure 10 Only one set is shown in the figure. An insulating layer 351 is formed on the side above the wiring layers 333, 332, 331 in the connection area 302, that is, around the contact 341 and the support post SP described below.

[0152] Multiple support pillars SP are formed in the connection region 302. The support pillars SP are provided during the manufacturing process of the semiconductor memory device 10 for the purpose of reinforcing the stepped insulating layer 350. The support pillars SP are formed, for example, from silicon oxide.

[0153] The wiring layers 333, 332, and 331, which are formed in a stepped shape, are respectively with Figure 10 The wiring layers 333, 332, and 331 in the left-side unit region 301 are directly connected. Additionally, the stepped wiring layers 333, 332, and 331 are each connected to… Figure 10The wiring layers 333, 332, and 331 of the cell region 301 located on the right side are electrically connected via a bridge portion BR formed in a left-right direction extending on the inside or near the front of the paper. Additionally, in Figure 10 In the middle, only one of the bridge sections BR is represented by a dashed line, which is arranged in a manner that is arranged in multiple ways along the vertical direction.

[0154] With this structure, voltage can be applied independently to each of the wiring layers 333, 332, and 331 of the cell region 301 via the contact 341. By adopting a configuration in which a connection region 302 is provided in the center of the block BLK and voltage is applied from the connection region 302 to the wiring layers 333, 332, and 331 of the cell regions 301 located on the left and right sides, the potential of the wiring layer 331, etc., can reach the target potential in a short time.

[0155] refer to Figure 11 The circuitry used to adjust the potential of source line layer 320 is described. Figure 11 The diagram schematically depicts the source line layer 320 and multiple dummy pillars DP disposed on the source line layer 320. Additionally, Figure 11 The multiple dummy columns (DPs) shown are dummy columns set in different blocks (BLKs) and are connected to the same dummy bit line (DBL). Furthermore, in each block (BLK) of the storage cell array 110, at least one dummy column (DP) is connected to the same dummy bit line (DBL). Figure 11 The dummy bit line DBL shown is connected to the dummy post DP.

[0156] A dummy bit line DBL, which connects to multiple dummy posts DP, is connected to one end of transistor TR11 via wiring 401. Transistor TR11 is a circuit element disposed on semiconductor substrate 300 as part of peripheral circuit PER, along with comparator CP, transistors TR12, TR13, and TR14, which will be described later. Wiring 401 includes, for example, contacts extending perpendicularly to the surface of semiconductor substrate 300.

[0157] The other end of transistor TR11 is connected to input terminal IP1 of comparator CP. Another input terminal IP2 of comparator CP is connected to the reference potential REF. The output terminal of comparator CP is connected to the gate of transistor TR14.

[0158] One end of transistor TR14 is connected to source line layer 320 via wiring 405 and conductor LI, and the other end is grounded. Wiring 405 includes, for example, contacts extending perpendicularly to the surface of semiconductor substrate 300. In addition, conductor LI connecting wiring 405 may be a part or all of the plurality of conductors LI included in memory cell array 110.

[0159] The comparator CP adjusts the opening of transistor TR14 based on the magnitude of the voltages input to input terminals IP1 and IP2. Specifically, when the voltage input to input terminal IP1 increases, the opening of transistor TR14 is increased, thereby increasing the current flowing to the ground side through transistor TR14.

[0160] Wiring 402 connects to the portion between the dummy bit line DBL in wiring 401 and transistor TR11. Wiring 402 branches into wiring 403 and wiring 404. A potential VERA is input to wiring 403 via transistor TR12. A potential VDDSA is input to wiring 404 via transistor TR13. The switching operations of transistors TR11, TR12, and TR13 are all controlled by sequence generator 41.

[0161] exist Figure 11 The circuit depicted below the source line layer 320 can be configured as follows: Figure 2 A portion of the voltage generation circuit 43 shown.

[0162] The circuit operation during the readout process is explained. During the readout process, the sequence generator 41 closes transistor TR11 (turns on) and turns transistors TR12 and TR13 open (turns off).

[0163] For reference Figure 8 As explained, during the read operation, a voltage of, for example, 5V is applied to the select gate line SGDsel and the select gate line SGS. Additionally, a read voltage Vr is applied to the select word line WLsel, and a read path voltage VPASS_READ is applied to the other non-select word lines WLusel.

[0164] The same voltage applied to each wiring is also applied to the dummy pillars DP included in the same selected block BLK. In this dummy pillar DP, all transistors arranged along its length are in a closed state, and the dummy bit line DBL is connected to the source line layer 320 via this dummy pillar DP. In the dummy pillars DP included in other non-selected blocks BLK, each transistor is in an open state; therefore, in the non-selected block BLK, the dummy bit line DBL is not connected to the source line layer 320.

[0165] At this time, the potential of the portion of the source line layer 320 connected to the lower end of the dummy pillar DP included in the selection block BLK is input to the input terminal IP1 of the comparator CP. Based on the signal output from the output terminal OP of the comparator CP, the opening degree of transistor TR14 is adjusted, thereby adjusting the potential of the source line layer 320. As a result, the potential input to the input terminal IP1 eventually becomes consistent with the reference potential REF. That is, the potential of the portion of the source line layer 320 connected to the lower end of the dummy pillar DP included in the selection block BLK becomes consistent with the reference potential REF. Therefore, if the reference potential REF is preset to the target potential of the source line SL during the readout operation (in... Figure 8 In the example, if the voltage is 0.5V, then the potential directly below at least the selected block BLK in the source line layer 320 is automatically adjusted to the target potential.

[0166] exist Figure 11 In the circuit shown, the wiring from the dummy post DP, contact plug 340, dummy bit line DBL, wiring 401, transistor TR11 and the wiring from transistor TR11 to the input terminal IP1 functions as a circuit for obtaining the potential of the source line layer 320, and is therefore equivalent to the "obtaining circuit" in this embodiment.

[0167] In addition, Figure 11 In the circuit shown, the comparator CP, transistor TR14, wiring 405, and conductor LI function as a circuit to adjust the potential of the source line layer 320 to a predetermined target potential (i.e., reference potential REF), and are therefore equivalent to the "first adjustment circuit" in this embodiment.

[0168] The potential of the source line layer 320 acquired by the acquisition circuit is performed during the readout operation as described above. Additionally, the potential adjustment of the source line layer 320 by the first adjustment circuit is also performed during the readout operation.

[0169] However, among the multiple transistors included in the dummy pillar DP, it is assumed that if a portion of the threshold voltage rises above the readout voltage Vr, the transistor remains on and does not conduct based on the dummy pillar DP. Therefore, the acquisition circuit cannot acquire the potential of the source line layer 320 as described above.

[0170] Therefore, during programming, it is necessary to prevent the threshold voltage of each transistor in the dummy bit DP from rising and to maintain each threshold voltage at the "ER" level. Therefore, in this embodiment, the sequence generator 41 turns on transistors TR11 and TR12 during programming, while turning off transistor TR13. Thus, the potential of the dummy bit line DBL connected to each block BLK becomes potential VDDSA. Potential VDDSA is, for example, 2.5V. Figure 7In the example, the potential applied to BL(1) is given. When the potential of the dummy bit line DBL becomes potential VDDSA, the transistor corresponding to the selection transistor ST1 in the dummy pillar DP becomes off, so the threshold voltage of each transistor included in the dummy pillar DP does not rise. Potential VDDSA can be called "the potential at which no data is written to the transistors of the dummy pillar DP".

[0171] In this way, during programming, by adjusting the potential of the dummy bit line DBL to the potential VDDSA, the threshold voltage of each transistor included in the dummy pillar DP will not rise, thus maintaining the initial "ER" level unchanged.

[0172] exist Figure 11 In the circuit shown, transistor TR13, wiring 404, wiring 401, dummy bit line DBL, and contact plug 340 function as a circuit for adjusting the potential of dummy bit line DBL, and are therefore equivalent to the "second adjustment circuit" in this embodiment.

[0173] In this embodiment, during the erase operation, the sequence generator 41 turns on transistors TR11 and TR13, while turning off transistor TR12. As a result, the potential of the dummy bit line DBL connected to each block BLK becomes potential VERA. As described above, "VERA" is the potential required to erase data from the memory cell transistor MT, for example, 20V. During the erase operation, the potential of the dummy bit line DBL becomes potential VERA; therefore, in the dummy column DP connected to the dummy bit line DBL, similarly to the other memory columns MP included in the same block, the threshold voltage of each transistor drops to the "ER" level. By performing the above operation during the erase operation, the threshold voltage of each transistor in the memory column MP can be maintained at the "ER" level more reliably. Potential VERA can be referred to as "the potential for erasing data from the transistors of the dummy column DP".

[0174] exist Figure 11 In the circuit shown, transistor TR12, wiring 403, wiring 401, dummy bit line DBL, and contact plug 340 function as a circuit for adjusting the potential of dummy bit line DBL, and are therefore equivalent to the "second adjustment circuit" in this embodiment.

[0175] Furthermore, in transistor TR11, which is part of the acquisition circuit, a relatively high voltage, such as 20V, is applied during the erase operation. Therefore, a high-voltage transistor is used as transistor TR11. High-voltage transistors are also used in the same way for transistors TR12, TR13, and TR14. High-voltage transistors are configured such that insulation failure does not occur even when a relatively high voltage is applied, which is significant compared to conventional transistors.

[0176] To illustrate the advantages of the structure using this embodiment, Figure 12 The comparative example shown will be explained. In this comparative example, the comparator CP and transistor TR14 are also included as circuit elements for adjusting the potential of the source line layer 320. However, in this comparative example, the dummy pillar DP and dummy bit line DBL are not provided.

[0177] The wiring extending from transistor TR14 is connected to source line layer 320.

[0178] Wiring 401 is connected to input terminal IP1 of comparator CP. Wiring 401 is used to obtain the potential near the selected block BLK in the readout operation of source line layer 320. Wirings 410, 413, 416, and 419 are connected to wiring 401. Wiring 410 is connected to the portion directly below block BLK0 in source line layer 320. Wiring 413 is connected to the portion directly below block BLK3 in source line layer 320. Wiring 416 is connected to the portion directly below block BLK6 in source line layer 320. Wiring 419 is connected to the portion directly below block BLK9 in source line layer 320.

[0179] A transistor TR20 is positioned midway through wiring 410. A transistor TR23 is positioned midway through wiring 413. A transistor TR26 is positioned midway through wiring 416. A transistor TR29 is positioned midway through wiring 419. The switching operation of these transistors is controlled by a sequence generator 41. High-voltage transistors are used as transistors TR20, TR23, TR26, and TR29.

[0180] For example, when block BLK0 becomes the selected block BLK in the readout operation, transistor TR20, which is directly below it, is closed, while transistors TR23, TR26, and TR29 are open. As a result, the potential near block BLK0, which serves as the selected block, in the source line layer 320 is adjusted to become the reference potential REF. Similarly, for example, when block BL6 becomes the selected block BLK in the readout operation, transistor TR26, which is directly below it, is closed, while transistors TR20, TR23, and TR29 are open. As a result, the potential near block BLK6, which serves as the selected block, in the source line layer 320 is adjusted to become the reference potential REF.

[0181] On the other hand, when block BLK1 becomes the selected block BLK in the readout operation, transistor TR20 connected nearby becomes closed, while transistors TR23, TR26, and TR29 become open. In this case, the potential near block BLK0 in the source line layer 320 is adjusted to the reference potential REF.

[0182] Here, block BLK1, serving as the selection block, is located separately from block BLK0. During the read operation, current from each memory cylinder MP flows through the source line layer 320, and the resistance of the source line layer 320 is relatively high. Therefore, a potential difference easily arises between the source line layer 320 directly below block BLK1 and the source line layer 320 directly below block BLK0. As a result, in the selection block (BLK1) during the read operation, the potential of the source line layer 320 directly below it becomes a different potential from the target potential (reference potential REF), potentially preventing correct data readout.

[0183] To solve this problem, one could simply connect the same wiring as wiring 410 directly below all blocks BLK in the memory cell array 110, and place transistors such as transistor TR20 along the middle of these wirings. However, such a structure would result in a larger semiconductor memory device 2, and is therefore not preferred. In particular, in structures where peripheral circuits PER are provided below the source line layer 320, the existing wiring used to connect the wiring on the upper side where bit lines BL are located to the peripheral circuits PER on the lower side is often wound around, making it difficult to provide additional wiring. Furthermore, as for transistors such as TR20, in order to prevent insulation damage even when a relatively high voltage is applied, high-voltage transistors larger than those of ordinary transistors are used. Therefore, as Figure 12 As with the comparative example, in the past, it was necessary to reduce the number of parts in the source line layer 320 that could be subject to potential adjustment, and sometimes it was not possible to properly adjust the potential of the source line layer 320.

[0184] In contrast, in the semiconductor memory device 2 of this embodiment, as described above, the potential directly below the select block BLK in the source line layer 320 is obtained via a dummy pillar DP, and this potential is automatically adjusted to the target potential. In this embodiment, it is also not necessary to set... Figure 12 The control of switching transistors such as TR20 shown, or switching transistors such as TR20 according to the selection block BLK, can simplify the structure of the semiconductor memory device 2.

[0185] Alternatively, the dummy post DP, which is part of the acquisition circuit, can be positioned near the stepped connection area 302 as in this embodiment, but it can also be positioned elsewhere. For example, in a part of the cell area 301, if a region is formed for electrically connecting the upper wiring to the lower peripheral circuit PER (i.e., a region for arranging vertically extending contacts), the dummy post DP can be positioned near that region.

[0186] The present embodiment has been described above with reference to specific examples. However, this disclosure is not limited to these specific examples. As long as these specific examples possess the features of this disclosure, they are all included within the scope of this disclosure. The elements, their configurations, conditions, shapes, etc., possessed by the above-described specific examples are not limited to the illustrated content and can be appropriately modified. The elements possessed by the above-described specific examples can be appropriately combined as long as they do not create technical contradictions.

[0187] [Explanation of reference numerals in the attached figures]

[0188] 2: Semiconductor memory device; 331, 332, 333: Wiring layer; Source line layer 320; MP: Memory pillar; DP: Dummy pillar; MT: Memory cell transistor.

Claims

1. A semiconductor memory device comprising: Multiple layers of letter lines are stacked alternately and spaced apart from each other; A memory column is a columnar body that runs through multiple word line layers, and the part that intersects with the word line layers functions as a memory cell transistor. The source line layer is connected to the end of the memory pillar; The circuit obtains the potential of the source line layer; as well as The first adjustment circuit adjusts the potential of the source line layer to a predetermined target potential. The acquisition circuit includes a dummy pillar that penetrates multiple word line layers. It is a pillar-shaped body whose ends are connected to the source line layer, and the portion that intersects with the word line layer functions as a transistor.

2. The semiconductor memory device according to claim 1, wherein, It also includes bit lines, which are conductors extending in a direction intersecting the direction in which the plurality of word line layers are stacked, and connected to the end of the memory pillar opposite to the source line layer. The acquisition circuit includes a dummy bit line, which is a conductor extending parallel to the bit line and connected to the end of the dummy pillar opposite to the source line layer.

3. The semiconductor memory device according to claim 2, wherein, The acquisition circuit acquires the potential of the source line layer when performing a readout operation to read data from the memory cell transistor.

4. The semiconductor memory device according to claim 3, wherein, It also includes a second adjustment circuit for adjusting the potential of the dummy bit line. When the second adjustment circuit performs the erase operation to erase data from the memory cell transistor, it adjusts the potential of the dummy bit line to the potential of the transistor that erases data from the dummy pin.

5. The semiconductor memory device according to claim 3, wherein, It also includes a second adjustment circuit for adjusting the potential of the dummy bit line. When the second adjustment circuit performs a programming operation to write data to the transistor of the memory cell, it adjusts the potential of the dummy bit line to a potential at which data is not written to the transistor of the dummy pin.

6. The semiconductor memory device according to claim 1, wherein, A circuit for controlling the operation of the memory cell transistor is provided at a position opposite to the memory pillar, separated by the source line layer.

7. The semiconductor memory device according to claim 1, wherein, The storage columns are arranged in multiple directions. The dummy column is positioned further outward along the specified direction compared to the storage column located at the very end along the specified direction.

8. The semiconductor memory device according to any one of claims 1 to 7, wherein, The acquisition circuit includes a high-voltage transistor.

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