Image sensor and manufacturing method

Abstract

The application relates to the technical field of image sensors, and provides an image sensor and a manufacturing method.The image sensor comprises a semiconductor substrate, a plurality of pixel regions, a metal interconnection layer and a blocking structure.The blocking structure is composed of an isolation structure arranged in the semiconductor substrate, a crosstalk modulation structure and a first contact hole structure which are sequentially arranged in a dielectric layer and correspond to the isolation structure.The blocking structure can form an effective light blocking wall structure on one hand, preventing light of one pixel region from being reflected by the metal interconnection layer and crosstalking into an adjacent pixel region; and on the other hand, the blocking structure can prevent over-etching of the isolation structure during processing of the first contact hole structure, thereby reducing the enrichment and diffusion of charges in the isolation structure, effectively improving the dark current performance of the device, and simultaneously reducing optical crosstalk and electrical crosstalk of the image sensor, which is conducive to improving the imaging quality of the image sensor.

Description

Technical Field

[0001] This application belongs to the field of image sensor technology, and more specifically, relates to an image sensor and a manufacturing method thereof. Background Technology

[0002] An image sensor is a device that uses the photoelectric conversion function of an optoelectronic device to convert a light image on a photosensitive surface into an electrical signal that is proportional to the light image. It can be divided into complementary metal-oxide-semiconductor (CMOS) image sensors and charge-coupled device (CCD) image sensors.

[0003] CCD image sensors excel in photosensitivity and noise reduction, but they are difficult to integrate and have high power consumption. In contrast, CMOS image sensors have simpler manufacturing processes and are suitable for applications requiring high integration and low power consumption. Therefore, CMOS image sensors are widely used and have become a research hotspot. In CMOS image sensors, crosstalk itself causes a decrease in color saturation, and the magnitude of crosstalk affects the quality of the final output image; the greater the crosstalk, the worse the final image quality. Furthermore, as pixel size continues to decrease, optical and electrical crosstalk become more severe, and the widespread application of CMOS image sensors places increasingly higher demands on the optical and electrical crosstalk components. Summary of the Invention

[0004] The purpose of this application is to provide an image sensor and a manufacturing method to solve the technical problem of poor image sensor imaging quality caused by crosstalk in the prior art.

[0005] To achieve the above objectives, the technical solution adopted in this application is: to provide an image sensor, including a semiconductor substrate, multiple pixel regions, a metal interconnect layer, and a blocking structure;

[0006] A plurality of pixel regions are disposed in the semiconductor substrate, and an isolation region for electrically isolating the pixel regions is defined between adjacent pixel regions. The metal interconnect layer is disposed in a dielectric layer on the front surface of the semiconductor substrate, and the blocking structure is disposed corresponding to the isolation region and the blocking structure is located at least between the isolation region and the metal interconnect layer.

[0007] The blocking structure includes an isolation structure disposed in the semiconductor substrate, a first contact hole structure disposed in the dielectric layer and corresponding to the isolation structure, and a crosstalk modulation structure disposed in the dielectric layer and corresponding to the isolation structure and the first contact hole structure; the isolation structure extends from the front surface into the interior of the semiconductor substrate.

[0008] Optionally, the number of metal interconnect layers is at least two layers, with the first metal interconnect layer being closer to the front surface of the semiconductor substrate. The side of the first metal interconnect layer closest to the front surface is in contact with the first contact hole structure. The crosstalk modulation structure is disposed on the front surface, and the first contact hole structure connected to the first metal interconnect layer is in contact with the crosstalk modulation structure.

[0009] Optionally, the image sensor further includes a device gate structure disposed on the front surface of the semiconductor substrate and located in the dielectric layer, the device gate structure being located between the pixel region and the metal interconnect layer, the crosstalk modulation structure being made of the same material as the device gate structure, and the crosstalk modulation structure being formed during the formation process of the device gate structure.

[0010] Optionally, the image sensor further includes a second contact hole structure disposed in the dielectric layer, the second contact hole structure being located between the pixel region and the metal interconnect layer, the first contact hole structure and the second contact hole structure being made of the same material, and the first contact hole structure being formed during the formation process of the second contact hole structure.

[0011] Optionally, the isolation structure is a shallow trench isolation structure.

[0012] Optionally, the width of the crosstalk modulation structure is smaller than the width of the isolation structure; and / or, the etching ratio of the dielectric layer to the crosstalk modulation structure is greater than the etching ratio of the dielectric layer to the isolation structure.

[0013] Optionally, the blocking structure surrounds all or part of the pixel region; and / or, the projected area of ​​the isolation structure corresponding to the front surface of the semiconductor substrate is greater than the projected area of ​​the crosstalk modulation structure corresponding to the front surface of the semiconductor substrate; and / or, the projected area of ​​the crosstalk modulation structure corresponding to the front surface of the semiconductor substrate is greater than the projected area of ​​the first contact hole structure corresponding to the front surface of the semiconductor substrate.

[0014] Optionally, the image sensor further includes a color filter layer disposed between the pixel region and the incident light;

[0015] And / or, the image sensor further includes a microlens disposed between the pixel region and the incident light;

[0016] And / or, the image sensor further includes a metal grid structure disposed between the pixel region and the incident light and corresponding to the isolation region.

[0017] Optionally, the crosstalk modulation structure is located on the surface of the isolation structure, and the first contact hole structure is in contact with both the corresponding metal interconnect layer and the corresponding crosstalk modulation structure.

[0018] Optionally, the image sensor is a back-illuminated image sensor, the semiconductor substrate further includes a back surface opposite to the front surface, and the pixel region includes a photodiode, which is used to convert light signals entering the semiconductor substrate from the back surface into electrical signals.

[0019] Optionally, the image sensor further includes a deep trench isolation structure disposed within the semiconductor substrate and close to the back surface, the deep trench isolation structure extending from the back surface toward the front surface and disposed opposite to the isolation structure in the blocking structure.

[0020] This application also provides a method for manufacturing the above image sensors, comprising the following steps:

[0021] A semiconductor substrate is provided, wherein a plurality of pixel regions are formed in the semiconductor substrate and an isolation structure is located between adjacent pixel regions, the isolation structure extending from the front surface of the semiconductor substrate toward the interior of the semiconductor substrate;

[0022] The crosstalk modulation structure is formed on the front surface of the semiconductor substrate, and the crosstalk modulation structure is formed on the isolation structure;

[0023] The dielectric layer is formed on the front surface of the semiconductor substrate such that the crosstalk modulation structure is located inside the dielectric layer;

[0024] The dielectric layer is etched to form the first contact hole structure, which is formed on the crosstalk modulation structure.

[0025] The metal interconnect layer is formed on the first contact hole structure so that the metal interconnect layer contacts the first contact hole structure.

[0026] Optionally, when the image sensor includes the device gate structure, the crosstalk modulation structure is formed during the formation of the device gate structure;

[0027] And / or, when the image sensor includes the second contact hole structure, the first contact hole structure is formed during the formation process of the second contact hole structure.

[0028] The beneficial effects of the image sensor provided in this application are as follows: Compared with the prior art, the image sensor of this application includes a semiconductor substrate, multiple pixel regions, a metal interconnect layer, and a blocking structure. Adjacent pixel regions are electrically isolated through an isolation region. The blocking structure is composed of an isolation structure disposed in the semiconductor substrate, a crosstalk modulation structure corresponding to the isolation structure and sequentially disposed in the dielectric layer, and a first contact hole structure. The blocking structure is correspondingly disposed with respect to the isolation region, and at least a portion of the blocking structure is located between the isolation region and the metal interconnect layer. The blocking structure formed by the above three parts effectively alleviates the crosstalk problem of the image sensor. Furthermore, the blocking structure of this application, on the one hand, forms an effective light-blocking barrier between the isolation region and the metal interconnect layer, preventing light from one pixel region from crosstalking to adjacent pixel regions due to reflection from the metal interconnect layer; on the other hand, the crosstalk modulation structure located between the isolation structure and the first contact hole structure can effectively prevent over-etching problems in the isolation structure during the fabrication of the first contact hole structure, thereby reducing charge accumulation and diffusion in the isolation structure and effectively improving the dark current performance of the device. In other words, by setting the above blocking structure, both optical and electrical crosstalk of the image sensor can be reduced simultaneously, which is beneficial to improving the imaging quality of the image sensor. The manufacturing method of the image sensor provided in this application is fully compatible with existing CMOS standard processes, and an image sensor with the above blocking structure can be manufactured without adding process steps, which can simultaneously reduce both optical and electrical crosstalk of the image sensor, thus improving the imaging quality of the image sensor. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the optical path of an existing image sensor (taking a back-illuminated sensor as an example).

[0031] Figure 2 (a), (b), (c), and (d) in the diagram are schematic diagrams of the process of directly connecting a conventional metal contact hole structure to an isolation structure.

[0032] Figure 3 This is a schematic cross-sectional view of the image sensor provided in an embodiment of this application;

[0033] Figure 4 This is a schematic diagram of the optical path of the image sensor provided in an embodiment of this application;

[0034] Figure 5 (a), (b), (c), and (d) in the figures are schematic diagrams of the manufacturing process of the image sensor provided in the embodiments of this application;

[0035] Figure 6 (a), (b), (c), and (d) are schematic diagrams of the image sensor provided in the embodiments of this application.

[0036] The following are the labeling elements in the figure:

[0037] 1. Semiconductor substrate; 11. Pixel area; 12. Isolation area; 13. Front surface; 14. Back surface; 15. Deep trench isolation structure; 2. First metal interconnect layer; 3. Barrier structure; 31. Isolation structure; 32. First contact hole structure; 33. Crosstalk modulation structure; 4. Dielectric layer; 5. Device gate structure; 6. Second contact hole structure; 7. Color filter layer; 8. Microlens; 9. Metal grid structure. Detailed Implementation

[0038] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0039] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0040] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0042] The image sensor provided in the embodiments of this application will now be described. In existing image sensors, when light passes through the metal interconnect layer (such as in a front-illuminated image sensor) or when longer wavelength light waves penetrate the semiconductor substrate and incident on the metal interconnect layer (such as in a back-illuminated image sensor), there is a problem where the metal interconnect layer reflects light, causing crosstalk to adjacent pixel areas, thereby affecting the image quality of the image sensor. See also... Figure 1 This application addresses this problem existing in image sensors by making innovative improvements. Without violating relevant process design standards or changing standard process flow, it achieves effective reduction of optical crosstalk and significantly improves the dark current performance of the device.

[0043] It is understood that the image sensor of this application, in addition to the elements and structures involved in the inventive points of this application, also includes other elements and structures included in existing image sensors, such as decoders, drivers, converters and other various elements. In order to clearly illustrate the technical solution of this application, the following description focuses only on the core elements and structures that contribute to the technical problem to be solved by this application. Those skilled in the art should be able to understand the other elements and structures included in the image sensor of this application in combination with the prior art.

[0044] Please refer to the following: Figure 3 and Figure 6 The image sensor provided in this application includes a semiconductor substrate 1, multiple pixel regions 11, a metal interconnect layer, and a blocking structure 3.

[0045] Among them, the semiconductor substrate 1 serves as the substrate of the image sensor. The appropriate substrate material and structure can be selected according to actual needs. For example, the semiconductor substrate 1 material can be silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium. The semiconductor substrate 1 can also be a silicon substrate on an insulator or a germanium substrate on an insulator. The following example uses a silicon substrate as the semiconductor substrate.

[0046] Among them, combined Figure 6Multiple pixel regions 11 are disposed in a semiconductor substrate 1, and an isolation region 12 is defined between adjacent pixel regions 11 for electrically isolating the pixel regions 11. Specifically, the arrangement of the multiple pixel regions 11 in the semiconductor substrate 1 can be configured in accordance with common arrangement methods in the prior art, such as a matrix arrangement. Here, the pixel region 11 specifically refers to the effective pixel region 11. To prevent crosstalk such as light incident on each pixel region 11 to adjacent pixel regions 11, an isolation region 12 is defined between adjacent pixel regions 11, thereby electrically isolating each pixel region 11 from other pixel regions 11. Figure 6 From the planar view of the image sensor, each pixel region 11 is surrounded by an isolation region 12, and the pixel region 11 and the isolation region 12 mutually define each other's areas. The arrangement of the pixel region 11 and the isolation region 12 in the semiconductor substrate 1 can be designed with reference to relevant existing technologies.

[0047] Among them, combined Figure 3 A metal interconnect layer is disposed in a dielectric layer 4 on the front surface 13 of the semiconductor substrate 1. A barrier structure 3 is disposed corresponding to the isolation region 12, and the barrier structure 3 is located at least between the isolation region 12 and the metal interconnect layer. Specifically, one end face of the semiconductor substrate 1 is defined as the front surface 13. A dielectric layer 4 is disposed on the front surface 13 as an interlayer insulating layer according to the existing CMOS standard process flow. A metal interconnect layer is disposed in the interlayer dielectric layer 4, which can be used to realize the interconnection and electrical extraction of relevant electrical signals in the image sensor.

[0048] Combination Figure 1 Because existing image sensors suffer from crosstalk caused by reflections from the metal interconnect layer, relying solely on the isolation region 12 is insufficient to prevent this problem. Therefore, in combination with... Figure 3 Based on the isolation area 12, a blocking structure 3 is set so that the blocking structure 3 is set in correspondence with the isolation area 12.

[0049] Specifically, the barrier structure 3 is located at least between the isolation region 12 and the metal interconnect layer, combined with Figure 3 The longitudinal cross-sectional view of the image sensor shows that, with the blocking structure 3 and the isolation region 12 correspondingly set, at least a portion of the structure in the blocking structure 3 is located between the semiconductor substrate 1 and the metal interconnect layer.

[0050] The blocking structure 3 includes an isolation structure 31 disposed in the semiconductor substrate 1, a first contact hole structure 32 disposed in the dielectric layer 4 and corresponding to the isolation structure 31, and a crosstalk modulation structure 33 disposed in the dielectric layer 4 and corresponding to the isolation structure 31 and the first contact hole structure 32; the isolation structure 31 extends from the front surface 13 into the interior of the semiconductor substrate 1.

[0051] Specifically, the barrier structure 3 is composed of an isolation structure 31 disposed in the semiconductor substrate 1, a crosstalk modulation structure 33 corresponding to the isolation structure 31 and disposed sequentially in the dielectric layer 4, and a first contact hole structure 32.

[0052] The isolation structure 31, as part of the barrier structure 3, extends from the front surface 13 of the semiconductor substrate 1 into the interior of the semiconductor substrate 1. The isolation structure 31 can be a trench structure (such as a shallow trench isolation structure or a deep trench isolation structure), or other structures that can electrically isolate adjacent pixel regions 11, or it can be a local oxide of silicon (LOCOS) isolation structure. The isolation structure 31 is mainly composed of oxides.

[0053] In general, a portion of the barrier structure 3 (crosstalk modulation structure 33 and first contact hole structure 32) is located between the semiconductor substrate 1 and the metal interconnect layer, while another portion of the barrier structure 3 (isolation structure 31) extends into the semiconductor substrate 1. The isolation structure 31 extending into the semiconductor substrate 1 is located within the isolation region 12.

[0054] Specifically, in combination Figure 2 In embodiments (a) to (d), the isolation structure 31, as part of the isolation region 12, is formed in the semiconductor substrate 1, and extends from the front surface 13 into the interior of the semiconductor substrate 1. Using existing image sensor manufacturing processes, the isolation structure 31 is directly adjacent to or in contact with the contact hole structure. During the processing of the contact hole structure, over-etching can easily occur, causing the contact hole structure and the corresponding isolation structure 31 to be etched through together. This results in the accumulation and diffusion of charge in the metal within the isolation structure 31, affecting the device's dark current performance. Therefore, the crosstalk modulation structure 33 disposed between the isolation structure 31 and the first contact hole structure 32 has an etching-preventing function. It can effectively prevent over-etching of the isolation structure 31 during the processing of the first contact hole structure 32, preventing some charge from entering the interior of the isolation structure 31 due to over-etching, causing accumulation and diffusion, and thus triggering dark current. The crosstalk modulation structure 33, while constituting a light-blocking structure, can also effectively improve and reduce dark current.

[0055] Compared with the prior art, the image sensor provided in this application includes a semiconductor substrate 1, multiple pixel regions 11, a metal interconnect layer, and a blocking structure 3. Adjacent pixel regions 11 are electrically isolated by an isolation region 12. The blocking structure 3 is composed of an isolation structure 31 disposed in the semiconductor substrate 1, a crosstalk modulation structure 33 corresponding to the isolation structure 31 and sequentially disposed in the dielectric layer 4, and a first contact hole structure 32. The blocking structure 3 is correspondingly disposed to the isolation region 12, and at least a portion of the blocking structure 3 is located between the isolation region 12 and the metal interconnect layer. The blocking structure 3, on the one hand, provides electrical isolation between the isolation region 11 and the metal interconnect layer. An effective light-blocking structure is formed between domain 12 and the metal interconnect layer to prevent light from one pixel region 11 from being reflected by the metal interconnect layer and crosstalking into adjacent pixel regions 11. On the other hand, the crosstalk modulation structure 33 located between the isolation structure 31 and the first contact hole structure 32 can effectively prevent over-etching problems of the isolation structure 31 during the processing of the first contact hole structure 32, thereby reducing the accumulation and diffusion of charge in the isolation structure 31 and effectively improving the dark current performance of the device. That is, by setting the above blocking structure 3, the optical crosstalk and electrical crosstalk of the image sensor can be reduced at the same time, which is beneficial to improving the imaging quality of the image sensor.

[0056] In another embodiment of this application, please refer to Figure 3 and Figure 4 The number of metal interconnect layers is at least two. The first metal interconnect layer 2 is located near the front surface 13 of the semiconductor substrate 1. The side of the first metal interconnect layer 2 near the front surface 13 is in contact with the first contact hole structure 32. The crosstalk modulation structure 33 is disposed on the front surface 13, and the first contact hole structure 32 connected to the first metal interconnect layer 2 is in contact with the crosstalk modulation structure 33.

[0057] Specifically, in this embodiment, at least two metal interconnect layers can be provided according to different circuit processing requirements, that is, two or more metal interconnect layers can be provided in a stacked manner. The layer closest to the front surface 13 of the semiconductor substrate 1 is defined as the first metal interconnect layer 2, and the blocking structure 3 is mainly provided for the first metal interconnect layer 2. Specifically, the crosstalk modulation structure 33 is provided on the front surface 13 of the semiconductor substrate 1, that is, the crosstalk modulation structure 33 is adjacent to the corresponding isolation structure 31. One end of the first contact hole structure 32 contacts the side of the first metal interconnect layer 2 closest to the front surface 13 of the semiconductor substrate 1, while the other end of the first contact hole structure 32 contacts the corresponding crosstalk modulation structure 33.

[0058] Preferably, the crosstalk modulation structure 33 contacts the first contact hole structure 32, and the first contact hole structure 32 contacts the first metal interconnect layer 2. This can be understood as the three being tightly connected in sequence without gaps, thereby ensuring the formation of a tight light-blocking wall structure. Figure 4 The blocking structure 3 can prevent light reflected by the first metal interconnect layer 2 from entering the adjacent pixel area 11, thereby reducing optical crosstalk caused by such reflection.

[0059] In other embodiments, for cases involving multiple metal interconnect layers, light incident on other metal interconnect layers besides the first metal interconnect layer 2 can be blocked using contact hole structures at points where conduction is required between the interconnect layers. Alternatively, in other embodiments, the blocking structure can also contact other metal interconnect layers besides the first metal interconnect layer 2; that is, the first contact hole structure 32 is formed between the crosstalk modulation structure 33 and other corresponding metal interconnect layers and contacts both of them.

[0060] In another embodiment of this application, please refer to Figure 3 , Figure 5 In (a) to (d), the image sensor also includes a device gate structure 5 disposed on the front surface 13 of the semiconductor substrate 1 and located in the dielectric layer 4. The device gate structure 5 is located between the pixel region 11 and the metal interconnect layer. The crosstalk modulation structure 33 is made of the same material as the device gate structure 5 and is formed during the formation of the device gate structure 5.

[0061] Specifically, in this embodiment, the device gate structure 5 can be the gate structure of any transistor in the pixel region of the prior art, such as the gate of the transmission transistor TX, the gate of the reset transistor REST, etc. Before forming the dielectric layer 4 on the surface of the semiconductor substrate 1, the device gate structure 5 is prepared according to the standard process flow. At the same time, the crosstalk modulation structure 33 is also completed, that is, the crosstalk modulation structure 33 can be prepared without adding additional process steps or changing the standard CMOS process flow.

[0062] Specifically, the crosstalk modulation structure 33 and the device gate structure 5 are made of the same material and are formed in the same process, and can have the same structure. Optionally, both the crosstalk modulation structure 33 and the device gate structure 5 are polysilicon gates; in other embodiments, a gate dielectric layer is also formed between the device gate structure 5 and the front surface 13 of the semiconductor substrate 1.

[0063] Without changing the existing CMOS process flow or process design standards, the crosstalk modulation structure 33 in the blocking structure 3 of this application is fabricated simultaneously with the fabrication of the device gate structure 5, which can reduce the crosstalk phenomenon of the image sensor without increasing the processing and manufacturing cost of the image sensor.

[0064] In another embodiment of this application, please refer to Figure 5 In (a) to (d), the image sensor also includes a second contact hole structure 6 disposed in the dielectric layer 4. The second contact hole structure 6 is located between the device gate structure 5 and the metal interconnect layer. The first contact hole structure 32 is made of the same material as the second contact hole structure 6. The first contact hole structure 32 is formed during the formation process of the second contact hole structure 6.

[0065] The figure shows that the second contact hole structure 6 is located on the device gate structure 5. Of course, the second contact hole structure 6 can also be set in other areas of the pixel region 11 that require electrical lead-out, such as the floating diffusion region FD. The second contact hole structure 6 can be other electrical interconnect and lead-out structures set in the art according to actual needs.

[0066] Specifically, in this embodiment, after forming a dielectric layer 4 on the front surface 13 of the semiconductor substrate 1 (making the thickness of the dielectric layer 4 greater than the thickness of the device gate structure 5, i.e., completely covering the device gate structure 5), an etching process is used to form a second contact hole structure 6 for conduction with the metal interconnect layer. At the same time, the first contact hole structure 32 is also prepared. That is, the first contact hole structure 32 in the blocking structure 3 of this application can be prepared without adding additional process steps or changing the standard CMOS process flow.

[0067] Specifically, the first contact hole structure 32 and the second contact hole structure 6 are made of the same material and are formed in the same process, and may have the same structure. Optionally, the first contact hole structure 32 and the second contact hole structure 6 are metal contact holes, such as metal contact holes with deposited tungsten. In some other embodiments, metal contact holes containing other elements, such as TiAl or Al, may also be provided as needed.

[0068] Without changing the existing CMOS process flow or process design standards, the first contact hole structure 32 in the blocking structure 3 of this application is fabricated simultaneously with the fabrication of the second contact hole structure 6, which can reduce the crosstalk phenomenon of the image sensor without increasing the manufacturing cost of the image sensor.

[0069] In another embodiment of this application, please refer to Figure 3 The isolation structure 31 is a shallow trench isolation structure.

[0070] Specifically, in this embodiment, the isolation structure 31 is preferably a shallow trench isolation (STI) structure. The shallow trench isolation structure extends from the front surface 13 of the semiconductor substrate 1 into the interior of the semiconductor substrate 1, effectively preventing surface inversion of the semiconductor substrate 1. The active region and field region on the semiconductor substrate 1 can be distinguished through the shallow trench isolation structure. The shallow trench isolation structure can be fabricated according to existing STI standard process flow. Furthermore, the isolation structure 31 serves as part of the isolation region 12, realizing isolation between adjacent pixel regions 11.

[0071] Preferably, in some embodiments, the sidewalls of the shallow trench isolation structure are inclined at a certain angle in the vertical direction, so as to facilitate effective doping implantation of the sidewalls of the shallow trench isolation structure during the subsequent ion implantation process.

[0072] Specifically, oxides, such as silicon dioxide, are deposited inside the shallow trench isolation structure using a chemical vapor deposition (CVD) process.

[0073] The isolation structure 31 is configured as a shallow trench isolation structure, which is directly compatible with existing CMOS processing technology. While ensuring good isolation effect, it helps to reduce production and processing costs.

[0074] Specifically, compared to directly creating metal contact holes (the first contact hole structure) on the isolation structure, forming the crosstalk modulation structure 33 first on the isolation structure, and then creating the metal contact hole on the crosstalk modulation structure 33, can change the stress of the isolation structure itself. Data shows that this improves the dark current performance of the device. For example, the isolation structure is a shallow trench isolation structure (STI) made of silicon oxide, the crosstalk modulation structure 33 is made of polycrystalline silicon, and the first contact hole structure is made of tungsten. Simultaneously, since the metal is not in direct contact with the STI, it can prevent the migration of the metal's charge within the shallow trench isolation structure, thereby improving dark current performance. This effectively improves the device's optical crosstalk resistance and dark current performance without altering its electrical isolation performance.

[0075] In another embodiment of this application, please refer to Figure 3 The width d1 of the crosstalk modulation structure 33 is smaller than the width d2 of the isolation structure 31.

[0076] Specifically, in this embodiment, the width d1 of the crosstalk modulation structure 33 is set to be smaller than the width d2 of the isolation structure 31, thereby effectively blocking light from crosstalking to adjacent pixel areas 11. This can prevent the crosstalk modulation structure 33 from affecting the pixel area devices, and effectively achieve isolation of adjacent pixel areas based on the isolation structure 31.

[0077] In another embodiment of this application, the etching ratio of the dielectric layer 4 to the crosstalk modulation structure 33 is greater than the etching ratio of the dielectric layer 4 to the isolation structure 31.

[0078] Specifically, in this embodiment, the etching ratio typically refers to the ratio of the etching rate of the etched material to the etching rate of another material. The etching ratio of the dielectric layer 4 to the crosstalk modulation structure 33 is greater than the etching ratio of the dielectric layer 4 to the isolation structure 31. This allows the crosstalk modulation structure 33 to effectively prevent over-etching of the isolation structure 31 during the fabrication of the first contact hole structure 32, thereby effectively reducing dark current. For example, in an optional example, the dielectric layer 4 is made of silicon oxide, the crosstalk modulation structure 33 is made of polysilicon, and the isolation structure 31 is made of silicon oxide.

[0079] In another embodiment of this application, the blocking structure 3 surrounds all or part of the pixel region 11.

[0080] Specifically, such as Figure 6 As shown in (a) in this embodiment, just as the isolation region 12 completely surrounds each pixel region 11, the blocking structure 3 can be designed to completely surround the corresponding pixel region 11, so that the devices have a strong anti-crosstalk capability.

[0081] Specifically, in another embodiment, depending on the specific structural design of the image sensor, the blocking structure 3 can also be designed to partially surround the corresponding pixel region 11. In one example, the isolation structure 31 is intermittently arranged around the pixel region 11, such as... Figure 6 As shown in (b); furthermore, the isolation structure 31 is selected as a shallow trench isolation structure, and the shallow trench isolation structure is intermittently arranged around the pixel region 11, which can alleviate interface defects and their resulting electrical crosstalk while achieving pixel electrical isolation. In other examples, the crosstalk modulation structure 33 may be located on the isolation structure 31 and extend into the isolation region 12 between adjacent isolation structures 31, and the crosstalk modulation structure 33 may also be intermittently arranged.

[0082] In another embodiment of this application, the projected area of ​​the isolation structure 31 corresponding to the front surface 13 of the semiconductor substrate is greater than the projected area of ​​the crosstalk modulation structure 33 corresponding to the front surface 13 of the semiconductor substrate.

[0083] Specifically, in another embodiment, the projected area of ​​the isolation structure 31 corresponding to the front surface 13 of the semiconductor substrate is larger than the projected area of ​​the crosstalk modulation structure 33 corresponding to the front surface 13 of the semiconductor substrate. That is, the projection of the crosstalk modulation structure 31 onto the front surface 13 of the semiconductor substrate is within the projection range of the isolation structure 31 onto the front surface 13 of the semiconductor substrate. This helps prevent the formation of the crosstalk modulation structure 31 from affecting other structures in the pixel area, such as... Figure 6 As shown in (c) and (d) in the diagram. For example, the isolation structure 31 can be arranged intermittently around the pixel region 11, with the crosstalk modulation structure 33 located on the spaced isolation structure 31 and not extending into the isolation region surrounding the isolation structure 31, as shown in the diagram. Figure 6 As shown in (d) in the figure; optionally, the material of the isolation region around the isolation structure 31 can be selected as ion implantation isolation. The above method can effectively achieve optical isolation while realizing pixel electrical isolation and alleviate interface defects and their resulting electrical crosstalk.

[0084] In another embodiment of this application, the projected area of ​​the crosstalk modulation structure 33 corresponding to the front surface 13 of the semiconductor substrate is greater than the projected area of ​​the first contact hole structure 32 corresponding to the front surface 13 of the semiconductor substrate; the projection of the first contact hole structure 32 corresponding to the front surface 13 of the semiconductor substrate is located within the projection range of the crosstalk modulation structure 33 corresponding to the front surface 13 of the semiconductor substrate, which is beneficial to effectively improve the electrical crosstalk caused during the device fabrication process.

[0085] In another embodiment of this application, please refer to Figure 3 The image sensor also includes a color filter layer 7 disposed between the pixel region 11 and the incident light;

[0086] In another embodiment of this application, please refer to Figure 3 The image sensor also includes a microlens 8 disposed between the pixel region 11 and the incident light;

[0087] In another embodiment of this application, please refer to Figure 3 The image sensor also includes a metal grid structure 9 disposed between the pixel region 11 and the incident light and corresponding to the isolation region 12.

[0088] Specifically, in this embodiment, combining existing CMOS processing technology, a color filter layer 7 is set between the pixel region 11 and the incident light. The color filter layer 7 is typically a color filter array, including three colors: red, green, and blue, which can only transmit light of the corresponding wavelengths of red, green, and blue, respectively. Of course, in some other embodiments, a filter such as a yellow filter can also be used. The array arrangement of the filters in the color filter layer 7 can be designed as needed. In one embodiment, 16 pixel regions 11 can constitute a pixel unit, such as forming an RGGB arrangement, with each color including four pixel regions 11, which are merged to obtain image data. Of course, other arrangements can also be designed according to actual design needs.

[0089] Specifically, in some embodiments, there are two different types of isolation in the pixel unit. The first type of isolation is the isolation between the four pixel regions 11 corresponding to each color block, and the second type of isolation is the isolation between the four pixel regions 11 corresponding to adjacent color blocks. The blocking structure 3 of this application can be made only for the isolation between the four pixel regions 11 corresponding to adjacent color blocks.

[0090] In another embodiment, the image sensor further includes a microlens 8 disposed between the pixel region 11 and the incident light. Specifically, for image sensors, a microlens array is typically provided to focus light onto the opening of the photosensitive area of ​​the pixel, thereby increasing photoelectric conversion efficiency and reducing optical signal crosstalk between adjacent pixel regions 11. For details regarding the configuration of the microlens 8, please refer to relevant prior art.

[0091] In another embodiment, the image sensor further includes a metal grid structure 9 disposed between the pixel region 11 and the incident light, and corresponding to the isolation region 12. Specifically, the metal grid structure 9 is disposed corresponding to the isolation region 12 to reduce light crosstalk. The metal grid structure 9 is generally located between the pixel region 11 and the incident light. In some embodiments, the metal grid structure 9 may be disposed below the color filter layer 7; in other embodiments, the metal grid structure 9 may be disposed in the same layer as the color filter layer 7.

[0092] In another embodiment of this application, please refer to Figure 3 and Figure 4 The crosstalk modulation structure 33 is located on the surface of the isolation structure 31, and the first contact hole structure 32 is in contact with the corresponding metal interconnect layer and the corresponding crosstalk modulation structure 33.

[0093] Specifically, in this embodiment, the crosstalk modulation structure 33 is located on the surface of the isolation structure 31, that is, the crosstalk modulation structure 33 is in contact with the isolation structure 31. At the same time, the first contact hole structure 32 is in contact with the corresponding metal interconnect layer and the corresponding crosstalk modulation structure 33. That is, the isolation structure 31, the crosstalk modulation structure 33, the first contact hole structure 32 and the corresponding metal interconnect layer are in contact in sequence, and there are no gaps between the structures, forming a tight light-blocking wall structure to block crosstalk of light between adjacent pixel areas 11.

[0094] In another embodiment of this application, please refer to Figure 3 and Figure 4 The image sensor is a back-illuminated image sensor. The semiconductor substrate 1 also includes a back surface 14 opposite to the front surface 13. The pixel region 11 includes a photodiode, which is used to convert the light signal entering the semiconductor substrate 1 from the back surface 14 into an electrical signal.

[0095] Specifically, in this embodiment, the image sensor including the blocking structure 3 is a back-illuminated image sensor (BSI). In the back-illuminated image sensor, the semiconductor substrate 1 also includes a back surface 14 opposite to the front surface 13, and light enters the semiconductor substrate 1 through the back surface 14. A photodiode is disposed in the pixel region 11, and the photodiode converts the light signal incident into the interior of the semiconductor substrate 1 into an electrical signal.

[0096] Specifically, in one embodiment, combined with Figure 1 Light enters from the photosensitive portion of the back surface 14 of the BSI, passes through the microlens 8 and the color filter layer 7, and then enters the semiconductor substrate 1. Taking a silicon substrate as an example, since different wavelengths of light have different lifetimes in silicon, longer wavelengths of light (such as red light or infrared light) travel a longer distance in the silicon substrate, thus easily penetrating the silicon substrate and entering the metal interconnect layer on the front surface 13. After reflection by the metal interconnect layer, crosstalk light is formed, which interferes into adjacent pixel areas 11, ultimately reducing the image quality of the sensor. To address this problem of existing back-illuminated image sensors, the blocking structure 3 described in the above embodiments of this application is provided, combined with... Figure 4 The blocking structure 3 corresponds to the isolation area 12 and can form a tight light-blocking wall structure between the first metal interconnect layer 2 and the semiconductor substrate 1, thereby blocking reflected light from interfering with the adjacent pixel area 11.

[0097] In another embodiment of this application, please refer to Figure 3The image sensor also includes a deep trench isolation structure 15 disposed within the semiconductor substrate 1 and close to the back surface 14. The deep trench isolation structure 15 extends from the back surface 14 toward the front surface 13 and is disposed opposite to the isolation structure 31 in the blocking structure 3.

[0098] Specifically, in this embodiment, a deep trench isolation structure 15 (DTI) is formed within the semiconductor substrate 1. The related processing technology and specific structure of the deep trench isolation structure 15 can be understood in conjunction with relevant existing technologies. The deep trench isolation structure 15 extends from the back surface 14 to the front surface 13 within the semiconductor substrate 1 and is close to or in contact with the isolation structure 31 in the barrier structure 3. In other words, the deep trench isolation structure 15 is also located within the isolation region 12 between the pixel regions 11. The isolation region 12 includes the isolation structure 31 and the deep trench isolation structure 15 corresponding to the isolation structure 31. When the isolation structure 31 in the barrier structure 3 is a shallow trench isolation structure, the isolation region 12 includes the shallow trench isolation structure and the deep trench isolation structure 15 aligned with the shallow trench isolation structure.

[0099] The depth, width and other parameters of the deep trench isolation structure 15 are designed according to the actual breakdown voltage and other requirements. The deep trench isolation structure 15 can further effectively isolate the photosensitive elements (photodiodes) between pixel areas 11 and reduce crosstalk between pixel areas 11.

[0100] Please see Figure 5 In addition to (a) to (d) above, this application also provides a method for manufacturing an image sensor as described in the above embodiments, comprising the following steps:

[0101] See Figure 5 In (a), a semiconductor substrate 1 is provided, in which a plurality of pixel regions 11 are formed and an isolation structure 31 is located between adjacent pixel regions 11. The isolation structure 31 extends from the front surface 13 of the semiconductor substrate 1 into the interior of the semiconductor substrate 1.

[0102] See Figure 5 In (b), a crosstalk modulation structure 33 is formed on the front surface 13 of the semiconductor substrate 1, and the crosstalk modulation structure 33 is formed on the isolation structure 31;

[0103] See Figure 5 (c) In this case, a dielectric layer 4 is formed on the front surface 13 of the semiconductor substrate 1 so that the crosstalk modulation structure 33 is located inside the dielectric layer 4;

[0104] See Figure 5In step (d), the dielectric layer 4 is etched to form the first contact hole structure 32, which is formed on the crosstalk modulation structure 33;

[0105] A metal interconnect layer is formed on the first contact hole structure 32 so that the metal interconnect layer contacts the first contact hole structure 32.

[0106] Specifically, in this embodiment, the process flow for forming the isolation structure 31, the crosstalk modulation structure 33, the dielectric layer 4, the first contact hole structure 32, and the metal interconnect layer is fully compatible with the standard CMOS process flow and does not require additional process steps.

[0107] The crosstalk modulation structure 33 can be formed using photolithography and patterning. When the image sensor includes a device gate structure 5, the crosstalk modulation structure 33 is formed during the formation of the device gate structure 5. During the formation of the device gate structure 5, the device gate structure 5 is defined between the pixel region 11 and the metal interconnect layer. At the same time, a gate region (i.e., the location of the crosstalk modulation structure 33) is defined above the isolation structure 31. After patterning using photolithography, the crosstalk modulation structure 33 and the device gate structure 5 are formed simultaneously.

[0108] When forming the first contact hole structure 32, an etching process can be used to form the contact hole, and then filling is used to form the corresponding contact hole structure. When the image sensor includes a second contact hole structure 6, the first contact hole structure 32 is formed during the formation of the second contact hole structure 6. During the formation of the second contact hole structure 6, a patterned mask layer is formed on the dielectric layer 4. This mask layer defines the position and size of the predetermined contact hole. The second contact hole structure 6 is defined above the device gate structure 5 through the mask layer. At the same time, the first contact hole structure 32 is defined above the crosstalk modulation structure 33. The first contact hole structure 32 and the second contact hole structure 6 are formed simultaneously.

[0109] During the formation of the first contact hole structure 32 and the second contact hole structure 6, the crosstalk modulation structure 33 acts as an etching stop, preventing over-etching that would cause the first contact hole structure 32 to be directly etched through the isolation structure 31. During etching, the etched-through isolation structure 31 would affect the isolation effect, and furthermore, during the fabrication of the first contact hole structure 32 and the second contact hole structure 6, charges in the metal would accumulate and diffuse within the isolation structure 31, affecting the device's dark current performance. Therefore, the etching stop function of the crosstalk modulation structure 33 can effectively reduce the device's dark current.

[0110] The image sensor manufacturing method provided in this application is fully compatible with existing standard CMOS process flow. It can manufacture an image sensor with the above-mentioned blocking structure 3 without adding process steps, which can simultaneously reduce optical crosstalk and electrical crosstalk of the image sensor, and is beneficial to improving the imaging quality of the image sensor.

[0111] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An image sensor, characterized in that, This includes a semiconductor substrate, multiple pixel regions, a metal interconnect layer, and a barrier structure; A plurality of pixel regions are disposed in the semiconductor substrate, and an isolation region for electrically isolating the pixel regions is defined between adjacent pixel regions. The metal interconnect layer is disposed in a dielectric layer on the front surface of the semiconductor substrate, and the blocking structure is disposed corresponding to the isolation region and the blocking structure is located at least between the isolation region and the metal interconnect layer. The blocking structure includes an isolation structure disposed in the semiconductor substrate, a first contact hole structure disposed in the dielectric layer and corresponding to the isolation structure, and a crosstalk modulation structure disposed in the dielectric layer and corresponding to the isolation structure and the first contact hole structure; the isolation structure extends from the front surface into the interior of the semiconductor substrate; The isolation structure is a shallow trench isolation structure; The image sensor also includes a device gate structure disposed on the front surface of the semiconductor substrate and located in the dielectric layer, wherein the crosstalk modulation structure is made of the same material as the device gate structure.

2. The image sensor as described in claim 1, characterized in that, The number of metal interconnect layers is at least two layers. The first metal interconnect layer is located near the front surface of the semiconductor substrate. The side of the first metal interconnect layer near the front surface is in contact with the first contact hole structure. The crosstalk modulation structure is disposed on the front surface, and the first contact hole structure connected to the first metal interconnect layer is in contact with the crosstalk modulation structure.

3. The image sensor as described in claim 1, characterized in that, The device gate structure is located between the pixel region and the metal interconnect layer, and the crosstalk modulation structure is formed during the formation of the device gate structure.

4. The image sensor as described in claim 1, characterized in that, The image sensor further includes a second contact hole structure disposed in the dielectric layer. The second contact hole structure is located between the pixel region and the metal interconnect layer. The first contact hole structure and the second contact hole structure are made of the same material. The first contact hole structure is formed during the formation process of the second contact hole structure.

5. The image sensor as described in claim 1, characterized in that, The isolation structure is a shallow trench isolation structure.

6. The image sensor as claimed in claim 1, characterized in that, The width of the crosstalk modulation structure is smaller than the width of the isolation structure; and / or, the etching ratio of the dielectric layer to the crosstalk modulation structure is greater than the etching ratio of the dielectric layer to the isolation structure.

7. The image sensor as claimed in claim 1, characterized in that, The blocking structure surrounds all or part of the pixel region; and / or, the projected area of ​​the isolation structure corresponding to the front surface of the semiconductor substrate is greater than the projected area of ​​the crosstalk modulation structure corresponding to the front surface of the semiconductor substrate; and / or, the projected area of ​​the crosstalk modulation structure corresponding to the front surface of the semiconductor substrate is greater than the projected area of ​​the first contact hole structure corresponding to the front surface of the semiconductor substrate.

8. The image sensor as claimed in claim 1, characterized in that, The image sensor also includes a color filter layer disposed between the pixel area and the incident light; And / or, the image sensor further includes a microlens disposed between the pixel region and the incident light; And / or, the image sensor further includes a metal grid structure disposed between the pixel region and the incident light and corresponding to the isolation region.

9. The image sensor as claimed in claim 1, characterized in that, The crosstalk modulation structure is located on the surface of the isolation structure, and the first contact hole structure is in contact with both the corresponding metal interconnect layer and the corresponding crosstalk modulation structure.

10. The image sensor according to any one of claims 1 to 9, characterized in that, The image sensor is a back-illuminated image sensor, and the semiconductor substrate also includes a back surface opposite to the front surface. The pixel region includes a photodiode, which is used to convert light signals entering the semiconductor substrate from the back surface into electrical signals.

11. The image sensor as claimed in claim 10, characterized in that, The image sensor further includes a deep trench isolation structure disposed in the semiconductor substrate and close to the back surface, the deep trench isolation structure extending from the back surface toward the front surface and disposed opposite to the isolation structure in the blocking structure.

12. A method for manufacturing an image sensor as described in any one of claims 1 to 11, characterized in that, Includes the following steps: A semiconductor substrate is provided, wherein a plurality of pixel regions are formed in the semiconductor substrate and an isolation structure is located between adjacent pixel regions, the isolation structure extending from the front surface of the semiconductor substrate toward the interior of the semiconductor substrate; The crosstalk modulation structure is formed on the front surface of the semiconductor substrate, and the crosstalk modulation structure is formed on the isolation structure; The dielectric layer is formed on the front surface of the semiconductor substrate such that the crosstalk modulation structure is located inside the dielectric layer; The dielectric layer is etched to form the first contact hole structure, which is formed on the crosstalk modulation structure. The metal interconnect layer is formed on the first contact hole structure so that the metal interconnect layer contacts the first contact hole structure.

13. The method for manufacturing an image sensor according to claim 12, characterized in that, When the image sensor includes the device gate structure, the crosstalk modulation structure is formed during the formation process of the device gate structure; And / or, when the image sensor includes a second contact hole structure, the first contact hole structure is formed during the formation of the second contact hole structure.

Images