IO interface rapid test system

Abstract

The application provides an IO interface rapid test system, which comprises a digital board and host computer software, the digital board is connected with a measured digital board and a measured adapter board through a connector clamp, and the host computer software completes IO interface rapid test on the measured digital board and the measured adapter board. The application provides an IO interface rapid test system, which meets the requirements of generalization, low cost and high flexibility of IO interface rapid test.

Description

Technical Field

[0001] This invention belongs to the field of radar control, specifically relating to a rapid testing system for I / O interfaces. Background Technology

[0002] In radar control, I / O (Input / Output) interfaces are commonly used control interfaces, primarily for health management monitoring, beam control, and time-division multiplexing control. In radar components, I / O interface signals are typically generated or received by programmable logic devices such as FPGAs (Field-Programmable Gate Arrays) on the digital board, and then transmitted to the final-stage module via flexible circuit boards or low-frequency cables. Testing and troubleshooting the functionality of I / O interface paths can improve component production efficiency and reliability.

[0003] In radar control and monitoring systems, there are many types and numbers of I / O interface paths. Traditional testing methods mainly involve a combination of oscilloscope, test center, and host computer, or a combination of logic analyzer and host computer to build a test booth. This method is resource-intensive and costly, and cannot meet the current production needs for generalization, low cost, and high flexibility. Summary of the Invention

[0004] To address the challenges of existing technologies, this invention provides a rapid I / O interface testing system, comprising a digital board and host computer software. The digital board is connected to the digital board under test (DUT) and the adapter board under test via connector fixtures. The host computer software performs rapid I / O interface testing on the DUT and the adapter board under test. The digital board includes a power module, a clock link, an FPGA chip, a level-shifting bidirectional driver chip, a DIP switch, and a connector fixture. The FPGA chip communicates with the host computer in the host computer software via an FPGA downloader link, receiving configuration commands from the host computer, outputting specified I / O signals, and transmitting the received input I / O signals to the host computer software via the FPGA downloader link. The output I / O level terminals of the level-shifting bidirectional driver chip are connected to the common terminal of the DIP switch, allowing the output I / O level of the level-shifting bidirectional driver chip to be switched via the DIP switch. The clock link provides a clock signal to the FPGA chip. The I / O interface of the FPGA chip is connected to the level-shifting bidirectional driver chip, and the input / output direction control pins of the level-shifting bidirectional driver chip are also introduced into the FPGA chip. Under the control of the host computer software, the FPGA chip configures the I / O interface of the level-shifting bidirectional driver chip.

[0005] Furthermore, the host computer software includes a test control module, an IO logic judgment setting module, an IO sequence number setting module, a host computer, and a test report generation module; the IO logic judgment setting module is used to set the IO logic criteria; the IO sequence number setting module is used to set the input and output IO sequence numbers corresponding to the digital board.

[0006] Furthermore, the rapid interface testing specifically includes the following steps:

[0007] Set the corresponding input and output I / O serial numbers of the digital board according to the I / O interface connection relationship between the digital board and the device under test;

[0008] Set the IO logic criteria to either an IO interval level toggling strategy or an IO bit-by-bit level toggling strategy according to the test requirements;

[0009] Based on the logic level of the I / O port of the device under test, the DIP switch on the digital board is toggled to configure the output I / O level of the digital board; the device under test is the digital board under test or the adapter board under test.

[0010] After confirming the system connection, perform test control through the user interface of the host computer software and start the test;

[0011] The digital board receives control commands from the host computer through the FPGA downloader link, outputs the corresponding logic level on the output IO port, and receives the corresponding logic level of the device under test on the input IO port.

[0012] For the adapter board under test that does not generate I / O signals independently, the I / O interface test forms a self-loop. The output I / O signal of the digital board enters the adapter board under test, flows through the I / O path of the adapter board under test, and then flows into the input I / O port of the digital board through the interface of the adapter board under test. The digital board transmits the received I / O signal to the host computer through the FPGA downloader link. The host computer software performs logical judgment on the received I / O signal according to the pre-set I / O logic criteria and I / O sequence number. If it meets the I / O logic criteria, the I / O interface path of the adapter board under test is deemed qualified, and the host computer software generates a test report.

[0013] For testing the input I / O interface of the digital board under test (DUT) that generates I / O signals autonomously, the DUT also establishes an FPGA downloader link with the host computer. The output I / O signal of the digital board enters the DUT, flows through the I / O path of the DUT, is received by the programmable logic device of the DUT, and is then transmitted to the host computer through the FPGA downloader link of the DUT. The host computer software performs logical judgment on the received I / O signal according to the pre-set I / O logic criteria and I / O sequence number. If it meets the I / O logic criteria, the input I / O interface path of the DUT is deemed qualified, and the host computer software generates a test report.

[0014] For the test of the output IO interface of the digital board under test that generates IO signals independently, the digital board under test establishes an FPGA downloader link with the host computer, receives control instructions from the host computer, generates corresponding IO signals and outputs them through the output IO interface of the digital board under test, flows into the input IO port of the digital board, and the digital board transmits the received IO signals to the host computer through the FPGA downloader link. The host computer software makes a logical judgment on the received IO signals according to the pre-set IO logic criteria and IO serial numbers. If it meets the IO logic criteria, it is judged that the output IO interface path of the digital board under test is qualified, and the host computer software generates a test report.

[0015] Further, the IO logic criteria include an IO interval level flip strategy, and the IO interval level flip strategy specifically includes the following steps:

[0016] Step 1: Configure all odd-numbered IO output ports of the digital board as 0 and all even-numbered IO output ports as 1. The host computer makes a logical judgment on the received IO input port signals. If the odd-numbered IO input ports are judged as 0 and the even-numbered IO input ports are judged as 1, the result of passing the test in Step 1 is output; otherwise, the interface serial number corresponding to the incorrect level is output.

[0017] Step 2: Configure all odd-numbered IO output ports of the digital board as 1 and all even-numbered IO output ports as 0. The host computer makes a logical judgment on the received IO input port signals. If the odd-numbered IO input ports are judged as 1 and the even-numbered IO input ports are judged as 0, the result of passing the test in Step 2 is output; otherwise, the interface serial number corresponding to the incorrect level is output.

[0018] Step 3: After both Step 1 and Step 2 are judged to be qualified, the host computer software outputs a test qualified report; otherwise, the test result of the interface serial number corresponding to the incorrect level is output.

[0019] Further, the IO logic criteria include an IO bit-by-bit level flip strategy, and the steps of the IO bit-by-bit level flip strategy are specifically as follows:

[0020] Configure the corresponding IO output ports of the digital board as 1 in sequence from the lowest to the highest serial number, and the rest of the IO output ports as 0. The host computer makes a logical judgment on the received IO input port signals each time. If the IO input port corresponding to the current serial number is judged as 1 and the rest of the IO input ports are judged as 0, the test result of the current serial number IO interface is qualified. After traversing each IO interface, if each IO interface is judged to be qualified, the host computer software outputs a test qualified report; otherwise, the test result of the interface serial number corresponding to the incorrect level is output.

[0021] Further, the power supply module generates FPGA configuration levels, clock circuit drive levels, FPGA logic levels, and various output IO levels.

[0022] Furthermore, the connector fixture includes a crimp connector, a device under test (DUT) mating connector, and a wire. The crimp connector and the DUT mating connector are connected by the wire, and the wire is fixed to the crimp connector by crimping. The DUT is a digital board under test or an adapter board under test.

[0023] Compared with the prior art, the present invention has the following technical effects:

[0024] 1. This invention uses a self-developed digital board to test the continuity of IO interface signals, which significantly reduces costs compared to the conventional method of using oscilloscopes, control centers, and logic analyzers.

[0025] 2. This invention allows for flexible replacement of different connector fixtures for different test devices, achieving universality in IO interface testing.

[0026] 3. This invention allows for flexible switching of different IO levels for different devices under test, achieving universality in IO interface testing.

[0027] 4. This invention allows for flexible configuration of different numbers of input / output I / O interfaces for different devices under test, achieving universality in I / O interface testing.

[0028] 5. This invention allows for flexible configuration of IO channel IO logic criteria, balancing testing efficiency and testing reliability.

[0029] 6. The self-developed digital board of this invention has a short production cycle and a simple testing system setup, which can greatly improve testing efficiency. Attached Figure Description

[0030] Figure 1 This is a block diagram of the IO interface rapid testing system according to an embodiment of the present invention.

[0031] Figure 2 This is a block diagram of the digital board in an embodiment of the present invention.

[0032] Figure 3 This is a schematic diagram of the IO interval level switching strategy according to an embodiment of the present invention.

[0033] Figure 4 This is a schematic diagram of the bit-by-bit level toggling strategy for IO according to an embodiment of the present invention. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0035] The rapid testing system for IO interfaces described in this embodiment includes a digital board and host computer software. It can realize multi-channel bidirectional IO transmission and reception functions, and is compatible with multiple IO levels. That is, it can output IO signals of different levels and receive IO signals of different levels. The host computer software can generate test reports.

[0036] The host computer software includes a test control module, an IO logic judgment and setting module, an IO sequence number setting module, a host computer, and a test report generation module.

[0037] The host computer software connects to the digital board and the digital board under test (DUT) via an FPGA downloader link. The digital board connects to the DUT and the adapter board via connector fixtures. The connector fixtures interface with the I / O interfaces of the DUT (either the DUT or the adapter board), and different connector fixtures can be flexibly replaced for different DUTs. The host computer software performs rapid I / O interface testing on the DUT and the adapter board.

[0038] The digital board can generate multiple voltage levels, which can be flexibly configured by switching them using DIP switches to access the external I / O interfaces of the digital board.

[0039] like Figure 2 As shown, the digital board includes a power module, clock link, FPGA chip, level conversion bidirectional driver chip, DIP switch and connector fixture.

[0040] An external power supply is input into the power module, which generates FPGA configuration level, clock circuit drive level, FPGA logic level, and various output I / O levels.

[0041] The FPGA chip communicates with the host computer through the FPGA programmer link, receives configuration instructions from the host computer, outputs specified IO signals, and transmits the received input IO signals to the host computer software through the FPGA programmer link.

[0042] The output I / O level terminal of the level conversion bidirectional driver chip is connected to the common terminal of the DIP switch. The output I / O level of the level conversion bidirectional driver chip can be flexibly switched by moving the DIP switch.

[0043] The clock link provides a clock signal to the FPGA chip. The FPGA chip communicates with the host computer through the programmer link interface to receive commands and upload input I / O logic levels. The FPGA chip's I / O interface can be arbitrarily configured as input or output based on the received commands from the host computer. The FPGA chip's I / O interface is connected to a level-shifting bidirectional driver chip, and the input / output direction control pins of the level-shifting bidirectional driver chip are also introduced into the FPGA chip. Under the control of the host computer software, the FPGA chip configures the I / O interface input / output of the level-shifting bidirectional driver chip, thus flexibly switching the input / output direction of the level-shifting bidirectional driver chip's I / O ports.

[0044] The connector fixture includes a crimp connector, a device under test (DUT) mating connector, and a cable. The crimp connector and the DUT mating connector are connected by the cable. The DUT mating connector and the cable together form a cable assembly. The cable is fixed to the crimp connector by crimping, allowing for flexible replacement.

[0045] like Figure 1 As shown, the rapid testing process for IO interfaces includes the following steps:

[0046] Set the corresponding input and output I / O serial numbers of the digital board according to the connection relationship of the connector fixture (the connection relationship of the I / O interfaces between the digital board and the device under test);

[0047] Then, based on the actual testing needs (pipeline testing or troubleshooting), set the IO logic criteria to either an IO interval level toggling strategy or an IO bit-by-bit level toggling strategy, such as... Figure 3 , 4 As shown;

[0048] Based on the logic level of the I / O port of the device under test, the DIP switch on the digital board is toggled to configure the output I / O level of the digital board;

[0049] After confirming the system connection, perform test control through the user interface of the host computer software and start the test;

[0050] The digital board receives control commands from the host computer via the FPGA downloader link, outputs the corresponding logic level on the output I / O port, and receives the corresponding logic level of the device under test on the input I / O port; the device under test is the digital board under test or the adapter board under test.

[0051] For the adapter board under test that does not generate I / O signals independently, the I / O interface test forms a self-loop. The output I / O signal of the digital board enters the adapter board under test, flows through the I / O path of the adapter board under test, and then flows into the input I / O port of the digital board through the interface of the adapter board under test. The digital board transmits the received I / O signal to the host computer through the FPGA downloader link. The host computer software performs logical judgment on the received I / O signal according to the pre-set I / O logic criteria and I / O sequence number. If it meets the I / O logic criteria, the I / O interface path of the adapter board under test is deemed qualified, and the host computer software generates a test report.

[0052] For testing the input I / O interface of the digital board under test (DUT) that generates I / O signals autonomously, the DUT also establishes an FPGA downloader link with the host computer. The output I / O signal of the digital board enters the DUT, flows through the I / O path of the DUT, is received by the programmable logic device (FPGA, etc.) of the DUT, and is then transmitted to the host computer through the FPGA downloader link of the DUT. The host computer software performs logical judgment on the received I / O signal according to the pre-set I / O logic criteria and I / O sequence number. If it meets the I / O logic criteria, the input I / O interface path of the DUT is deemed qualified, and the host computer software generates a test report.

[0053] For testing the output I / O interface of a digital board under test (DUT) that generates I / O signals autonomously, the DUT establishes an FPGA downloader link with the host computer and receives control commands from the host computer, generates corresponding I / O signals, and outputs them from the DUT's output I / O interface. These signals flow into the DUT's input I / O port. The DUT then transmits the received I / O signals to the host computer via the FPGA downloader link. The host computer software performs logical judgments on the received I / O signals based on pre-set I / O logic criteria and I / O sequence numbers. If the I / O logic criteria are met, the output I / O interface of the DUT is deemed to be qualified, and a test report is generated by the host computer software.

[0054] In this embodiment, the IO channel IO logic criteria can be flexibly configured via host computer software. For large-scale testing, an IO interval level toggling method is used to improve testing efficiency.

[0055] The IO logic criteria include two parts: the IO interval level toggling strategy and the IO bit-by-bit level toggling strategy.

[0056] like Figure 3 As shown, the IO interval level toggling strategy includes the following steps:

[0057] Step 1: Configure all odd IO output ports of the digital board as 0 and all even IO output ports as 1. The host computer makes a logical judgment on the IO input port signals received. If the odd IO input ports are determined as 0 and the even IO input ports are determined as 1, then output the result that the test in Step 1 is qualified; otherwise, output the interface number corresponding to the error level.

[0058] Step 2: Configure all odd IO output ports of the digital board as 1 and all even IO output ports as 0. The host computer makes a logical judgment on the IO input port signals received. If the odd IO input ports are determined as 1 and the even IO input ports are determined as 0, then output the result that the test in Step 2 is qualified; otherwise, output the interface number corresponding to the error level.

[0059] Step 3: After both Step 1 and Step 2 are determined to be qualified, the host computer software outputs a qualified test report; otherwise, output the test result of the interface number corresponding to the error level.

[0060] As Figure 4 shown, the steps of the IO bit-by-bit level inversion strategy are specifically as follows:

[0061] Configure the corresponding IO output ports of the digital board as 1 in sequence according to the numbers from low to high, and configure the remaining IO output ports as 0. The host computer makes a logical judgment on the IO input port signals received each time. If the IO input port corresponding to the current number is determined as 1 and the remaining IO input ports are determined as 0, then the test result of the current number IO interface is qualified. After traversing each IO interface, if each IO interface is determined to be qualified, the host computer software outputs a qualified test report; otherwise, output the test result of the interface number corresponding to the error level.

[0062] When troubleshooting a faulty component, using the IO bit-by-bit level inversion method for testing can improve the reliability of troubleshooting.

[0063] The IO interface test strategy is open to users in the host computer software, and users can configure the output IO signal waveform and the logical judgment method of the IO interface according to product requirements.

[0064] The advantages of the present invention are as follows:

[0065] 1. Use a low-cost digital board to replace the IO interface test instrument. The digital board can communicate with the host computer, and the number of input / output IO interfaces can be flexibly configured.

[0066] 2. Use a low-cost digital board to replace the IO interface test instrument. The output IO level can be configured through switches on the digital board, which is compatible with the DUTs with different IO levels.

[0067] 3. Use a connector fixture. The fixture adopts a crimping connection method and can flexibly connect to the DUTs with different IO interface connectors.

[0068] 4. For devices under test that also use programmable logic devices to generate I / O signals autonomously, the device under test can be added to the host computer communication to form I / O mutual transmission test, thereby improving the test speed.

[0069] 5. The IO interface testing strategy can be flexibly configured using the host computer software. The system testing method can be configured as an IO interval level toggling strategy to improve testing efficiency, or as an IO bit-by-bit level toggling strategy to improve testing reliability.

[0070] 6. The IO interface testing strategy is made available to users in the host computer software. Users can configure the output IO signal waveform and the logical judgment method of the IO interface according to product requirements.

[0071] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0072] In the several embodiments provided in this application, it should be understood that the disclosed systems and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0073] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0074] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0075] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the IO interface rapid testing system described in the various embodiments of this application. The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0076] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. An IO interface quick test system, characterized in that, The IO interface rapid test system comprises a digital board and host computer software, the digital board is connected with a measured digital board and a measured adapter board through a connector clamp, and the host computer software completes IO interface rapid test on the measured digital board and the measured adapter board; the digital board comprises a power module, a clock link, an FPGA chip, a level conversion bidirectional drive chip, a dial switch and the connector clamp; the FPGA chip communicates with a host computer in the host computer software through an FPGA downloader link, receives configuration instructions of the host computer, outputs specified IO signals, and transmits received input IO signals to the host computer software through the FPGA downloader link; an output IO level terminal of the level conversion bidirectional drive chip is connected with a common terminal of the dial switch, and the dial switch is used for switching the output IO level of the level conversion bidirectional drive chip; the clock link provides a clock signal for the FPGA chip; the IO interface of the FPGA chip is connected with the level conversion bidirectional drive chip, and an input / output direction control pin of the level conversion bidirectional drive chip is also introduced into the FPGA chip; The FPGA chip is controlled by the host computer software, and the FPGA chip configures the level conversion bidirectional drive chip for IO interface input / output.

2. The IO interface quick test system of claim 1, wherein, The host computer software comprises a test control module, an IO logic judgment setting module, an IO serial number setting module, a host computer and a test report generation module; the IO logic judgment setting module is used for setting IO logic criteria; and the IO serial number setting module is used for setting input and output IO serial numbers corresponding to the digital board.

3. The IO interface quick test system of claim 1, wherein, The IO interface rapid test system is used for performing IO interface rapid test, and the test comprises the following steps: Input and output IO serial numbers corresponding to the digital board are set according to the IO interface connection relationship between the digital board and a measured piece; the measured piece comprises a measured digital board and a measured adapter board; IO logic criteria are set as an IO interval level flip strategy or an IO bit-by-bit level flip strategy according to test needs; According to the logic level of an IO port of the measured piece, a dial switch on the digital board is dialed to configure the output IO level of the digital board; After system connection is confirmed, test control is performed on a user interactive interface of the host computer software, and the test is started; The digital board receives control instructions from the host computer through the FPGA downloader link, and outputs corresponding logic levels at the output IO port and receives corresponding logic levels of the measured piece at the input IO port; For the measured adapter board which does not generate IO signals autonomously, the IO interface test forms a self-loop, the output IO signal of the digital board enters the measured adapter board, the signal flows through the IO channel of the measured adapter board and then flows into the input IO port of the digital board through the interface of the measured adapter board, the digital board transmits the received IO signal to the host computer through the FPGA downloader link, the host computer software performs logic judgment on the received IO signal according to the pre-set IO logic criteria and IO serial numbers, and if the IO logic criteria are met, it is judged that the IO interface channel of the measured adapter board is qualified, and a test report is generated by the host computer software. For the IO signal of the measured digital board input IO interface test, the measured digital board also establishes a FPGA downloader link with the host computer, the output IO signal of the digital board enters the measured digital board, and the signal flows through the IO channel of the measured digital board and is received by the programmable logic device of the measured digital board, and then is transmitted to the host computer through the FPGA downloader link of the measured digital board, the host computer software performs logical judgment on the received IO signal according to the pre-set IO logic criterion and IO sequence number, if the IO logic criterion is met, it is judged that the input IO interface channel of the measured digital board is qualified, and a test report is generated by the host computer software; For the IO signal of the measured digital board output IO interface test, the measured digital board establishes a FPGA downloader link with the host computer and receives control instructions from the host computer, generates corresponding IO signals and outputs them through the output IO interface of the measured digital board, flows into the input IO port of the digital board, and the digital board transmits the received IO signal to the host computer through the FPGA downloader link, the host computer software performs logical judgment on the received IO signal according to the pre-set IO logic criterion and IO sequence number, if the IO logic criterion is met, it is judged that the output IO interface channel of the measured digital board is qualified, and a test report is generated by the host computer software.

4. The IO interface quick test system of claim 3, wherein, The IO logic criterion includes an IO interval level flip strategy, and the IO interval level flip strategy specifically includes the following steps: Step 1, configure all odd IO output ports of the digital board as 0 and even IO output ports as 1, the host computer performs logical judgment on the received IO input port signal, the odd IO input port is judged as 0 and the even IO input port is judged as 1, then the test result of step 1 is output, otherwise the interface sequence number corresponding to the error level is output; Step 2, configure all odd IO output ports of the digital board as 1 and even IO output ports as 0, the host computer performs logical judgment on the received IO input port signal, the odd IO input port is judged as 1 and the even IO input port is judged as 0, then the test result of step 2 is output, otherwise the interface sequence number corresponding to the error level is output; Step 3, after both step 1 and step 2 are judged to be qualified, the host computer software outputs a test qualified report, otherwise the interface sequence number corresponding to the error level is output.

5. The IO interface quick test system of claim 3, wherein, The IO logic criterion includes an IO bit-by-bit level flip strategy, and the steps of the IO bit-by-bit level flip strategy are specifically: According to the sequence number from low to high, the corresponding IO output port of the digital board is configured as 1, and the remaining IO output port is configured as 0, the host computer performs logical judgment on the received IO input port signal each time, the IO input port corresponding to the current sequence number is judged as 1, and the remaining IO input port is judged as 0, then the test result of the current sequence number IO interface is qualified, after traversing each IO interface, if each IO interface is judged to be qualified, the host computer software outputs a test qualified report, otherwise the interface sequence number corresponding to the error level is output.

6. The IO interface quick test system of claim 1, wherein, The power module generates FPGA configuration level, clock circuit driving level, FPGA logic level and multiple output IO levels.

7. The IO interface quick test system of claim 1, wherein, The connector clamp comprises a crimping connector, a device-under-test butt connector and a wire, the crimping connector and the device-under-test butt connector are connected through the wire, and the wire is fixed on the crimping connector through a crimping mode. The device under test is a digital board or a conversion board.

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