Wide bandgap semiconductor trench mosfet device structure and method of making same

Abstract

The application provides a wide-bandgap semiconductor trench MOSFET device structure and a manufacturing method thereof. The wide-bandgap semiconductor trench MOSFET device structure comprises a substrate, a P well region, a source N+ region, a P+ mask layer, an N+ conducting layer and a gate. The P well region and the source N+ region are sequentially arranged on the substrate. The P+ mask layer is arranged on the upper part of the substrate and is wrapped by the substrate. The N+ conducting layer is arranged in the P+ mask layer along a first direction. The gate is embedded in the upper part of the substrate, the P well region and the source N+ region along the first direction, and the bottom of the gate is in contact with the P+ mask layer and the upper end of the N+ conducting layer. The wide-bandgap semiconductor trench MOSFET device structure has the following advantages: the P+ mask layer is constructed below the gate, so that the electric field at the groove corner can be effectively reduced; the N+ conducting layer is constructed in the P+ mask layer, so that the current path can be further expanded, the on-resistance is reduced, and the stability and reliability of the device performance can be effectively improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a wide bandgap semiconductor trench MOSFET device structure and its fabrication method. Background Technology

[0002] Currently, in power switching applications, Baliga's figure-of-merit (BFOM) is an indicator used to represent the suitability of semiconductor materials for power electronics, and it is expressed as: BFOM = εμE 3 Where ε is the dielectric constant, μ is the mobility, and E is the breakdown field strength of the semiconductor. The BFOM value is approximately equal to the bandgap width E. g The bandgap is positively correlated with the sixth power of the voltage. Therefore, a larger bandgap semiconductor means lower power loss and higher conversion efficiency in power device applications, thus enabling better and more ideal power electronics applications. Among wide bandgap semiconductor materials, Ga2O3 has a bandgap of 4.8 eV, an ideal breakdown electric field strength of 8 MV / cm, and a BFOM value as high as 3400, which is about 4 times that of GaN and 10 times that of SiC. Therefore, in today's power electronics applications with higher power density and lower power consumption requirements, Ga2O3 material has greater research significance and broader market application prospects.

[0003] Silicon carbide (SiC) devices can achieve P-type doping through ion implantation or epitaxial growth. However, it is more difficult to achieve P-type doping through ion implantation for materials with larger band gaps than silicon carbide, such as gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), and aluminum nitride (AlN). P-type doping can be achieved through special processes such as epitaxial growth or oxides.

[0004] Several problems exist in the actual fabrication and application of trench MOSFETs made of wide-bandgap semiconductor materials:

[0005] 1. The high electric field in the material drift region leads to a very high electric field on the gate dielectric layer. This problem is exacerbated at the slot corner, resulting in rapid breakdown of the gate dielectric layer under high drain voltage. It has poor electrostatic effects in harsh environments and poor tolerance to high voltage spikes in the circuit.

[0006] 2. Since wide bandgap semiconductor power MOSFETs are mainly used in high voltage, high frequency and high current fields, parasitic parameters in the circuit will cause spikes such as overshoot during high frequency switching, resulting in instantaneous overvoltage in the device current path and increasing the loss during the switching process; or large surge voltages may be generated due to changes in power load, etc.

[0007] 3. The limited depth of ion implantation makes it difficult to implement many targeted trench gate protection structures and surge protection designs from a process perspective.

[0008] In summary, the high electric field in the drift region of wide-bandgap semiconductor materials leads to a very high electric field on the gate dielectric layer. This problem is exacerbated at the trench corner, resulting in rapid breakdown of the gate dielectric layer under high drain voltage. Existing MOSFET devices do not inherently possess surge voltage suppression or overvoltage protection capabilities, often requiring the design of complex buffer circuits, surge voltage suppression circuits, and overvoltage protection circuits in practical applications. However, these externally matched suppression and overvoltage protection circuits often have time delays, meaning that the high-frequency spike voltage surges during actual switching processes are still absorbed by the device itself. This can sometimes lead to breakdown failure in the device channel region, as well as gradual failure of the gate structure and electrode ohmic contact areas, causing device reliability issues.

[0009] Therefore, a new wide-bandgap semiconductor MOSFET device structure needs to be designed as a more ideal semiconductor material. Summary of the Invention

[0010] Based on the above description, the present invention provides a wide bandgap semiconductor trench MOSFET device structure and its fabrication method, so as to optimize the surge voltage resistance and overvoltage protection of existing MOSFET device structures and improve the reliability of the device.

[0011] The technical solution of the present invention to solve the above-mentioned technical problems is as follows:

[0012] In a first aspect, the present invention provides a wide bandgap semiconductor trench MOSFET device structure, comprising: a substrate, a P-well region, a source N+ region, a P+ masking layer, an N+ current-conducting layer, and a gate.

[0013] The P-well region and the source N+ region are sequentially disposed on the substrate;

[0014] The P+ masking layer is disposed on the upper part of the substrate and is wrapped by the substrate;

[0015] The N+ flow guiding layer is disposed in the P+ masking layer along the first direction;

[0016] The gate is embedded in the upper part of the substrate, the P-well region and the source N+ region along the first direction, and the bottom of the gate is in contact with the upper end of the P+ masking layer and the N+ current guiding layer.

[0017] Based on the above technical solution, the present invention can be further improved as follows.

[0018] Further, the gate includes: a gate dielectric layer, a gate silicon, and a gate trench;

[0019] The gate trench is U-shaped and extends along the first direction;

[0020] The gate dielectric layer is disposed on the inner wall side of the gate trench; the gate silicon fills the middle of the gate trench and is in contact with the gate dielectric layer.

[0021] Furthermore, the wide bandgap semiconductor trench MOSFET device structure also includes an interlayer dielectric layer;

[0022] The interlayer dielectric layer is disposed at the opening of the gate trench, and its middle portion is in contact with the upper end face of the gate dielectric layer and the gate silicon.

[0023] Furthermore, the wide bandgap semiconductor trench MOSFET device structure also includes a source and a source contact region;

[0024] The source contact region is disposed on the source N+ region, the source is disposed on the source contact region, and the interlayer dielectric layer is embedded in the source and the source contact region along the first direction shown.

[0025] Furthermore, the N+ guiding layer is filled in the P+ masking layer so that the cross-section of the P+ masking layer has a U-shaped structure;

[0026] The upper surfaces of the P+ masking layer and the N+ current guiding layer are in contact with the lower surface of the gate trench.

[0027] Furthermore, the P+ masking layer includes multiple P+ masking regions;

[0028] The plurality of P+ shielding zones are arranged sequentially at intervals along the first direction, and the N+ flow guiding layer passes through the plurality of P+ shielding zones.

[0029] Furthermore, the substrate comprises an N+ substrate layer and an N- epitaxial layer;

[0030] The N- epitaxial layer is disposed on the N+ substrate layer;

[0031] The P+ masking layer and the N+ guiding layer are disposed in the upper region of the N- epitaxial layer; the P-well region is disposed on the upper surface of the N- epitaxial layer.

[0032] Furthermore, the wide bandgap semiconductor trench MOSFET device structure also includes a drain;

[0033] The drain electrode is located on the lower surface of the N+ substrate layer.

[0034] In a second aspect, the present invention also provides a method for fabricating a wide-bandgap semiconductor trench MOSFET device structure as described in any one of the first aspects, comprising:

[0035] P-type oxides were fabricated on the substrate to obtain P-well regions;

[0036] The source N+ region is formed by ion implantation in the P-well region;

[0037] Dry etching is performed on the substrate, the P-well region, and the source N+ region to obtain a gate trench;

[0038] Silicon oxide / polysilicon / silicon oxide are sequentially deposited on the gate trench to form a "sandwich" structure mask, and then etched to form an ion implantation mask;

[0039] Ion implantation is performed on the substrate at the bottom of the gate trench to obtain a P+ masking layer;

[0040] Ion implantation is performed on the P+ masking layer to obtain the N+ conduction layer, and the mask is removed after implantation is completed.

[0041] Gate dielectric growth, gate silicon growth and interlayer dielectric deposition are performed sequentially on the gate trench to obtain the gate and interlayer dielectric layers. Ohmic contact metal is deposited and annealed on the source N+ region to obtain the source contact region.

[0042] Metal is deposited and etched on the upper surface of the source contact region to form the source electrode; metal is deposited on the lower surface of the substrate to form the drain electrode.

[0043] Based on the above technical solution, the present invention can be further improved as follows.

[0044] Furthermore, the process of fabricating the p-type oxide on the substrate further includes:

[0045] An N- epitaxial layer is grown on an N+ substrate to obtain the substrate.

[0046] Compared with the prior art, the technical solution of this application has the following beneficial technical effects:

[0047] The wide bandgap trench MOSFET device structure provided by this invention comprises a substrate, a P-well region, a source N+ region, a P+ masking layer, an N+ current-conducting layer, and a gate. The P+ masking layer is disposed on the upper part of the substrate and is enclosed by the substrate. The N+ current-conducting layer fills the trench of the P+ masking layer along a first direction. The bottom of the gate contacts the upper ends of the P+ masking layer and the N+ current-conducting layer. Compared with the prior art, this wide bandgap trench MOSFET device structure has the following advantages:

[0048] First, the high electric field in the drift region of wide bandgap semiconductor materials leads to a very high electric field on the gate dielectric layer. This problem is exacerbated at the trench corner, which causes the gate dielectric layer to break down rapidly under high drain voltage. This setup can effectively reduce the electric field at the trench corner by constructing a P+ masking layer under the gate.

[0049] Second, constructing an N+ current-conducting layer within the P+ masking layer can further expand the current path and reduce the on-resistance.

[0050] In summary, the wide bandgap semiconductor trench MOSFET device structure provided by this invention can effectively improve the stability and reliability of device performance. Attached Figure Description

[0051] Figure 1 This is a three-dimensional structural schematic diagram of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 1 of the present invention;

[0052] Figure 2 This is a schematic diagram of the cross-sectional structure at point A of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 1 of the present invention;

[0053] Figure 3 This is a schematic diagram of the cross-sectional structure at point B of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 1 of the present invention;

[0054] Figure 4 This is a schematic diagram of the cross-sectional structure at point C of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 1 of the present invention;

[0055] Figure 5 This is a three-dimensional structural diagram of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 2 of the present invention;

[0056] Figure 6 This is a three-dimensional structural schematic diagram of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 3 of the present invention;

[0057] Figure 7 This is a three-dimensional structural schematic diagram of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 4 of the present invention;

[0058] Figure 8 This is a three-dimensional structural diagram of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 5 of the present invention;

[0059] Figure 9 This is a three-dimensional structural schematic diagram of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 6 of the present invention;

[0060] Figure 10This is a schematic diagram of the cross-sectional structure at point A of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 6 of the present invention;

[0061] Figure 11 This is a schematic diagram of the cross-sectional structure at point B of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 6 of the present invention;

[0062] Figure 12 This is a schematic diagram of the cross-sectional structure at point C of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 6 of the present invention;

[0063] Figure 13 This is a three-dimensional structural schematic diagram of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 7 of the present invention;

[0064] Figure 14 This is a schematic diagram of the cross-sectional structure at point A of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 7 of the present invention;

[0065] Figure 15 This is a schematic diagram of the cross-sectional structure at section B of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 7 of the present invention;

[0066] Figure 16 This is a schematic diagram of the cross-sectional structure at point C of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 7 of the present invention;

[0067] Figure 17 This is a three-dimensional structural schematic diagram of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 8 of the present invention;

[0068] Figure 18 This is a schematic diagram of the cross-sectional structure at section A of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 8 of the present invention;

[0069] Figure 19 This is a schematic diagram of the cross-sectional structure at point B of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 8 of the present invention;

[0070] Figure 20 This is a schematic diagram of the cross-sectional structure at point C of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 8 of the present invention;

[0071] Figure 21 This is a schematic diagram of the fabrication process of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 1 of the present invention;

[0072] Figure 22This is a schematic diagram of the fabrication process of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 6 of the present invention;

[0073] Figure 23 This is a schematic diagram of the fabrication process of the wide bandgap semiconductor trench MOSFET device structure provided in Embodiment 7 of the present invention;

[0074] Figure label:

[0075] 1. Substrate; 101. N+ substrate layer; 102. N- epitaxial layer

[0076] 2. P-well region;

[0077] 3. Source N+ region;

[0078] 4. P+ masking layer;

[0079] 5. N+ duct layer;

[0080] 6. Gate; 601. Gate dielectric layer; 602. Gate silicon; 603. Gate trench;

[0081] 7. Interlayer dielectric layer;

[0082] 8. Drain electrode;

[0083] 9. Source pole;

[0084] 10. Source electrode contact region. Detailed Implementation

[0085] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0086] SiC and GaN are third-generation wide-bandgap semiconductor materials. They have advantages over Si in physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity. Power devices made from them, such as diodes, transistors, and power modules, have superior electrical characteristics. They can overcome the shortcomings of silicon-based materials in meeting the requirements of high power, high voltage, high frequency, and high temperature applications. They are also one of the breakthrough paths that can surpass Moore's Law. Therefore, they are widely used in the new energy field (photovoltaics, energy storage, charging piles, electric vehicles, etc.).

[0087] In recent years, ultra-wide bandgap semiconductor materials with band gaps larger than SiC and GaN, such as gallium oxide, diamond, and aluminum nitride, have been recognized as an exciting and challenging new research field due to their superior optical and electrical properties. The larger band gap allows devices to be used in many extreme environments: in the context of geothermal energy production and oil and gas extraction, they enable higher drilling speeds and lower failure rates; in high-temperature environments, they allow for higher operating temperatures in aluminum plants, steel mills, and coal-fired and gas-fired power plants controlled by electronic sensors, thereby improving the energy efficiency of these industrial processes.

[0088] Among wide bandgap semiconductor materials, Ga2O3 possesses a bandgap of 4.8 eV, an ideal breakdown electric field strength of 8 MV / cm, and a BFOM value as high as 3400, approximately four times that of GaN and ten times that of SiC. Therefore, in today's power electronics applications demanding higher power density and lower power consumption, Ga2O3 materials hold significant research importance and have broader market application prospects.

[0089] Among them, surge voltage self-suppression capability and overvoltage protection capability are important indicators for evaluating the performance of MOSFET devices. However, trench MOSFETs made of wide bandgap semiconductor materials do not inherently possess surge voltage self-suppression capability and overvoltage protection capability. Therefore, it is often necessary to design complex buffer circuits, surge voltage suppression circuits, and overvoltage protection circuits in practical applications.

[0090] To better protect the gate oxide layer of trench MOSFETs, especially the bottom and trench corners, the industry primarily employs two technical solutions and device structures for wide-bandgap trench MOSFETs. These include Infineon's "P+ semi-enclosed asymmetric trench structure" and Rohm's approach, which uses a dual-trench source structure on both sides of the gate trench to shield the bottom of the gate trench. However, the external matching suppression and overvoltage protection circuits described above often have a time delay. In actual switching processes, high-frequency voltage spikes are still absorbed by the device itself, sometimes leading to breakdown failure in the device's channel region and gradual failure of the gate structure and electrode ohmic contact areas, causing device reliability issues.

[0091] This invention provides a wide bandgap semiconductor trench MOSFET device structure that can effectively solve the above problems. The embodiments of this invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are used to illustrate this invention, but should not be used to limit the scope of this invention.

[0092] Example 1

[0093] like Figures 1 to 4As shown, the wide bandgap semiconductor trench MOSFET device structure provided in this embodiment consists of a substrate 1, a P-well region 2, a source N+ region 3, a P+ masking layer 4, an N+ current-conducting layer 5, and a gate 6.

[0094] P-well region 2 and source N+ region 3 are sequentially disposed on the substrate.

[0095] The P+ masking layer 4 is disposed on the upper part of the substrate 1 and is wrapped by the substrate 1.

[0096] The N+ guiding layer 3 is disposed in the P+ shielding layer 4 along the first direction.

[0097] The gate 6 is embedded in the upper part of the substrate 1, the P-well region 2 and the source N+ region 3 along the first direction, and the bottom of the gate 6 is in contact with the upper end of the P+ masking layer 4 and the N+ current guiding layer 5.

[0098] definition Figure 1 The length direction of the middle structure is the first direction.

[0099] Furthermore, the gate 6 includes: a gate dielectric layer 601, a gate silicon layer 602, and a gate trench 603.

[0100] The gate trench 603 is U-shaped and extends along the first direction.

[0101] The gate dielectric layer 601 is disposed on the inner wall side of the gate trench; the gate silicon 602 fills the middle of the gate trench 603 and is in contact with the gate dielectric layer 601.

[0102] like Figure 1 As shown, the wide bandgap semiconductor trench MOSFET device structure also includes an interlayer dielectric layer 7. The interlayer dielectric layer 7 covers the opening of the gate trench 603, and its middle part contacts the upper end face of the gate dielectric layer 601 and the gate silicon 602.

[0103] Furthermore, the wide bandgap semiconductor trench MOSFET device structure also includes a source 9 and a source contact region 10.

[0104] The source contact region 10 is disposed on the source N+ region 3, the source 9 is disposed on the source contact region 10, and the interlayer dielectric layer 7 is embedded in the source 9 and the source contact region 10 along the first direction shown.

[0105] The N+ current-conducting layer 5 is filled in the P+ masking layer 4 so that the cross-section of the P+ masking layer 4 has a U-shaped structure; the upper surfaces of the P+ masking layer 4 and the N+ current-conducting layer 5 are in contact with the lower surface of the gate trench 603.

[0106] like Figure 2 As shown, the N+ flow guide layer 5 is a single-layer structure with a square cross-section.

[0107] Among them, the P+ shielding layer 4 includes multiple P+ shielding areas; the multiple P+ shielding areas are arranged sequentially at intervals along the first direction, and the N+ flow guiding layer 5 passes through the multiple P+ shielding areas.

[0108] Based on the above embodiments, the substrate 1 further includes an N+ substrate layer 101 and an N- epitaxial layer 102; the N- epitaxial layer 102 is disposed on the N+ substrate layer 101.

[0109] The P+ masking layer 4 and the N+ guiding layer 5 are disposed in the upper region of the N- epitaxial layer 102; the P-well region 2 is disposed on the upper surface of the N- epitaxial layer 102.

[0110] In addition, the wide bandgap semiconductor trench MOSFET device structure also includes a drain 8; the drain 8 is disposed on the lower surface of the N+ substrate layer 101.

[0111] The wide bandgap trench MOSFET device structure provided in this embodiment includes a substrate 1, a P-well region 2, a source N+ region 3, a P+ masking layer 4, an N+ current-conducting layer 5, and a gate 6. The P+ masking layer 3 is disposed on the upper part of the substrate 1 and is enclosed by the substrate 1. The N+ current-conducting layer 5 is filled in the trench of the P+ masking layer 4 along a first direction. The bottom of the gate 6 contacts the upper ends of the P+ masking layer 4 and the N+ current-conducting layer 5. Compared with the prior art, this wide bandgap trench MOSFET device structure has the following advantages:

[0112] First, the high electric field in the drift region of wide bandgap semiconductor materials leads to a very high electric field on the gate dielectric layer. This problem is exacerbated at the trench corner, which causes the gate dielectric layer to break down rapidly under high drain voltage. This setup can effectively reduce the electric field at the trench corner by constructing a P+ masking layer 4 under the gate 6.

[0113] Second, constructing an N+ current-conducting layer 5 in the P+ masking layer 4 can further expand the current path and reduce the on-resistance.

[0114] In summary, the wide bandgap semiconductor trench MOSFET device structure provided by the embodiments of the present invention provides better protection for the gate dielectric layer at the corner of the trench by forming a P+ masking layer 4 directly below the gate trench and constructing an N+ current-conducting layer 5 within the P+ masking layer 4, while expanding the current path and effectively improving the stability and reliability of the device performance.

[0115] Example 2

[0116] This embodiment provides a wide bandgap semiconductor trench MOSFET device structure, such as Figure 5 As shown, the difference from Example 1 is that the N+ flow guiding layer 5 can be multi-layered, and the multi-layered layers can be separated.

[0117] Example 3

[0118] This embodiment provides a wide bandgap semiconductor trench MOSFET device structure, such as Figure 6 As shown, the difference from Example 1 is that the N+ flow guiding layer 5 can be multi-layered, and the multi-layered layers can be connected by one or more N+ flow guiding columns.

[0119] Example 4

[0120] This embodiment provides a wide bandgap semiconductor trench MOSFET device structure, such as Figure 7 As shown, the difference from Embodiment 1 is that the N+ guiding layer 5 is lowered by one or more N+ guiding pillars that pass through the P+ masking layer to reach the N- epitaxial layer 102.

[0121] Example 5

[0122] This embodiment provides a wide bandgap semiconductor trench MOSFET device structure, such as Figure 8 As shown, the difference from Example 1 is that one side of the P+ masking layer 4 is connected to the source and grounded.

[0123] Example 6

[0124] This embodiment provides a wide bandgap semiconductor trench MOSFET device structure, such as Figures 9 to 12 As shown, the difference from Embodiment 1 is that the sidewall of the gate trench 603 is inclined, and the P+ masking layer 4 is injected through the trench sidewall to form a corner trench, and the injection window of the N+ current guiding layer 5 is in the middle of the P+ masking layer 4.

[0125] Example 7

[0126] This embodiment provides a wide bandgap semiconductor trench MOSFET device structure, such as Figures 13 to 16 As shown, the difference from Embodiment 1 is that the sidewall of the gate trench 603 is inclined, and it can be a trench shape of various shapes such as V-shape; the P+ masking layer 4 is injected through the trench sidewall to form a corner trench, and the N+ current guiding layer 5 injection window is to the left or right of the P+ masking layer 4.

[0127] Example 8

[0128] This embodiment provides a wide bandgap semiconductor trench MOSFET device structure, such as Figures 17 to 20 As shown, the difference from Example 1 is that there can be one or more steps at the bottom of the gate trench, which allows the P+ masking layer 4 to be injected deeper and provides a better masking effect.

[0129] Example 9

[0130] This invention also provides a method for fabricating the wide bandgap semiconductor trench MOSFET device structure of Embodiment 1, such as... Figure 21As shown, it includes:

[0131] Step S1: Grow an N- epitaxial layer on the N+ substrate to obtain the substrate.

[0132] Step S2: Fabricate a P-type oxide on the substrate to obtain a P-well region; form a source N+ region in the P-well region by ion implantation.

[0133] Step S3: Perform dry etching on the substrate, P-well region and source N+ region to obtain gate trench.

[0134] Step S4: Sequentially deposit silicon oxide / polysilicon / silicon oxide on the gate trench to form a "sandwich" structure mask.

[0135] Step S5: Etch the “sandwich” structure to form an ion implantation mask.

[0136] Step S6: Ion implantation is performed on the substrate at the bottom of the gate trench to obtain a P+ masking layer, and the mask in the middle is removed after implantation.

[0137] Step S7: Perform ion implantation on the P+ masking layer to obtain the N+ conduction layer, and remove all masks after implantation.

[0138] Step S8: Sequentially perform gate dielectric growth, gate silicon growth, and interlayer dielectric deposition on the gate trench to obtain the gate and interlayer dielectric layers, and deposit and anneal ohmic contact metal on the source N+ region to obtain the source contact region.

[0139] Step S9: Deposit and etch metal on the upper surface of the source contact region to create the source electrode; deposit metal on the lower surface of the substrate to create the drain electrode.

[0140] Since this fabrication method is used to fabricate wide bandgap semiconductor trench MOSFET device structures, the beneficial effects of wide bandgap semiconductor trench MOSFET device structures are also applicable to this fabrication method. For its beneficial effects, please refer to Example 1, which will not be elaborated here.

[0141] Example 10

[0142] This invention also provides a method for fabricating the wide bandgap semiconductor trench MOSFET device structure of Embodiment 6, such as... Figure 22 As shown, the difference from Example 9 is:

[0143] Methods for fabricating P+ shielding layers and N+ guide layers (taking section A as an example):

[0144] 1. Fabricate a gate trench with inclined sidewalls and a trapezoidal cross-section.

[0145] 2. An ion implantation mask with a “sandwich” structure is formed by sequentially depositing silicon oxide / polysilicon / silicon oxide, wherein the bottom of the bottom silicon oxide and polysilicon are both trapezoidal structures.

[0146] Polycrystalline silicon has excellent hole-filling ability, which can fill the trenches to facilitate subsequent silicon oxide deposition and photolithography processes. The etching selectivity between silicon oxide and polycrystalline silicon can be very high, which makes it easy to stop on the underlying dielectric. When etching polycrystalline silicon, it can stop on silicon oxide, avoiding over-etching of silicon carbide.

[0147] 2. Etching forms a mask for ion implantation.

[0148] 3. Ion implantation forms a P+ masking layer, and the ion implantation mask is removed after ion implantation is completed.

[0149] 4. Sequentially deposit silicon oxide / polysilicon / silicon oxide to form a "sandwich" structure ion implantation mask, dry etch, perform ion implantation of the N+ conduction layer, and remove the mask after implantation.

[0150] Example 11

[0151] This invention also provides a method for fabricating the wide bandgap semiconductor trench MOSFET device structure of Embodiment 7, such as... Figure 23 As shown, the difference from Example 9 is:

[0152] Fabrication process of N+ guide layer (taking section A as an example):

[0153] 1. Fabricate a gate trench with inclined sidewalls and a trapezoidal cross-section.

[0154] 2. Sequentially deposit silicon oxide / polysilicon / silicon oxide to form a "sandwich" structure ion implantation mask: Polysilicon has a good hole-filling ability, which can fill the trenches to facilitate the subsequent deposition of silicon oxide 2 and photolithography process; the etching selectivity between silicon oxide and polysilicon can be very high, so it can be easy to stop on the lower dielectric layer. When etching polysilicon, it can stop on silicon oxide 1 to avoid over-etching of silicon carbide.

[0155] 2. Etching forms the ion implantation mask; ion implantation forms the P+ masking layer; after ion implantation, the ion implantation mask is removed.

[0156] 3. Sequentially deposit silicon oxide / polysilicon / silicon oxide to form a "sandwich" structure ion implantation mask, perform dry etching, and then implant the N+ conduction layer. After implantation, remove the mask. At this point, as shown... Figure 21 As shown, the injected N+ channel layer is higher on the right than on the left. In an optional embodiment, it can also be set so that the left is higher than the right.

[0157] In the description of this specification, references to terms such as "specific example" or "some examples" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0158] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wide bandgap semiconductor trench MOSFET device structure, characterized by, Comprise: a substrate, a P well region, a source N+ region, a P+ mask layer, an N+ conducting layer and a gate electrode; the P well region and the source N+ region are sequentially arranged on the substrate; the P+ mask layer is arranged on the upper part of the substrate and is wrapped by the substrate; the N+ conducting layer is arranged in the P+ mask layer along a first direction; the gate electrode is embedded in the upper part of the substrate, the P well region and the source N+ region along the first direction, and the bottom of the gate electrode is in contact with the upper end of the P+ mask layer and the N+ conducting layer; the gate electrode comprises a gate dielectric layer, a gate silicon and a gate trench; the gate trench is in U shape and extends along the first direction; the gate dielectric layer is arranged on the inner wall of the gate trench; the gate silicon is filled in the middle of the gate trench and is in contact with the gate dielectric layer; the N+ conducting layer is filled in the P+ mask layer, so that the cross section of the P+ mask layer is in U shape structure; the upper surfaces of the P+ mask layer and the N+ conducting layer are in contact with the lower surface of the gate trench; the P+ mask layer comprises a plurality of P+ mask regions; a plurality of the P+ mask regions are sequentially and spacedly arranged along the first direction, and the N+ conducting layer is arranged through the plurality of P+ mask regions.

2. The wide bandgap semiconductor trench MOSFET device structure of claim 1, wherein, The wide band gap semiconductor trench MOSFET device structure further comprises an interlayer dielectric layer; the interlayer dielectric layer is arranged on the opening of the gate trench, and the middle part is in contact with the upper end surface of the gate dielectric layer and the gate silicon.

3. The wide bandgap semiconductor trench MOSFET device structure of claim 2, wherein, The wide band gap semiconductor trench MOSFET device structure further comprises a source electrode and a source contact region; the source contact region is arranged on the source N+ region, the source electrode is arranged on the source contact region, and the interlayer dielectric layer is embedded in the source electrode and the source contact region along the first direction.

4. The wide bandgap semiconductor trench MOSFET device structure of claim 1, wherein, The substrate comprises an N+ substrate layer and an N- epitaxial layer; the N- epitaxial layer is arranged on the N+ substrate layer; the P+ mask layer and the N+ conducting layer are arranged on the upper region of the N- epitaxial layer; and the P well region is arranged on the upper surface of the N- epitaxial layer.

5. The wide bandgap semiconductor trench MOSFET device structure of claim 4, wherein, The wide band gap semiconductor trench MOSFET device structure further comprises a drain electrode; the drain electrode is arranged on the lower surface of the N+ substrate layer.

6. A method for fabricating a wide bandgap semiconductor trench MOSFET device structure as claimed in any one of claims 1 to 5, characterized by, Comprise: forming a P type oxide on a substrate to obtain a P well region; forming a source N+ region on the P well region by ion implantation; applying dry etching to the substrate, the P well region and the source N+ region to obtain a gate trench; depositing silicon oxide / polysilicon / silicon oxide on the gate trench in sequence to form a "sandwich" structure mask, and etching to form an ion implantation mask; performing ion implantation on the substrate at the bottom of the gate trench to obtain a P+ mask layer; performing ion implantation on the P+ mask layer to obtain an N+ conducting layer, and removing the mask after the implantation is completed; performing gate dielectric growth, gate silicon growth and interlayer dielectric deposition on the gate trench in sequence to obtain a gate electrode and an interlayer dielectric layer, and depositing and annealing ohmic contact metal on the source N+ region to obtain a source contact region; depositing and etching metal on the upper surface of the source contact region to form a source electrode, and depositing metal on the lower surface of the substrate to form a drain electrode.

7. The method of manufacturing according to claim 6, wherein, The method further comprises, before making the P-type oxide on the substrate: growing an N- epitaxial layer on the N+ substrate layer to obtain the substrate.

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