Programmable gain amplifier and method of controlling the same

Abstract

The application discloses a programmable gain amplifier and a control method thereof. The programmable gain amplifier comprises a first differential amplifier circuit, a first set of gain resistors, a second set of gain resistors, a set of sampling capacitors, a first set of switches and a second differential amplifier circuit. The first set of switches is used for selectively coupling the first set of gain resistors between an inverting input voltage and an input of the first differential amplifier circuit, coupling the second set of gain resistors between a common-mode voltage source and the input of the first differential amplifier circuit, and coupling the set of sampling capacitors with respective outputs of the first differential amplifier circuit during a first stage of an offset calibration of the first differential amplifier circuit. Through storage of the sampling capacitors and negative feedback of the second differential amplifier circuit, an offset voltage on the first differential amplifier circuit is offset, so that the influence of the offset voltage on a front-stage amplifier circuit on detection accuracy can be effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and more specifically, to a programmable gain amplifier and its control method. Background Technology

[0002] Gain amplifiers are crucial circuit modules widely used in analog / mixed-signal integrated circuit design, such as analog front-ends (AFEs), ADC converters, and DC / DC converters. They often play a key role in the entire analog / mixed-signal integrated circuit, namely, amplifying the input signal gain. Because the signals to be amplified in high-precision sensor measurements are generally very weak, the pre-amplified PGA (programmable gain amplifier) ​​must have the lowest possible offset voltage.

[0003] Traditional variable gain amplifiers (PGA) eliminate offset voltage by chopping the operational amplifier within the PGA. However, this method has drawbacks: it only chops the operational amplifier, eliminating its offset voltage, but not the offset voltage of the gain resistor. Furthermore, using chopping technology requires adding a notch filter circuit to eliminate the ripple introduced by chopping, increasing circuit complexity. Summary of the Invention

[0004] In view of the above problems, the purpose of this invention is to provide a programmable gain amplifier and its control method, which can effectively reduce the impact of offset voltage on detection accuracy in the preamplifier circuit.

[0005] According to one aspect of the present invention, a programmable gain amplifier is provided, comprising: a first differential amplifier circuit including a set of inputs and a set of outputs; a first set of gain resistors having a second terminal coupled to a corresponding input of the first differential amplifier circuit; a second set of gain resistors having a first terminal coupled to a corresponding input of the first differential amplifier circuit; a set of sampling capacitors; a first set of switches for selectively coupling a first terminal of the first set of gain resistors to an inverting input voltage, coupling a second terminal of the second set of gain resistors to a common-mode voltage source, and coupling the set of sampling capacitors to a corresponding output of the first differential amplifier circuit during a first stage of offset calibration of the first differential amplifier circuit; and a second differential amplifier circuit coupled between the set of sampling capacitors and the first differential amplifier circuit for feeding back an offset voltage stored on the set of sampling capacitors to the first differential amplifier circuit during the first stage.

[0006] Optionally, the offset voltage includes the offset generated by the first differential amplifier circuit and the offset generated by the first set of gain resistors and the second set of gain resistors.

[0007] Optionally, the programmable gain amplifier further includes: a second set of switches, used to selectively couple the first terminal of the first set of gain resistors to a non-inverting input voltage and an inverting input voltage respectively during the second stage of signal amplification by the first differential amplifier circuit, couple the second terminal of the second set of gain resistors to the corresponding outputs of the first differential amplifier circuit respectively, and couple the output of the first differential amplifier circuit in series with the ADC.

[0008] Optionally, the first group of switches and the second group of switches are configured to be non-overlapping conductions.

[0009] Optionally, the first differential amplifier circuit includes: a first transconductance amplifier, a load stage circuit, and an output stage circuit connected in series.

[0010] Optionally, the first transconductance amplifier has a non-inverting input terminal and an inverting input terminal. The non-inverting input terminal is coupled to the second terminal of the first gain resistor in the first group of gain resistors and the first terminal of the third gain resistor in the second group of gain resistors. The inverting input terminal is coupled to the second terminal of the second gain resistor in the first group of gain resistors and the first terminal of the fourth gain resistor in the second group of gain resistors.

[0011] Optionally, the second differential amplifier circuit includes: a second transconductance amplifier having a non-inverting input coupled to a first sampling capacitor in the set of sampling capacitors, an inverting input coupled to a second sampling capacitor in the set of sampling capacitors, and a differential output coupled to the output of the first transconductance amplifier.

[0012] According to another aspect of the present invention, a control method for a programmable gain amplifier is provided, which utilizes a set of sampling capacitors selectively coupled to a first differential amplifier circuit and a second differential amplifier circuit. The control method includes: during a first stage of offset calibration of the first differential amplifier circuit, selectively coupling a first set of gain resistors between an inverting input voltage and a corresponding input of the first differential amplifier circuit via a first set of switches, coupling a second gain resistor between a common-mode voltage source and a corresponding input of the first differential amplifier circuit, and coupling the set of sampling capacitors to a corresponding output of the first differential amplifier circuit; and coupling the second differential amplifier circuit between the set of sampling capacitors and the first differential amplifier circuit to feed back the offset voltage stored on the set of sampling capacitors to the first differential amplifier circuit.

[0013] Optionally, the offset voltage includes the offset generated by the first differential amplifier circuit and the offset generated by the first set of gain resistors and the second set of gain resistors.

[0014] Optionally, the control method further includes: during the second stage of signal amplification by the first differential amplifier circuit, selectively coupling the first set of gain resistors between the non-inverting / inverting input voltage and the input of the first differential amplifier circuit via a second set of switches, coupling the second set of gain resistors between the input and output of the first differential amplifier circuit, and connecting the output of the first differential amplifier circuit in series with the ADC.

[0015] Optionally, the first group of switches and the second group of switches are configured to be non-overlapping conductions.

[0016] In summary, the programmable gain amplifier and its control method proposed in this embodiment include a first differential amplifier circuit, a second differential amplifier circuit, multiple gain resistors, and a set of sampling capacitors. Before each ADC conversion, the sampling capacitors are coupled to the output of the first differential amplifier circuit. The sampling capacitors store the offset voltage generated by the first differential amplifier circuit and the gain resistors. The offset voltage on the first differential amplifier circuit is canceled by the negative feedback of the second differential amplifier circuit, thereby achieving the purpose of offset calibration. This can effectively reduce the impact of the offset voltage on the front-end amplifier circuit on the detection accuracy. The structure is simple, the area is smaller, and it is easy to integrate. It is suitable for the front-end amplifier circuit of ADC for high-precision detection. Attached Figure Description

[0017] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0018] Figure 1 A schematic circuit diagram of a programmable gain amplifier according to an embodiment of the present invention is shown;

[0019] Figure 2 The following diagram illustrates the signal timing of different stages of a programmable gain amplifier according to an embodiment of the present invention. Detailed Implementation

[0020] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0021] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "coupled to" another element or "coupled between" two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly coupled to" another element, it means that there are no intermediate elements between them.

[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0023] Figure 1 A schematic circuit diagram of a programmable gain amplifier 100 according to an embodiment of the present invention is shown. Figure 2 The following diagram illustrates the signal timing of different stages of a programmable gain amplifier 100 according to an embodiment of the present invention. Figure 2 The signals P1 and P2 shown can be generated by the controller in response to an external timing signal (e.g., a clock signal). The controller may include digital circuitry and / or may be implemented by a machine or computer.

[0024] like Figure 1 As shown, the programmable gain amplifier 100 of this embodiment includes a first differential amplifier circuit 110, a second differential amplifier circuit 120, a first set of gain resistors, a second set of gain resistors, a set of sampling capacitors, and two sets of switches.

[0025] In this configuration, a first set of gain resistors is selectively coupled between the inverting input voltage VIN and the corresponding input of the first differential amplifier circuit 110 during the first stage of offset calibration. A second set of gain resistors is selectively coupled between the common-mode voltage source VCM and the corresponding input of the first differential amplifier circuit during the first stage. A set of sampling capacitors is selectively coupled to the corresponding output of the first differential amplifier circuit 110 during the first stage. Thus, the offset voltage generated across the first and second sets of gain resistors, as well as the offset voltage generated by the first differential amplifier circuit 110, is amplified to its output by the first differential amplifier circuit 110 and then sampled and stored by the set of sampling capacitors. The second differential amplifier circuit 120 is coupled between the set of sampling capacitors and the first differential amplifier circuit 110. The set of sampling capacitors samples the output voltage and feeds it back to the first differential amplifier circuit 110 through the second differential amplifier circuit 120. Under the action of negative feedback, the voltage stored on the set of sampling capacitors will cancel the influence of the gain resistor and the offset voltage of the first differential amplifier circuit 110 on the output terminal. Therefore, in the subsequent ADC conversion stage, due to the effect of the set of sampling capacitors, the offset voltage of the main operational amplifier is basically eliminated, and high-precision detection is achieved.

[0026] Furthermore, the first differential amplifier circuit 110 includes a transconductance amplifier GM1 101, a load stage circuit R 102, and an output stage circuit A1 103. The second differential amplifier circuit 120 includes a transconductance amplifier GM2 105. The first set of switches includes switches S1, S2, S3, S8, and S9, and the second set of switches includes switches S0, S4, S5, S6, and S7. Both the first differential amplifier circuit 110 and the second differential amplifier circuit 120 include differential inputs and differential outputs. The first set of gain resistors includes gain resistors R1 and R2, the second set of gain resistors includes gain resistors R3 and R4, and the first set of sampling capacitors includes sampling capacitors C1 and C2.

[0027] The second terminal of gain resistor R1 is coupled to the non-inverting input terminal of transconductance amplifier GM1 101, and the second terminal of gain resistor R2 is coupled to the inverting input terminal of transconductance amplifier GM1 101. The inverting and non-inverting input terminals of transconductance amplifier GM1 101 constitute the differential input of the first differential amplifier circuit 110. The first terminal of gain resistor R1 is coupled to the non-inverting input voltage VIP via switch S0, and the first terminal of gain resistor R2 is coupled to the inverting input voltage VIN. These inputs VIP and VIN together form the differential input of programmable gain amplifier 100. Switch S1 is coupled between the first terminals of gain resistor R1 and gain resistor R2.

[0028] The first terminal of gain resistor R3 is coupled to the non-inverting input terminal of transconductance amplifier GM1 101. The second terminal of gain resistor R3 is coupled to one output (output OUTP) of output stage circuit 130 of the first differential amplifier circuit 110 via switch S4. The second terminal of gain resistor R3 is also coupled to common-mode voltage source VCM via switch S8. The first terminal of gain resistor R4 is coupled to the inverting input terminal of transconductance amplifier GM1 101. The second terminal of gain resistor R4 is coupled to another output (output OUTN) of output stage circuit 130 via switch S5. The second terminal of gain resistor R4 is also coupled to common-mode voltage source VCM via switch S9. Outputs OUTP and OUTN constitute the differential output of the first differential amplifier circuit 110.

[0029] The first terminal of sampling capacitor C1 is coupled to one output OUTN of output stage circuit A1 103 in the first differential amplifier circuit 110 via switch S2, and the second terminal is grounded. The first terminal of sampling capacitor C2 is coupled to another output OUP of output stage circuit A1 103 in the first differential amplifier circuit 110 via switch S3, and the second terminal is grounded.

[0030] The non-inverting input of transconductance amplifier GM2 105 is coupled to the first terminal of sampling capacitor C1, and the inverting input is coupled to the first terminal of sampling capacitor C2. Its differential output is coupled to the differential output of transconductance amplifier GM1 101.

[0031] The two outputs OUTP and OUTN of the output stage circuit A1 103 in the first differential amplifier circuit 110 are coupled to the ADC (Analog to Digital Converter) 104 via switches S6 and S7, respectively.

[0032] The following is for reference Figure 2 The working principle of the programmable gain amplifier 100 according to an embodiment of the present invention will be described in detail. In this embodiment, the transconductance amplifier GM1 101, the load stage circuit R 102, and the output stage circuit A1 103 constitute the main operational amplifier for signal amplification, and the transconductance amplifier GM2 105 is an auxiliary operational amplifier. Figure 2 As shown, the operation of the programmable gain amplifier 100 of the present invention includes two stages: an offset calibration stage for the first differential amplifier circuit 110 when signal P1 is at a logic high value, and a stage where signal P2 is amplified by the first differential amplifier circuit 110 for ADC conversion when signal P2 is at a logic high value, wherein signals P1 and P2 are non-overlapping signals.

[0033] Specifically, when signal P1 is at a logic high value, the first set of switches S1, S2, S3, S8, and S9 are set to the closed state, and the second set of switches S0, S4, S5, S6, and S7 are set to the open state. The first terminals of gain resistors R1 and R2 are both coupled to the inverting input voltage VIN. Gain resistor R3 is coupled between the non-inverting input terminal of transconductance amplifier GM1 101 and the common-mode voltage source VCM. Gain resistor R4 is coupled between the inverting input terminal of transconductance amplifier GM1 101 and the common-mode voltage source VCM. The first terminal of sampling capacitor C1 is coupled to the output OUTN of output stage circuit A1 103, and the first terminal of sampling capacitor C2 is coupled to the output OUTP of output stage circuit A1 103. The offset voltages of gain resistors R1 to R4 and the offset voltage of transconductance amplifier GM1101 are amplified to the output by the gain GM1*R*A1. Sampling capacitors C1 and C2 sample the output voltage. Through the negative feedback of transconductance amplifier GM2105, we can obtain:

[0034] (Vc1-Vc2)×GM2=Vos×GM1

[0035] Where Vc1 and Vc2 are the voltages stored on sampling capacitors C1 and C2, respectively, Vos is the offset voltage equivalent to the input of the main operational amplifier, GM1 is the gain of transconductance amplifier GM1 101, and GM2 is the gain of transconductance amplifier GM2 105.

[0036] Through the above process, the offset voltage of the first differential amplifier circuit 110 is stored in the sampling capacitors C1 and C2. When the signal P2 is at a logic high value, the first set of switches S1, S2, S3, S8, and S9 are set to the open state, and the second set of switches S0, S4, S5, S6, and S7 are set to the closed state. Gain resistor R1 is coupled between the non-inverting input voltage VIP and the non-inverting input terminal of transconductance amplifier GM1 101, gain resistor R2 is coupled between the inverting input voltage VIN and the inverting input terminal of transconductance amplifier GM1 101, gain resistor R3 is coupled between the non-inverting input terminal of transconductance amplifier GM1 101 and the output OUTP of output stage circuit A1 103, and gain resistor R4 is coupled between the inverting input terminal of transconductance amplifier GM1 101 and the output OUTN of output stage circuit A1 103. The differential outputs OUTP and OUTN of output stage circuit A1 103 are coupled to ADC 104. The first differential amplifier circuit 110 amplifies the input differential voltages VIP and VIN, and then performs normal analog-to-digital conversion via ADC 104. Due to the effect of sampling capacitors C1 and C2, the offset voltage of the first differential amplifier circuit 110 is essentially canceled out, thus enabling high-precision detection.

[0037] It should be noted that the gain of transconductance amplifier GM2 105 in this embodiment is much smaller than that of transconductance amplifier GM1 101. This significantly suppresses the offset voltage on transconductance amplifier GM2 105 when it is equivalent to the differential input, thus avoiding the introduction of additional offset voltage during offset calibration of the main operational amplifier. Furthermore, to reduce the impact of capacitor leakage on circuit accuracy, the offset voltage of the first differential amplifier circuit 110 needs to be re-stored after each conversion interval, which further improves the circuit's detection accuracy.

[0038] In summary, the programmable gain amplifier and its control method proposed in this embodiment include a first differential amplifier circuit, a second differential amplifier circuit, multiple gain resistors, and a set of sampling capacitors. Before each ADC conversion, the sampling capacitors are coupled to the output of the first differential amplifier circuit. The sampling capacitors store the offset voltage generated by the first differential amplifier circuit and the gain resistors. The offset voltage on the first differential amplifier circuit is canceled by the negative feedback of the second differential amplifier circuit, thereby achieving the purpose of offset calibration. This can effectively reduce the impact of the offset voltage on the front-end amplifier circuit on the detection accuracy. The structure is simple, the area is smaller, and it is easy to integrate. It is suitable for the front-end amplifier circuit of ADC for high-precision detection.

[0039] Those skilled in the art will understand that the terms “during,” “when,” and “when…” used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately upon the initiation of a startup action, but rather that there may be some small but reasonable delay or one or more delays, such as various propagation delays, between the startup action and the reaction action initiated by it. The terms “approximately” or “substantially” used herein mean that an element value is expected to be close to the declared value or position. However, as is well known in the art, there are always small deviations that make it difficult for the value or position to be strictly the declared value. It has been properly determined in the art that a deviation of at least ten percent (10%) (or at least twenty percent (20%) for semiconductor doping concentration) is a reasonable deviation from the described accurate ideal target. When used in conjunction with signal states, the actual voltage value or logic state of the signal (e.g., “1” or “0”) depends on whether positive or negative logic is used.

[0040] Furthermore, it should be noted that relational terms such as "first" and "second" used herein are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0041] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. A programmable gain amplifier, comprising: The first differential amplifier circuit includes a set of inputs and a set of outputs; The first set of gain resistors has a second terminal coupled to the corresponding input of the first differential amplifier circuit; The second set of gain resistors has a first terminal coupled to the corresponding input of the first differential amplifier circuit; A set of sampling capacitors; The first set of switches is used to selectively couple the first terminal of the first set of gain resistors to the inverting input voltage, the second terminal of the second set of gain resistors to the common-mode voltage source, and the set of sampling capacitors to the corresponding output of the first differential amplifier circuit during the first stage of offset calibration of the first differential amplifier circuit. as well as A second differential amplifier circuit, coupled between the set of sampling capacitors and the first differential amplifier circuit, is used to feed back the offset voltage stored on the set of sampling capacitors to the first differential amplifier circuit during the first stage.

2. The programmable gain amplifier according to claim 1, wherein, The offset voltage includes the offset generated by the first differential amplifier circuit and the offset generated by the first set of gain resistors and the second set of gain resistors.

3. The programmable gain amplifier according to claim 1, further comprising: The second set of switches is used to selectively couple the first terminal of the first set of gain resistors to the non-inverting input voltage and the inverting input voltage respectively during the second stage of signal amplification by the first differential amplifier circuit, couple the second terminal of the second set of gain resistors to the corresponding output of the first differential amplifier circuit respectively, and couple the output of the first differential amplifier circuit in series with the ADC.

4. The programmable gain amplifier according to claim 3, wherein, The first group of switches and the second group of switches are configured to conduct without overlapping.

5. The programmable gain amplifier according to claim 4, wherein, The first differential amplifier circuit includes: The first transconductance amplifier, the load stage circuit, and the output stage circuit are connected in series.

6. The programmable gain amplifier according to claim 5, wherein, The first transconductance amplifier has a non-inverting input terminal and an inverting input terminal. The non-inverting input terminal is coupled to the second terminal of the first gain resistor in the first group of gain resistors and the first terminal of the third gain resistor in the second group of gain resistors. The inverting input terminal is coupled to the second terminal of the second gain resistor in the first group of gain resistors and the first terminal of the fourth gain resistor in the second group of gain resistors.

7. The programmable gain amplifier according to claim 6, wherein, The second differential amplifier circuit includes: The second transconductance amplifier has a non-inverting input coupled to a first sampling capacitor in the set of sampling capacitors, an inverting input coupled to a second sampling capacitor in the set of sampling capacitors, and a differential output coupled to the output of the first transconductance amplifier.

8. A control method for a programmable gain amplifier, comprising using a set of sampling capacitors selectively coupled to a first differential amplifier circuit and a second differential amplifier circuit, the control method comprising: During the first stage of offset calibration of the first differential amplifier circuit, the first set of gain resistors is selectively coupled between the inverting input voltage and the corresponding input of the first differential amplifier circuit by means of the first set of switches, the second gain resistor is coupled between the common-mode voltage source and the corresponding input of the first differential amplifier circuit, and the set of sampling capacitors is coupled to the corresponding output of the first differential amplifier circuit. as well as The second differential amplifier circuit is coupled between the set of sampling capacitors and the first differential amplifier circuit to feed back the offset voltage stored on the set of sampling capacitors to the first differential amplifier circuit.

9. The control method according to claim 8, wherein, The offset voltage includes the offset generated by the first differential amplifier circuit and the offset generated by the first set of gain resistors and the second set of gain resistors.

10. The control method according to claim 8, wherein, Also includes: During the second stage of signal amplification by the first differential amplifier circuit, the first set of gain resistors is selectively coupled between the non-inverting / inverting input voltage and the input of the first differential amplifier circuit by the second set of switches, the second set of gain resistors is coupled between the input and output of the first differential amplifier circuit, and the output of the first differential amplifier circuit is coupled in series with the ADC.

11. The control method according to claim 10, wherein, The first group of switches and the second group of switches are configured to conduct without overlapping.

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