An antenna feed network and antenna

Abstract

The application relates to the technical field of antennas and discloses an antenna feed network and an antenna, the antenna feed network comprising M latch circuits, the M latch circuits being connected in negative feedback cascade, and the M latch circuits connected in negative feedback cascade being used for outputting quadrature signals, wherein M is an integer greater than 1. The quadrature signals are realized by the latch circuits connected in negative feedback cascade, the quadrature signals can replace a four-phase feed network composed of a traditional microstrip line power divider, a 90-degree bridge or a phase shifter connected in cascade, the size of the quadrature signals is only a chip size, the quadrature signals are easy to integrate, and the quadrature signals are suitable for a wide range of applications.

Description

Technical Field

[0001] This invention relates to the field of antenna technology, and in particular to an antenna feed network and an antenna. Background Technology

[0002] Antenna polarization is classified into linear polarization and circular polarization. Compared to linearly polarized antennas, circularly polarized antennas have the following advantages: they can receive incoming waves from any direction, have better suppression of multipath effects, are more resistant to rain and fog interference, and can eliminate polarization distortion losses caused by the ionospheric Faraday rotation effect. Therefore, circularly polarized antennas are widely used in wireless communication, satellite communication, satellite navigation, and electronic warfare.

[0003] In recent years, with the development of communication technology, there is a growing demand for circularly polarized antennas with wide bandwidth, low axial ratio, and high integration. Common methods to achieve wide bandwidth and low axial ratio include multi-feed and multi-element methods. Multi-feed methods typically have four feed points, while multi-element methods correspond to four array elements rotated sequentially by 90° or -90°. Both require a feeding network to generate four sets of feed networks with equal amplitude and phase differences of 90° or -90°. However, traditional feeding networks are usually composed of microstrip power dividers, 90° bridges, or cascaded phase shifters. These networks have narrow bandwidth, large size, and can only be adapted to antennas in specific frequency bands, resulting in low versatility. Therefore, how to provide a novel feeding network for circularly polarized antennas is a pressing issue that needs to be addressed. Summary of the Invention

[0004] This invention provides an antenna feed network and an antenna to solve the aforementioned technical problems in the prior art.

[0005] According to a first aspect of the present invention, an antenna feed network is provided.

[0006] The antenna feed network includes M latch circuits, which are cascaded with negative feedback. The M latch circuits after negative feedback cascade are used to output quadrature signals, where M is an integer greater than 1.

[0007] The time interval between latching circuits is 1 / 4 of a clock cycle.

[0008] The number of latching circuits, M, is 2.

[0009] The latching circuit includes MOSFETs 1 through MOSFET 6. The sources of MOSFET 1 and MOSFET 2 are connected to the power supply voltage. The drains of MOSFET 1 and MOSFET 2 are connected to the source of MOSFET 5. The gate of MOSFET 5 is connected to the clock input signal, and the drain of MOSFET 5 is grounded. The source of MOSFET 3 is connected to the source of MOSFET 2. The drain of MOSFET 3 is connected to the source of MOSFET 6. The gate of MOSFET 3 is connected to the source of MOSFET 4. The gate of MOSFET 4 is connected to the source of MOSFET 3. The drain of MOSFET 4 is connected to the source of MOSFET 6. The drain of MOSFET 6 is grounded, and the gate of MOSFET 6 is connected to the inverted clock input signal.

[0010] In this configuration, between adjacent latch circuits, the gate of MOSFET 1 in the first latch circuit is connected to the source of MOSFET 3 in the second latch circuit; the gate of MOSFET 2 in the first latch circuit is connected to the source of MOSFET 1 and MOSFET 4 in the second latch circuit; the gate of MOSFET 1 in the second latch circuit is connected to the source of MOSFET 1 and MOSFET 4 in the first latch circuit; and the gate of MOSFET 2 in the second latch circuit is connected to the source of MOSFET 3 in the first latch circuit.

[0011] The latching circuit further includes a first load and a second load, wherein the first load is connected between the power supply voltage and the source of MOSFET one, and the second load is connected between the power supply voltage and the source of MOSFET two.

[0012] Wherein, both the first load and the second load are load resistors or load inductors.

[0013] The latching circuit further includes: capacitor one and capacitor two. One end of capacitor one is connected to the source of MOSFET three, and the other end of capacitor one is grounded. One end of capacitor two is connected to the source of MOSFET four, and the other end of capacitor two is grounded.

[0014] The latching circuit also includes a tail current source, which is connected between the drains of MOSFET five and MOSFET six and ground.

[0015] According to a second aspect of the invention, an antenna is provided having the antenna feed network described above.

[0016] The technical solution provided by this invention may include the following beneficial effects:

[0017] This invention achieves quadrature signals through a cascaded negative feedback latch circuit, which can replace the four-phase power supply network composed of traditional microstrip power dividers, 90° bridges, or cascaded phase shifters. Its size is only that of a chip, making it easy to integrate and widely applicable.

[0018] Furthermore, this invention can output wideband four-phase signals with equal amplitude and orthogonality within an octave bandwidth. Based on the four-phase orthogonal signals generated by the chip, the consistency and accuracy are far superior to traditional PCB or mechanical processing methods, with the phase typically controllable within ±0.5°. In addition, the antenna feed network of this invention has strong adaptability and can be adapted to circularly polarized antennas of different structures, frequency bands, and feed methods.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0021] Figure 1 This is a schematic diagram of the structure of an antenna feed network with a load resistor, according to an exemplary embodiment.

[0022] Figure 2 This is a schematic diagram of the structure of an antenna feed network in the case of a tailless current source, according to an exemplary embodiment.

[0023] Figure 3 This is a schematic diagram of the structure of an antenna feed network with a load inductor, according to an exemplary embodiment.

[0024] Figure 4 This is a schematic diagram of the structure of an antenna feed network with a tailless current source and a load inductor, according to an exemplary embodiment.

[0025] Figure 5 This is an output waveform diagram of an antenna feed network illustrated according to an exemplary embodiment. Detailed Implementation

[0026] The following description and accompanying drawings fully illustrate specific embodiments described herein to enable those skilled in the art to practice them. Some embodiments may include or substitute parts and features of other embodiments. The scope of the embodiments herein encompasses the entire scope of the claims and all available equivalents thereof. Throughout this document, the terms “first,” “second,” etc., are used only to distinguish one element from another without requiring or implying any actual relationship or order between the elements. Indeed, a first element can also be referred to as a second element, and vice versa. Furthermore, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a structure, apparatus, or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a structure, apparatus, or device. Without further limitation, an element defined by the phrase “comprising one…” does not exclude the presence of other identical elements in the structure, apparatus, or device that includes said element. The various embodiments described herein are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0027] The terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer" used in this document to indicate orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings. They are used solely for the convenience of describing the document and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In the description herein, unless otherwise specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to mechanical or electrical connections, or internal connections between two elements; they can be direct connections or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances.

[0028] In this document, unless otherwise stated, the term "multiple" means two or more.

[0029] In this article, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0030] In this article, the term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0031] Where there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0032] Example 1

[0033] Figure 1 An embodiment of the antenna feed network of the present invention with a load resistor is shown. In this optional embodiment, the antenna feed network includes: two latch circuits, which are cascaded with negative feedback. The two latch circuits after negative feedback cascade are used to output quadrature signals, and the time interval between the two latch circuits is 1 / 4 clock cycle. Each latch circuit includes: MOSFETs M1-M6, a first load resistor R1, a second load resistor R2, capacitors C1 and C2, and a tail current source ISS.

[0034] Specifically, the sources of MOSFET M1 and M2 are connected to the power supply voltage VDD. The drains of MOSFET M1 and M2 are connected to the source of MOSFET M5. The gate of MOSFET M5 is connected to the clock input signal CK, and the drain of MOSFET M5 is grounded. The source of MOSFET M3 is connected to the source of MOSFET M2. The drain of MOSFET M3 is connected to the source of MOSFET M6. The gate of MOSFET M3 is connected to the source of MOSFET M4. The gate of MOSFET M4 is connected to the source of MOSFET M3. The drain of MOSFET M4 is connected to the source of MOSFET M6. The drain of MOSFET M6 is grounded, and the gate of MOSFET M6 is connected to the inverted clock input signal CK. Between adjacent latch circuits, the gate of MOSFET M1 in the first latch circuit is connected to the source of MOSFET M3 in the second latch circuit; the gate of MOSFET M2 in the first latch circuit is connected to the source of MOSFET M1 and the source of MOSFET M4 in the second latch circuit; the gate of MOSFET M1 in the second latch circuit is connected to the source of MOSFET M1 and the source of MOSFET M4 in the first latch circuit; the gate of MOSFET M2 in the second latch circuit is connected to the source of MOSFET M1 and the source of MOSFET M4 in the first latch circuit; The source of MOSFET M3 is connected; the first load resistor R1 is connected between the power supply voltage VDD and the source of MOSFET M1, and the second load resistor R2 is connected between the power supply voltage VDD and the source of MOSFET M2; one end of capacitor C1 is connected to the source of MOSFET M3, and the other end of capacitor C1 is grounded; one end of capacitor C2 is connected to the source of MOSFET M4, and the other end of capacitor C2 is grounded; the tail current source ISS is connected between the drain of MOSFET M5 and MOSFET M6 and ground.

[0035] Example 2

[0036] Figure 2 An embodiment of the antenna feed network under the tailless current source condition of the present invention is shown. In this optional embodiment, the antenna feed network includes: two latch circuits, which are cascaded with negative feedback. The two latch circuits after negative feedback cascade are used to output quadrature signals, and the time interval between the two latch circuits is 1 / 4 clock cycle. Each latch circuit includes: MOSFETs M1-M6, a first load resistor R1, a second load resistor R2, a capacitor C1, and a capacitor C2.

[0037] Specifically, the sources of MOSFET M1 and M2 are connected to the power supply voltage VDD. The drains of MOSFET M1 and M2 are connected to the source of MOSFET M5. The gate of MOSFET M5 is connected to the clock input signal CK, and the drain of MOSFET M5 is grounded. The source of MOSFET M3 is connected to the source of MOSFET M2. The drain of MOSFET M3 is connected to the source of MOSFET M6. The gate of MOSFET M3 is connected to the source of MOSFET M4. The gate of MOSFET M4 is connected to the source of MOSFET M3. The drain of MOSFET M4 is connected to the source of MOSFET M6. The drain of MOSFET M6 is grounded, and the gate of MOSFET M6 is connected to the inverted clock input signal CK. Between adjacent latch circuits, the gate of MOSFET M1 in the first latch circuit is connected to the source of MOSFET M3 in the second latch circuit; the gate of MOSFET M2 in the first latch circuit is connected to the source of MOSFET M1 and the source of MOSFET M4 in the second latch circuit; the gate of MOSFET M1 in the second latch circuit is connected to the source of MOSFET M1 and the source of MOSFET M4 in the first latch circuit; the gate of MOSFET M2 in the second latch circuit is connected to the source of MOSFET M3 in the first latch circuit; a first load resistor R1 is connected between the power supply voltage VDD and the source of MOSFET M1; a second load resistor R2 is connected between the power supply voltage VDD and the source of MOSFET M2; one end of capacitor C1 is connected to the source of MOSFET M3, and the other end of capacitor C1 is grounded; one end of capacitor C2 is connected to the source of MOSFET M4, and the other end of capacitor C2 is grounded.

[0038] Example 3

[0039] Figure 3An embodiment of the antenna feed network of the present invention with a load inductor is shown. In this optional embodiment, the antenna feed network includes: two latch circuits, which are cascaded with negative feedback. The two latch circuits after negative feedback cascade are used to output quadrature signals, and the time interval between the two latch circuits is 1 / 4 clock cycle. Each latch circuit includes: MOSFETs M1-M6, a first load inductor L1, a second load inductor L2, capacitors C1 and C2, and a tail current source ISS.

[0040] Specifically, the sources of MOSFET M1 and M2 are connected to the power supply voltage VDD. The drains of MOSFET M1 and M2 are connected to the source of MOSFET M5. The gate of MOSFET M5 is connected to the clock input signal CK, and the drain of MOSFET M5 is grounded. The source of MOSFET M3 is connected to the source of MOSFET M2. The drain of MOSFET M3 is connected to the source of MOSFET M6. The gate of MOSFET M3 is connected to the source of MOSFET M4. The gate of MOSFET M4 is connected to the source of MOSFET M3. The drain of MOSFET M4 is connected to the source of MOSFET M6. The drain of MOSFET M6 is grounded, and the gate of MOSFET M6 is connected to the inverted clock input signal CK. Between adjacent latch circuits, the gate of MOSFET M1 in the first latch circuit is connected to the source of MOSFET M3 in the second latch circuit; the gate of MOSFET M2 in the first latch circuit is connected to the source of MOSFET M1 and the source of MOSFET M4 in the second latch circuit; the gate of MOSFET M1 in the second latch circuit is connected to the source of MOSFET M1 and the source of MOSFET M4 in the first latch circuit; the gate of MOSFET M2 in the second latch circuit is connected to the source of MOSFET M1 and the source of MOSFET M4 in the first latch circuit; The source of MOSFET M3 is connected; the first load inductor L1 is connected between the power supply voltage VDD and the source of MOSFET M1, and the second load inductor L2 is connected between the power supply voltage VDD and the source of MOSFET M2; one end of capacitor C1 is connected to the source of MOSFET M3, and the other end of capacitor C1 is grounded; one end of capacitor C2 is connected to the source of MOSFET M4, and the other end of capacitor C2 is grounded; the tail current source ISS is connected between the drain of MOSFET M5 and MOSFET M6 and ground.

[0041] Example 4

[0042] Figure 4An embodiment of the antenna feed network of the present invention, wherein the tailless current source is used and the load is a load inductor, is shown. In this optional embodiment, the antenna feed network includes: two latch circuits, which are cascaded with negative feedback. The two latch circuits after negative feedback cascade are used to output quadrature signals, and the time interval between the two latch circuits is 1 / 4 clock cycle. Each latch circuit includes: MOSFETs M1-M6, a first load inductor L1, a second load inductor L2, a capacitor C1, and a capacitor C2.

[0043] Specifically, the sources of MOSFET M1 and M2 are connected to the power supply voltage VDD. The drains of MOSFET M1 and M2 are connected to the source of MOSFET M5. The gate of MOSFET M5 is connected to the clock input signal CK, and the drain of MOSFET M5 is grounded. The source of MOSFET M3 is connected to the source of MOSFET M2. The drain of MOSFET M3 is connected to the source of MOSFET M6. The gate of MOSFET M3 is connected to the source of MOSFET M4. The gate of MOSFET M4 is connected to the source of MOSFET M3. The drain of MOSFET M4 is connected to the source of MOSFET M6. The drain of MOSFET M6 is grounded, and the gate of MOSFET M6 is connected to the inverted clock input signal CK. Between adjacent latching circuits, the gate of MOSFET M1 in the first latching circuit is connected to the source of MOSFET M3 in the second latching circuit; the gate of MOSFET M2 in the first latching circuit is connected to the source of MOSFET M1 and the source of MOSFET M4 in the second latching circuit; the gate of MOSFET M1 in the second latching circuit is connected to the source of MOSFET M1 and the source of MOSFET M4 in the first latching circuit; the gate of MOSFET M2 in the second latching circuit is connected to the source of MOSFET M3 in the first latching circuit; the first negative load inductor L1 is connected between the power supply voltage VDD and the source of MOSFET M1; the second load inductor L2 is connected between the power supply voltage VDD and the source of MOSFET M2; one end of capacitor C1 is connected to the source of MOSFET M3, and the other end of capacitor C1 is grounded; one end of capacitor C2 is connected to the source of MOSFET M4, and the other end of capacitor C2 is grounded.

[0044] In practical applications, the latch operates when the clock input signal CK is high ( CKWhen the current is low, it is defined as the sampling phase. At this time, MOSFET M5 is turned on, MOSFET M6 is turned off, and the tail current source ISS flows through MOSFET M5. As a result, MOSFETs M1 and M2 are working, while MOSFETs M3 and M4 are not working. Since the drain and gate of the MOSFETs are out of phase, LOI+ and LOQ+ are out of phase at this time (LOI- and LOQ- are also out of phase).

[0045] The latch operates when the clock input signal CK is low ( CK When the voltage is high, it is defined as the hold phase, meaning the output remains unchanged for one clock cycle. During this time, MOSFET M5 is off, MOSFET M6 is on, and the tail current source ISS flows through MOSFET M6. Consequently, MOSFETs M1 and M2 are not working, while MOSFETs M3 and M4 are working. The positive feedback connection of MOSFETs M3 and M4 ensures that their drain voltage remains constant.

[0046] Based on the above process, it can be seen that the output of the latch remains unchanged within one clock signal cycle; it takes two clock signal cycles for the output of the register to change state. That is, after two latches are cascaded with negative feedback, the output signal frequency can be half the input signal frequency. At the same time, the output of the two latches only changes state at the rising or falling edge of the clock signal, that is, there is a 1 / 4 cycle delay between the latches, thus generating quadrature signal output.

[0047] Figure 5 The output waveform of the antenna feed network is shown. Figure 5 As can be seen from the output, LOI+, LOI-, LOQ+, and LOQ- are four orthogonal signals with a time interval of 1 / 4 of a period, i.e., a phase interval of 90 degrees.

[0048] Therefore, this invention utilizes chip-level active circuitry to achieve orthogonal four-phase signals, replacing traditional four-phase feed networks composed of microstrip power dividers, 90° bridges, or cascaded phase shifters. Its size is only that of a chip, making it easy to integrate and widely applicable. Furthermore, the four-phase feed network of this invention can output equal-amplitude, orthogonal, wideband four-phase signals within an octave bandwidth. The consistency and accuracy of the four-phase orthogonal signals generated by the chip are far superior to those produced by traditional PCB or mechanical processing methods, with the phase typically controllable within ±0.5°. This invention is highly adaptable and can be adapted to circularly polarized antennas of different structures, frequency bands, and feed methods.

[0049] This invention is not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this invention is limited only by the appended claims.

Claims

1. An antenna feed network, characterized in that, include: There are M latch circuits, which are cascaded with negative feedback. The M latch circuits after negative feedback cascading are used to output quadrature signals, where M is an integer greater than 1.

2. The antenna feed network according to claim 1, characterized in that, The time interval between latching circuits is 1 / 4 of a clock cycle.

3. The antenna feed network according to claim 1, characterized in that, The number of latching circuits, M, is 2.

4. The antenna feed network according to claim 1, characterized in that, The latching circuit includes: MOSFETs 1-6. The sources of MOSFETs 1 and 2 are connected to the power supply voltage. The drains of MOSFETs 1 and 2 are connected to the source of MOSFET 5. The gate of MOSFET 5 is connected to the clock input signal, and the drain of MOSFET 5 is grounded. The source of MOSFET 3 is connected to the source of MOSFET 2. The drain of MOSFET 3 is connected to the source of MOSFET 6. The gate of MOSFET 3 is connected to the source of MOSFET 4. The gate of MOSFET 4 is connected to the source of MOSFET 3. The drain of MOSFET 4 is connected to the source of MOSFET 6. The drain of MOSFET 6 is grounded, and the gate of MOSFET 6 is connected to the inverting clock input signal.

5. The antenna feed network according to claim 4, characterized in that, Between adjacent latch circuits, the gate of MOSFET 1 in the first latch circuit is connected to the source of MOSFET 3 in the second latch circuit; the gate of MOSFET 2 in the first latch circuit is connected to the source of MOSFET 1 and MOSFET 4 in the second latch circuit; the gate of MOSFET 1 in the second latch circuit is connected to the source of MOSFET 1 and MOSFET 4 in the first latch circuit; and the gate of MOSFET 2 in the second latch circuit is connected to the source of MOSFET 3 in the first latch circuit.

6. The antenna feed network according to claim 4, characterized in that, The latching circuit further includes a first load and a second load, wherein the first load is connected between the power supply voltage and the source of MOSFET one, and the second load is connected between the power supply voltage and the source of MOSFET two.

7. The antenna feed network according to claim 6, characterized in that, Both the first load and the second load are load resistors or load inductors.

8. The antenna feed network according to claim 4, characterized in that, The latching circuit also includes: capacitor one and capacitor two. One end of capacitor one is connected to the source of MOSFET three, and the other end of capacitor one is grounded. One end of capacitor two is connected to the source of MOSFET four, and the other end of capacitor two is grounded.

9. The antenna feed network according to claim 4, characterized in that, The latching circuit also includes a tail current source, which is connected between the drains of MOSFET five and MOSFET six and ground.

10. An antenna, characterized in that, The antenna has an antenna feed network as described in any one of claims 1-9.

Images