A Fourier interpolation method suitable for fast time base gear of oscilloscope

Abstract

The present invention discloses a Fourier interpolation method suitable for the fast time base gear of an oscilloscope. First, the sampling data stream x(n) is divided into a main path and a slave path. The slave path is started after delaying N / 2 valid data. The interpolation results corresponding to the middle part of the main / slave path interpolation results with smaller errors are alternately spliced ​​and the remaining data points are directly discarded, thereby reducing the data error caused by spectrum leakage caused by non-periodic truncation. At the same time, the present invention uses the interpolation multiple 8*2 k The high frequency part is filled with zeros, and the middle part of the interpolation result of the master / slave path is selected and the splicing result after the splicing process is processed by sliding average sampling to obtain the interpolation result y corresponding to the oscilloscope interpolation multiple L L (n), thereby achieving the ADC real-time sampling rate F s Less than the display sampling rate F x The waveform is effectively displayed while reducing the non-2 M The IFFT transform length and spectrum leakage caused by non-periodic truncation cause data errors.

Description

Technical Field

[0001] The present invention belongs to the technical field of waveform interpolation, and more specifically, relates to a Fourier interpolation method suitable for a fast time base gear of an oscilloscope, which performs corresponding interpolation processing on sampling data points and realizes the effect of data waveform interpolation, and is used to solve the problem of insufficient ADC sampling rate of an oscilloscope. Background Art

[0002] As a typical and commonly used method in data processing, digital interpolation technology plays a decisive role in waveform reconstruction of sampled signals. In an oscilloscope, when the ADC of the oscilloscope samples and digitizes the analog signal, the number of sampled data points is only a few and the waveform cannot be fully restored. In some fast time base positions of the oscilloscope, the ADC real-time sampling rate F s Less than the display sampling rate F x The problem is that the sampled data points cannot effectively display the waveform. At this time, it is necessary to use interpolation technology to insert corresponding data points between the sampled data points to complete the reconstruction of the waveform.

[0003] With the further development of science and technology, the demand for interpolation in oscilloscope acquisition modules has shown the characteristics of large-rate and multi-rate interpolation. However, the interpolation multiple L (L = F x / F s ) is usually in the form of 2, 5, 10, 20, 40, 80, etc. Except for the 2-times interpolation, the data after the zero-filling of the FFT transformation of the other interpolation multiples cannot meet the IFFT transformation length of 2. M Taking the 40-fold interpolation of a 64-point sampling sequence x(n) as an example, after FFT transformation and zero padding in the frequency domain, x(n) will contain a total of 2560 frequency domain data points. The integer 2560 is not 2 M IFFT transformation length will cause data errors.

[0004] In addition, during the interpolation process, data truncation is usually non-periodic truncation, which will cause spectrum leakage and also cause large data errors. Summary of the invention

[0005] The purpose of the present invention is to overcome the disadvantages and solve the problem that there is non-2 M In order to solve the problem of data error caused by spectrum leakage due to IFFT transform length and non-periodic truncation, a Fourier interpolation method suitable for the fast time base gear of oscilloscope is provided to achieve the real-time sampling rate F of ADC. s Less than the display sampling rate F x The waveform is effectively displayed while reducing the non-2 M The IFFT transform length and spectrum leakage caused by non-periodic truncation cause data errors.

[0006] To achieve the above-mentioned purpose, the present invention is applicable to a Fourier interpolation method for a fast time base gear of an oscilloscope, and is characterized in that it comprises the following steps:

[0007] (1) The sampled data stream x(n) is sent to the master and slave paths respectively. When the master path receives N / 2 valid data, the slave path starts to perform FFT transformation synchronously with the master path.

[0008] (2) After the master / slave path completes the FFT transformation of a frame of sampled data, i.e., N sampled data, the frequency domain data X(jω) / X0(jω) is obtained and written into the corresponding cache FIFO;

[0009] (3) The frequency domain zero-filling modules of the master / slave paths respectively control the read enable of their respective cache FIFOs reasonably, fill the high frequency part with zeros, and send the zero-filling result V(jω) / V0(jω) to the corresponding IFFT transformation modules respectively. If the oscilloscope interpolation multiple L corresponding to the fast time base gear of the oscilloscope is 2, the high frequency part is filled with zeros according to the interpolation multiple 2. If the oscilloscope interpolation multiple L corresponding to the fast time base gear of the oscilloscope is 5 / 2 k Multiple, k = 0, 1, 2, ..., then the interpolation multiple is 8*2 k The high frequency part is filled with zero, where the oscilloscope interpolation factor L = F x / F s , F x To display the sampling rate, F s is the ADC real-time sampling rate F s ;

[0010] (4) First, the interpolation result y(n) / y0(n) after the IFFT transformation module of the master / slave path completes the IFFT transformation is synchronized. Then, if the oscilloscope interpolation multiple L corresponding to the oscilloscope fast time base gear is 2, the splicing module selects the middle N / 2×L data of the interpolation result y(n) and the middle N / 2×L data of the interpolation result y0(n) for splicing to obtain the final interpolation result y L (n); If the interpolation factor L of the oscilloscope corresponding to the fast time base gear of the oscilloscope is 2 of 5 k When k = 0, 1, 2, ..., the splicing module selects the middle N / 2×L×8 / 5 data of the interpolation result y(n) and the middle N / 2×L×8 / 5 data of the interpolation result y0(n) for splicing to obtain the splicing result y L×8 / 5 (n) and sent to the 5 / 8 sampling module, which splices the result y L×8 / 5(n) Use sliding average to extract points: For every 8 data, with a sliding window size of 4, take the sum and average of every 4 selected points as the extraction result, so that 5 extraction results are obtained. All the extraction results are combined in sequence to obtain the final interpolation result y L (n).

[0011] The object of the invention of the present invention is achieved in this way:

[0012] The present invention is applicable to the Fourier interpolation method of the fast time base gear of the oscilloscope. First, the sampling data stream x(n) is divided into a main path and a slave path. The slave path is started after N / 2 valid data delay. In this way, the interpolation result corresponding to the last 1 / 4 of the data of the nth frame of the main path and the interpolation result corresponding to the first 1 / 4 of the data of the n+1th frame are the parts with larger errors, and this part of the data happens to be the area with smaller errors in the slave path. Therefore, the present invention alternately splices the interpolation results corresponding to the part with smaller errors of the main / slave path interpolation results, that is, the middle part, and directly discards the remaining data points to achieve effective reconstruction of the interpolated data and reduce the data error caused by spectrum leakage caused by non-periodic truncation. At the same time, the present invention is aimed at the IFFT transform length of non-2 after high-frequency zero padding of the sampled data. M The data error caused by zero filling in the frequency domain is calculated by the interpolation multiple 8*2 k The high frequency part is padded with zeros, and the middle part of the interpolation result of the master / slave path is selected and the spliced ​​result after the splicing process is processed by sliding average sampling to obtain the interpolation result yL(n) corresponding to the oscilloscope interpolation multiple L, so as to achieve the ADC real-time sampling rate F s When the waveform is less than the display sampling rate Fx, the non-2 M The IFFT transform length and spectrum leakage caused by non-periodic truncation cause data errors.

[0013] The present invention solves the problem that the real-time sampling rate of ADC is less than the display sampling rate under the fast time base gear of the oscilloscope, and the sampling data points cannot effectively display the waveform. At the same time, through the Fourier interpolation and error processing method designed by the present invention, interpolation processing with large magnification and multiple magnification switching can be realized, and the method has the characteristics of good interpolation effect, low resource consumption and good reuse and transplantation. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a flow chart of a specific implementation method of the Fourier interpolation method applicable to the fast time base gear of the oscilloscope of the present invention;

[0015] Figure 2 This is a schematic diagram of 5 / 8 sampling points using the sliding average method;

[0016] Figure 3 It is a schematic diagram of the hardware design of "overlapping frames";

[0017] Figure 4 It is a hardware design structure block diagram of the Fourier interpolation method applicable to the fast time base gear of the oscilloscope of the present invention;

[0018] Figure 5 is the waveform of the data to be interpolated;

[0019] Figure 6 It is the result of 40 times Fourier interpolation data processing. DETAILED DESCRIPTION

[0020] The specific implementation of the present invention is described below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0021] Example

[0022] In order to solve the problem that the real-time sampling rate of ADC is lower than the display sampling rate under the fast time base gear of some oscilloscopes, and the sampling data points cannot effectively display the waveform, in this embodiment, an interpolation method based on frequency domain processing (Fourier interpolation) is designed based on FPGA. First, the Fourier interpolation processing module of the sampled data is designed through the FFT / IFFT IP core embedded in Xilinx FPGA, and on this basis, the spectrum leakage caused by non-periodic truncation and the IFFT transform length of non-2 after high-frequency zero padding of the sampled data are solved. M The data errors caused by the interpolation are processed by the "overlapping frame" and "sliding average sampling" methods to obtain the final interpolation results, as follows:

[0023] (1) The IP core embedded in Xilinx FPGA completes the Fourier interpolation related data processing processes such as FFT transformation of sampled data, high-frequency data processing, and IFFT transformation;

[0024] (2) In the FFT transformation process of sampled data, the interpolation results caused by spectrum leakage due to non-periodic truncation mainly show the characteristics of large errors at both ends and small errors in the middle. Based on this error characteristic, the master-slave path "overlapping frames" method is used to retain and splice the smaller error fragments, that is, the middle part, so as to reduce the error impact caused by spectrum leakage;

[0025] (3) After the sampling data is zero-filled in the frequency domain, the data point length is not 2 M The problem that IFFT transformation cannot be completed through IP core, the present invention uses the "sliding average sampling" method to complete the sampling of the data after the master and slave paths are spliced, and obtains the final interpolation result.

[0026] In summary, the present invention can be divided into three parts: Fourier interpolation related data processing such as FFT transformation, frequency domain processing, IFFT transformation based on the IP core embedded in Xilinx FPGA, master-slave path "overlapping frame" data splicing, and "sliding average" decimal point sampling.

[0027] Figure 1 The present invention is a flowchart of a specific implementation of the Fourier interpolation method applicable to the fast time base gear of the oscilloscope.

[0028] In this embodiment, if Figure 1 As shown, the Fourier interpolation method applicable to the fast time base gear of the oscilloscope of the present invention comprises the following steps:

[0029] Step S1: The sampled data stream is divided into a main path and a slave path with N / 2 valid data delays

[0030] The sampled data stream x(n) is sent to the master and slave paths respectively. When the master path receives N / 2 valid data, the slave path starts to perform FFT transformation synchronously with the master path.

[0031] Step S2: Perform FFT transformation on N sampled data of a frame and write them into the corresponding buffer FIFO

[0032] After the master / slave path completes the FFT transformation of one frame of sampling data, that is, N sampling data, the frequency domain data X(jω) / X0(jω) is obtained and written into the corresponding cache FIFO.

[0033] Fourier interpolation is an interpolation algorithm based on zero padding in the frequency domain. The core idea of ​​the algorithm is to transform the time domain signal back with more frequency domain points, which can increase the time domain sampling points to achieve the interpolation effect. Perform N-point Fourier transform on the sampled data stream x(n) to obtain X(jw), and then perform high-frequency zero padding (LN) on X(jw) to obtain Y(jw). Y(jw) can be expressed as:

[0034]

[0035] Wherein, N1 represents the total number of frequency domain points after zero padding, N1 = N*L. The interpolated time domain sequence y(n) can be obtained by performing N1-point inverse Fourier transform (IFFT) on the zero-padded spectrum sequence Y(jw) in equation (1).

[0036] Step S3: According to the interpolation multiple 8*2 k Perform zero padding on the high frequency part and perform IFFT transformation on the frequency domain data after zero padding

[0037] The frequency domain zero-filling modules of the master / slave paths respectively control the read enable of their respective cache FIFOs reasonably, fill the high frequency part with zeros, and send the zero-filling result V(jω) / V0(jω) to the corresponding IFFT transformation modules respectively. If the oscilloscope interpolation multiple L corresponding to the fast time base gear of the oscilloscope is 2, the high frequency part is filled with zeros according to the interpolation multiple 2. If the oscilloscope interpolation multiple L corresponding to the fast time base gear of the oscilloscope is 2 of 5, k Multiple, k = 0, 1, 2, ..., then the interpolation multiple is 8*2 k The high frequency part is filled with zero, where the oscilloscope interpolation factor L = F x / F s , F x To display the sampling rate, F s is the ADC real-time sampling rate F s .

[0038] In this embodiment, the FFT / IFFT transformation is designed based on the IP core embedded in the Xilinx FPGA, and its transformation length can only be 2 M , according to the ADC real-time sampling rate F s Between the display sampling rate F x The relationship between the oscilloscope interpolation factor L (L = F x / F s ) is usually in the form of 2, 5, 10, 20, 40, 80, etc. Except for the 2-times interpolation, the data after the zero-filling of the FFT transformation of the other interpolation multiples cannot meet the IFFT transformation length of 2. M Taking the 64-point sampling sequence x(n) 40 times interpolation as an example, after FFT transformation and frequency domain zero padding, x(n) will contain a total of 2560 frequency domain data points. The integer 2560 is not 2 M At this time, the FFT IP core cannot be used for IFFT transformation. To solve the above problem, the present invention will find the interpolation multiples that can meet the IFFT transformation length, that is, the interpolation multiples 8*2 k Perform data interpolation and extract the interpolation results to obtain the theoretically required interpolation multiples. For oscilloscope interpolation multiples of 5, 10, 20, 40, and 80, the actual interpolation multiples are 8, 16, 32, 64, and 128.

[0039] Step S4: Select the intermediate data for splicing in overlapping frame mode and perform 5 / 8 sampling

[0040] First, the interpolation result y(n) / y0(n) after the IFFT transformation module of the master / slave path completes the IFFT transformation is synchronized. Then, if the oscilloscope interpolation multiple L corresponding to the oscilloscope fast time base gear is 2, the splicing module selects the middle N / 2×L data of the interpolation result y(n) and the middle N / 2×L data of the interpolation result y0(n) to splice and obtain the final interpolation result yL(n); if the oscilloscope interpolation multiple L corresponding to the oscilloscope fast time base gear is 2 of 5, the splicing module selects the middle N / 2×L data of the interpolation result y(n) and the middle N / 2×L data of the interpolation result y0(n) to ...). k When k = 0, 1, 2, ..., the splicing module selects the middle N / 2×L×8 / 5 data of the interpolation result y(n) and the middle N / 2×L×8 / 5 data of the interpolation result y0(n) for splicing to obtain the splicing result y L×8 / 5 (n) and sent to the 5 / 8 sampling module, which splices the result y L×8 / 5 (n) Use sliding average to extract points: For every 8 data, with a sliding window size of 4, take the sum and average of every 4 selected points as the extraction result, so that 5 extraction results are obtained. All the extraction results are combined in sequence to obtain the final interpolation result y L (n).

[0041] The actual interpolation multiples are 8, 16, 32, 64, and 128. Therefore, the interpolation results need to be processed by 5 / 8, 10 / 16, 20 / 32, 40 / 64, 80 / 128, etc., respectively. By simplifying the decimation multiples to 5 / 8, in order to fully consider the information of each sampling data point, the present invention will process the interpolated data points in a manner similar to sliding average, and sum and average every 4 points as the decimation result. 8 data points produce exactly 5 results, thereby realizing 5 / 8 decimation. This scheme fully considers the data information of each point. The data processing implementation diagram is shown in FIG. Figure 1 shown.

[0042] from Figure 1 It can be seen that for the sample data x n+0 ~x n+3 The sum and average result is taken as the first sampling result y n+0 , sample data x n+1 ~x n+4 The same process is performed to produce the second sampling result y n+1 , similarly x n+2 ~x n+5 Corresponding to y n+2 , x n+3 ~x n+6 Corresponding to y n+3 , x n+4 ~x n+7 Corresponding to y n+4 .

[0043] Since the number of sampling points N for each Fourier transform is always certain, the waveform depicted by this number of points N is not an integer multiple of the period length of the measured periodic signal in most cases. From the FFT transform theory, it can be known that the Fourier transform result of N points with non-positive period truncation will have spectrum leakage. At this time, the reconstructed data after Fourier interpolation will have certain errors, and its errors show the characteristics of larger errors at both ends of the data and smaller errors in the middle. Based on the characteristics of the error position of the interpolation result, the middle part of the data with smaller errors is retained, and the data at both ends with larger errors are spliced. That is, the "overlapping frame" method can effectively reduce the error impact caused by spectrum leakage. Taking 64 sampling points and 40 times interpolation as an example, the "overlapping frame" hardware design diagram is shown as follows Figure 3 shown.

[0044] When the interpolation is 40 times, the 64-point FFT transform of the nth frame can be divided into x n+0 ~x n+15 、x n+16 ~x n+47 、x n+48 ~x n+63 3 parts, from the simulation results we can know that x n+16 ~x n+47 The interpolation result error corresponding to the data point is small. The present invention realizes "overlapping frames" through the master / slave path method. The basic idea is as follows: the master path starts working first, and the slave path starts 32 beats after the master path data starts. The two paths start from the sampling sequence x 32 Start synchronous interpolation processing. The nth frame data of the main path interpolation operation is x n+0 ~x n+63 , the nth frame data for interpolation from the path is x n+32 ~x n+95 , the overlapping part of the two frames of data is x n+32 ~x n+79 From the error characteristics, we can know that the nth frame data x n+48 ~x n+63 The corresponding interpolation result and the n+1 frame data x n+63 ~x n+79 The corresponding interpolation result is the part with larger error, and this part of the data happens to be the area with smaller error in the slave path. Therefore, the parts with smaller error in the master / slave path interpolation results are alternately spliced, and the remaining data points are directly discarded to achieve effective reconstruction of the interpolation data and reduce data errors caused by spectrum leakage.

[0045] Figure 4 The invention is a hardware design structure block diagram of the Fourier interpolation method applicable to the fast time base gear of the oscilloscope.

[0046] In this embodiment, the sampled data stream x(n) will be sent to the master and slave paths for data processing under the UI_LCK clock. When the master path receives N / 2 valid data, the slave path starts to process data synchronously with the master path. After the master / slave path completes the FFT transformation of a frame of data, the transformed frequency domain data X(jω) / X0(jω) is written into the cache FIFO within N clock cycles and waits for zero filling. In the frequency domain zero filling module, the cache FIFO read enable is reasonably controlled, and the interpolation multiple is 8*2. k The high-frequency part is padded with zeros and the zero-padded result V(jω) / V0(jω) is sent to the IFFT transformation module; the interpolation results after the master / slave path completes the IFFT transformation will be sent to MUX FIFO1 / MUXFIFO2 for data synchronization respectively, and the splicing module will complete the data splicing by alternately selecting the area with smaller y(n) / y0(n) data error and send the splicing result to the 5 / 8 sampling module synchronously; in the sampling module, the decimal sampling is completed based on the "sliding average" method to obtain the final interpolation result.

[0047] The ILA logic analyzer that comes with the vivado software is used to capture, verify and analyze the signals involved in the Fourier interpolation module data processing. Taking 40x interpolation as an example, a 1GHz sine wave is input through the signal source. At this time, the ADC sampling rate is 12.5GSPS. The entire interpolation module performs 40x Fourier interpolation related data processing at a 200MHz clock cycle. The waveform data and related parameters before interpolation are as follows: Figure 5 shown.

[0048] from Figure 5It can be seen that there are 10 clock cycles (clk_ddr3) within 1400ns-1450ns, and each clock cycle is 5ns, that is, 200MHz. fft_data_in is the data waveform before interpolation, and its data transmission time for one cycle is 62ns. When the fft_data_in data is valid (fft_data_in=1), the data fft_data_in before interpolation and the clock clk_ddr3 are in a one-to-one correspondence. It can be calculated that there are about 12.4 sampling points (62 / 5) in one waveform cycle, which is consistent with expectations. The variable fft_data_out_abs represents the spectrum of the data before interpolation, and the variable fft_data_out_x_index represents its spectrum coordinates. It can be seen from the figure that its spectrum is symmetrical. The highest point represents its DC component, and the spectrum coordinates of the second highest point (fft_data_out_x_index) are 6. Since the variable fft_data_out_abs is a reg type value after processing and calculation under the clk_ddr3 clock, the coordinate value represented by fft_data_out_abs in the spectrum coordinates should be one beat ahead, that is, the actual coordinate value of the second highest point spectrum is 5 at this time. It can be calculated that the frequency point represented by the current second highest point is 1GHz, which is consistent with the frequency of the signal source input signal.

[0049] In addition to FFT transformation of interpolated data, the Fourier interpolation process also includes frequency domain zero padding, IFFT transformation, master-slave path data splicing, sliding average sampling and other data processing processes. The results of other related data processing of 40 times Fourier interpolation are as follows Figure 6 shown.

[0050] Figure 6In the figure, the variables ifft_real_data / o_ifft_real_data represent the time domain interpolation results after IFFT transformation of the master / slave path respectively, and ifft_data_out_tlast / o_ifft_data_out_tlast represent the IFFT transformation signals of one frame of data of the master and slave paths respectively. When the signal is pulled high, it means that the transformation of one frame of data is completed. It can be seen from the figure that under the working clock of 200MHz, the transmission time of one cycle of ifft_real_data / o_ifft_real_data is 4000ns, and the transmission time of one cycle of waveform before interpolation is 62ns. The difference between the two is about 64 times, that is, the interpolation multiple is about 64 times, which is consistent with expectations. In addition, it can be seen from the above figure that there is obvious distortion and discontinuity between the data frames and frames after ifft_real_data / o_ifft_real_data interpolation. This phenomenon is caused by spectrum leakage caused by non-periodic truncation through the analysis of the above chapters. The present invention processes data by master / slave path data splicing, i.e., "overlapping frames". ifft_overlap_data represents the interpolated waveform data after overlapping frame processing. It can be seen from the above figure that the data error caused by spectrum leakage is significantly improved, and the waveform is smooth and delicate as a whole. Since the FFT / IFFT IP core can only process data with a transformation length of 2M (i.e., the interpolation multiple is 64 times at this time), the present invention designs 5 / 8 sampling points to achieve the conversion of interpolation multiples by sliding average. data_after_div represents the interpolated waveform data of ifft_overlap_data after the 5 / 8 sampling module. Under the 200MHz clock, the transmission time of one cycle waveform data of ifft_overlap_data is about 2500ns. Compared with the data before interpolation, the difference between the two is about 40 times, and the result is almost the same as expected.

[0051] The ILA waveform capture results show that the 40-fold Fourier interpolation reconstructed waveform is smooth and delicate overall, and the parameters are almost the same as expected, indicating that the hardware logic function design of the Fourier interpolation module is correct. The present invention is based on the logic design of the relevant data processing of the FPGA design model xcku040. The vivado comprehensive report shows that the hardware resource consumption of the entire interpolation module is shown in Table 1.

[0052]

[0053]

[0054] Table 1

[0055] The FFT / IFFT transformation in the present invention is a data processing based on the Radix-2 butterfly operation mode. Each Radix-2 butterfly operation unit consumes only two multipliers and one adder. One multiplier consumes one DSP unit. The adder is implemented through the LUT lookup table. The master-slave path contains two sets of FFT / IFFT transformations in total. Therefore, the entire interpolation module consumes 8 multipliers, that is, 8 DSPs. Figure 6 It can be seen from the table that it accounts for 0.42% of the entire DSP resources, and the remaining hardware resource consumption can also be seen from Table 1 that only a small part of the resources are used.

[0056] Although the above describes the illustrative specific embodiments of the present invention to facilitate those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations using the concept of the present invention are protected.

Claims

1. A Fourier interpolation method suitable for fast time base gear of oscilloscope, characterized in that: The following steps are involved: (1) The sampled data stream x(n) is sent to the master and slave paths respectively. When the master path receives N / 2 valid data, the slave path starts to perform FFT transformation synchronously with the master path. (2) After the master / slave path completes the FFT transformation of a frame of sampled data, i.e., N sampled data, the frequency domain data X(jω) / X0(jω) is obtained and written into the corresponding cache FIFO; (3) The frequency domain zero-filling modules of the master / slave paths respectively control the read enable of their respective cache FIFOs reasonably, fill the high frequency part with zeros, and send the zero-filling result V(jω) / V0(jω) to the corresponding IFFT transformation modules respectively. If the oscilloscope interpolation multiple L corresponding to the fast time base gear of the oscilloscope is 2, the high frequency part is filled with zeros according to the interpolation multiple 2. If the oscilloscope interpolation multiple L corresponding to the fast time base gear of the oscilloscope is 5 / 2 k Multiple, k = 0, 1, 2, ..., then the interpolation multiple is 8*2 k The high frequency part is filled with zero, where the oscilloscope interpolation factor L = F x / F s , F x To display the sampling rate, F s is the ADC real-time sampling rate F s ; (4) First, the interpolation result y(n) / y0(n) after the IFFT transformation module of the master / slave path completes the IFFT transformation is synchronized. Then, if the oscilloscope interpolation multiple L corresponding to the oscilloscope fast time base gear is 2, the splicing module selects the middle N / 2×L data of the interpolation result y(n) and the middle N / 2×L data of the interpolation result y0(n) for splicing to obtain the final interpolation result y L (n); If the interpolation factor L of the oscilloscope corresponding to the fast time base gear of the oscilloscope is 2 of 5 k When k = 0, 1, 2, ..., the splicing module selects the middle N / 2×L×8 / 5 data of the interpolation result y(n) and the middle N / 2×L×8 / 5 data of the interpolation result y0(n) for splicing to obtain the splicing result y L×8 / 5 (n) and sent to the 5 / 8 sampling module, which splices the result y L×8 / 5 (n) Use sliding average to extract points: For every 8 data, with a sliding window size of 4, take the sum and average of every 4 selected points as the extraction result, so that 5 extraction results are obtained. All the extraction results are combined in sequence to obtain the final interpolation result y L (n).

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