A wideband high-speed digital frequency hopping system and method based on direct frequency generation

Abstract

The application discloses a kind of wideband high-speed digital frequency hopping system and method based on direct frequency generation.The system includes FPGA, digital-analog converter and clock chip, wherein the FPGA has differential high-speed serial interface, is configured as JESD204B high-speed interface;The digital-analog converter captures entire spectrum at a time, built-in DDC digital frequency conversion and FIR filter, support up to 6GHz radio frequency frequency direct generation;The clock chip generates two-way 256MHz differential LVDS clock, and the working clock of FPGA and digital-analog converter is all used 256MHz clock.The method includes baseband IQ signal generation, baseband IQ signal interpolation filtering, odd-even sequence splitting, odd-even sequence digital frequency conversion, odd-even sequence merging sending, digital up-conversion and radio frequency output these steps.The application has high reliability, low cost, small volume, low power consumption, and has excellent anti-interference performance.

Description

Technical Field

[0001] This invention relates to the field of broadband high-speed digital frequency hopping application technology, and in particular to a broadband high-speed digital frequency hopping system and method based on direct frequency generation. Background Technology

[0002] Military communications typically require systems to possess anti-jamming capabilities, with frequency hopping being a commonly used anti-jamming technique. For tracking jamming, a higher frequency hopping rate makes tracking jamming more difficult; for blocking jamming, a wider frequency hopping bandwidth makes blocking jamming more difficult. Therefore, the anti-jamming capability indicators for frequency hopping communication systems are primarily frequency hopping bandwidth and frequency hopping rate. In the L-band, the frequency hopping frequency range covers the entire operating frequency band up to several hundred megahertz, with frequency hopping rates reaching tens of thousands of hops per second.

[0003] Traditional frequency hopping typically employs a fixed intermediate frequency (IF) plus analog frequency conversion. The frequency generated by the control frequency synthesizer rapidly changes, and then is analog-mixed with the IF to achieve high-speed frequency hopping excitation output. Hardware implementation generally requires two modules: a data baseband board and a channel board. In the data baseband board, an FPGA generates a fixed low-IF digital signal, which is then converted to an analog signal with the fixed IF via a DAC. In the channel board, the IF signal output from the data baseband board is analog-up-converted according to the current frequency hopping frequency, realizing the conversion from IF to RF excitation. The local oscillator signal of the mixer in the channel board is typically designed using a DDS+PLL configuration. Because high-speed frequency hopping rates can reach tens of thousands of hops per second, with each hop dwell time only around tens of microseconds, the required frequency switching time is only a few microseconds. However, the frequency lock time of DDS+PLL is relatively long, making it impossible to complete the frequency switching and locking within a few microseconds. Therefore, in order to meet the requirements of fast frequency switching of frequency hopping, the channel board usually adopts a dual DDS+PLL ping-pong fast switching design, in which the two DDS+PLLs work in turn, increasing the frequency switching time of the DDS+PLL, thereby realizing high-speed frequency switching of frequency hopping.

[0004] Using a fixed intermediate frequency plus analog frequency conversion method is more complex in terms of hardware circuit design. The design needs to consider frequency generation, signal isolation, frequency switching, and filtering after signal mixing by dual DDS+PLL. The hardware implementation is difficult and costly, and it will also lead to an increase in the size, weight and power consumption of the communication equipment. Summary of the Invention

[0005] The purpose of this invention is to provide a broadband high-speed digital frequency hopping system and method based on direct frequency generation that is highly reliable, low-cost, small in size, low in power consumption, and has excellent anti-interference performance.

[0006] The technical solution to achieve the purpose of this invention is: a broadband high-speed digital frequency hopping system based on direct frequency generation, which includes an FPGA, a digital-to-analog converter, and a clock chip, wherein:

[0007] The FPGA has a differential high-speed serial interface, configured as a JESD204B high-speed interface.

[0008] The digital-to-analog converter captures the entire spectrum at once, with built-in DDC digital frequency conversion and FIR filter, supporting direct generation of radio frequency up to 6GHz.

[0009] The clock chip generates two 256MHz differential LVDS clocks, and the FPGA and digital-to-analog converter both use a 256MHz clock.

[0010] The FPGA generates a wideband digital frequency hopping signal via software. Using a 256MHz operating clock generated by a clock chip, it generates a 512MHz ultra-wideband IQ data signal by interpolating and filtering a 256MHz baseband IQ data stream through FIR interpolation. The data is then split into odd and even sequences and digitally converted to generate ultra-wideband frequency hopping data with varying rates. Data transmission between the FPGA and the digital-to-analog converter uses a JESD204B high-speed interface, with four pairs of differential LANEs in hardware, each pair having a data rate of 5.12Gbps, transmitting the ultra-wideband frequency hopping data generated by the FPGA to the digital-to-analog converter in real time.

[0011] Furthermore, the FPGA is based on Intel's Stratix 5 series FPGA, and the digital-to-analog converter is Analog Devices' AD9172 broadband RF digital-to-analog converter chip.

[0012] A broadband high-speed digital frequency hopping method based on direct frequency generation is proposed. This method employs the aforementioned broadband high-speed digital frequency hopping system based on direct frequency generation. The method is designed for broadband high-speed digital frequency hopping in the L-band from 1 GHz to 2 GHz, and supports a maximum frequency hopping bandwidth of 512 MHz. The parameters are defined as follows:

[0013] Operating frequency band: f Low ~f High ;

[0014] Frequency bandwidth: f High -f Low ≤512MHz;

[0015] Frequency hopping operating frequency F H :F H ∈[f Low ,f High ];

[0016] DAC digital upconversion frequency f NCO :

[0017] FPGA digital frequency hopping frequency f Hop :f Hop =F H -f NCO f Hop ∈[f Low -f NCO ,f High -f NCO ];

[0018] The specific steps are as follows:

[0019] Step 1: Baseband IQ signal generation: The data frame to be transmitted is first encoded and modulated in the FPGA according to the waveform design, and then the modulated data is split into multiple frequency hopping pulse baseband IQ data according to the frequency hopping pattern;

[0020] Step 2, Baseband IQ signal interpolation and filtering: The baseband IQ data is interpolated and filtered to increase the data rate to 512MHz;

[0021] Step 3, Odd / Even Sequence Splitting: Split the baseband IQ data into odd and even sequences and perform digital frequency conversion on each;

[0022] Step 4, Odd / Even Sequence Digital Frequency Conversion: Based on the current frequency hopping operating frequency F H The digital frequency hopping frequency f of the current frequency hopping pulse is obtained. Hop The odd and even baseband IQ data sequences are digitally frequency converted to obtain odd and even sequence digital frequency hopping data.

[0023] Step 5, Odd-Even Sequence Merging and Transmission: Merge the odd-even sequence IQ data after digital frequency conversion. The merged digital frequency hopping data rate is 512MHz. Use the JESD204B interface IP core inside the FPGA to send the digital frequency hopping data to the digital-to-analog converter.

[0024] Step 6: Digital up-conversion and RF output: The digital-to-analog converter receives digital frequency hopping data sent by the FPGA through the JESD204B interface, performs digital up-conversion and filtering inside the chip, and after filtering and digital-to-analog conversion, the up-converted data is directly output as a high-speed analog frequency hopping signal through the RF interface.

[0025] Furthermore, in step 1, the baseband IQ data rate is 256MHz, and the IQ data bit width is 16bit respectively.

[0026] Furthermore, in step 2, the FIR IP core inside the FPGA is used, with the interpolation coefficient set to 2, to perform a 2x interpolation filter on the baseband IQ data, changing the baseband IQ data rate to 512MHz. This enables the input of one pair of baseband IQ data per FPGA working clock cycle, and after FIR interpolation filtering, the output of two pairs of baseband IQ data per FPGA working clock cycle.

[0027] Furthermore, in step 3, the rate of the split odd-even data sequence is reduced to 256MHz.

[0028] Furthermore, in step 4, the transmitted data frame contains multiple frequency hopping pulses, and the frequency hopping operating frequency covers the entire frequency bandwidth. The algorithm for digital frequency conversion of the odd and even baseband IQ data sequences is as follows:

[0029] Let the filtered baseband IQ sequence be x(n), and the data rate be f. S =512MHz, digital frequency hopping frequency is f Hop If the frequency-hopping IQ data sequence after digital frequency conversion is y(n), then:

[0030]

[0031] In the FPGA, the baseband IQ data is split into odd and even sequences, and digital frequency conversion is performed on each sequence to obtain the frequency-converted data of the odd and even sequences. Then:

[0032] Even sequence frequency conversion data:

[0033]

[0034] Odd sequence frequency conversion data:

[0035]

[0036] From the odd-even sequence frequency conversion formula above, the sampling rate of the data after splitting becomes f. S / 2, changing from 512MHz to 256MHz, directly using a 256MHz operating clock for digital frequency conversion in the FPGA;

[0037] Design digital frequency converters (NCOs) for odd and even sequences in the FPGA, with the NCO's frequency conversion frequency being f. Hop Furthermore, the digital frequency conversion NCO of the odd-even sequence has a fixed phase difference f. Hop / f S The phase difference and the current digital frequency f Hop Related.

[0038] Furthermore, in step 5, the bit width of the digital frequency hopping IQ data is 16 bits, and the total bit width is 32 bits. The data is transmitted after 8B / 10B encoding in the IP core. The total bandwidth BW of JESD204B data transmission is:

[0039] BW=512MHz×32bit×10 / 8=20.48Gbps

[0040] The JESD204B interface between the FPGA and the digital-to-analog converter in the hardware circuit uses four parallel LANEs, each with a transmission rate of 5.12Gbps.

[0041] Furthermore, in step 6, a fixed frequency f is used for digital up-conversion. NCO .

[0042] Furthermore, in step 6, the frequency F of the up-converted frequency hopping data... H for:

[0043] F H =f Hop +f NCO

[0044] Compared with the prior art, the significant advantages of this invention are: (1) The communication equipment using this invention uses baseband digital frequency hopping instead of the traditional local oscillator analog frequency hopping design; (2) The baseband signal generation, digital NCO, digital up-conversion, frequency hopping control and other functions are realized in the FPGA and DAC through software development and configuration; (3) The RF excitation signal is directly generated by the DAC, and the entire frequency hopping excitation output function is realized in a baseband board. The hardware design eliminates the complex RF circuits such as frequency synthesizer, analog amplification, mixing and filtering, and the circuit design is greatly simplified; (4) The reliability is improved, the cost is greatly reduced, the equipment size is reduced, the weight is reduced, the power consumption is reduced, and the anti-interference performance is better. Attached Figure Description

[0045] Figure 1 This is a hardware platform design block diagram.

[0046] Figure 2 This is a block diagram of a broadband digital frequency hopping design.

[0047] Figure 3 This is a schematic diagram of the spectrum transformation of a 1300MHz pulse. Detailed Implementation

[0048] This invention relates to a broadband high-speed digital frequency hopping system based on direct frequency generation. The system includes an FPGA, a digital-to-analog converter, and a clock chip, wherein:

[0049] The FPGA has a differential high-speed serial interface, configured as a JESD204B high-speed interface.

[0050] The digital-to-analog converter captures the entire spectrum at once, with built-in DDC digital frequency conversion and FIR filter, supporting the direct generation of radio frequency up to 6GHz.

[0051] The clock chip generates two 256MHz differential LVDS clocks, and the FPGA and digital-to-analog converter both use a 256MHz clock.

[0052] The FPGA generates a wideband digital frequency hopping signal via software. Using a 256MHz operating clock generated by a clock chip, it generates a 512MHz ultra-wideband IQ data signal by interpolating and filtering a 256MHz baseband IQ data stream through FIR interpolation. The data is then split into odd and even sequences and digitally converted to generate ultra-wideband frequency hopping data with varying rates. Data transmission between the FPGA and the digital-to-analog converter uses a JESD204B high-speed interface, with four pairs of differential LANEs in hardware, each pair having a data rate of 5.12Gbps, transmitting the ultra-wideband frequency hopping data generated by the FPGA to the digital-to-analog converter in real time.

[0053] As a specific example, the FPGA is based on Intel's Stratix 5 series FPGA, and the digital-to-analog converter is Analog Devices' AD9172 broadband RF digital-to-analog converter chip.

[0054] This invention also relates to a broadband high-speed digital frequency hopping method based on direct frequency generation, employing the aforementioned broadband high-speed digital frequency hopping system based on direct frequency generation. The method is for broadband high-speed digital frequency hopping in the L-band from 1 GHz to 2 GHz, supporting a maximum frequency hopping bandwidth of 512 MHz. The parameters are defined as follows:

[0055] Operating frequency band: f Low ~f High ;

[0056] Frequency bandwidth: f High -f Low ≤512MHz;

[0057] Frequency hopping operating frequency F H :F H ∈[f Low ,f High ];

[0058] DAC digital upconversion frequency f NCO :

[0059] FPGA digital frequency hopping frequency fHop :f Hop =F H -f NCO f Hop ∈[f Low -f NCO ,f High -f NCO ];

[0060] The specific steps are as follows:

[0061] Step 1: Baseband IQ signal generation: The data frame to be transmitted is first encoded and modulated in the FPGA according to the waveform design, and then the modulated data is split into multiple frequency hopping pulse baseband IQ data according to the frequency hopping pattern;

[0062] Step 2, Baseband IQ signal interpolation and filtering: The baseband IQ data is interpolated and filtered to increase the data rate to 512MHz;

[0063] Step 3, Odd / Even Sequence Splitting: Split the baseband IQ data into odd and even sequences and perform digital frequency conversion on each;

[0064] Step 4, Odd / Even Sequence Digital Frequency Conversion: Based on the current frequency hopping operating frequency F H The digital frequency hopping frequency f of the current frequency hopping pulse is obtained. Hop The odd and even baseband IQ data sequences are digitally frequency converted to obtain odd and even sequence digital frequency hopping data.

[0065] Step 5, Odd-Even Sequence Merging and Transmission: Merge the odd-even sequence IQ data after digital frequency conversion. The merged digital frequency hopping data rate is 512MHz. Use the JESD204B interface IP core inside the FPGA to send the digital frequency hopping data to the digital-to-analog converter.

[0066] Step 6: Digital up-conversion and RF output: The digital-to-analog converter receives digital frequency hopping data sent by the FPGA through the JESD204B interface, performs digital up-conversion and filtering inside the chip, and after filtering and digital-to-analog conversion, the up-converted data is directly output as a high-speed analog frequency hopping signal through the RF interface.

[0067] As a specific example, in step 1, the baseband IQ data rate is 256MHz, and the IQ data bit width is 16bit respectively.

[0068] As a specific example, in step 2, the FIR IP core inside the FPGA is used, with the interpolation coefficient set to 2, to perform a 2x interpolation filter on the baseband IQ data, changing the baseband IQ data rate to 512MHz. This enables the input of one pair of baseband IQ data per FPGA working clock cycle, and after FIR interpolation filtering, the output of two pairs of baseband IQ data per FPGA working clock cycle.

[0069] As a specific example, in step 3, the rate of the split odd-even data sequence is reduced to 256MHz.

[0070] As a specific example, in step 4, the transmitted data frame contains multiple frequency hopping pulses, and the frequency hopping operating frequency covers the entire frequency bandwidth. The algorithm for digital frequency conversion of the odd and even baseband IQ data sequences is as follows:

[0071] Let the filtered baseband IQ sequence be x(n), and the data rate be f. S =512MHz, digital frequency hopping frequency is f Hop If the frequency-hopping IQ data sequence after digital frequency conversion is y(n), then:

[0072]

[0073] In the FPGA, the baseband IQ data is split into odd and even sequences, and digital frequency conversion is performed on each sequence to obtain the frequency-converted data of the odd and even sequences. Then:

[0074] Even sequence frequency conversion data:

[0075]

[0076] Odd sequence frequency conversion data:

[0077]

[0078] From the odd-even sequence frequency conversion formula above, the sampling rate of the data after splitting becomes f. S / 2, changing from 512MHz to 256MHz, directly using a 256MHz operating clock for digital frequency conversion in the FPGA;

[0079] Design digital frequency converters (NCOs) for odd and even sequences in the FPGA, with the NCO's frequency conversion frequency being f. Hop Furthermore, the digital frequency conversion NCO of the odd-even sequence has a fixed phase difference f. Hop / f S The phase difference and the current digital frequency f Hop Related.

[0080] As a specific example, in step 5, the bit width of the digital frequency hopping IQ data is 16 bits, and the total bit width is 32 bits. The data is transmitted after 8B / 10B encoding in the IP core. The total bandwidth BW of JESD204B data transmission is:

[0081] BW=512MHz×32bit×10 / 8=20.48Gbps

[0082] The JESD204B interface between the FPGA and the digital-to-analog converter in the hardware circuit uses four parallel LANEs, each with a transmission rate of 5.12Gbps.

[0083] As a specific example, in step 6, digital upconversion is performed using a fixed frequency f. NCO .

[0084] As a specific example, in step 6, the frequency F of the up-converted frequency hopping data... H for:

[0085] F H =f Hop +f NCO

[0086] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0087] Example

[0088] This embodiment is based on a broadband high-speed digital frequency hopping system generated by direct frequency. It uses FPGA and high-speed DAC chips to design the circuit and realizes high-speed broadband digital frequency hopping output in a digital baseband board. Unlike the traditional local oscillator frequency hopping, the frequency hopping method is baseband digital frequency hopping, digital up-conversion, and then the DAC chip directly outputs the radio frequency hopping excitation signal.

[0089] The broadband high-speed digital frequency hopping implementation method in this embodiment is to transmit the broadband frequency hopping data signal generated by the FPGA to a high sampling rate digital-to-analog converter through the JESD204B high-speed serial interface. After digital up-conversion, a fast-hopping radio frequency signal is directly generated.

[0090] This embodiment uses FPGA software to implement ultra-wideband digital frequency hopping signals. Using a 256MHz operating clock, a 256MHz baseband IQ data signal is generated by FIR interpolation filtering to produce an ultra-wideband IQ data signal with a rate of 512MHz. The data is then split into odd and even sequences, and digital frequency conversion is performed on each sequence to generate ultra-wideband frequency hopping data with rate hopping.

[0091] 1) Hardware circuit design

[0092] Combination Figure 1 The hardware is based on Intel's Stratix 5 series FPGA, Analog Devices' AD9172 broadband RF digital-to-analog converter chip, and a clock chip. The FPGA has a differential high-speed serial interface that can be configured as a JESD204B high-speed interface; the AD9172 digital-to-analog converter has a high sampling rate, can capture the entire spectrum at once, and has built-in DDC digital frequency conversion and FIR filters, supporting direct generation of RF frequencies up to 6GHz.

[0093] The clock chip generates two 256MHz differential LVDS clocks. Both the FPGA and AD9172 use 256MHz clocks for operation. Data transmission between the FPGA and AD9172 uses the JESD204B high-speed interface. The hardware design employs four pairs of differential LANEs, each with a data rate of 5.12Gbps, to transmit the high-speed broadband digital frequency hopping signal generated by the FPGA to the AD9172 in real time.

[0094] 2) Software Design

[0095] This invention primarily targets the implementation of broadband high-speed digital frequency hopping in the L-band (1GHz~2GHz), featuring high hopping rate, wide hopping bandwidth, and supporting a maximum hopping frequency bandwidth of 512MHz. The main parameters are defined as follows:

[0096] Operating frequency band: f Low ~f High ;

[0097] Frequency bandwidth: f High -f Low ≤512MHz;

[0098] Frequency hopping operating frequency F H :F H ∈[f Low ,f High ];

[0099] DAC digital upconversion frequency f NCO :

[0100] FPGA digital frequency hopping frequency f Hop :f Hop =F H -f NCO f Hop ∈[f Low -f NCO ,f High -f NCO ].

[0101] Combination Figure 2 The software implementation steps are as follows:

[0102] ① Baseband IQ signal generation

[0103] In the FPGA, the transmitted data frame is first encoded and modulated according to the waveform design. Then, according to the frequency hopping pattern, the modulated data is split into multiple frequency hopping pulse baseband IQ data. The baseband IQ data rate is 256MHz and the IQ data bit width is 16bit.

[0104] ② Baseband IQ signal interpolation filtering

[0105] Frequency hopping communication supports a maximum operating frequency bandwidth of 512MHz, while the baseband IQ data rate is 256MHz. This data rate is less than the frequency hopping operating bandwidth, making direct digital frequency hopping impossible. Therefore, the baseband IQ data must first undergo interpolation filtering to increase the data rate to 512MHz.

[0106] Using the FPGA's internal FIR IP core, with an interpolation factor set to 2, the baseband IQ data is interpolated and filtered by a factor of 2, reducing the baseband IQ data rate to 512MHz. This allows for the input of one pair of baseband IQ data per FPGA clock cycle, followed by FIR interpolation filtering, resulting in the output of two pairs of baseband IQ data per FPGA clock cycle.

[0107] ③ Parity Sequence Decomposition

[0108] After FIR interpolation filtering, the baseband IQ data rate becomes 512MHz, while the FPGA's operating clock is 256MHz, making it impossible to directly digitally convert the 512MHz baseband IQ data. Therefore, the baseband IQ data needs to be split into odd and even sequences for separate digital conversion, reducing the data rate of the split odd and even sequences to 256MHz.

[0109] ④ Odd-even sequence digital frequency conversion

[0110] The transmitted data frame contains multiple frequency-hopping pulses, and the frequency hopping operation covers the entire frequency bandwidth. Based on the current frequency hopping frequency F... H The digital frequency hopping frequency f of the frequency hopping pulse is obtained. Hop The odd and even baseband IQ data sequences are digitally frequency converted separately to obtain odd and even sequence digital frequency hopping data. The algorithm is as follows:

[0111] Let the filtered baseband IQ sequence be x(n), and the data rate be f. S =512MHz, digital frequency hopping frequency is f Hop If the frequency-hopping IQ data sequence after digital frequency conversion is y(n), then:

[0112]

[0113] In the FPGA, the baseband IQ data is split into odd and even sequences, and digital frequency conversion is performed on each sequence to obtain the frequency-converted data of the odd and even sequences. Then:

[0114] Even sequence frequency conversion data:

[0115]

[0116] Odd sequence frequency conversion data:

[0117]

[0118] From the odd-even sequence frequency conversion formula above, we can see that after the data is split, the sampling rate of the data becomes f. S / 2, changing from 512MHz to 256MHz, can be directly digitally converted using a 256MHz operating clock in the FPGA. Digital frequency converters (NCOs) with odd and even sequences are designed in the FPGA, with the NCO's conversion frequency being f. Hop Furthermore, the digital frequency conversion NCO of the odd-even sequence has a fixed phase difference f. Hop / f S The phase difference and the current digital frequency f Hop Related.

[0119] ⑤ Parity sequence merging and transmission

[0120] The odd-even sequence IQ data after digital frequency conversion are combined, and the combined digital frequency-hopping data rate reaches 512MHz. The digital frequency-hopping data is sent to the AD9172 chip using the JESD204B interface IP core inside the FPGA.

[0121] The digital frequency-hopping IQ data has a bit width of 16 bits each, for a total bit width of 32 bits. The data is transmitted after 8B / 10B encoding in the IP core. The total bandwidth (BW) for JESD204B data transmission is:

[0122] BW=512MHz×32bit×10 / 8=20.48Gbps.

[0123] In terms of hardware circuitry, the JESD204B interface line between the FPGA and AD9172 uses four parallel LANEs, with each LANE having a transmission rate of 5.12Gbps.

[0124] ⑥ Digital upconversion and RF output

[0125] The AD9172 receives digital frequency-hopping data from the FPGA via the JESD204B interface, performs digital up-conversion and filtering internally, and uses a fixed frequency f for up-conversion. NCO After up-conversion, the data is filtered and converted from digital to analog, and then directly output as a high-speed analog frequency-hopping signal via the RF interface.

[0126] 3) Application Examples

[0127] To make the technical problem to be solved by this invention clearer, the invention will be described in detail below with reference to examples. It should be noted that the specific examples described herein are only for explaining the invention and are not intended to limit the invention.

[0128] In a certain type of data transmission equipment, a high-speed frequency hopping waveform design is adopted, with a frequency hopping operating frequency band of 1300MHz~1700MHz, a total frequency hopping bandwidth of 400MHz, a frequency hopping interval of 16MHz, and a frequency hopping rate of not less than 20000 hops / s.

[0129] We employ a broadband high-speed digital frequency hopping implementation method based on direct frequency generation to achieve excitation RF output with a working frequency band of 1300MHz to 1700MHz and a frequency hopping bandwidth of 400MHz. First, a high-speed frequency hopping digital waveform output with a bandwidth of -200MHz to 200MHz is implemented in the FPGA; then, the frequency hopping data waveform input to the FPGA is digitally up-converted in the AD9172 to achieve a full-bandwidth frequency hopping RF output of 1300MHz to 1700MHz.

[0130] The following explanation uses 1300MHz as an example to illustrate the specific implementation process; the implementation methods for other frequency hopping frequencies are the same.

[0131] Frequency hopping operating frequency: F H =1300MHz;

[0132] The digital inverter NCO frequency in AD9172:

[0133] The conversion frequency of digital frequency hopping in FPGA: f Hop =F H -f NCO =1300-1500=-200MHz.

[0134] The FPGA baseband IQ data rate is 256MHz, while the total frequency hopping bandwidth is 400MHz. First, interpolation filtering is performed on the baseband data to increase the data rate to 512MHz. Then, the filtered baseband IQ data is split into odd and even sequences, reducing the data rate of the split odd and even sequences to 256MHz.

[0135] The odd and even sequences are frequency-converted separately, and odd and even NCOs are designed separately in the FPGA. The NCO frequency is -200MHz, and the odd and even NCOs have a fixed phase difference. The digital NCO is designed using the CORDIC algorithm. The frequency control word M has a bit width of 32 bits. A lookup table method is used to accumulate the phase using the frequency control word to obtain the digital NCO frequency. The processing clock f of the digital NCO in the FPGA is... C It is 256MHz.

[0136] Even sequence frequency control word M:

[0137]

[0138] Based on the rotational properties of NCO, representing M using two's complement yields:

[0139] M=2 32 -0xC8000000 = 0x38000000

[0140] The frequency control word is the same for odd sequences and even sequences, M = 0x38000000, but after the NCO of odd sequences uses the frequency control word for phase accumulation, a fixed phase difference f needs to be added. Hop / f S Let the frequency word of this phase difference be N, then we can obtain:

[0141]

[0142] Based on the rotational properties of NCO, representing N using two's complement, we get:

[0143] N=2 32 -0x64000000 = 0x9C000000

[0144] The baseband IQ data of the odd and even sequences are mixed with the odd and even NCOs respectively to obtain the digital frequency hopping IQ data of the odd and even sequences. The digital frequency hopping data of the odd and even sequences are combined and sent to AD9172 through the JESD204B interface.

[0145] The AD9172 receives digital frequency hopping data from the FPGA and performs digital up-conversion on the data. The AD9172 chip is internally configured with f... NCO It is 1500MHz.

[0146] Combination Figure 3 The frequency of the frequency-hopping data after up-conversion is:

[0147] F H =f Hop +f NCO =-200+1500=1300MHz

[0148] After upconversion, the data is filtered and converted from digital to analog in the AD9172 before being directly output as an RF signal.

[0149] In summary, the communication device of this invention uses baseband wideband digital frequency hopping instead of the traditional local oscillator analog frequency hopping design. Baseband signal generation, digital NCO, digital up-conversion, and frequency hopping control are implemented through software development and configuration in the FPGA and DAC. The RF excitation signal is directly generated by the DAC, and the entire frequency hopping excitation output function is implemented on a single baseband board. The hardware design eliminates complex RF circuits such as frequency synthesizers, analog amplifiers, mixers, and filters, greatly simplifying the circuit design, improving reliability, significantly reducing cost, reducing device size, weight, and power consumption, and improving anti-interference performance.

Claims

1. A broadband high-speed digital frequency hopping method based on direct frequency generation, characterized in that, For L-band 1GHz~2GHz broadband high-speed digital frequency hopping, the maximum supported frequency hopping bandwidth is 512MHz, and the parameters are defined as follows: Operating frequency band: ; Frequency bandwidth: ; Frequency hopping operating frequency : ; DAC digital upconversion frequency : ; FPGA digital frequency hopping frequency : , ; The specific steps are as follows: Step 1: Baseband IQ signal generation: The data frame to be transmitted is first encoded and modulated in the FPGA according to the waveform design, and then the modulated data is split into multiple frequency hopping pulse baseband IQ data according to the frequency hopping pattern; Step 2, Baseband IQ signal interpolation and filtering: The baseband IQ data is interpolated and filtered to increase the data rate to 512MHz; Step 3, Odd / Even Sequence Splitting: Split the baseband IQ data into odd and even sequences and perform digital frequency conversion on each; Step 4, Odd / Even Sequence Digital Frequency Conversion: Based on the current frequency hopping operating frequency The digital frequency hopping frequency of the current frequency hopping pulse is obtained. The odd and even baseband IQ data sequences are digitally frequency converted to obtain odd and even sequence digital frequency hopping data. Step 5, Odd-Even Sequence Merging and Transmission: Merge the odd-even sequence IQ data after digital frequency conversion. The merged digital frequency hopping data rate is 512MHz. Use the JESD204B interface IP core inside the FPGA to send the digital frequency hopping data to the digital-to-analog converter. Step 6, Digital Up-conversion and RF Output: The digital-to-analog converter receives digital frequency hopping data sent by the FPGA through the JESD204B interface, performs digital up-conversion and filtering inside the chip, and after filtering and digital-to-analog conversion, the up-converted data is directly output as a high-speed analog frequency hopping signal through the RF interface. In step 4, the transmitted data frame contains multiple frequency hopping pulses, and the frequency hopping operating frequency covers the entire frequency bandwidth. The algorithm for digital frequency conversion of the odd and even baseband IQ data sequences is as follows: Let the filtered baseband IQ sequence be Data rate =512 MHz, digital frequency hopping frequency is The frequency-hopping IQ data sequence after digital frequency conversion is Then we have: Where N is the length of the IQ sequence; In the FPGA, the baseband IQ data is split into odd and even sequences, and digital frequency conversion is performed on each sequence to obtain the frequency-converted data of the odd and even sequences. Then: Even sequence frequency conversion data: Odd sequence frequency conversion data: From the odd-even sequence frequency conversion formula above, the sampling rate of the data after splitting becomes... / 2, changing from 512 MHz to 256 MHz, directly using a 256 MHz operating clock for digital frequency conversion in the FPGA; Design digital frequency converters (NCOs) for odd and even sequences in the FPGA. The frequency conversion frequency of the NCO is... Furthermore, the digital frequency conversion NCO of the odd-even sequence has a fixed phase difference. This phase difference and the current digital frequency conversion Related; In step 5, the bit width of the digital frequency hopping IQ data is 16 bits, with a total bit width of 32 bits. The data is transmitted after 8B / 10B encoding in the IP core, where B represents a byte. The total bandwidth BW of JESD204B data transmission is: BW = 512MHz×32bit×10 / 8 = 20.48 Gbps The JESD204B interface between the FPGA and the digital-to-analog converter in the hardware circuit uses four differential lines for parallel transmission, with each differential line having a transmission rate of 5.12Gbps.

2. The broadband high-speed digital frequency hopping method based on direct frequency generation according to claim 1, characterized in that, In step 1, the baseband IQ data rate is 256MHz, and the IQ data bit width is 16bit.

3. The broadband high-speed digital frequency hopping method based on direct frequency generation according to claim 1, characterized in that, In step 2, the FIR IP core inside the FPGA is used, with the interpolation coefficient set to 2, to perform a 2x interpolation filter on the baseband IQ data, changing the baseband IQ data rate to 512MHz. This enables the input of one pair of baseband IQ data per FPGA working clock cycle, and after FIR interpolation filtering, the output of two pairs of baseband IQ data per FPGA working clock cycle.

4. The broadband high-speed digital frequency hopping method based on direct frequency generation according to claim 1, characterized in that, In step 3, the rate of the split odd-even data sequence is reduced to 256 MHz.

5. The broadband high-speed digital frequency hopping method based on direct frequency generation according to claim 1, characterized in that, In step 6, a fixed frequency is used for digital up-conversion. .

6. The broadband high-speed digital frequency hopping method based on direct frequency generation according to claim 1, characterized in that, In step 6, the frequency of the up-converted frequency hopping data... for: 。 7. A broadband high-speed digital frequency hopping system based on direct frequency generation, characterized in that, This system is used to implement the broadband high-speed digital frequency hopping method according to any one of claims 1 to 6. The system includes an FPGA, a digital-to-analog converter, and a clock chip, wherein: The FPGA has a differential high-speed serial interface, configured as a JESD204B high-speed interface. The digital-to-analog converter captures the entire spectrum at once, with built-in DDC digital frequency conversion and FIR filter, supporting the direct generation of radio frequency up to 6GHz. The clock chip generates two 256MHz differential LVDS clocks, and the FPGA and digital-to-analog converter both use a 256MHz clock. The FPGA generates a wideband digital frequency hopping signal via software. Using a 256MHz operating clock generated by a clock chip, it generates a 512MHz ultra-wideband IQ data signal by interpolating and filtering a 256MHz baseband IQ data stream through FIR interpolation. The data is then split into odd and even sequences and digitally converted to generate ultra-wideband frequency hopping data with varying rates. Data transmission between the FPGA and the digital-to-analog converter uses a JESD204B high-speed interface, with four pairs of differential lines in hardware, each pair having a data rate of 5.12Gbps, transmitting the ultra-wideband frequency hopping data generated by the FPGA to the digital-to-analog converter in real time.

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