Subscriber station for a serial bus system and method for communication in a serial bus system

Abstract

A subscriber station (10; 30) for a serial bus system (1) and a method for communication in a serial bus system (1) are provided. The subscriber station (10; 30) has a communication control device (11; 31) for controlling communication of the subscriber station (10; 20; 30) with at least one further subscriber station (10; 20; 30) of the bus system (1) and for evaluating a signal (VDIFF) received from a bus (40) of the bus system (1), in which signal a bit time (t_bt1) in a first communication phase (451) can be different from a bit time (t_bt2) in a second communication phase (452), wherein the communication control device (11; 31) is designed to sample and evaluate the signal (VDIFF) received from the bus (40) on the basis of a transmission signal (TxD_TC) generated by a further subscriber station (10; 20; 30) in accordance with a predetermined frame (450; 450A).

Description

Technical Field

[0001] The present invention relates to a user station for a serial bus system and a method for communication in a serial bus system, the serial bus system operating with high data rates, high flexibility and high fault tolerance. Background Technology

[0002] For example, bus systems in vehicles used for communication between sensors and control devices are designed to handle large data volumes, depending on the number of functions of the technical system or vehicle. Here, it is typically required that data be transmitted from the sender to the receiver faster than before, and that large data packets can be transmitted when needed.

[0003] In the vehicle sector, the bus system is currently in the introduction phase. During this phase, data is transmitted as messages under the ISO 11898-1:2015 standard, which specifies the CAN protocol with CAN FD. These messages are transmitted between user stations within the bus system, such as sensors, control devices, transmitters, etc. For this purpose, messages are sent onto the bus in frames, switching between two communication phases within each frame. In the first communication phase (arbitration), it is negotiated which user station in the bus system is allowed to send its frame onto the bus in the subsequent second communication phase (data phase or transmission of valid data). In vehicles, CAN FD is initially used by most manufacturers at an arbitration bit rate of 500 kbit / s and a data bit rate of 2 Mbit / s. That is, during transmission on the bus, switching between slow and fast operating modes is required.

[0004] To achieve even higher data rates in the second communication phase, a successor bus system to CAN FD, called CAN XL, is currently under development and is being standardized by the CAN in Automation (CiA) organization. In addition to pure data transmission via the CAN bus, CAN XL is also designed to support other functions such as functional safety, data security, and Quality of Service (QoS). These are fundamental characteristics required in autonomous vehicles.

[0005] CAN XL is designed to support high bit rates during the data phase, such as up to 15 Mbit / s or even 20 Mbit / s. To achieve this, transmitting / receiving devices are used, and their operating modes can be switched to achieve the required high bit rates during the data phase. On the other hand, the bit rate during the arbitration phase is maintained at approximately 500 kbit / s to enable arbitration. To enable particularly high bit rates during the data phase, the transmitting / receiving devices currently standardized for CAN XL can switch their operating modes. To eliminate the need for additional connection points (pins) to signal the mode switching, a MICI module (Media Independent CAN Interface) is used between the communication control unit (especially its protocol controller) and the transmitting / receiving device.

[0006] In the case of CAN XL, the communication control unit, especially its protocol controller, signals to the transmitting / receiving unit that it wants to switch its operating mode from slow to fast or from fast to slow. For this signaling notification, the communication control unit, especially its protocol controller, or the downstream MICI module, uses encoding by means of pulse width modulation, also known as PWM encoding. The transmitting / receiving unit performs PWM decoding so that it can drive the individual bits as differential voltages on the CAN bus.

[0007] The problem is that both PWM encoding in the communication control unit and the corresponding PWM decoding in the transmitting / receiving unit require time. Therefore, the transit time from the transmitting to the receiving communication control unit is longer during the data phase and during the ADH bit at the end of that data phase than during the arbitration phase. During the transition from the data phase to the arbitration phase, the user station of the message currently being transmitted via the bus (the receiving node) must synchronize with the shortened transit time between the transmitting user station (the transmitting node) and the receiving node during the DAS field provided in the CANXL frame. However, the bits provided for this purpose in the DAS field may end prematurely due to the shortened transit time. Consequently, the receiving node cannot reliably sample this bit in all cases, and thus cannot synchronize correctly.

[0008] As a result, a phase error exists in the receiving node, caused by the shortened transit time when switching from the data phase to the arbitration phase. Consequently, the CANXL protocol cannot function properly or achieve reliable and robust communication.

[0009] Additionally, it's possible that if the receiving node samples the AH1 bit in the DAS field as 0, it will recognize a format error in the currently transmitted frame. This results in the frame being considered invalid and discarded by the receiving node. This is a systematic error and means that certain bit rate settings are unavailable in the case of CAN XL, and other bit rate settings will not work robustly. Summary of the Invention

[0010] Therefore, the objective of this invention is to provide a user station for a serial bus system and a method for communication in a serial bus system, which solves the aforementioned problems. In particular, it aims to provide a user station for a serial bus system and a method for communication in a serial bus system, wherein high fault tolerance of communication can be achieved even at high data rates (with no exceptions for certain bit rates) and with an increased effective data amount per frame.

[0011] This task is solved by a user station for a serial bus system. The user station has: a communication control device for controlling communication between the user station and at least one other user station in the bus system, and for evaluating signals received from the bus of the bus system, wherein bit times in a first communication phase may differ from bit times in a second communication phase; wherein the communication control device is designed to sample and evaluate signals received from the bus according to predetermined frames, the signals being based on transmission signals generated by another user station; wherein in the predetermined frame, a predetermined field indicating a transition from the second communication phase to the first communication phase has two or three bits with a logic value of 1 between the start of the predetermined field and a subsequent falling edge; wherein the communication control device is designed to evaluate the frame sampled from the signals received from the bus as a predetermined frame and thus as valid with respect to the predetermined field, regardless of whether only one bit or two consecutive bits with a logic value of 1 are sampled between the start of the field and the subsequent falling edge; and wherein the communication control device is designed to perform synchronization at the falling edge of the predetermined field.

[0012] In this user station, a sampling rule is implemented for the DAS field at the end of the data phase. Based on this sampling rule, the CAN XL receiving node can be robustly synchronized within the DAS field. Thus, this synchronization no longer depends on the bit timing configuration or pulse width modulation (PWM) configuration of the transmitted signal. Furthermore, in the case of transitioning from the second communication phase (data phase) to the first communication phase (arbitration phase), the bit rate switching after the second communication phase (data phase) also functions reliably.

[0013] Therefore, reliable and robust communication can be achieved using CAN XL via this user station. This also applies to extreme system parameter settings such as clock tolerance, PWM symbol length, bit timing settings, or other bus system parameters.

[0014] Another advantage is that the design scheme described for the user station used to solve the above tasks can be implemented simply and at low cost.

[0015] Therefore, by utilizing this user station, the arbitration known from CAN can be maintained in the first communication phase of the bus system, and the transmission rate can still be significantly improved again compared to CAN or CAN FD.

[0016] If there is at least one CAN user station and / or at least one CAN FD user station in the bus system that transmits messages according to the CAN protocol and / or CAN FD protocol, then the method performed by that user station can also be used.

[0017] Other advantageous design options for this user station are described below.

[0018] According to one design, the predetermined field has four bits, which have bit times for a first communication phase, wherein the predetermined field has a bit sequence with a logic value of 1101, and wherein the communication control device is designed to: after sampling a bit with a logic value of 1 in the signal received from the bus between the start and the subsequent falling edge of the field, evaluate the next bit in the signal received from the bus that is sampled with a logic value of 0 and is the third bit of the expected bit sequence 1101 at the latest as the third bit of the expected bit sequence 1101.

[0019] In this context, according to one embodiment, the communication control device can be designed to evaluate a frame sampled from signals received from the bus as erroneous if the first bit of the predetermined field has not been sampled as logic 1. The communication control device can also be designed to activate hard synchronization if the first bit of the predetermined field is sampled as logic 1.

[0020] According to one embodiment, the communication control device can also be designed to: if neither the first bit nor the second bit of the predetermined field has been sampled as logic 1, then evaluate a frame sampled by the communication control device from the signal received from the bus as erroneous. In this case, the communication control device can be designed to: if the first bit of the predetermined field has been sampled as logic 0 and the second bit of the predetermined field has been sampled as logic 1, or if the first bit of the predetermined field has been sampled as logic 1 and the second bit of the predetermined field has been sampled as logic 0, then evaluate the frame sampled by the communication control device from the signal received from the bus not as erroneous, but as valid regarding the predetermined field. In this case, the communication control device can be designed to: activate hard synchronization or synchronization if the first bit of the predetermined field is sampled as logic 1 or if the second bit of the predetermined field is sampled as logic 1.

[0021] According to another design, the predetermined field has five bits, which represent the bit time of the first communication phase. In this case, the predetermined field may have a bit sequence with a logic value of 11101, and the communication control device (11; 31) is designed such that, after sampling a bit with a logic value of 1 for the second bit of the bit sequence in the signal received from the bus, the next bit in the signal received from the bus that is sampled with a logic value of 0 and is at most the fourth bit of the expected bit sequence will be evaluated as the fourth bit of the expected bit sequence.

[0022] The communication control device can also be designed to: ignore the sampled value of the first bit of the predetermined field in the frame sampled from the signal received from the bus, and evaluate any value of the third bit of the predetermined field as error-free. Specifically, the communication control device is designed to: evaluate the frame sampled from the signal received from the bus as error-free if the second bit of the predetermined field has been sampled as logic 0. Alternatively, the communication control device can be designed to: activate hard synchronization if the second bit of the predetermined field has been sampled as logic 1.

[0023] The user station may also have transmitting / receiving devices for transmitting signals to the bus of the bus system and / or for receiving signals from the bus of the bus system. In this case, the communication control device may be designed to generate a transmitting signal, wherein the communication control device is further designed to signal the transmitting / receiving device by means of pulse width modulation in the transmitting signal that the transmitting / receiving device wants to switch its operating mode to an operating mode for transmitting in the first communication phase or to an operating mode for transmitting in the second communication phase.

[0024] Additionally, the user station may have a signal improvement module for accelerating the transition from a dominant bus level to a recessive bus level that can be covered by the dominant bus level during the first communication phase on the bus. The transmitting / receiving device may be designed to activate the signal improvement module if the user station is the sender of a transmission signal on the bus, and the transmitting / receiving device switches from an operating mode in which the communication control device sends the transmission signal to the bus of the bus system during the second communication phase to an operating mode in which the communication control device sends the transmission signal to the bus of the bus system during the first communication phase. This activation is further used to accelerate the transition from one of the bus levels of the second communication phase to the recessive level of the first communication phase.

[0025] The pre-defined frame can be constructed in compatibility with CAN FD, wherein, in the first communication phase, it is negotiated which user station in the bus system will obtain at least temporary exclusive, conflict-free access to the bus in the subsequent second communication phase.

[0026] The aforementioned user station may be part of a bus system that includes a bus and at least two user stations connected to each other via the bus, enabling them to communicate serially with each other. In this case, at least one of the at least two user stations is the aforementioned user station.

[0027] The aforementioned task is also solved by a method for communication in a serial bus system. The method is performed using a user station of a bus system, the user station having a communication control device, wherein the method comprises the following steps: using the communication control device to control communication between the user station and at least one other user station of the bus system, and evaluating a signal received from the bus of the bus system, wherein the bit time in a first communication phase may differ from the bit time in a second communication phase, wherein the communication control device samples and evaluates the signal received from the bus according to a predetermined frame, the signal being based on a transmission signal generated by another user station, wherein in the predetermined frame, a predetermined field indicating a transition from the second communication phase to the first communication phase has two or three bits with a logic value of 1 between the start of the predetermined field and the subsequent falling edge, wherein regardless of whether only one bit or two consecutive bits with a logic value of 1 are sampled between the start of the field and the subsequent falling edge in the signal received from the bus, the communication control device evaluates the frame sampled from the signal received from the bus as a predetermined frame and thus evaluates it as valid with respect to the predetermined field, and wherein the communication control device performs synchronization at the falling edge of the predetermined field.

[0028] This method offers the same advantages as those previously mentioned regarding this user site.

[0029] Other possible implementations of the invention include combinations of features or implementations not explicitly mentioned in the preceding or hereinafter described with reference to embodiments. Those skilled in the art will also consider individual aspects as improvements or supplements to the corresponding basic form of the invention. Attached Figure Description

[0030] The present invention will then be described in more detail with reference to the accompanying drawings and embodiments.

[0031] in:

[0032] Figure 1 A simplified block diagram of the bus system according to the first embodiment is shown;

[0033] Figure 2 A diagram is shown illustrating the structure of a message that can be sent by a user station of a bus system according to the first embodiment;

[0034] Figure 3 A simplified schematic block diagram of a user station in a bus system according to a first embodiment is shown;

[0035] Figure 4 The time-varying process of bus signals CAN-XL_H and CAN-XL_L is shown in the case of a user station according to the first embodiment;

[0036] Figure 5 The time-varying process of the differential voltage VDIFF of bus signals CAN-XL_H and CAN-XL_L is shown in the case of a user station according to the first embodiment;

[0037] Figures 6 to 8 The changes of the signal over time are shown respectively. If the user station according to the first embodiment is the sender of the message, and the operation mode of the sending / receiving device is switched from the first communication stage to the second communication stage when the message is sent, the signal appears at the connection end of the user station when the frame is sent.

[0038] Figures 9 to 11 The changes of the signal over time are shown respectively. If the user station according to the first embodiment is the sender of the message, and the operation mode of the sending / receiving device is switched from the second communication stage to the first communication stage when the message is sent, the signal appears at the connection end of the user station when the frame is sent.

[0039] Figure 12 The following diagram illustrates the change of signal state over time, if another user station is the sender of the message and generates a signal according to... Figures 9 to 11 If a signal is received, the receiving node will treat these signal states as received signals at its receiving connection end.

[0040] Figure 13 The following diagram illustrates the change of signal state over time, if another user station is the sender of the message and generates a signal according to... Figures 9 to 11 If the signal is received, the receiving node will expect these signal states to be received signals at its receiving connection end;

[0041] Figure 14 A schematic block diagram of a user station in a bus system according to a second embodiment is shown;

[0042] Figure 15 A schematic block diagram of a user station in a bus system according to a third embodiment is shown; and

[0043] Figure 16 A diagram is shown to illustrate the structure of messages that can be sent by a user station of a bus system according to a third embodiment.

[0044] In these accompanying drawings, unless otherwise stated, the same or functionally equivalent elements are given the same reference numerals. Detailed Implementation

[0045] Figure 1 Bus system 1 is shown as an example, which is specifically designed for use with CAN bus systems, CANFD bus systems, CANXL bus systems and / or their variations, as described below. Bus system 1 can be used in vehicles, especially motor vehicles, aircraft, etc., or in hospitals, etc.

[0046] exist Figure 1 In the bus system 1, there are multiple user stations 10, 20, and 30, which are respectively connected to a bus 40 having a first bus core line 41 and a second bus core line 42. Bus core lines 41 and 42 can also be referred to as CAN_H and CAN_L or CAN-XL_H and CAN-XL_L, and are used for electrical signal transmission after coupling a dominant input level or generating a recessive level or other levels in the transmit state. Messages 45 and 46 can be serially transmitted between the user stations 10, 20, and 30 in signal form via bus 40. If an error occurs on bus 40 during communication, such as through… Figure 1 As indicated by the jagged black square arrow, error frame 47 (Error Flag) can be optionally sent. User stations 10, 20, and 30 are, for example, vehicle control equipment, sensors, display devices, etc.

[0047] like Figure 1As shown, user station 10 has a communication control device 11, a transmitting / receiving device 12, and a phase error compensation module 15. User station 20 has a communication control device 21, a transmitting / receiving device 22, and optionally a phase error compensation module 25. User station 30 has a communication control device 31, a transmitting / receiving device 32, and a phase error compensation module 35. The transmitting / receiving devices 12, 22, and 32 of user stations 10, 20, and 30 are directly connected to bus 40, even if this... Figure 1 This is not explained in the text.

[0048] Communication control devices 11, 21, and 31 are respectively used to control the communication between the corresponding user stations 10, 20, and 30 and at least one other user station among the user stations 10, 20, and 30 connected to the bus 40 via the bus 40.

[0049] Communication control devices 11 and 31 create and read first messages 45, which are, for example, modified CAN messages 45. In this case, the modified CAN messages 45 are constructed based on the CAN XL format, which references... Figure 2 The following description is provided in more detail, and it includes the use of corresponding phase error compensation modules 15 and 35. The communication control devices 11 and 31 can also be implemented to provide or receive CAN XL messages 45 or CAN FD messages 46 from the transmitting / receiving device 32 as needed. In this case, the corresponding phase error compensation modules 15 and 35 are also used. That is, the communication control devices 11 and 31 create and read the first message 45 or the second message 46, wherein the first and second messages 45 and 46 are distinguished by their data transmission standard, i.e., in this case, CAN XL or CAN FD.

[0050] The communication control device 21 can be implemented like a conventional CAN controller according to ISO 11898-1:2015, that is, like a Classical CAN controller or a CAN FD controller that tolerates CAN FD. Optionally, a phase error compensation module 25 is present, which has the same function as phase error compensation modules 15 and 35. The communication control device 21 creates and reads a second message 46, such as a CAN FD message 46. In the case of a CAN FD message 46, it may include 0 to 64 data bytes, and these data bytes are transmitted at a significantly faster data rate than in the case of a Classical CAN message. In particular, the communication control device 21 is implemented like a conventional CAN FD controller.

[0051] The transmitting / receiving device 22 can be implemented as a conventional CAN transceiver or CAN FD transceiver according to ISO 11898-1:2015. The transmitting / receiving devices 12 and 32 can be implemented to provide or receive messages 45 in CANXL format or messages 46 in the current CAN FD format as needed from their respective communication control devices 11 and 31.

[0052] Using two user stations 10 and 30, it is possible to form and then transmit a message 45 in CANXL format, as well as to receive such a message 45.

[0053] Figure 2 Message 45 illustrates a CANXL frame 450, provided by the communication control unit 11 to the transmitting / receiving unit 12 for transmission onto the bus 40. In this case, the communication control unit 11 creates frame 450 in the current embodiment to be compatible with CAN FD, as shown in... Figure 2 As explained in the text, the same applies to the communication control device 31 and the transmitting / receiving device 32 of the user station 30.

[0054] according to Figure 2 CANXL frame 450 is divided into different communication phases 451 and 452 for CAN communication on bus 40: arbitration phase 451 and data phase 452. Following the start bit (SOF), frame 450 has: an arbitration field 453; a control field 454 containing an ADS field 1510 for switching between communication phases 451 and 452; a data field 455; a checksum field 456; and a frame termination field 457 containing a DAS field 1520 for switching between communication phases 452 and 451. Then comes the end-of-frame field EOF.

[0055] During arbitration phase 451, user stations 10, 20, and 30 negotiate bit-by-bit using an identifier (ID) with bits such as ID28 to ID18 in the arbitration field 453: which user station 10, 20, or 30 wants to send the highest priority messages 45 and 46 and thus obtain exclusive access to bus 40 of bus system 1 for transmission in the next data phase 452. During arbitration phase 451, a physical layer, similar to that used in CAN and CAN-FD, is employed. The physical layer corresponds to the bit transport layer or Layer 1 of the well-known OSI model (Open Systems Interconnection Model 1).

[0056] The focus during phase 451 is that the well-known CSMA / CR method is available, allowing user stations 10, 20, and 30 to simultaneously access bus 40 without disrupting higher-priority messages 45 and 46. This makes it relatively easy to add other bus user stations 10, 20, and 30 to bus system 1, which is highly advantageous.

[0057] The CSMA / CR method results in the existence of so-called recessive states on bus 40, which can be overridden by dominant states on bus 40 used by other user stations 10, 20, and 30. In the recessive state, high impedance conditions exist at each user station 10, 20, and 30, which, combined with parasites in the bus wiring, leads to a longer time constant. This limits the maximum bit rate of the current CAN-FD physical layer to approximately 2 megabits per second in real-world vehicle applications.

[0058] In data phase 452, in addition to a portion of control field 454, valid data from data field 455 and checksum field 456 of CAN-XL frame or message 45 are transmitted. Then comes DAS field 1520, which is used to switch back from data phase 452 to data phase 451.

[0059] When user station 10, as the sender, wins the arbitration and thereby exclusively accesses bus 40 of bus system 1 for transmission, the sender of message 45 begins to send the bits of data stage 452 onto bus 40.

[0060] Very generally, the following differences can be achieved in bus systems with CAN XL compared to CAN or CANFD:

[0061] a) Employ and, where necessary, adapt proven features, especially frame structures with identification codes and arbitration based on the CSMA / CR method, which are responsible for the robustness and user-friendliness of CAN and CAN FD;

[0062] b) Increase the net data transfer rate, especially to approximately 10 megabits per second;

[0063] c) Increase the size of the effective data in each frame, especially to about 2 kilobytes or any other value.

[0064] like Figure 2As shown, user station 10 uses the format known from CAN / CAN-FD according to ISO 11898-1:2015 in part, and particularly up to the FDF bit (inclusive), during the arbitration phase 451, which is the first communication phase. On the other hand, user station 10 uses the CAN XL format from the FDF bit in the first communication phase and in the second communication phase, i.e., the data phase 452, which will be described later.

[0065] In the current embodiment, CANXL and CANFD are compatible. In this case, the res bit, known from CAN FD, is used for switching from the CAN FD format to the CAN XL format; this res bit is subsequently referred to as the XLF bit. Thus, the frame formats of CANFD and CANXL are the same up to the res bit or the XLF bit. The receiver identifies the format in which frame 450 was transmitted solely at the res bit. CAN XL user stations, i.e., user stations 10 and 30 here, also support CAN FD.

[0066] Replace in Figure 2 The frame 450 shown uses 11-bit identifiers ID28 to ID18. Optionally, it can implement the CANXL extended frame format, which uses a 29-bit identifier. Up to the FDF bit, this extended frame format is identical to the well-known CAN FD extended frame format from ISO 11898-1:2015.

[0067] according to Figure 2 Frame 450, from the SOF bit up to including the FDF bit, is identical to the CAN FD basic frame format according to ISO 11898-1:2015. Therefore, the well-known structure is not further elaborated here. Figure 2 The bit shown in bold at the bottom of the line is transmitted as dominant or "0" in frame 450. Figure 2 The bit shown in bold at the top of the line is transmitted as recessive or "1" in frame 450. In CANXL data phase 452, symmetrical "1" and "0" levels are used instead of recessive and dominant levels.

[0068] Typically, two different padding rules are applied when generating frame 450. Up to the FDF bit in the arbitration field 453, the dynamic bit padding rule of CAN FD is applied, ensuring that an opposite padding bit is inserted after five consecutive identical bits. In the data phase 452, up to the FCP field, a fixed padding rule is applied, ensuring that a fixed number of padding bits are inserted after a fixed number of bits. Alternatively, instead of just one padding bit, two or more bits can be inserted as fixed padding bits.

[0069] In frame 450, immediately following the FDF bit is the XLF bit, which corresponds from this position to the "res bit" in the CANFD basic frame format, as described above. If the XLF bit is transmitted as 1, i.e., recessively, then the XLF bit identifies frame 450 as a CANXL frame. For CANFD frames, the communication control device 11 sets the XLF bit to 0, i.e., dominant.

[0070] In frame 450, following the XLF bit is the resXL bit, which is the dominant bit for future use. For frame 450, resXL must be transmitted as 0, i.e., dominant. However, if user station 10 receives a resXL bit as 1, i.e., recessive, then receiving user station 10 enters, for example, a Protocol Exception State, as interpreted in the case of CAN FD message 46 for res=1. Alternatively, the resXL bit may be restricted in the opposite way, i.e., it must be transmitted as 1, i.e., recessive. In this case, the receiving user station enters a Protocol Exception State with a dominant resXL bit.

[0071] In frame 450, following the resXL bit is the ADS (Arbitration Data Switch) sequence, in which a predetermined bit sequence is encoded. This bit sequence allows for a simple and reliable switch from the bit rate of arbitration phase 451 (arbitration bit rate) to the bit rate of data phase 452 (data bit rate). The first bit of ADS field 1510 is the ADH bit. Optionally, the operating mode of the transmitting / receiving devices 12, 32 is switched within this ADH bit. Despite the optional switching of the operating mode of the transmitting / receiving devices during the ADH bit and the associated voltage fluctuations, the ADH bit is transmitted on the bus at least in its last portion, for example, the last 50% of the bit, as a logic 1. This ADH bit is the last bit of arbitration phase 451. The next three bits, DH1, DH2, and DL1, have already been transmitted at the data bit rate. Therefore, in the case of CAN XL, bits DH1, DH2, and DL1 are the shorter bits of data phase 452. Bits DH1 and DH2 each have a logic value of 1. The last bit is bit DL1, which has a logic value of 0. After the bit rate switch, the receiving node synchronizes with the falling edge at the beginning of bit DL1. ADS field 1510 is used for the transition from the first communication stage 451 to the second communication stage 452.

[0072] In frame 450, following the ADS sequence is the SDT field, which indicates the content of data field 455. The content of the SDT field specifies what type of information is included in data field 455. For example, the SDT field indicates whether an Internet Protocol (IP) frame, a tunneled Ethernet frame, or something else is present in data field 455.

[0073] Following the SDT field is the SEC field, which indicates whether Frame 450 is protected using the CAN security protocol. The SEC field is 1 bit wide and, like the SDT field, serves to specify the type of information contained in Data Field 455.

[0074] Following the SEC field is the DLC field. A Data Length Code (DLC = Data Length Code) is inserted into this DLC field, indicating the number of data bytes in data field 455 of frame 450. The number of data bytes in data field 455 can take any value from 1 to the maximum number of bytes in data field 455 or the data field length. If the maximum data field length is, in particular, 2048 bits, then the Data Length Code (DLC) requires 11 bits, assuming DLC ​​= 0 indicates a data field length of 1 byte and DLC = 2047 indicates a data field length of 2048 bytes. Alternatively, a data field 455 of length 0 may be allowed, such as in the case of CAN. In this case, DLC = 0 would, for example, encode a data field length of 0 bytes. The maximum encodeable data field length is, for example, 11 bits, then (2 11 )-1=2047.

[0075] In frame 450, following the DLC field is the SBC bit count field (Stuff-Bit-Count). This field indicates the number of dynamic padding bits transmitted in the arbitration field 453. The receiving node uses the signal from the SBC bit count field to check whether it has received the correct number of dynamic padding bits.

[0076] Following the SBC bit count field is the preamble checksum PCRC, also known as preamble-CRC. The PCRC is a checksum used to protect the frame format of frame 450; that is, it's a checksum of all variable bits from the start of the SOF bits in frame 450 up to the start of the PCRC, including all dynamically and optionally fixed padding bits up to the start of the PCRC. The length of the PCRC, and consequently the checksum polynomial according to CRC, should be selected based on the desired Hamming distance.

[0077] In frame 450, following the preamble checksum and PCRC is the VCID (Virtual CANBus ID) field. The VCID field is 1 byte long and contains the number of the virtual CAN bus.

[0078] In frame 450, following the VCID field is the AF (Acceptance Field). The AF field is 32 bits long. It contains the address or other values ​​used for acceptance filtering.

[0079] In frame 450, following field AF is data field 455 (DataField). Data field 455 consists of P bytes B, where, as mentioned above, P is encoded in the DLC field. P is a natural number greater than or equal to 1.

[0080] In frame 450, following the data field 455 is a checksum field 456, which has a frame checksum (FCRC) and an FCP field. The FCRC consists of FCRC bits, which, for example, has 32 bits. The length of the FCRC and the CRC polynomial thereon should be selected according to the desired Hamming distance. The FCRC protects the entire frame 450. Alternatively, optionally only the data field 455 may be protected using the FCRC.

[0081] In frame 450, following the frame check and FCRC is the FCP field, where FCP = Frame Check Pattern. The FCP field consists of four bits, specifically a bit sequence of 1100. The receiving node uses the FCP field to check whether it is in sync with the transmitted data stream. Furthermore, the receiving node synchronizes with the falling edge of the FCP field.

[0082] Following the FCP field is the Frame End Field 457. The Frame End Field 457 consists of two fields: the DAS field 1520 and the Acknowledgment or ACK field, which has at least one ACK bit and one ACK-Dlm bit.

[0083] DAS field 1520 includes the sequence DAS (Data Arbitration Switch) in which a pre-bit sequence is encoded. Bit sequences DAH, AH1, and AL1 allow for a simple and reliable switch from the data bit rate of data phase 452 to the arbitration bit rate of arbitration phase 451. Furthermore, during DAS field 1520, the operating mode of transmitting / receiving devices 12 and 32 is switched, optionally from operating mode FAST to operating mode SLOW. Figure 2 In the DAS field 1520, bits DAH, AH1, AL1, and AH2 are present. Bit AH2 is used to maintain distance from the acknowledgment (ACK) field. The DAS field has at least three bits. Figure 2 In the example, the bit sequence of the DAS sequence has an arbitration bit DAH and an arbitration bit AH1, each with a logic value of 1. Within the DAH bit, the operating mode of the physical layer, i.e., the transmitting / receiving devices 12 and 32, switches from FAST_TX or FAST_RX to SLOW. Following bit AH1 are bits AL1 (logic 0) and AH2 (logic 1). These two bits, DAH and AH1, ensure that there is sufficient time for the operating mode switch of transmitting / receiving device 11, and that all user stations 10 and 30 see a recessive level significantly longer than the duration of one arbitration bit before the beginning edge of bit AL2 (logic 0). This ensures reliable synchronization of user stations currently re-integrating into communication on the bus system.

[0084] In frame termination field 457, following the sequence of DAS field 1520 is the acknowledgment (ACK) field. The ACK field provides bits for acknowledging or denying that frame 450 was correctly received. Figure 2In the example, an ACK bit and an ACK-dlm bit are provided; alternatively, the ACK bit may be called an ACK slot and may optionally have more than one bit. Alternatively, NACK bits and NACK-dlm bits may also be present. If receiving user stations 10 and 30 have correctly received frame 450, these receiving user stations will send the ACK bit as dominant. The transmitting user stations will send the ACK bit as recessive. Therefore, the ACK bit or ACK slot is a placeholder for one or more feedbacks from the receiving node. Thus, bits initially sent to bus 40 in frame 450 can be overridden by receiving user stations 10 and 30. The ACK-dlm bit is sent as a recessive bit to separate it from other fields. The NACK bit and NACK-dlm bit are used by the receiving user stations to signal incorrect reception of frame 450 on bus 40. These bits function the same as the ACK bit and ACK-dlm bit.

[0085] In frame 450, the end-of-frame (EOF) field follows the frame termination field 457. The bit sequence of the EOF field indicates the end of frame 450. The EOF field causes 8 recessive bits to be sent at the end of frame 450. This bit string cannot appear within frame 450. Therefore, user stations 10, 20, and 30 can reliably identify the end of frame 450.

[0086] The End-of-Flight (EOF) field has a different length depending on whether a dominant or recessive bit was seen in the ACK bit sequence. If the sending user station receives a dominant ACK bit, the EOF field has 7 recessive bits. Otherwise, the EOF field has only 5 recessive bits.

[0087] In frame 450, after the End of Field (EOF) is... Figure 2 The interframe space (IFS) is not shown in the diagram. This interframe space (IFS) is designed according to ISO 11898-1:2015, as in CAN FD.

[0088] Figure 3 The basic structure of user station 10 is shown. This user station includes a communication control device 11, a transmitting / receiving device 12, and a phase error compensation module 15, which is part of the communication control device 11. User station 30 is connected to... Figure 3 The situation shown is constructed in a similar manner, however, according to Figure 1 The phase error compensation module 35 is arranged independently of the communication control device 31 and the transmitting / receiving device 32. Therefore, the user station 30 is not described separately.

[0089] according to Figure 3 In addition to the communication control unit 11 and the transmitting / receiving unit 12, the user station 10 also includes: a microcontroller 13, to which the communication control unit 11 is assigned; and a system ASIC 16 (ASIC = Application-Specific Integrated Circuit), which may alternatively be a system base chip (SBC) on which multiple functions required for the electronic equipment components of the user station 10 are combined. In the system ASIC 16, in addition to the transmitting / receiving unit 12, a power supply unit 17 is also installed, which supplies power to the transmitting / receiving unit 12. The power supply unit 17 typically provides a 5V voltage for CAN_Supply. However, the power supply unit 17 may provide different voltages with different values ​​as needed. Additionally or alternatively, the power supply unit 17 may be designed as a current source.

[0090] Phase error compensation module 15 has: an insertion block 151, which will Figure 2 The pre-defined DAS field 1520 and optionally the ADS field 1510 are inserted into frame 450; and signaling block 152. Blocks 151 and 152 are described in more detail thereafter.

[0091] The transmitting / receiving device 12 also includes a transmitting module 121 and a receiving module 122, and optionally a signal improvement module 125. Even though the transmitting / receiving device 12 is always referred to thereafter, the receiving module 122 can alternatively be located in a separate device outside the transmitting module 121. The transmitting module 121 and the receiving module 122 can be constructed as in the case of a conventional transmitting / receiving device 22. The transmitting module 121 may in particular have at least one operational amplifier and / or transistor. The receiving module 122 may in particular have at least one operational amplifier and / or transistor.

[0092] The transmitting / receiving device 12 is connected to bus 40, more specifically to the first bus line 41 for CAN_H or CAN-XL_H and the second bus line 42 for CAN_L or CAN-XL_L. The power supply device 17 is supplied with voltage via at least one connection terminal 43 to supply electrical energy, particularly the supply voltage CAN-Supply, to the first and second bus lines 41, 42. Connection to ground or CAN_GND is achieved via connection terminal 44. The first and second bus lines 41, 42 are terminated by terminating resistor 49.

[0093] In the transmitting / receiving device 12, the first and second bus cores 41 and 42 are connected not only to the transmitting module 121, also known as the transmitter, but also to the receiving module 122, also known as the receiver. Figure 3 For simplicity, this connection is not shown.

[0094] When the bus system 1 is running, the transmitting module 121 converts the transmitting signal TXD or TxD of the communication control device 11 into corresponding signals CAN-XL_H and CAN-XL_L for the bus core lines 41 and 42, and transmits these signals CAN-XL_H and CAN-XL_L to the bus 40 at the connection terminals for CAN_H and CAN_L.

[0095] Receiver module 122 according to Figure 4 The signals CAN-XL_H and CAN-XL_L received from bus 40 are used to form a receive signal RXD or RxD, and this receive signal is then transferred to the communication control device 11, such as... Figure 3 As shown in the diagram. Except in idle or standby mode, the transmitting / receiving device 12 always listens for the transmission of data or messages 45, 46 on the bus 40 during normal operation using the receiving module 122, more precisely regardless of whether the transmitting / receiving device 12 is the sender of message 45.

[0096] according to Figure 4 For example, signals CAN-XL_H and CAN-XL_L have dominant and recessive bus levels 401 and 402, respectively, at least during the arbitration phase 451, as is known from CAN. These levels are formed on bus 40. Figure 5 The differential signal VDIFF = CAN-XL_H - CAN-XL_L is shown for arbitration phase 451. Each bit of signal VDIFF, with a bit time t_bt1, can be identified in arbitration phase 451 using a reception threshold T_a, for example, 0.7V. In data phase 452, the bits of signals CAN-XL_H and CAN-XL_L are transmitted faster than in arbitration phase 451, i.e., with a shorter bit time t_bt2. According to... Figures 6 to 9 To describe this in more detail. Therefore, the difference between signals CAN-XL_H and CAN-XL_L in the data phase 452 and the regular signals CAN_H and CAN_L lies at least in their faster bit rate.

[0097] Figure 4 The sequences of states 401 and 402 of signals CAN-XL_H and CAN-XL_L, and the resulting... Figure 5 The change process of voltage VDIFF is only used to illustrate the function of user station 10. The sequence of data states for bus states 401 and 402 can be selected as needed.

[0098] Optionally present signal improvement module 125 is designed to perform the SIC function (SIC = Signal Improvement Capability). This SIC function causes, during arbitration phase 451, to accelerate the differential voltage VDIFF on the bus core from dominant ( Figure 5 401) to recessive ( Figure 5 The signal improvement module 125 triggers the SIC function when the TXD input of the transmitting / receiving device 12 transitions from 0 to 1. This SIC function (SIC = Signal Improvement Capability) is only active during the first operating mode B_451 (SLOW), which has both dominant and recessive signal states.

[0099] In other words, according to Figure 4 When the transmitting module 121 is switched to the first operating mode B_451 (SLOW), it generates: a first data state, which is a bus state 402 having different bus levels for the two bus cores 41 and 42 of the bus line; and a second data state, which is a bus state 401 having the same bus level for the two bus cores 41 and 42 of the bus line of the bus 40.

[0100] Furthermore, the transmitting module 121 transmits bits to the bus 40 at a higher bit rate based on the time-varying process of the signals CAN-XL_H and CAN-XL_L in the second operating mode B_452_TX (FAST_TX) including the data phase 452. In the data phase 452, the CAN-XL_H and CAN-XL_L signals can also be generated using a different physical layer than in the case of CAN FD. Therefore, the bit rate in the data phase 452 can be further increased compared to the case of CAN FD. In the data phase 452, the user station that is not the sender of frame 450 sets the third operating mode B_452_RX (FAST_RX) in its transmitting / receiving device.

[0101] To signal the switch from operating mode B_451 to operating mode B_452_TX (FAST_TX) or operating mode B_452_RX (FAST_RX), the communication control unit 11 performs pulse width modulation (PWM) on the transmit signal TxD. For this purpose, the communication control unit 11 uses one or more PWM symbols for each logic bit of the CANXL frame 450. In principle, a PWM symbol consists of two phases, i.e., phase 0 and phase 1. Furthermore, the PWM symbol is defined by two identical edges, for example, by two rising edges.

[0102] Figure 3The phase error compensation module 15, and especially the insertion block 151 of the phase error compensation module, is used to: when the user station 10 acts as the sender of frame 450, Figure 2 The DAS field 1520 and optionally the ADS field 1510 are inserted into frame 450. Furthermore, the phase error compensation module 15, and in particular its signaling block 152, can perform pulse width modulation (PWM), as described later for switching between operating modes B_451 (SLOW) and B_452_TX (FAST_TX).

[0103] At time t, Figure 6 The digital transmission signal TxD obtained during the transition from arbitration phase 451 to data phase 452 of frame 450 is shown; in other words, during the transition from phase 451 to phase 452. After bit resXL, the ADS field 1510 is inserted into frame 450. The transmission signal TxD is serially transmitted to the transmitting / receiving device 12 by the communication control device 11, which is the sender of frame 450, as described in more detail later. Up to bit ADH, the bits of frame 450 have a bit duration t_bt1. Starting from bit DH1, i.e., the first bit of data phase 452, the bits of frame 450 have a bit duration t_bt2. Figure 6 In the example, the bit duration t_b2 is shorter than the bit duration t_bt1.

[0104] As in Figure 2 China and also Figure 6 As already shown, the ADH bit is sent with a logic value of 1 in the current embodiment.

[0105] Figure 7 The states obtained from the transmitted signal TxD at time t are shown, and these states appear serially at the connection point TXD between the communication control device 11 and the transmitting / receiving device 12. For this purpose, the communication control device 11, such as the phase error compensation module 15, and especially the signaling block 152, performs [operations] in the ADH bit and in the data phase 452. Figure 6 The transmitted signal TxD is pulse-width modulated (PWM). More specifically, Figure 6 The pulse width modulation (PWM) of the transmit signal TxD begins at the ADH bit. During the arbitration phase 451 preceding this ADH bit, no pulse width modulation (PWM) is performed on the transmit signal TxD.

[0106] Because the signal edge frequency at the TXD connection is high, the transmitting / receiving device 12 determines that it should switch from the arbitration phase operating mode B_451 to one of the fast operating modes B_452_TX (FAST_TX) or B_452_RX (FAST_RX), or remain there. The transmitting / receiving device 12 determines whether it should switch to operating mode B_452_TX (FAST_TX) or operating mode B_452_RX (FAST_RX) based on the value of the previously transmitted resXL bit. Additionally or alternatively, the transmitting / receiving device 12 determines which operating mode it should switch to based on the value of the first PWM symbol or the first S PWM symbols. S is a natural number greater than or equal to 1. Due to the performed PWM encoding, the signal at the TXD connection is delayed by a duration T_V1 relative to the TxD signal. The signaling block 152 generates the first S PWM symbols according to the operating mode to which the transmitting / receiving device should be switched. That is, the first S PWM symbols are encoded independently of the value of the ADH bit. Additionally or alternatively, the first S PWM symbols can be used in the transmitting node to implement a gradual transition of the dominant +2V differential voltage VDIFF on bus 40 via a +1V differential voltage VDIFF for logic 0 in data phase 452 to a -1V differential voltage VDIFF for logic 1 in data phase 452.

[0107] exist Figure 7 In the example, in the case of PWM symbol SB_D0, 0 is longer than 1, which corresponds to the bit with logic value 0 in data phase 452 in the transmit signal TxD. On the other hand, in the case of PWM symbol SB_D1, 1 is longer than 0, which corresponds to the bit with logic value 1. Of course, PWM symbols SB_D0 and SB_D1 can be defined in other ways, especially in ways completely opposite to the above.

[0108] In addition, Figure 7 In the example, the first two PWM symbols in the signal at the connection terminal TXD have a logic value of 0 (SB_D0). Transmitter / receiver devices 12 and 32 evaluate the first two PWM symbols to determine which operating mode the transmitter / receiver devices 12 and 32 should be switched to. Figure 7 In the current example, due to the two PWM symbols having a logic value of 0, the transmit / receive devices 12 and 32 of the transmitting node should switch to operating mode B_452_TX (FAST_TX). In the ADH bit, at least one additional value of the first two PWM symbols is used to signal the switch to operating mode B_452_RX (FAST_RX).

[0109] like Figure 7 As shown, the communication control device 11, such as the phase error compensation module 15, and especially the signaling block 152, executes subsequent actions... Figure 6 The pulse width modulation (PWM) of the ADH bit of the transmit signal TxD causes all subsequent PWM symbols of the ADH bit to be transmitted with a logic value of 1. Therefore, in the second part of the ADH bit, that is, the part after signaling the type of operation mode B_452 for the data phase 452 of the transmitting / receiving devices 12, 32, only the symbol SB_D1 exists.

[0110] Figure 8 The diagram illustrates the time-varying process of the signal TxD_TC, which is generated by the transmitting / receiving device 12 based on... Figure 7 Decoding is done based on the state at the TXD terminal of the connection. Figure 8 In the example, the transmitting / receiving device 12 switches its operating mode B_451, in which frame 450 has bits of duration t_bt1, to operating mode B_452_TX (FAST_TX), in the bit ADH, where frame 450 has bits of duration t_bt2. Furthermore, as described above, the bits of frame 450 can be transmitted onto bus 40 at a different physical layer in operating mode B_451 than in operating mode B_452_TX.

[0111] That is, the transmitting / receiving device 12 will Figure 7 The state at the TXD terminal of the connection is decoded according to... Figure 8 The signal TxD_TC. For the ADH bit, a logic value of 0 is generated for the first part of the ADH bit, ADH_0. For Figure 8 The second and last part of the ADH bit, ADH_1, produces the logic value 1.

[0112] At the connection terminal TXD, each PWM symbol in SB_D0 and SB_D1 can only be decoded at the end of the corresponding PWM symbol SB_D0 or SB_D1. Therefore, the decoding in the transmitting / receiving device 12 inserts an additional delay duration T_V2 into the signal TxD_TC to be serially transmitted to the bus 40. The delay duration T_V2 is equal to the duration of the symbol length of one of the PWM symbols SB_D0 and SB_D1, such as... Figure 8 As shown in the diagram. The phase error T_P caused by PWM encoding and decoding in the transmitting user station is T_P = T_V1 + T_V2.

[0113] In the transmitting / receiving device 12 will Figure 7 The state at the TXD terminal of the connection is decoded according to... Figure 8After transmitting the signal TxD_TC, the transmitting / receiving device 12 sends the signal TxD_TC as a differential voltage VDIFF onto the bus 40. The differential voltage VDIFF based on the signal TxD_TC can be received by the receiving node on the bus 40. The relevant signals in the receiving node are not shown here.

[0114] After data phase 452, the pulse width modulation (PWM) of the transmitted signal TxD ends. The switching from operating mode B_452_TX (FAST_TX) or operating mode B_452_RX (FAST_RX) to operating mode B_451 (SLOW) is signaled by stopping PWM encoding and thus by making many edges disappear.

[0115] Figure 9 The digital transmission signal TxD obtained during the transition from data phase 452 to arbitration phase 451 of frame 450 is shown at time t. After bits FCP3, FCP2, FCP1, and FCP0, the DAS field 1520 is inserted into frame 450. Up to bit FCP0, the last bit of data phase 452, the bits of frame 450 still have a bit duration t_bt2. Starting from bit DAH, the first bit of subsequent data phase 451, the bits of frame 450 have a bit duration t_bt1. (See also: Regarding...) Figure 6 As already explained, in the example described here, the bit duration t_b2 is shorter than the bit duration t_bt1.

[0116] As in Figure 2 China and also Figure 9 As already shown, the DAH bit and the subsequent AH1 bit are transmitted as a logic value of 1 in frame 450 in the current embodiment.

[0117] Figure 10 The states obtained from the transmitted signal TxD at time t are shown, and these states appear serially at the connection point TXD between the communication control device 11 and the transmitting / receiving device 12. As previously described, the communication control device 11, such as the phase error compensation module 15, and especially the signaling block 152, executes in the data phase 452. Figure 9 The transmitted signal TxD is pulse width modulated (PWM). As described above, delays T_V1 and T_V2 occur due to PWM encoding and subsequent PWM decoding in the transmitting / receiving device.

[0118] Figure 9 The pulse width modulation (PWM) of the transmitted signal TxD ends at the FCP0 bit, that is, before the DAH bit. Figure 10The signal TXD was not pulse-width modulated (PWM) during the arbitration phase 451, i.e. after the FCP0 bit.

[0119] At the end of data phase 452, the transmitting / receiving device 12 determines, based on the now lower frequency caused by the absence of numerous edges of the signal at the TXD connection, that it should either switch from the operating mode of data phase 452 to the operating mode B_451 of the arbitration phase, or remain there. In operating mode B_451, the transmitting / receiving device 12 no longer performs... Figure 10 PWM decoding of the signal TxD. Therefore, in Figure 11 The delay T_P = T_V1 + T_V2 is omitted during the DAH bit period in the signal TxD_TC. These delays were previously included in the signal TXD_TC during data phase 452 due to the PWM encoding and decoding of the signal TxD. Therefore, in Figure 11 The AH1 bit in the signal TxD_TC ends T_P = T_V1 + T_V2 ahead of time, which results in a phase error of T_P at the receiver.

[0120] exist Figure 11 In the example, the transmitting / receiving device 12 switches the operating mode B_452_TX (FAST_TX) of the data phase 452 of the transmitting / receiving device to the operating mode B_451 in which the frame 450 has a bit duration of t_bt1. Furthermore, as described above, the physical layer can be switched.

[0121] like Figure 12 As shown, the communication control device 11 (protocol controller) in the receiving node is synchronized with the edge of the digital signal RxD received from the transmitting node during the data phase 452. If the transmitting node stops PWM encoding from the DAH bit, as previously mentioned... Figures 9 to 10 As described, the transit time from the sending node to the receiving node is shortened by T_P = T_V1 + T_V2. This sudden introduction of phase error at the receiver (receiving node) corresponds to a phase jump. However, the receiving node expects the end of the AH1 bit to be delayed by T_P = T_V1 + T_V2, as can be achieved using... Figure 13 The digital signal RxD_E is shown in the figure.

[0122] The result of this phase transition is that, for the receiving node, according to Figure 12 The AH1 bit ratio at the receiving node is determined by the receiving node according to... Figure 13The expected situation of the signal RxD_E ended earlier than T_P = T_V1 + T_V2. In order to compensate for this phase transition, the phase error compensation modules 15 and 25 and 35 of user stations 10, 20 and 30 take action as described below.

[0123] The receiving node, or more precisely, the communication control device 11 of the receiving node, according to... Figure 13 The received signal RxD is sampled at times t_1 and t_2 based on the previous synchronization in the signal RxD_E. Sampling time t_1 is the sampling time of the DAH bit. Sampling time t_2 is the sampling time of the AH1 bit.

[0124] In the relevant user stations 10, 20, and 30, which act as receiving nodes, the phase error compensation modules 15, 25, and 35 tolerate one or two consecutively sampled bits with a logic value of 1, starting from the bit position of DAH. Then, the first bit sampled with a logic value of 0 is accepted as the AL1 bit.

[0125] exist Figure 12 and Figure 13 In the example, the receiving node will Figure 12 The signal RxD is sampled as a bit sequence DAH, AL1. Therefore, the AH1 bit is lost. However, the phase error compensation modules 15, 25, and 35 of the receiving node tolerate the loss of the AH1 bit.

[0126] Very generally, the phase error compensation modules 15, 25, and 35 of the receiving nodes assume that the first falling edge after the DAH bit defines the start of the AL1 bit. All receiving nodes are synchronized with the edge at the start of the AL1 bit, which corresponds to... Figure 12 The time point t_SY in the data.

[0127] Furthermore, hard synchronization is activated when the DAH bit is sampled as logic 1. Therefore, performing hard synchronization at the next edge allows for synchronization that corrects for arbitrarily large phase errors. This hard synchronization is performed at time point t_SY, as follows: Figure 12 As shown in the image.

[0128] Furthermore, the phase error compensation modules 15, 25, and 35 of the receiving node are designed such that sampling the DAH bit as logic 0 is evaluated as a format error. In this case, such a sampled frame is evaluated as erroneous and / or considered invalid and discarded. Additionally, an erroneous frame 47 can be sent to bus 40.

[0129] This ensures that the receiving node compensates for the phase jump caused by the shortened transit time and the possible loss of the AH1 bit through proper synchronization after switching from the data phase 452 to the arbitration phase 451.

[0130] According to one modification of the DAS field described above, the DAS field can have four more bits at the end than described. However, these four bits are advantageous in terms of maximizing the net data rate.

[0131] Additionally or alternatively, it is possible that at least one of these user stations 10, 20, 30 is designed to ensure connectivity on bus 40 until [following / in accordance with / etc.]. Figure 13 A stable recessive level appears up to sampling point t_1 of the DAH bit.

[0132] Therefore, for example in the case of the transmitting / receiving device 12, the signal improvement module 125 is designed to perform the SIC function (SIC = Signal Improvement Capability) not only in operating mode B_451 (SLOW) when the TxD signal transitions from 0 to 1. The first trigger condition for performing the SIC function has been previously described. Additionally or alternatively, the signal improvement module 125 can be designed to implement a second trigger condition for performing the SIC function.

[0133] The second triggering condition for performing the SIC function is that the transmitting / receiving devices 12, 22, and 32 of the transmitting node change from operating mode 452_TX (FAST_TX) to operating mode B_451 of the arbitration phase 451, such as... Figure 9 As shown in the diagram, the SIC function, therefore performed by the signal improvement module 125, causes the transition from the bus level of the data phase 452 to the recessive level of the arbitration phase 451 to be accelerated. The second trigger condition for performing the SIC function is independent of how the communication control device 11 signals the change in operating mode to the transmitting / receiving device.

[0134] This allows us to advantageously ensure that the receiving node can sample the DAH bit as a logic 1.

[0135] Another advantage of the design scheme described for the signal improvement module 125 is that a larger CAN topology can be used due to the accelerated transition from the level of the data phase 452 to the recessive level of the arbitration phase 451 caused by the SIC function. Thus, the signal improvement module 125 can also advantageously achieve the goal that the described level transitions do not need to be considered separately when designing these topologies.

[0136] If the operation mode switching of transmitting / receiving devices 12 and 32 should not be performed, then no operation will occur for... Figure 6 The transmitted signal TxD is encoded using pulse width modulation (PWM) signal notification. Therefore, when the transmitting / receiving devices 12 and 32 act as transmitting nodes, they drive the signal as a differential voltage VDIFF onto bus 40. Figure 6The transmitted signal TxD is the same. Since no PWM encoding is performed and therefore no decoding is performed, no one-time phase error T_P is generated between the transmitted signal TxD_TC and the transmitted signal TxD in the transmitting / receiving devices 12 and 32.

[0137] Figure 14 A user station 10A with a phase error compensation module 15A according to a second embodiment is shown. Except for the phase error compensation module 15A, the user station 10A has the same structure as the user station 10 according to the previous embodiment.

[0138] The phase error compensation module 15A is designed to tolerate a value of DAH=0 when the user station 10A acts as the receiving node.

[0139] In other words, if, despite the fact that in signal RxD_E, according to Figure 13 The DAH bit must actually be logic 1, but in Figure 12 If the DAH bit in the signal RxD is sampled as logic 0, then the phase error compensation module 15A tolerates this DAH bit.

[0140] However, the phase error compensation module 15A is designed not to evaluate samples of the DAH and AH1 bits as logic 1s as format errors. In this case, such sample frames are evaluated as erroneous and / or considered invalid and discarded. Furthermore, error frames 47 can be sent to bus 40.

[0141] Furthermore, when the DAH bit or AH1 bit is sampled as logic 1, hard synchronization or synchronization is activated. Therefore, this is also... Figure 12 Synchronization is performed at time point t_SY, and this synchronization can correct arbitrarily large phase errors.

[0142] In this way, it is also ensured that: after the user station 10A, as the receiving node, switches from the data phase 452 to the arbitration phase 451, it compensates for the phase jump caused by the shortened transit time and the possible loss of the AH1 bit through appropriate synchronization.

[0143] The advantage of this phase transition compensation in the second embodiment is that more time is available for the transition on bus 40 from the level of data phase 452 to the recessive level of arbitration phase 451.

[0144] Figure 15 A user station 10B with a phase error compensation module 15B according to a third embodiment is shown. Except for the phase error compensation module 15B, the user station 10B has the same structure as the user station 10 according to the first embodiment.

[0145] Phase error compensation module 15B is designed to ignore the DAH bit when user station 10B acts as a receiving node. Furthermore, phase error compensation module 15A is designed to insert a modified DAS field 1521 into frame 450 when user station 10B acts as a transmitting node, such as... Figure 16 As shown in the image.

[0146] The modified DAS field 1521 has five bits: DAH, AH1, AH1B, AL1, and AH2. Therefore, it differs from... Figure 2 The DAS field, DAS field 1521 has an additional bit in the frame format, namely bit AH1B.

[0147] Furthermore, the phase error compensation module 15B is designed to tolerate one or two consecutively sampled bits with a logic value of 1, starting from the bit position of AH1, when the user station 10B acts as the receiving node. When the AH1 bit is sampled as a logic 1, the phase error compensation module 15B activates hard synchronization. This hard synchronization is performed at time point t_SY, as follows... Figure 12 As shown in the image.

[0148] However, the phase error compensation module 15B is designed to evaluate samples of the AH1 bit as logic 0 as format errors. In this case, such sample frames are evaluated as erroneous and / or considered invalid and discarded. Furthermore, error frames 47 can be sent to bus 40.

[0149] The advantage of this phase transition compensation is that more time is available for the transition on bus 40 from the level of data phase 452 to the recessive level 402 of arbitration phase 451. However, the DAS field 1521 incurs more control bit overhead due to the additional bit AH1B. As a result, the net data rate is reduced compared to the previous embodiment.

[0150] All the above-described design schemes for the user stations 10, 20, and 30 of the bus system 1 and the methods executed therein can be applied individually or in all possible combinations. In particular, all features of the above embodiments and / or their modifications can be combined arbitrarily. Additionally or alternatively, the following modifications are particularly conceivable.

[0151] Even though this invention has been described previously using a CAN bus system as an example, it can be applied to any communication network and / or communication method that uses two different communication phases, in which the bus states generated for these different communication phases differ. In particular, this invention can be used to develop other serial bus networks, such as Ethernet and / or 100Base-T1 Ethernet, fieldbus systems, etc.

[0152] The bus system 1 according to these embodiments can in particular be a communication network in which data can be serially transmitted at two different bit rates. It is advantageous, but not mandatory, that exclusive, conflict-free access to the common channel by user stations 10, 20, and 30 is ensured in the bus system 1, at least within a certain time interval.

[0153] Of course, the ADS field 1510 may have more bits than the bits ADH to DH2 described in these embodiments. Alternatively or additionally, the DAS field 1520 may have more bits than the bits DAH to AH2 described in these embodiments.

[0154] The number and layout of user stations 10, 20, and 30 in the bus system 1 of these embodiments are arbitrary. In particular, user station 20 in bus system 1 can be omitted. It is possible that one or more user stations of user station 10 or 30 exist in bus system 1. It is conceivable that all user stations in bus system 1 are designed to be identical, i.e., only user station 10 or only user station 30 exist.

Claims

1. A user station (10; 30) for a serial bus system (1), the user station having: A communication control device (11; 31) is configured to control communication between the user station (10; 20; 30) and at least one other user station (10; 20; 30) of the bus system (1), and to evaluate a signal (VDIFF) received from the bus (40) of the bus system (1), wherein the bit time (t_bt1) in the first communication phase (451) may differ from the bit time (t_bt2) in the second communication phase (452). in, The communication control device (11; 31) is designed to sample and evaluate a signal (VDIFF) received from the bus (40) according to a predetermined frame (450; 450A), the signal being based on a transmission signal (TxD_TC) generated by another user station (10; 20; 30). In the predetermined frame (450; 450A), the predetermined field (1520; 1521) indicating the transition from the second communication stage (452) to the first communication stage (451) has two or three bits with a logic value of 1 between the beginning of the predetermined field (1520; 1521) and the subsequent falling edge. The communication control device (11; 31) is designed to evaluate the frame sampled by the communication control device (11; 31) from the signal (VDIFF) received from the bus (40) as a predetermined frame (450; 450A) and thus as valid with respect to the predetermined field (1520; 1521), regardless of whether only one bit or two consecutive bits with a logic value of 1 are sampled in the signal (VDIFF) received from the bus (40) between the start and subsequent falling edge of the field. The communication control device (11; 31) is designed to perform synchronization at the falling edge of the predetermined field (1520; 1521).

2. The user station (10; 30) according to claim 1, in, The predetermined field (1520) has four bits, which have the bit time (t_bt1) of the first communication phase (451), and The predetermined field (1520) has a bit sequence with a logical value of 1101, and The communication control device (11; 31) is designed such that, after sampling a bit with a logic value of 1 in the signal (VDIFF) received from the bus (40) between the start and subsequent falling edge of the field, the next bit in the signal (VDIFF) received from the bus (40) with a logic value of 0 and the third bit of the expected bit sequence 1101 sampled at the latest is evaluated as the third bit (AL1) of the expected bit sequence 1101.

3. The user station (10; 30) according to claim 1 or 2, wherein, The communication control device (11; 31) is designed to evaluate a frame sampled by the communication control device (11; 31) from the signal (VDIFF) received from the bus (40) as erroneous if the first bit (DAH) of the predetermined field (1520) has not been sampled as logic 1.

4. The user station (10; 30) according to claim 1 or 2, wherein, The communication control device (11; 31) is designed to activate hard synchronization if the first bit (DAH) of the predetermined field (1520) is sampled as logic 1.

5. The user station (10; 30) according to claim 2, wherein, The communication control device (11; 31) is designed to evaluate a frame sampled by the communication control device (11; 31) from the signal (VDIFF) received from the bus (40) as erroneous if neither the first bit (DAH) nor the second bit (AH1) of the predetermined field (1520) has been sampled as logic 1.

6. The user station (10; 30) according to claim 5, wherein, The communication control device (11; 31) is designed as follows: If the first bit (DAH) of the predetermined field (1520) has been sampled as logic 0, and the second bit (AH1) of the predetermined field (1520) has been sampled as logic 1, or If the first bit (DAH) of the predetermined field (1520) has been sampled as logic 1, and the second bit (AH1) of the predetermined field (1520) has been sampled as logic 0, The frame sampled by the communication control device (11; 31) from the signal (VDIFF) received from the bus (40) is not evaluated as having an error, but is evaluated as valid with respect to the predetermined field (1520).

7. The user station (10; 30) according to claim 5 or 6, wherein, The communication control device (11; 31) is designed to activate hard synchronization or synchronization if the first bit (DAH) of the predetermined field (1520) is sampled as logic 1 or if the second bit (AH1) of the predetermined field (1520) is sampled as logic 1.

8. The user station (10; 30) according to claim 1, in, The predetermined field (1521) has five bits, which have the bit time (t_bt1) of the first communication phase (451). The predetermined field (1521) has a bit sequence with a logical value of 11101, and The communication control device (11; 31) is designed such that, after sampling the second bit of the bit sequence in the signal (VDIFF) received from the bus (40) to a bit with a logic value of 1, the next bit in the signal (VDIFF) received from the bus (40) that is sampled with a logic value of 0 and is the latest expected bit sequence 11101 to be sampled is evaluated as the fourth bit (AL1) of the expected bit sequence 11101.

9. The user station (10; 30) according to claim 8, in, The communication control device (11; 31) is designed to: ignore the sampled value of the first bit (DAH) of the predetermined field (1521) in the frame sampled from the signal (VDIFF) received by the communication control device (11; 31) from the bus (40), and evaluate any value for the third bit (AH1) of the predetermined field (1521) as error-free, and The communication control device (11; 31) is designed to evaluate a frame sampled from the signal (VDIFF) received by the communication control device (11; 31) from the bus (40) as having an error if the second bit (AH1) of the predetermined field (1521) has been sampled as logic 0.

10. The user station (10; 30) according to claim 8 or 9, wherein, The communication control device (11; 31) is designed to activate hard synchronization if the second bit (AH1) of the predetermined field (1521) is sampled as logic 1.

11. The user station (10; 30) according to any one of claims 1, 2, 5, 6, 8 or 9, The user station also has a transmitting / receiving device (12; 32) for transmitting a transmitting signal (TxD) to the bus (40) of the bus system (1) and / or for receiving a signal (VDIFF) from the bus (40) of the bus system (1).

12. The user station (10; 30) according to claim 11, in, The communication control device (11; 31) is designed to generate the transmitted signal (TxD), and The communication control device (11) is designed to signal the transmitting / receiving device (12; 32) by means of pulse width modulation in the transmitted signal (TxD) that the transmitting / receiving device (12; 32) wants to switch its operating mode to an operating mode for transmitting in the first communication phase (451) or to an operating mode for transmitting in the second communication phase (452).

13. The user station (10; 30) according to claim 11, The user station also has a signal improvement module (125) for accelerating the transition on the bus (40) from a dominant bus level (401) to a recessive bus level (402) that can be covered by the dominant bus level (401) during the first communication phase (451). in, The transmitting / receiving device (12; 22; 32) is designed such that if the user station (10; 30) is the sender of a transmit signal (TxD) to the bus (40), and the transmitting / receiving device (12; 22; 32) switches from an operating mode in which the communication control device (11; 31) transmits the transmit signal (TxD) to the bus (40) of the bus system (1) in the second communication phase (452) to an operating mode in which the communication control device (11; 31) transmits the transmit signal (TxD) to the bus (40) of the bus system (1) in the first communication phase (451), then the signal improvement module (125) is activated, additionally for accelerating the transition from one of the bus levels in the second communication phase (452) to the recessive level in the first communication phase (451).

14. The user station (10; 30) according to any one of claims 1, 2, 5, 6, 8 or 9, The predetermined frame (450) is constructed in compatibility with CAN FD, and During the first communication phase (451), it is negotiated which of the user stations (10, 20, 30) of the bus system (1) will obtain at least temporary exclusive, conflict-free access to the bus (40) in the subsequent second communication phase (452).

15. A bus system (1), the bus system having: Bus (40); and At least two user stations (10; 20; 30) are connected to each other via the bus (40) so that the at least two user stations can communicate serially with each other, and at least one of the at least two user stations (10; 30) is a user station (10; 30) according to any one of the preceding claims.

16. A method for communication in a serial bus system (1), wherein the method is performed using a user station (10; 30) of the bus system (1), the user station having a communication control device (11; 31), wherein the method comprises the following steps: Using the communication control device (11; 31), the communication between the user station (10; 20; 30) and at least one other user station (10; 20; 30) of the bus system (1) is controlled, and the signal (VDIFF) received from the bus (40) of the bus system (1) is evaluated, in which the bit time (t_bt1) in the first communication phase (451) can be different from the bit time (t_bt2) in the second communication phase (452). in, The communication control device (11; 31) samples and evaluates the signal (VDIFF) received from the bus (40) according to a predetermined frame (450; 450A), the signal being based on a transmission signal (TxD_TC) generated by another user station (10; 20; 30). In the predetermined frame (450; 450A), the predetermined field (1520; 1521) indicating the transition from the second communication stage (452) to the first communication stage (451) has two or three bits with a logic value of 1 between the start and the subsequent falling edge. Wherein, regardless of whether only one bit or two consecutive bits with a logic value of 1 are sampled in the signal (VDIFF) received from the bus (40) between the start and subsequent falling edge of the field, the communication control device (11; 31) evaluates the frame sampled from the signal (VDIFF) received from the bus (40) as a predetermined frame (450; 450A) and thus evaluates it as valid with respect to the predetermined field (1520; 1521), and The communication control device (11; 31) performs synchronization at the falling edge of the predetermined field (1520; 1521).

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