Memory device and method of manufacturing the same

Abstract

The present application relates to memory devices and methods of manufacturing the same. A memory device includes a stack structure and main plugs passing through the stack structure, the main plugs being spaced apart from each other in a first direction. The memory device further includes a separation pattern separating the main plugs in a second direction and a slit pattern separating the stack structure into a first memory block and a second memory block, the slit pattern having an elliptical shape.

Description

Technical Field

[0001] This disclosure relates to a memory device and a method for manufacturing the same, and more specifically, to a three-dimensional memory device and a method for manufacturing the same. Background Technology

[0002] Memory devices can be classified as volatile memory devices that lose stored data when power is interrupted, or non-volatile memory devices that retain stored data even when power is interrupted.

[0003] Non-volatile memory devices may include NAND flash memory, NOR flash memory, resistive random access memory (ReRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-torque random access memory (STT-RAM), etc.

[0004] A NAND flash memory system may include a memory device configured to store data and a controller configured to control the memory device. The memory device may include an array of memory cells for storing data and peripheral circuitry configured to perform programming, reading, or erasing operations in response to commands sent from the controller.

[0005] A memory cell array may include multiple memory blocks, and each of the multiple memory blocks may include multiple memory cells.

[0006] As memory devices become more integrated, there is a need for memory devices capable of storing large amounts of data, and a need to simplify manufacturing processes to reduce manufacturing costs. Summary of the Invention

[0007] Embodiments of this disclosure relate to a memory device capable of improving integration and a simplified method for manufacturing the memory device.

[0008] According to an embodiment of the present disclosure, a memory device includes: a stacked structure; main plugs passing through the stacked structure and arranged to be spaced apart from each other in a first direction; a separation pattern separating the main plugs in a second direction; and a slit pattern separating the stacked structure into a first memory block and a second memory block, the slit pattern having an elliptical shape.

[0009] According to an embodiment of the present disclosure, a memory device includes: a stacked structure formed on a source line; main plugs passing through the stacked structure and arranged to be spaced apart from each other in a first direction; a separation pattern separating the main plugs in a second direction; and a slit separating the stacked structure into a first memory block and a second memory block, the slit including a slit pattern having an elliptical shape.

[0010] According to an embodiment of this disclosure, a method of manufacturing a memory device includes the following steps: alternately stacking a first material layer and a second material layer on a lower structure defining a cell region and a connection region; forming a main plug through the first material layer and the second material layer in the cell region; forming a separation hole that separates the main plug into a first sub-plug and a second sub-plug; forming a slit hole in the connection region while forming the separation hole; forming a separation pattern in the separation hole; removing the second material layer exposed through the slit hole; forming a conductive layer between the first material layers where the second material layer has been removed; removing a portion of the conductive layer adjacent to the slit hole; forming an insulating layer along the side surface of the slit hole where the conductive layer has been partially removed; and forming a source contact in the slit hole where the insulating layer has been formed.

[0011] According to this technology, the integration density of memory devices can be increased, and the manufacturing steps of memory devices can be simplified. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0013] Figure 2 This is a diagram showing the configuration of the memory cell array and peripheral circuitry.

[0014] Figure 3 This is a diagram showing the structure of a memory cell array.

[0015] Figure 4 This is a diagram illustrating the layout of a memory device according to an embodiment of the present disclosure.

[0016] Figure 5 This illustrates the layout of the plug region structure according to an embodiment of the present disclosure.

[0017] Figure 6 This is a cross-sectional view showing the structure of the plug region according to an embodiment of the present disclosure.

[0018] Figure 7 This illustrates the layout of the slit region structure according to an embodiment of the present disclosure.

[0019] Figure 8A and Figure 8B This is a cross-sectional view showing the structure of the slit region according to an embodiment of the present disclosure.

[0020] Figure 9 This is a perspective view showing the structure of the slit and storage block according to an embodiment of the present disclosure.

[0021] Figures 10A to 10N This is a layout illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure.

[0022] Figures 11A to 11N This is a cross-sectional view illustrating a method for manufacturing a memory device according to an embodiment of the present disclosure.

[0023] Figure 12 This is a diagram illustrating a solid-state drive (SSD) system using the memory device disclosed herein.

[0024] Figure 13 This is a diagram illustrating a memory card system using a memory device according to the present disclosure. Detailed Implementation

[0025] The specific structure and function of the embodiments are disclosed in this specification or application to teach the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be performed in various forms and should not be construed as limited to the specific embodiments described herein.

[0026] Figure 1 This is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0027] Reference Figure 1 The memory device 100 may include peripheral circuitry 190 and a memory cell array 110.

[0028] The peripheral circuitry 190 can be configured to perform programming and verification operations for storing data in the memory cell array 110, read operations for outputting data stored in the memory cell array 110, or erase operations for erasing data stored in the memory cell array 110. The peripheral circuitry 190 may include a voltage generation circuitry 130, a row decoder 120, a source line driver 140, a control circuitry 150, a page buffer 160, a column decoder 170, and an input-output circuitry 180.

[0029] The memory cell array 110 may include a plurality of memory cells for storing data. In one embodiment, the memory cell array 110 may include a three-dimensional memory cell array. The plurality of memory cells may store single-bit or two-bit or more-bit data according to a programming method. The plurality of memory cells may be configured into multiple strings. The memory cells included in each string are electrically connected to each other via channels. The channels included in the strings are connected to the page buffer 160 via bit lines BL.

[0030] The voltage generating circuit 130 can generate various operating voltages Vop for programming, reading, or erasing operations in response to the operation signal OP_S. For example, the voltage generating circuit 130 can be configured to selectively generate and output operating voltages Vop, including programming voltage, verification voltage, pass voltage, read voltage, erase voltage, etc.

[0031] The row decoder 120 can be connected to the memory cell array 110 via multiple drain select lines DSL, multiple word lines WL, and multiple source select lines SSL. The row decoder 120 can send an operating voltage Vop to the multiple drain select lines DSL, multiple word lines WL, and multiple source select lines SSL in response to the row address RADD.

[0032] The source line driver 140 can send a source voltage Vsl to the memory cell array 110 in response to a source line control signal SL_S. For example, the source voltage Vsl can be sent to a source line connected to the memory cell array.

[0033] Control circuit 150 can output operation signal OP_S, row address RADD, source line control signal SL_S, page buffer control signal PB_S and column address CADD in response to command CMD and address ADD.

[0034] Page buffer 160 can be connected to memory cell array 110 via bit lines BL. Page buffer 160 can temporarily store data DATA received via multiple bit lines BL in response to page buffer control signal PB_S. Page buffer 160 can sense the voltage or current of multiple bit lines BL during read operations.

[0035] Column decoder 170 can send data DATA input from input-output circuit 180 to page buffer 160 in response to column address CADD, or send data DATA stored in page buffer 160 to input-output circuit 180. Column decoder 170 can send and receive data DATA from input-output circuit 180 via column line CLL, and can send and receive data DATA from page buffer 160 via data line DTL.

[0036] The input-output circuit 180 can send commands CMD and addresses ADD received from an external device (e.g., a controller) connected to the memory device 100 to the control circuit 150, and output data received from the column decoder 170 to the external device.

[0037] Figure 2 This is a diagram showing the configuration of the memory cell array 110 and the peripheral circuitry 190.

[0038] Reference Figure 2 The memory cell array 110 can be stacked on the peripheral circuitry 190. For example, when the substrate is formed along the XY plane, the peripheral circuitry 190 can be stacked from the substrate in the Z direction, and the memory cell array 110 can be stacked on the peripheral circuitry 190.

[0039] Figure 3This is a diagram showing the structure of the memory cell array 110.

[0040] Reference Figure 3 The memory cell array 110 may include first memory blocks BLK1 to i-th memory blocks BLKi (i is a positive integer). First memory blocks BLK1 to i-th memory blocks BLKi may be arranged spaced apart from each other in the Y direction and may be commonly connected to first bit lines BL1 to j-th bit lines BLj. For example, first bit lines BL1 to j-th bit lines BLj may extend along the Y direction and may be spaced apart from each other along the X direction. First memory blocks BLK1 to i-th memory blocks BLKi may be separated from each other by a slit SLT.

[0041] Figure 4 This is a diagram illustrating the layout of a memory device according to an embodiment of the present disclosure.

[0042] Reference Figure 4 The (n-1)th memory block BLK(n-1), the nth memory block BLKn, and the (n+1)th memory block BLK(n+1) included in the memory device may be spaced apart from each other in the Y direction. The (n-1)th memory block BLK(n-1), the nth memory block BLKn, and the (n+1)th memory block BLK(n+1) may be configured identically to each other and may be separated from each other by a slit SLT.

[0043] Since the (n-1)th storage block BLK(n-1), the nth storage block BLKn, and the (n+1)th storage block BLK(n+1) can be configured identically to each other, the nth storage block BLKn is described as an example among the (n-1)th storage block BLK(n-1), the nth storage block BLKn, and the (n+1)th storage block BLK(n+1).

[0044] The nth memory block BLKn may include multiple main plugs Pm, each containing memory cells. Each main plug Pm may include a first sub-plug 1Ps and a second sub-plug 2Ps separated by a separation pattern SP. Figure 4The diagram illustrates a structure where two main plugs Pm are separated into first sub-plugs 1Ps and second sub-plugs 2Ps by a separation pattern SP. However, the number of main plugs Pm separated by a separation pattern SP is not limited to the number shown in the diagram. For example, in different embodiments, one main plug Pm can be separated into first sub-plugs 1Ps and second sub-plugs 2Ps by a separation pattern SP, or each of three main plugs Pm can be separated into first sub-plugs 1Ps and second sub-plugs 2Ps by a separation pattern SP. The separation pattern SP may have an elliptical shape. The major axis of the separation pattern SP is in the X direction, and the minor axis is in the Y direction. In the embodiments described below, the structure where each of the two main plugs Pm is separated into first sub-plugs 1Ps and second sub-plugs 2Ps by a separation pattern SP is described.

[0045] Because different bit lines are connected to the first sub-plug 1Ps and the second sub-plug 2Ps, the memory cells included in the first sub-plug 1Ps and the second sub-plug 2Ps can be configured with different strings. For example, the first sub-plug 1Ps can be connected to the first bit line BL1 via the bit line contact BLC, and the second sub-plug 2Ps can be connected to the second bit line BL2 via the bit line contact BLC.

[0046] At least one drain separation pattern DSP can be formed in each of the (n-1)th memory block BLK(n-1) to the (n+1)th memory block BLK(n+1). The drain separation pattern DSP can be a pattern that separates the drain select lines included in the memory block. For example, the nth memory block BLKn may include first drain select lines DSL1 to third drain select lines DSL3 that are separated from each other by the drain separation pattern DSP. Since the first drain select lines DSL1 to third drain select lines DSL3 are separated from each other by the drain separation pattern DSP, different voltages can be applied to the first drain select lines DSL1 to third drain select lines DSL3.

[0047] exist Figure 4 In the layout shown, the drain separation pattern DSP is formed in the region that overlaps with the separation pattern SP along the X direction, but in other embodiments, the drain separation pattern DSP may be formed in the region that does not overlap with the separation pattern SP.

[0048] Since the (n-1)th memory block BLK(n-1) to the (n+1)th memory block BLK(n+1) are separated from each other by a slit SLT, the gating lines included in different memory blocks can be separated from each other by the slit SLT. For example, the gating lines included in the (n-1)th memory block BLK(n-1) and the gating lines included in the nth memory block BLKn can be separated from each other by the slit SLT.

[0049] The slit SLT according to this embodiment may include a plurality of slit patterns SPs. The layout of the slit patterns SPs may be the same as the layout of the separation patterns SP of the main plug Pm. Therefore, each slit pattern SPs may have an elliptical shape. The major axis of each slit pattern SPs is the X direction, and the minor axis is the Y direction. For example, when the length of the separation pattern SP in the X direction is a first length L1, the slit patterns SPs may also have a first length L1. When the width of the separation pattern SP in the Y direction is a first width W1, the slit patterns SPs may also have a first width W1. When the distance between adjacent separation patterns SPs in the Y direction is a first distance T1, the distance between the slit patterns SPs and the separation patterns SPs may also be a first distance T1.

[0050] Referring to the layout of the slit patterns SPs, the slit patterns SPs in the X direction should be spaced apart from each other, but the slit patterns SPs should touch each other at their lower parts. Here, the lower part of the slit patterns SPs refers to the lower part in the Z direction. Figure 4 The layout does not show the slit patterns SPs in contact with each other. For example, see later. Figure 8B and Figure 9 Describe the structure of slit patterns SPs through which they contact each other (CNS).

[0051] The following detailed description includes the plug region 41 of the memory cell and the slit region 42 of the separate memory block.

[0052] Figure 5 This shows the layout of the structure of the plug region 41 according to an embodiment of the present disclosure.

[0053] Reference Figure 5 A first main plug 1Pm, a second main plug 2Pm, and a separation pattern SP can be formed in the plug region 41. The first main plug 1Pm and the second main plug 2Pm can be arranged to be spaced apart from each other in the X direction, and each of the first main plug 1Pm and the second main plug 2Pm can be configured to extend along the Y direction. The separation pattern SP can extend along the X direction to separate each of the first main plug 1Pm and the second main plug 2Pm.

[0054] The first main plug 1Pm may include a first sub-plug 1Ps and a second sub-plug 2Ps separated by a separation pattern SP, and the second main plug 2Pm may include a third sub-plug 3Ps and a fourth sub-plug 4Ps separated by a separation pattern SP. The third sub-plug 3Ps may be formed with the same structure as the first sub-plug 1Ps, and the fourth sub-plug 4Ps may be formed with the same structure as the second sub-plug 2Ps. The structure of the first sub-plug 1Ps may be symmetrical with respect to the separation pattern SP and the structure of the second sub-plug 2Ps, and the structure of the third sub-plug 3Ps may be symmetrical with respect to the separation pattern SP and the structure of the fourth sub-plug 4Ps.

[0055] Since the first sub-plugs 1Ps to the fourth sub-plugs 4Ps are configured similarly to each other, the structure of the first sub-plug 1Ps among the first sub-plugs 1Ps to the fourth sub-plugs 4Ps is described as an example below.

[0056] The first sub-plug 1Ps may include a capping layer CAP, a channel layer CH, a tunnel insulating layer TO, a charge trapping layer CT, and a barrier layer BX. The capping layer CAP may be formed at the top end of the first sub-plug 1Ps formed vertically from the substrate and can be used to improve the electrical characteristics of the drain-select transistor. For example, the capping layer CAP may be formed of a conductive material. For example, the capping layer CAP may be formed of a doped polysilicon layer. Although Figure 5 Not shown, a core pillar may be formed below the capping layer CAP. For example, the core pillar may be formed of an insulating or conductive material. A channel layer CH may be formed around the capping layer CAP and the core pillar, and may be formed of a conductive material. For example, the channel layer CH may be formed of a polysilicon layer. A tunnel insulating layer TO may be formed around the channel layer CH, and may be formed of an insulating material. For example, the tunnel insulating layer TO may be formed of an oxide layer or a silicon oxide layer. A charge trapping layer CT may be formed around the tunnel insulating layer TO, and may be formed of a material capable of trapping electrons. For example, the charge trapping layer CT may be formed of a nitride layer. A barrier layer BX may be formed around the charge trapping layer CT, and may be formed of an insulating material. For example, the barrier layer BX may be formed of an oxide layer or a silicon oxide layer.

[0057] Although not shown in the figure, the first sub-plugs 1Ps to the fourth sub-plugs 4Ps can be electrically connected to different bit lines via different bit line contacts (BLC). For example, the channel layer CH of the first sub-plug 1Ps can be connected to the first bit line via a bit line contact, the channel layer CH of the second sub-plug 2Ps can be connected to the second bit line via a bit line contact, the channel layer CH of the third sub-plug 3Ps can be connected to the third bit line via a bit line contact, and the channel layer CH of the fourth sub-plug 4Ps can be connected to the fourth bit line via a bit line contact.

[0058] Reference Figure 6 Describe in detail the structure of the first sub-plug 1Ps and the second sub-plug 2Ps.

[0059] Figure 6 This is a cross-sectional view showing the structure of the plug region 41 according to an embodiment of the present disclosure.

[0060] Reference Figure 5 and Figure 6 The diagram shows a cross-section of the first sub-plug 1Ps and the second sub-plug 2Ps taken along the A1-A2 direction.

[0061] First sub-plugs 1Ps and second sub-plugs 2Ps, along with a separation pattern SP, can be formed vertically on the source line SL. The separation pattern SP can be formed between the first sub-plugs 1Ps and second sub-plugs 2Ps, and the capping layer CAP, core pillar CP, channel layer CH, tunnel insulation layer TO, charge trapping layer CT, and barrier layer BX, all contained in the first and second sub-plugs 1Ps and 2Ps, are separated by the separation pattern SP. A gate line GL can surround the first sub-plugs 1Ps, second sub-plugs 2Ps, and the separation pattern SP, and can be spaced apart from each other in the Z direction. The lower portion of the channel layer CH can contact the source line SL, and the upper portion of the channel layer CH can contact the bit line contact BLC.

[0062] In the gate line GL, the line formed at the bottom can be used as the source select line SSL, and the line formed at the top can be used as the drain select line DSL. The source select line SSL can be connected to the gate of the source select transistor SST, and the drain select line DSL can be connected to the gate of the drain select transistor DST. The source select transistor SST can be configured to be electrically connected or disconnected between the source line SL and the channel layer CH in the string, and the drain select transistor DST can be configured to be electrically connected or disconnected between the bit line and the channel layer CH in the string. In the gate line GL, the line formed between the source select line SSL and the drain select line DSL can be used as the word line WL. The word line WL can be connected to the gate of the memory cell MC.

[0063] Bit line contact BLC can be formed on the channel layer CH of the first sub-plug 1Ps, and bit line BL can be formed on bit line contact BLC.

[0064] Figure 7 This shows the layout of the structure of the slit region 42 according to an embodiment of the present disclosure.

[0065] Reference Figure 7 The slit SLT formed in slit region 42 may include a plurality of slit patterns SPs. Each of the plurality of slit patterns SPs may include an insulating layer IS and a source contact SC. The source contact SC may contact a source line formed beneath the memory block, and the insulating layer IS may be formed to electrically disconnect the source contact SC and the gate line. For example, the insulating layer IS may be formed to surround the periphery of the source contact SC. The insulating layer IS may be formed of an oxide layer or a silicon oxide layer. The source contact SC may be formed of a conductive material. For example, the source contact SC may be formed of doped polysilicon or tungsten.

[0066] The uppermost ends of multiple slit patterns SPs may be spaced apart from each other, but multiple slit patterns SPs may be connected to each other downward in the Z direction. The structure of the slit patterns SPs is described in more detail with reference to cross-sections taken along the B1-B2 direction and cross-sections taken along the C1-C2 direction.

[0067] Figure 8A and Figure 8B This is a cross-sectional view showing the structure of the slit region according to an embodiment of the present disclosure.

[0068] Figure 8A Show Figure 7 The B1-B2 cross section.

[0069] Reference Figure 7 and Figure 8A The slit SLT may include source contacts SC and an insulating layer IS. The source contacts SC may be formed vertically on source lines SL, and the insulating layer IS may be formed around the periphery of the source contacts SC. The gate lines GL included in the (n-1)th memory block BLK(n-1) and the nth memory block BLKn may be separated from each other by the slit SLT. For example, the gate lines GL may include a source select line SSL, a word line WL, and a drain select line DSL; and the source select line SSL, word line WL, and drain select line DSL may be included in each of the (n-1)th memory block BLK(n-1) and the nth memory block BLKn. The insulating layer IS may be formed around the source contacts SC such that the source contacts SC and the gate lines GL block each other. The insulating layer IS formed between the gate lines GL and the source contacts SC may be formed thicker than the insulating layer IS formed between the gate lines GL.

[0070] Figure 8B Show Figure 7 The cross-sections C1-C2.

[0071] Reference Figure 7 and Figure 8B Slit patterns SPs can be formed vertically from source lines SL, and adjacent slit patterns SPs can be connected to each other via connecting structures CNS. For example, the connecting structures CNS can be formed in a ladder shape 81 between adjacent slit patterns SPs. Figure 8B As shown, each connection structure CNS represents a rung of a ladder. For example, connection structures CNS may be formed for each layer forming the gate line GL. A connection structure CNS may include a conductive pattern SCP formed of the same material as the source contacts SC of adjacent slit patterns SPs, and an insulating pattern ISP surrounding the conductive pattern SCP. The insulating pattern ISP may be formed of the same material as the insulating layer IS. Interlayer insulation layers may be formed between the connection structures CNS.

[0072] Figure 9 This is a perspective view showing the structure of the slit and storage block according to an embodiment of the present disclosure.

[0073] Reference Figure 9The (n-1)th memory block BLK(n-1) and the nth memory block BLKn, which are formed in a three-dimensional structure, may include a plurality of sub-plugs 1Ps to 4Ps formed in the vertical direction from a substrate (not shown). For example, the first sub-plug 1Ps and the second sub-plug 2Ps can be separated from each other by a separation pattern SP, and the third sub-plug 3Ps and the fourth sub-plug 4Ps can also be separated from each other by a separation pattern SP.

[0074] A slit SLT formed between the (n-1)th memory block BLK(n-1) and the nth memory block BLKn can be formed from a substrate (not shown) in the vertical direction and can extend along the X direction. The slit SLT may include slit patterns SPs spaced apart from each other in the X direction and a connection structure CNS connecting the slit patterns SPs to each other. The slit patterns SPs and the connection structure CNS may include source contacts SC and an insulating layer IS surrounding the source contacts SC.

[0075] Figures 10A to 10N This is a layout illustrating a method for manufacturing a memory device according to an embodiment of the present disclosure. Figures 11A to 11N This is a cross-sectional view illustrating a method for manufacturing a memory device according to an embodiment of the present disclosure.

[0076] Figures 11A to 11N Show Figures 10A to 10N The cross-sectional structure of cross-sections D1-D2.

[0077] Reference Figure 10A and Figure 11A A first source layer 1S and a first sacrificial layer 1F may be stacked on a lower structure (not shown). The lower structure (not shown) may be a structure including a substrate or peripheral circuitry. Since the first source layer 1S is used as a source line, the first source layer 1S may be formed of a conductive material. For example, the first source layer 1S may be formed of a conductive material such as polysilicon, tungsten, or nickel. The first sacrificial layer 1F may be formed of a material that has etch selectivity relative to the first source layer 1S. An etch stop layer ST may be formed for a portion of the first sacrificial layer 1F. The etch stop layer ST may be a stop layer used to prevent over-etching during an etching process that forms a slit hole in a slit region. The etch stop layer ST may be formed of a conductive material such as tungsten. When the (n-1)th memory block BLK(n-1) and the nth memory block BLKn are arranged to be spaced apart from each other in the Y direction, the etch stop layer ST may be formed to extend in the X direction in the boundary region BR between the (n-1)th memory block BLK(n-1) and the nth memory block BLKn.

[0078] Reference Figure 10B and Figure 11BA second source layer 2S can be formed on the first sacrificial layer 1F and the etch stop layer ST. The second source layer 2S can be formed of the same material as the first source layer 1S. Although not shown in the figure, to protect the first source layer 1S and the second source layer 2S in subsequent processes, buffer layers can be further formed between the first source layer 1S and the first sacrificial layer 1F, and between the second source layer 2S and the first sacrificial layer 1F. For example, the buffer layer can be formed of an oxide layer. Subsequently, a first material layer 1M and a second material layer 2M can be alternately stacked on the second source layer 2S. For example, when the first material layer 1M is formed on the second source layer 2S, the second material layer 2M can be formed on the first material layer 1M, and the first material layer 1M can then be formed on the second material layer 2M. The first material layer 1M can be formed of an insulating material. For example, the first material layer 1M can be formed of an oxide layer or a silicon oxide layer. The second material layer 2M can be formed of a material that can be selectively removed in subsequent processes. Therefore, the second material layer 2M can be formed of a material with an etching selectivity different from that of the first material layer 1M. For example, the second material layer 2M can be formed of a nitride layer. In the structure of the first material layer 1M and the second material layer 2M stacked, the first material layer 1M can be formed at the bottommost and topmost positions.

[0079] Reference Figure 10C and Figure 11C A vertical via VH exposing the first source layer 1S can be formed in the cell regions CR of the (n-1)th memory block BLK(n-1) and the nth memory block BLKn. For example, an etching process for removing a portion of the first material layer 1M and the second material layer 2M, and an etching process for removing a portion of the second source layer 2S, the first sacrificial layer 1F, and a portion of the first source layer 1S can be performed. The etching process can be performed as a dry etching process to form the vertical via VH in a direction perpendicular to the substrate. The vertical via VH can be formed in the region for forming the main plug. The major axis of the vertical via VH is in the Y direction, and the minor axis is in the X direction. When the etching process for forming the vertical via VH is completed, the first source layer 1S can be exposed through the lower surface of the vertical via VH, and the first material layer 1M and the second material layer 2M can be exposed through the side surfaces of the vertical via VH.

[0080] Reference Figure 10D and Figure 11DA main plug Pm can be formed within a vertical via VH. The main plug Pm may include a barrier layer BX, a charge trapping layer CT, a tunnel insulating layer TO, a channel layer CH, a core pillar CP, and a capping layer CAP. For example, the barrier layer BX can be formed along the inner surface of the vertical via VH. Since the barrier layer BX does not fill the interior of the vertical via VH, it can be formed as a hollow cylinder or tube. Subsequently, the charge trapping layer CT can be formed along the inner surface of the barrier layer BX, and the tunnel insulating layer TO can be formed along the inner surface of the charge trapping layer CT. The channel layer CH can be formed along the inner surface of the tunnel insulating layer TO, and the core pillar CP can fill the interior surrounded by the channel layer CH. After forming the core pillar CP, an etching process can be performed to remove a portion of the upper region of the core pillar CP, and the capping layer CAP can be formed in the area where the core pillar CP is removed.

[0081] Reference Figure 10E and Figure 11E A separation aperture SH for separating the main plug Pm in the Y direction can be formed. At this time, a slit aperture SLH with the same pattern as the separation aperture SH can be simultaneously formed in the boundary region BR. For example, to simultaneously remove a portion of the first material layer 1M and the second material layer 2M of the boundary region BR, a mask pattern MP with openings in the boundary region BR and the cell region can be formed throughout the structure, and an etching process can be performed to etch the portion exposed through the openings of the mask pattern MP. All widths of the openings of the mask pattern MP can have a first width W1. Through the etching process, the separation aperture SH can be formed in the cell region, and the slit aperture SLH can be formed in the boundary region BR. An etching process for forming the separation aperture SH and the slit aperture SLH can be performed until the first source layer 1S of the cell region is exposed, so that the channel layer CH included in the main plug Pm can be separated. At this time, since the first source layer 1S is not exposed through the etch stop layer ST in the boundary region BR, the depth of the slit aperture SLH can be formed to be shallower than the depth of the separation aperture SH. The main plug Pm can be separated into the first sub-plug 1Ps and the second sub-plug 2Ps through the separation hole SH. When the etching process is finished, the mask pattern MP is removed.

[0082] Reference Figure 10F and Figure 11F A barrier pattern PP can be formed over the entire structure. The barrier pattern PP can be formed of a material with high step coverage, such that the upper parts of the slit holes SLH and SH are covered before the interiors of the slit holes SH are filled. The barrier pattern PP can be formed of an oxide layer with a step coverage higher than that of the first material layer 1M. Because the deposition rate of the material with high step coverage is faster than that of the general material, the upper openings of the slit holes SLH and SH can be covered without being filled.

[0083] Reference Figure 10G and Figure 11G An etching process can be performed to retain the blocking pattern PP formed on the upper part of the slit hole SLH and to remove the blocking pattern PP formed in the remaining area. For example, a planarization process can be performed until the first material layer 1M or the capping layer CAP is exposed. When the planarization process is performed, the blocking pattern PP formed on the first material layer 1M and the first sub-plugs 1Ps and the second sub-plugs 2Ps can be removed, and the blocking pattern PP formed in the slit hole SLH and the separation hole SH can be retained. Subsequently, an etched pattern can be formed on the boundary region BR to expose the cell region, and an etching process can be performed to remove the blocking pattern PP exposed through the opening of the etched pattern. Therefore, the blocking pattern PP can be retained on the upper part of the slit hole SLH, and the blocking pattern PP formed in the separation hole SH can be removed. Therefore, the first source layer 1S is exposed through the separation hole SH, and the slit hole SLH is not exposed by the blocking pattern PP.

[0084] Reference Figure 10H and Figure 11H A separation pattern SP can be formed within the separation hole SH that exposes the first source layer 1S. The separation pattern SP can be formed of an insulating material such that the channel layers CH of the first sub-plugs 1Ps and the second sub-plugs 2Ps are electrically disconnected from each other. For example, the separation pattern SP can be formed of an insulating material with a step coverage lower than that of the barrier pattern PP. For example, the separation pattern SP can be formed of an oxide layer or a silicon oxide layer. Since the slit hole SLH is not exposed through the barrier pattern PP, the separation pattern SP is not formed within the slit hole SLH when the process of filling the separation hole SH with the separation pattern SP is performed.

[0085] Reference Figure 10I and Figure 11I An etching process can be performed to remove the blocking pattern PP formed on the upper part of the slit hole SLH. When all the blocking pattern PP is removed, an etching process can be performed to selectively remove the etch stop layer ST because the etch stop layer ST is exposed through the slit hole SLH. Since the first sacrificial layer 1F is exposed through the slit hole SLH when the etch stop layer ST is removed, an etching process can be performed to remove the first sacrificial layer 1F.

[0086] Since the lower regions of the first sub-plugs 1Ps and the second sub-plugs 2Ps are partially exposed through the slit hole SLH when the first sacrificial layer 1F is removed, an etching process for removing the barrier layer BX, charge trapping layer CT, and tunnel insulating layer TO of the first sub-plugs 1Ps and the second sub-plugs 2Ps can be performed. In the cross-section along the D1-D2 direction, the first sub-plugs 1Ps are not exposed through the slit hole SLH. However, referring to the XY plane, a portion of the first sub-plugs 1Ps is exposed through the region where the first sacrificial layer 1F is removed. Therefore, the barrier layer BX, charge trapping layer CT, and tunnel insulating layer TO of the first sub-plugs 1Ps can be removed through the region where the first sacrificial layer 1F is removed and through the slit hole SLH. An etching process for removing the barrier layer BX, charge trapping layer CT, and tunnel insulating layer TO can be performed until the channel layer CH is exposed. Subsequently, a third source layer 3S can be formed in the region where the first sacrificial layer 1F is removed. The third source layer 3S can be formed of the same material as the first source layer 1S or the second source layer 2S. Therefore, a source line SL can be formed by configuring the first source layer 1S to the third source layer 3S.

[0087] Reference Figure 10J and Figure 11J An etching process can be performed to remove the second material layer 2M exposed through the slit hole SLH. The etching process can be performed using an etchant that allows the first material layer 1M to be retained and the second material layer 2M to be selectively removed as a wet etching process.

[0088] Reference Figure 10K and Figure 11K A deposition process for filling a third material layer 3M in the region where the second material layer 2M is removed can be performed. Since the third material layer 3M formed between the first material layers 1M serves as a gate line, the third material layer 3M can be formed of a conductive material. For example, the third material layer 3M can be formed of at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polysilicon (poly-Si). When the third material layer 3M is formed between the first material layers 1M, a stacked structure STK including the first material layer 1M and the third material layer 3M can be formed. When the third material layer 3M is formed between the first material layers 1M, the third material layer 3M can also be formed on the surface of the slot hole SLH.

[0089] Reference Figure 10L and Figure 11L An etching process can be performed to remove the third material layer 3M formed along the surface of the slit hole SLH. The etching process is performed to remove the third material layer 3M formed on the surface of the slit hole SLH, but portions of the third material layer 3M formed between the first material layers 1M that are adjacent to the slit hole SLH can also be removed together.

[0090] Reference Figure 10M and Figure 11M An insulating layer IS can be formed along the surface of the slit hole SLH. The insulating layer IS can be formed of an oxide layer or a silicon oxide layer. The insulating layer IS can be formed to cover all the third material layers 3M exposed through the side surface of the slit hole SLH. Since the insulating layer IS can be formed below the slit hole SLH, an etching process for exposing the third source layer 3S through the lower surface of the slit hole SLH can be performed after the formation of the insulating layer IS. The etching process can be performed as a dry etching process to maintain the insulating layer IS formed on the side surface of the slit hole SLH and selectively remove the insulating layer IS formed on the lower surface of the slit hole SLH.

[0091] Reference Figure 10N and Figure 11N A deposition process for forming source contacts SC in the slit aperture SLH can be performed. The source contacts SC can be formed of a conductive material. For example, the source contacts SC can be formed of doped polysilicon or tungsten. Since the insulating layer IS is formed between the third material layer 3M for the gate line GL and the source contacts SC, the gate lines GL included in each of the (n-1)th memory block BLK(n-1) and the nth memory block BLKn divided by the slit SLT can also be separated from each other.

[0092] Figure 12 This is a diagram illustrating a solid-state drive (SSD) system 4000 using the memory device disclosed herein.

[0093] Reference Figure 12 The SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals with the host 4100 through a signal connector 4001 and receives power through a power connector 4002. The SSD 4200 includes a controller 4210, multiple memory devices 4221 to 422n, an auxiliary power supply 4230, and a cache memory 4240.

[0094] Controller 4210 may control a plurality of memory devices 4221 to 422n in response to signals received from host 4100. For example, signals may be sent based on the interface between host 4100 and SSD 4200. For example, signals may be defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0095] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n may be compatible with... Figure 1 The memory devices 100 shown are configured identically. Multiple memory devices 4221 to 422n can communicate with the controller 4210 via channels CH1 to CHn.

[0096] Auxiliary power supply 4230 is connected to host 4100 via power connector 4002. Auxiliary power supply 4230 receives and charges power from host 4100 using this power supply voltage. When the power supply from host 4100 is unstable, auxiliary power supply 4230 can provide power to SSD 4200. For example, auxiliary power supply 4230 may be located inside or outside SSD 4200. For example, auxiliary power supply 4230 may be located on the motherboard and provide auxiliary power to SSD 4200.

[0097] Buffer memory 4240 operates as a buffer memory for SSD 4200. For example, buffer memory 4240 may temporarily store data received from host 4100 or data received from multiple memory devices 4221 to 422n, or it may temporarily store metadata (e.g., a mapping table) of memory devices 4221 to 422n. Buffer memory 4240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, or LPDDR SDRAM; or buffer memory 4240 may include non-volatile memory such as FRAM, ReRAM, STT-MRAM, or PRAM.

[0098] Figure 13 This is a diagram illustrating a memory card system 70000 using the memory device disclosed herein.

[0099] Reference Figure 13 The memory card system 70000 can be implemented as a memory card or a smart card. The memory card system 70000 may include a memory device 1100, a controller 1200, and a card interface 7100.

[0100] Memory device 1100 can be connected to Figure 1 The memory device 100 shown is configured similarly.

[0101] The controller 1200 controls the data exchange between the memory device 1100 and the card interface 7100. According to embodiments, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but is not limited thereto.

[0102] Card interface 7100 can interface for data exchange between host 60000 and controller 1200 according to the protocol of host 60000. According to the implementation, card interface 7100 can support Universal Serial Bus (USB) protocol and IC-USB protocol. Here, card interface 7100 can refer to hardware, software installed in the hardware, or signal transmission method capable of supporting protocols used by host 60000.

[0103] When the memory card system 70000 is connected to the host interface 6200 of a host 60000, such as a PC, tablet PC, digital camera, digital audio player, mobile phone, video game console hardware, or digital set-top box, the host interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the controller 1200 under the control of the microprocessor (μP) 6100.

[0104] Cross-reference to related applications

[0105] This application claims priority to Korean Patent Application No. 10-2022-0036937, filed with the Korean Intellectual Property Office on March 24, 2022, the full disclosure of which is incorporated herein by reference.

Claims

1. A memory device comprising: Layered structure; Main plugs, which pass through the stacked structure and are arranged to be spaced apart from each other in a first direction; A separation pattern that separates the main plug in a second direction; as well as A slit pattern, which separates the stacked structure into a first storage block and a second storage block, has an elliptical shape. The width of the slit pattern is the same as the width of the separation pattern.

2. The memory device according to claim 1, wherein, Each of the main plugs includes a first sub-plug and a second sub-plug separated from each other by the separation pattern.

3. The memory device according to claim 2, wherein, The first sub-plug and the second sub-plug have a structure that is symmetrical to each other across the separation pattern.

4. The memory device according to claim 3, wherein, Each of the first sub-plug and the second sub-plug includes a core post, a channel layer, a tunnel insulation layer, a charge trapping layer, and a barrier layer passing through the stacked structure.

5. The memory device according to claim 1, wherein, The slit pattern includes: Source contacts; and An insulating layer surrounds the side surface of the source contact.

6. The memory device according to claim 5, wherein, The insulating layer is formed between the source contact and the gate line included in the stacked structure.

7. The memory device according to claim 1, wherein, The separation pattern has the elliptical shape.

8. The memory device according to claim 1, wherein, The length of the slit pattern is the same as the length of the separation pattern.

9. The memory device according to claim 1, wherein, The stacked structure includes gate lines that are stacked and spaced apart from each other in the vertical direction.

10. A memory device comprising: A stacked structure is formed on the source line; Main plugs, which pass through the stacked structure and are arranged to be spaced apart from each other in a first direction; A separation pattern that separates the main plug in a second direction; as well as A slit, which separates the stacked structure into a first storage block and a second storage block, includes a slit pattern with an elliptical shape. The width of the slit pattern is the same as the width of the separation pattern.

11. The memory device according to claim 10, wherein, The slit patterns are arranged to be spaced apart from each other in the first direction.

12. The memory device according to claim 10, wherein, The slit patterns are connected to each other by a connecting structure.

13. The memory device according to claim 12, wherein, The connecting structures are arranged in a ladder shape between the slit patterns.

14. The memory device according to claim 12, wherein, The slit pattern includes: Source contacts, the source contacts being formed on the source line in a direction perpendicular to the plane defined by the first direction and the second direction; and An insulating layer surrounds the source contact.

15. The memory device according to claim 14, wherein, The connection structure includes: A conductive pattern that connects the source contacts to each other between adjacent slit patterns; and An insulating pattern that surrounds the conductive pattern.

16. A method of manufacturing a memory device, the method comprising the steps of: A first material layer and a second material layer are alternately stacked on a lower structure that defines unit regions and connecting regions; A main plug is formed in the unit region, passing through the first material layer and the second material layer; A separation hole is formed to separate the main plug into a first sub-plug and a second sub-plug; When the separation hole is formed, a slit hole is formed in the slit region; A separation pattern is formed in the separation hole; Remove the second material layer exposed through the slit hole; A conductive layer is formed between the first material layers where the second material layer is removed; Remove the portion of the conductive layer adjacent to the slit hole; An insulating layer is formed on the side surface of the slit hole where the portion of the conductive layer is removed; as well as A source contact is formed in the slit hole in which the insulating layer is formed.

17. The method according to claim 16, wherein, The step of alternately stacking the first material layer and the second material layer includes: The first material layer is formed as an oxide layer; and The second material layer is formed as a nitride layer.

18. The method according to claim 16, wherein, The steps of forming the separation hole and forming the slit hole include using a mask pattern in which openings are formed: Both the separation hole and the slit hole have the same width, and Both the separation hole and the slit hole have the same length.

19. The method according to claim 18, wherein, The steps of forming the separation hole and forming the slit hole include: forming the separation hole and the slit hole to have the same length.

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