A radar rapid prototyping verification system based on modular design

Abstract

The application discloses a radar rapid prototyping verification system based on modular design, belongs to the technical field of radar rapid prototyping verification, and is used for solving the technical problems that the existing radar engineering prototype has a long test period, high customization degree and no test universality. The method comprises the following steps: an antenna subsystem, a transmitting and receiving subsystem, an intermediate frequency preprocessing subsystem, a high-performance processing subsystem and a timing control subsystem; the antenna subsystem is connected with the transmitting and receiving subsystem, and is used for transmitting radar antenna signals in the antenna subsystem to the transmitting and receiving subsystem through a channel; the intermediate frequency preprocessing subsystem is connected with the output end of the transmitting and receiving subsystem and the input end of the high-performance processing subsystem respectively, and is used for collecting and generating intermediate frequency signals in each channel; the timing control subsystem is connected with the high-performance processing subsystem, and is used for recombining the working timing of non-real-time data according to a radar timing recombination mechanism in the timing control subsystem.

Description

Technical Field

[0001] This application relates to the field of rapid radar prototyping, and more particularly to a rapid radar prototyping system based on modular design. Background Technology

[0002] With the development of modern electronic countermeasures technology, higher demands are placed on radar performance. How radar operates in a countermeasured electromagnetic environment has become a key performance indicator. The development process typically involves first understanding the research and development objectives and requirements, then proceeding with the design, verifying key aspects of the design, followed by physical production and software development. After completing the engineering prototype, the physical radar undergoes hardware-in-the-loop testing and continuous iteration.

[0003] Currently, key design points are rarely verified before the development of engineering prototypes. Instead, engineering prototypes are used for testing to verify the design of new systems, algorithms, and ideas. However, engineering prototypes have long development cycles, high levels of customization, and lack versatility, which leads to delays in design risk identification, complex design iteration processes, and impacts the development cycle. Summary of the Invention

[0004] This application provides a rapid prototype verification system for radar based on modular design to solve the following technical problems: existing radar engineering prototypes have long testing cycles and high customization, lack test versatility, and are prone to delaying the detection of hidden risks in radar engineering prototypes, making it difficult to meet the needs of prototype verification of radar signal characteristics.

[0005] The embodiments of this application adopt the following technical solutions:

[0006] On one hand, this application provides a rapid prototype verification system for radar based on modular design, including: an antenna subsystem, a transmit / receive subsystem, an intermediate frequency (IF) preprocessing subsystem, a high-performance processing subsystem, and a timing control subsystem; the antenna subsystem is connected to the transmit / receive subsystem and is used to transmit radar antenna signals from the antenna subsystem to the transmit / receive subsystem through channels; the IF preprocessing subsystem is connected to the output terminal of the transmit / receive subsystem and the input terminal of the high-performance processing subsystem, respectively, and is used to acquire and generate IF signals in each channel and perform data processing on the IF signals; the timing control subsystem is connected to the high-performance processing subsystem and is used to recombine non-real-time data according to the radar timing reassembly mechanism in the timing control subsystem to achieve the normal operation of working parameters and working commands in the timing control subsystem.

[0007] In one feasible implementation, the antenna subsystem further includes: an antenna array module, a power divider / combiner network, a beam control network, a TR module, a power distribution network, and a heat dissipation system; the antenna array module includes 12 antenna subarrays, and each antenna subarray consists of 16 dual-polarized Ku antennas; the power divider / combiner network consists of a Ku-channel 16-way polarization and channel selection switch, a Ku-channel 16-way power divider, a Ku-channel 16-way analog sum-difference combiner, and a Ku-channel 16-channel power divider amplitude-phase modulation module; the beam control network controls the transmission and reception of the antenna subarrays, and can also control the switching and amplitude-phase of the power divider / combiner network; the TR module amplifies, phase-shifts, and attenuates the radar signals in the antenna subarrays; the power network supplies power to each module in the antenna subsystem; and the heat dissipation system cools each module in the antenna subsystem to ensure that the antenna subsystem operates normally under a stable temperature environment.

[0008] In one feasible implementation, the transmit / receive subsystem supports wide-band radar signal operating frequencies; wherein the operating frequency coverage range is 0.3~40GHz; the transmit / receive subsystem is also connected to the input terminal of the intermediate frequency preprocessing subsystem; the transmit / receive subsystem consists of a control module, a 32-channel upconversion module, a 32-channel downconversion module, a local oscillator module, and a chassis; through the transmit / receive subsystem, the control module, the 32-channel upconversion module, the 32-channel downconversion module, and the local oscillator module are configured and combined for various radar signal frequency bands to achieve the combination and replacement of various modules in the transmit / receive subsystem.

[0009] In one feasible implementation, the control module is used to receive external control commands and, based on the received external control commands, perform link control on the link power and link frequency of each link in the transmit-receive subsystem; the 32-channel upconversion module includes 32 receiving channels; through the 32-channel upconversion module, the intermediate frequency signals in the 32 receiving channels are frequency-converted to obtain radio frequency signals, and corresponding power control and signal conditioning control are performed on each of the 32 receiving channels; the 32-channel downconversion module includes 32 transmitting channels; through the 32-channel downconversion module, the radio frequency signals in the 32 transmitting channels are converted into fixed intermediate frequency signals, and corresponding power control and signal conditioning control are performed on each of the 32 transmitting channels; the local oscillator module provides the corresponding clock signals and reference signals to the 32-channel radio frequency upconversion module and the 32-channel downconversion module; the chassis is used to house the various modules and corresponding boards in the transmit-receive subsystem, and provides power to the various modules and corresponding boards through the chassis.

[0010] In one feasible implementation, the intermediate frequency (IF) preprocessing subsystem is used to acquire and generate 32 IF signals from the transmit-receive subsystem. The IF preprocessing subsystem consists of one clock synchronization board, two 16-channel synchronous acquisition boards, two 16-channel synchronous playback boards, one fiber optic data transmission board, and a chassis. Through the FPGA software reconfiguration mechanism in the IF preprocessing subsystem, the loading program in each board is dynamically reconfigured serially to achieve the switching configuration of each board in the IF preprocessing subsystem. The boards include the clock synchronization board, the synchronous acquisition board, the synchronous playback board, and the fiber optic data transmission board.

[0011] In one feasible implementation, each of the two 16-channel synchronous acquisition boards can synchronously sample the intermediate frequency (IF) signals in the 16 receiving channels of the IF preprocessing subsystem to perform adaptive beamforming, digital down-conversion, FIR filtering, and decimation algorithm signal processing on the IF signals; each of the two 16-channel synchronous playback boards can synchronously play the IF signals in the 16 transmitting channels of the IF preprocessing subsystem; and based on the synchronously played IF signals, generate conventional radar signals to support the loading of special waveform countermeasure signals; The fiber optic data transmission board is used to perform pulse compression, accumulation, and constant false alarm rate processing on the Ku dual-polarized signal and Ka signal in the intermediate frequency preprocessing subsystem; it sends the processed signal data to the timing control subsystem, and sends the data file cached in the intermediate frequency preprocessing subsystem to the high-performance processing subsystem through the optical interface of the fiber optic data transmission board; the clock synchronization board provides the corresponding clock signal and synchronization signal for each board in the intermediate frequency preprocessing subsystem; the chassis is used to house the various boards in the intermediate frequency preprocessing subsystem and to provide power to the various boards through the chassis.

[0012] In one feasible implementation, the timing control subsystem segments and records radar data based on coherent processing time according to the radar timing reassembly mechanism, and controls the non-real-time processing system in the timing control subsystem to perform corresponding data processing to determine an equivalent real-time data processing system; based on the real-time data processing system, it determines the working parameters and working instructions that enable the timing control subsystem to operate normally; the timing control subsystem consists of a main control board, an interface board, a high-speed storage board, an optical fiber data transmission board, a frequency measurement and large dynamic range detection module, and a chassis.

[0013] In one feasible implementation, the main control board runs a Windows operating system and radar line display and control software; the radar display and control software is used to simulate the flight control computer sending flight parameters and flight commands; the main control board is also used to control the human-machine interface and radar system in the timing control subsystem; there are two interface boards; each interface board has several data interfaces for issuing timing control commands and timing parameters in the timing control subsystem; the high-speed storage board consists of an array of 16 solid-state drives; each solid-state drive is 1TB and is used to store and record the working process data in the timing control subsystem; the fiber optic data transmission board is used for high-speed data transmission with the intermediate frequency preprocessing subsystem; the frequency measurement and large dynamic range detection module is used for monitoring the transmitted broadband electromagnetic spectrum and for large dynamic range detection of broadband dual-polarized echo signals.

[0014] In one feasible implementation, the high-performance processing subsystem is a high-performance server; the high-performance server has a built-in fiber optic PCIe card; the fiber optic PCIe card receives and stores radar data acquired or preprocessed from the timing control subsystem and the intermediate frequency preprocessing subsystem through a fiber optic interface; the high-performance processing subsystem adopts a semi-real-time mechanism to perform detection tracking, imaging, and target identification processing on the radar data.

[0015] In one feasible implementation, both the receiving channel and the transmitting channel in the transmitting and receiving subsystem are equipped with amplitude and phase correction modules. Through the amplitude and phase correction modules, and based on the ADBF algorithm, the phased array front-end signal transmitted by the antenna array module in the antenna subsystem is simulated to meet the amplitude and phase consistency of different radar antenna signals in different radar prototypes.

[0016] Compared with the prior art, the radar rapid prototyping system based on modular design provided in this application has the following advantages:

[0017] A modular radar rapid prototyping system combines standardized, modular physical radar components and uses a simulation control system to reassemble radar timing data, achieving simulation verification of the radar prototype. During this process, the radar signal passes through real microwave and analog circuits, achieving 100% link fidelity. The antenna subsystem, transmit / receive subsystem, intermediate frequency preprocessing subsystem, and timing control subsystem are all composed of standard modules. Each subsystem can be customized, operate collaboratively or independently, and the platform is scalable. This modular design greatly enhances the system's flexibility, providing multiple preprocessing models and reconstruction designs for signal preprocessing. For data processing, radar timing reassembly technology enables data processing on the CPU and supports general simulation software. Simultaneously, data monitoring and storage are provided at each signal processing node, avoiding the need for algorithm researchers to convert M-language programs to embedded language programs, and improving the efficiency of system fault location and troubleshooting. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0019] Figure 1 A structural diagram of a radar rapid prototyping system based on modular design is provided for embodiments of this application;

[0020] Figure 2 A block diagram of a radar rapid prototyping function system provided in this application embodiment;

[0021] Figure 3 An antenna subsystem block diagram provided in an embodiment of this application;

[0022] Figure 4 A block diagram of a transmit and receive subsystem provided in this application embodiment;

[0023] Figure 5 A block diagram of an intermediate frequency preprocessing subsystem provided in this application embodiment;

[0024] Figure 6 A timing control subsystem block diagram provided in this application embodiment;

[0025] Figure 7 A dynamic reconfigurable structure block diagram provided in an embodiment of this application;

[0026] Figure 8 A digital beamforming pattern provided in an embodiment of this application;

[0027] Figure 9 A flowchart illustrating a rapid prototyping process for radar, provided as an embodiment of this application;

[0028] Figure 10 This is a block diagram illustrating the implementation principle of frequency domain pulse compression, as provided in an embodiment of this application. Detailed Implementation

[0029] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0030] This application provides a rapid radar prototyping system based on modular design. Figure 1 A structural diagram of a radar rapid prototyping system based on modular design is provided for embodiments of this application, such as... Figure 1 As shown, a rapid prototyping system 100 for radar based on modular design is provided. The system includes: an antenna subsystem 110, a transmit and receive subsystem 120, an intermediate frequency preprocessing subsystem 130, a high-performance processing subsystem 140, and a timing control subsystem 150.

[0031] Specifically, such as Figure 1As shown, antenna subsystem 110 is connected to transmit / receive subsystem 120, and is used to transmit radar antenna signals from antenna subsystem 110 to transmit / receive subsystem 120 through channels. Intermediate frequency (IF) preprocessing subsystem 130 is connected to the output of transmit / receive subsystem 120 and the input of high-performance processing subsystem 140, respectively, and is used to acquire and generate IF signals from each channel, and to process the IF signals. Timing control subsystem 150 is connected to high-performance processing subsystem 140, and is used to recombine non-real-time data according to the radar timing reassembly mechanism in timing control subsystem 150, so as to achieve the normal operation of working parameters and commands in timing control subsystem 150.

[0032] Furthermore, Figure 3 This application provides a block diagram of an antenna subsystem. Figure 2 A block diagram of a radar rapid prototyping function system is provided for embodiments of this application, such as... Figure 3 as well as Figure 2 As shown, the antenna subsystem 110 also includes: an antenna array module 111, a power divider / combiner network 112, a beam control network 113, a TR module 114, a power distribution network 115, and a heat dissipation system 116. The antenna array module 111 includes 12 antenna subarrays, each consisting of 16 dual-polarized Ku-band antennas. The power divider / combiner network 112 consists of a 16-channel Ku-band polarization and channel selection switch, a 16-channel Ku-band power divider, a 16-channel Ku-band analog sum-difference combiner, and a 16-channel Ku-band power divider amplitude-phase modulation module. The beam control network 113 controls the transmission and reception of the antenna subarrays and also controls the switching and amplitude-phase operation of the power divider / combiner network 112. The TR module 114 amplifies, phase-shifts, and attenuates the radar signals in the antenna subarrays. The power distribution network 115 supplies power to each module in the antenna subsystem. The heat dissipation system 116 is used to dissipate heat from each module in the antenna subsystem 110 so that the antenna subsystem 110 can operate normally under a stable temperature environment.

[0033] As a possible implementation method, such as Figure 2As shown, the antenna subsystem 110 contains 16 subarrays, each containing Ku / Ka dual-frequency dual-polarized antenna elements and interconnected TR component arrays. When a radar signal is acquired, in-phase superposition of spatial signals arriving at each antenna element can enhance the signal. According to plane wave theory, in-phase superposition at the array output is only possible when the incident wave is perpendicular to the array plane. In other words, if the array rotates around its central axis, the incident wave must be perpendicular to the array plane when the array output is at its maximum. However, array rotation often falls short of practical requirements, especially for large antenna arrays where rotation is difficult. In-phase superposition can be achieved by phase compensation of the signals received by each element. However, phase differences are caused by the propagation delay of the incident wave to each element. If an appropriate weighting coefficient is selected for each element to compensate for its propagation delay, in-phase superposition of the array output in a certain direction is possible. In other directions, in-phase superposition is not possible, resulting in a smaller array output response.

[0034] As a feasible implementation method, Figure 8 A digital beamforming pattern provided in an embodiment of this application, such as Figure 8 As shown, in a uniform linear array of M elements in antenna subsystem 110, the incident signal is a narrowband signal, and the signal received by the antenna is given. Each element has a weighting coefficient to adjust its output. The output of each element and the weighting coefficient vector are given. The array output vector expression is The average power output of the entire array is then... ,

[0035] in, This represents the covariance of the received signal.

[0036] Assume that only one signal of interest (or desired signal) exists in the far field of space. To compensate for the time delays between array elements in the desired direction, coherent superposition is performed to form a main lobe. The weighting vector of a conventional beamformer in the direction of the desired signal can be configured as follows: Where M is the number of antennas. The angle between the beam and the array surface. Since the wavelength is given, the output is... As can be seen from the output formula, the signals received by each array element are weighted and summed, resulting in coherent superposition. Therefore, a conventional beamformer can also be called a spatially matched filter, which matches the desired signal to maximize the output power of the desired signal.

[0037] Furthermore, Figure 4 A block diagram of a transmit and receive subsystem provided in this application embodiment, such as Figure 4 as well as Figure 2As shown, the transmit / receive subsystem 120 supports wide-band radar signal operating frequencies. The operating frequency coverage ranges from 0.3 to 40 GHz. The transmit / receive subsystem 120 is also connected to the input of the intermediate frequency preprocessing subsystem 130. The transmit / receive subsystem 120 consists of a control module 121, a 32-channel upconversion module 122, a 32-channel downconversion module 123, a local oscillator module 124, and a chassis 125. Through the transmit / receive subsystem 120, the control module 121, the 32-channel upconversion module 122, the 32-channel downconversion module 123, and the local oscillator module 124 are configured and combined for various radar signal frequency bands, enabling the combination and replacement of various modules within the transmit / receive subsystem 120.

[0038] Furthermore, such as Figure 4 as well as Figure 2 As shown, the control module 121 receives external control commands and, based on these commands, controls the link power and frequency of each link in the transmit / receive subsystem 120. The 32-channel upconversion module 122 includes 32 receiving channels. Through the 32-channel upconversion module 122, the intermediate frequency (IF) signals in the 32 receiving channels are converted to radio frequency (RF) signals, and corresponding power control and signal conditioning control are performed on each of the 32 receiving channels. The 32-channel downconversion module 123 includes 32 transmitting channels. Through the 32-channel downconversion module, the RF frequency signals in the 32 transmitting channels are converted to fixed IF frequency signals, and corresponding power control and signal conditioning control are performed on each of the 32 transmitting channels. The local oscillator module 124 provides the necessary clock and reference signals to the 32-channel RF upconversion module 122 and the 32-channel downconversion module 123. The chassis 125 is used to house the various modules and corresponding boards in the transmit and receive subsystem 120, and to provide power to the various modules and corresponding boards through the chassis 125.

[0039] Furthermore, such as Figure 3 as well as Figure 1 As shown, amplitude and phase correction modules are added to both the receiving and transmitting channels in the transmit-receive subsystem 120. Through these modules, and based on the ADBF algorithm, the phased array front-end signal transmitted by the antenna array module 111 in the antenna subsystem 110 is simulated to ensure the amplitude and phase consistency of different radar antenna signals in different radar prototypes.

[0040] As a possible implementation method, such as Figure 2As shown, the 32-channel upconversion module 122 and 32-channel downconversion module 123 in the transmit / receive subsystem 120 each contain multiple channels. To meet the amplitude and phase consistency requirements of different radar prototypes, an amplitude and phase correction module is added to each channel, working in conjunction with the ADBF algorithm to simulate the phased array front-end signal. Channel amplitude and phase characteristic correction is used to correct a known signal with poor amplitude and phase characteristics. Amplitude and phase compensation is performed at different frequencies. Through filtering, the signal is transformed into a linear frequency modulated signal with more ideal amplitude and phase characteristics. This requires designing the coefficients of the filter. The ideal signal waveform is: The bandwidth is B=330MHz, the pulse width is T=50us, and the sampling rate is Fs=400MHz.

[0041] Assuming a non-ideal signal Find the filter coefficients. Use this filter to Filtering should yield an ideal signal. That is, the requirements are: In the above formula: These are actual measured data. An ideal signal was generated based on parameters, all of which are known quantities. It is a system of linear equations. By solving this system of linear equations, we can obtain... The design problem of complex coefficient FIR filters can be reduced to a complex Chebyshev approximation problem. The filter coefficients are obtained by using the complex Remez algorithm and a genetic algorithm, and the optimized solution is obtained by using the genetic algorithm based on the complex Remez algorithm.

[0042] Furthermore, Figure 5 A block diagram of an intermediate frequency preprocessing subsystem provided in this application embodiment is shown below. Figure 5 As shown, the intermediate frequency (IF) preprocessing subsystem 130 is used for the acquisition and generation of 32 IF signals from the transmit / receive subsystem 120. The IF preprocessing subsystem 130 consists of one clock synchronization board 134, two 16-channel synchronous acquisition boards 131, two 16-channel synchronous playback boards 132, one fiber optic data transmission board 133, and a chassis 135. Through the FPGA software reconfiguration mechanism in the IF preprocessing subsystem 130, the loading program in each board is dynamically reconfigured serially to achieve switching configuration of each board in the IF preprocessing subsystem 130. The boards include the clock synchronization board 134, the channel synchronous acquisition board 131, the channel synchronous playback board 132, and the fiber optic data transmission board 133.

[0043] Furthermore, such as Figure 5 as well as Figure 2As shown, each of the two 16-channel synchronous acquisition boards 131 can synchronously sample the intermediate frequency (IF) signals in the 16 receiving channels of the IF preprocessing subsystem 130 to perform adaptive beamforming, digital down-conversion, FIR filtering, and decimation algorithms on the IF signals. Each of the two 16-channel synchronous playback boards 132 can synchronously play the IF signals in the 16 transmitting channels of the IF preprocessing subsystem 130. Based on the synchronously played IF signals, conventional radar signals are generated to support the loading of special waveform countermeasure signals. The fiber optic data transmission board 133 is used for pulse compression, accumulation, and constant false alarm rate (CFAR) processing of the Ku dual-polarized and Ka signals in the IF preprocessing subsystem 130.

[0044] Furthermore, such as Figure 5 as well as Figure 1 As shown, the processed signal data is sent to the timing control subsystem 150, and the data file cached in the intermediate frequency preprocessing subsystem 130 is sent to the high-performance processing subsystem 140 through the optical interface of the fiber optic data transmission board 133. The clock synchronization board 134 provides the corresponding clock signal and synchronization signal for each board in the intermediate frequency preprocessing subsystem 130. The chassis 135 is used to house the various boards in the intermediate frequency preprocessing subsystem 130 and to provide power to each board.

[0045] As a possible implementation method, such as Figure 2 As shown, the intermediate frequency preprocessing subsystem 130 also includes functions such as ADC and DDC, digital beamforming, pulse compression, and data storage. As the core acquisition devices, ADC and DAC require synchronized acquisition of both channels to achieve a multi-channel synchronous acquisition system. This is a relatively explicit requirement. However, since radar systems determine operating status and target distance by acquiring transmitted echoes, an implicit requirement exists: synchronization between all channels' ADCs and DACs. The JESD204B SUBCLASS1 uses the SYSEF signal as the synchronization reference signal for the TX and RX devices. SYSREF is the source for synchronization with CLK. When the internal LMFC of the chip aligns with the CLK edge when SYSREF is high, deterministic delay can be achieved between the TX and RX devices. If the deterministic delay of each TX-RX link in the device is the same, multi-channel synchronization can be achieved.

[0046] The JESD204B SUBCLASS1 uses the SYSREF signal as the synchronization reference signal for the TX and RX devices. The SYSREF signal is a source synchronized with the CLK clock and can be a single pulse or a periodic signal. When the internal LMFC of the chip is aligned with the CLK edge when SYSREF is high, deterministic delay can be achieved between the TX and RX devices. If the deterministic delay of each TX-RX link in the device is the same, multi-channel synchronization can be achieved.

[0047] Based on the JESD204B synchronization mechanism, the following design is implemented to achieve synchronization;

[0048] 1) All Clock signals are of the same origin, and SYSREF signals are of the same origin, especially when SYSREF is a periodic or discontinuous periodic signal.

[0049] 2) Delay matching is performed on all Clock and SYSREF signal traces.

[0050] 3) Delay matching is performed on each SERDES link.

[0051] As a feasible implementation method, Figure 7 A dynamic reconfigurable structure block diagram provided in this application embodiment, such as Figure 7 as well as Figure 2 As shown, FPGA software reconfiguration is a new technology that enables flexible switching between different functions by configuring hardware with variable circuit structures. Systems implemented using reconfigurable technology offer the advantages of both flexibility and high performance, significantly shortening product development cycles while maintaining system performance. FPGA software reconfiguration is divided into dynamic reconfiguration and static reconfiguration. Static reconfiguration involves reconfiguring the hardware using an external controller via an external programmer. Dynamic reconfiguration configures the hardware in real time during system runtime without external control.

[0052] When the load device corresponding to the intermediate frequency preprocessing subsystem 130 is powered on, the pre-set firmware file inside the device is loaded first. The loading control FPGA determines whether online program loading is required based on parameters sent from the host computer. After loading is completed, it is determined whether the loading was successful. If unsuccessful, the loading control FPGA feeds back to the host computer for further processing. The two FPGAs on each board are loaded serially using the QSPI loading method. When the system powers on, the FPGA reads the loading file from the QSPI FLASH and loads it into the FPGA using the QSPI fast loading interface, based on the hardware configuration status. After the FPGA loads, it enters the running state, the DONE signal goes high, and the loading completion indicator lights up.

[0053] As a feasible implementation method, Figure 10A block diagram illustrating the implementation principle of frequency domain pulse compression provided in this application embodiment is shown below. Figure 2 as well as Figure 10 As shown, regarding pulse compression in the intermediate frequency preprocessing subsystem 130, digital pulse compression technology is implemented using the frequency domain method. Its basic principle is to use the FFT algorithm to calculate the spectrum of the sampled echo signal. The spectrum of the discrete impulse response of the filter Then, the product of the two spectra is calculated, and the inverse IFFT algorithm is used to transform the product to obtain the discrete signal after pulse compression. The whole process can be represented as: When processing signals with large time spans using this method, the complexity of circuit design is greatly reduced compared to time-domain convolution, and the simulation tool comes with FFT and IFFT modules, making it easy to use.

[0054] Furthermore, Figure 6 A timing control subsystem block diagram provided for embodiments of this application, such as Figure 6 As shown, the timing control subsystem 150, based on the radar timing reassembly mechanism, segments and records radar data according to coherent processing time, and controls the non-real-time processing system within the timing control subsystem 150 to perform corresponding data processing, thereby determining an equivalent real-time data processing system. Based on the real-time data processing system, the operating parameters and commands for the timing control subsystem 150 to operate normally are determined. The timing control subsystem 150 consists of a main control board 151, an interface board 152, a high-speed storage board 153, a fiber optic data transmission board 154, a frequency measurement and large dynamic range detection module 155, and a chassis 155.

[0055] Furthermore, such as Figure 6 as well as Figure 2 As shown, the main control board 151 runs a Windows operating system and radar line display and control software. The radar display and control software is used to simulate the flight control computer sending flight parameters and commands. The main control board 151 is also used to control the human-machine interface and radar system in the timing control subsystem 150. There are two interface boards 152. The interface boards 152 have several data interfaces for issuing timing control commands and timing parameters in the timing control subsystem 150. The high-speed storage board 153 consists of a 16-solicitation disk array. Each solid-state disk is 1TB and is used to store and record the working process data in the timing control subsystem 150. The fiber optic data transmission board 154 is used for high-speed data transmission with the intermediate frequency preprocessing subsystem 130. The frequency measurement and large dynamic range detection module 155 is used for monitoring the transmitted broadband electromagnetic spectrum and for large dynamic range detection of the broadband dual-polarized echo signal.

[0056] As a possible implementation method, such as Figure 6As shown, radar operation timing typically ranges from nanoseconds to seconds. We refer to short processing times as fast times, usually one PRI, while long processing times are called slow times, usually one CPI. Both fast and slow time processing are real-time signal processing, requiring short response times (within seconds).

[0057] As a feasible implementation method, the processing of a single pulse is completed on the shortest possible time scale. This is because the sampling rate, determined by the instantaneous bandwidth of the pulse, is typically in the range of several hundred MHz to several GHz, with corresponding sampling intervals ranging from a few microseconds to a fraction of a nanosecond. Signal processing operations on these samples tend to employ time lengths close to the sampling intervals. Fast-time signal processing includes: digital I / Q signal formation, beamforming, pulse compression or matched filtering, and sensitivity time control.

[0058] As a feasible implementation method, radar does not transmit just a single pulse, but typically transmits a continuous sequence of pulses, for example, processing M pulses as a group. The time interval between pulses is called the pulse repetition interval (PRI), and its reciprocal is the pulse repetition frequency (PRF). Typically, the PRI is on the order of tens of microseconds to hundreds of milliseconds, so the processing of multiple pulses also uses a time scale similar to the PRI. The dimension containing the number of pulses is called the slow time axis, and the time required to acquire data is M·PRI, usually called the coherent processing time (CPI). Except in some special cases, the PRI and radar frequency are usually fixed within a CPI, and the transmitted waveforms are identical for Doppler measurements. Compared to the sampling rate of a single pulse, the sampling here is slower, so this multi-pulse processing is called slow time processing. Typical slow time processing includes: coherent and incoherent accumulation, various types of Doppler processing (MTI / MTD), synthetic aperture imaging (SAR), and space-time adaptive processing (STAP).

[0059] Therefore, leveraging this characteristic of radar, the radar timing reconstruction method involves dividing the radar processing time according to CPI intervals and recording the current scene parameters and radar data. Sufficient time is allowed for the non-real-time processing system (an M-language program running on the CPU) to complete data processing, and then the entire scene is reconstructed using the recorded scene parameters and radar data. The process is analogous to repeatedly pressing the "pause" button at each CPI interval, waiting for the non-real-time processing system to complete processing, and then pressing the "continue" button.

[0060] Furthermore, such as Figure 1As shown, the high-performance processing subsystem 140 is a high-performance server. The high-performance server has a built-in fiber optic PCIe card. The fiber optic PCIe card receives and stores radar data acquired or pre-processed from the timing control subsystem and the intermediate frequency preprocessing subsystem via a fiber optic interface. The high-performance processing subsystem employs a semi-real-time mechanism to perform detection, tracking, imaging, and target identification processing on the radar data.

[0061] As a feasible implementation method, Figure 9 A flowchart illustrating a rapid prototyping process for radar, as provided in this application embodiment, is shown below. Figure 9 As shown, the working steps are as follows:

[0062] 1) After the operation begins, the main control software first sets the parameters of the DC power supply and controls the DC power supply to be powered on.

[0063] 2) The radar rapid prototyping system platform based on modular design reads local initialization parameters through the main control software and configures the initialization parameters of all the software and hardware in the device.

[0064] 3) After initialization, the radar rapid prototyping system platform based on modular design first performs a system self-test, including hardware status check and channel closed-loop detection.

[0065] 4) If the self-test result is abnormal, the abnormal status is recorded, an abnormal warning is displayed on the UI interface, and the initialization process is restarted. If the self-test result is normal, the normal working process is resumed.

[0066] 5) The device can be selected to perform a single test procedure or a flight test procedure.

[0067] 6) In the single test process, the main control software issues a set of fixed parameters and instructions.

[0068] 7) The equipment performs an anti-interference test based on the current parameters and instructions.

[0069] 8) Before the flight test process, you need to select the test trajectory file.

[0070] 9) The main control software sends out ballistic files, and the interface board reads the files periodically to control the working parameters of each subsystem.

[0071] 10) The antenna subsystem, transmit and receive subsystem, intermediate frequency preprocessing subsystem, and high-performance processing subsystem operate according to the set parameters.

[0072] 11) The antenna subsystem, transmit and receive subsystem, and intermediate frequency preprocessing subsystem cooperate to transmit signals and receive echo signals, and send the preprocessed data to the timing control subsystem. The timing control subsystem forwards the data to the high-performance processing subsystem. The high-performance processing subsystem feeds back the processing results to the control and storage subsystem, and sends the next working instructions and parameters to other subsystems.

[0073] 12) After the test is completed, the control and storage subsystem records the test process parameters and data.

[0074] 13) The main control software reads the recorded test process data.

[0075] 14) The main control software will analyze the data read from the test process, determine the anti-interference effect, and end the verification process of this test.

[0076] This application's embodiment is based on a modularly designed rapid radar prototyping system. By combining standardized, modular physical radar components and using a simulation control system for radar timing reconfiguration, the radar prototype is simulated and verified. During this process, the radar signal passes through real microwave and analog circuits, achieving 100% link fidelity. The antenna subsystem, transmit / receive subsystem, intermediate frequency preprocessing subsystem, and timing control subsystem are all composed of standard modules. Each subsystem can be customized, can work collaboratively or independently, and the platform is scalable. This modular design greatly enhances the system's flexibility, providing multiple preprocessing models and reconfiguration designs for signal preprocessing. For data processing, radar timing reconfiguration technology enables data processing on the CPU and supports general simulation software. Simultaneously, data monitoring and storage are provided at each signal processing node, avoiding the need for algorithm researchers to convert M-language programs to embedded language programs, and improving the efficiency of system fault location and problem diagnosis.

[0077] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0078] The foregoing has described specific embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0079] The above description is merely an embodiment of this application and is not intended to limit this application. For those skilled in the art, various modifications and variations can be made to the embodiments of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the embodiments of this application should be included within the scope of the claims of this application.

Claims

1. A radar rapid prototyping verification system based on modular design, characterized in that, The application relates to a radar system, which comprises an antenna subsystem, a transmitting-receiving subsystem, an intermediate frequency preprocessing subsystem, a high-performance processing subsystem and a timing control subsystem. The antenna subsystem is connected with the transmitting-receiving subsystem and is used for transmitting radar antenna signals in the antenna subsystem to the transmitting-receiving subsystem through channels. The intermediate frequency preprocessing subsystem is connected with the output end of the transmitting-receiving subsystem and the input end of the high-performance processing subsystem respectively and is used for collecting and generating intermediate frequency signals in each channel and performing data processing on the intermediate frequency signals. The timing control subsystem is connected with the high-performance processing subsystem and is used for recombining the working timing of non-real-time data according to a radar timing recombination mechanism in the timing control subsystem so as to realize the normal operation of working parameters and working instructions in the timing control subsystem. The timing control subsystem cuts and records radar data based on a coherent processing time according to a radar timing recombination mechanism, including cutting the radar processing time according to a CPI interval and recording current scene parameters and radar data. The timing control subsystem controls a non-real-time processing system to perform corresponding data processing and restores the whole scene by using the recorded scene parameters and radar data to determine an equivalent real-time data processing system. Based on the real-time data processing system, working parameters and working instructions are determined to make the timing control subsystem operate normally. The timing control subsystem is composed of a main control board, an interface board, a high-speed storage board, a fiber-optic data transmission board, a frequency measurement and large-dynamic detection module and a case. The antenna subsystem further comprises an antenna array module, a power division and synthesis network, a wave control network, a TR module, a power distribution network and a heat dissipation system.

2. The rapid prototyping radar system based on modular design of claim 1, wherein, The antenna array module comprises 12 antenna subarrays, and each antenna subarray is composed of 16 dual-polarized Ku antennas. The power division and synthesis network is composed of a Ku channel 16-way polarization and channel selection switch, a Ku channel 16-way power divider, a Ku channel 16-way analog and difference synthesizer and a Ku channel 16-way power division amplitude and phase modulation module. The wave control network is used for transmitting and receiving control of the antenna subarrays and also can be used for switch control and amplitude and phase control of the power division and synthesis network. The TR module is used for amplifying, phase-shifting and attenuating control of radar signals in the antenna subarrays. The power distribution network supplies power to each module in the antenna subsystem. The heat dissipation system is used for heat dissipation of each module in the antenna subsystem so that the antenna subsystem can normally operate in a stable temperature environment. The transmitting-receiving subsystem supports wide-band radar signal working frequencies, and the working frequencies cover a 0.3-40GHz frequency band.

3. The rapid prototyping radar system based on modular design of claim 1, wherein, The transmitting-receiving subsystem is also connected with the input end of the intermediate frequency preprocessing subsystem. The transmitting-receiving subsystem is composed of a control module, a 32-way up-conversion module, a 32-way down-conversion module, a local oscillator module and a case. ​ The transmitting-receiving subsystem is configured and combined with each radar signal frequency band of the control module, the 32-path up-conversion module, the 32-path down-conversion module and the local oscillator module to realize combination and replacement of each module in the transmitting-receiving subsystem.

4. The radar rapid prototyping system based on modular design according to claim 3, characterized in that, the control module is configured to receive an external control instruction and control the link power and the link frequency of each link in the transmitting-receiving subsystem according to the received external control instruction; the 32-path up-conversion module comprises 32 receiving channels; the 32-path up-conversion module is configured to convert the intermediate frequency signals in the 32 receiving channels to radio frequency signals and perform corresponding power control and signal conditioning control on each receiving channel in the 32 receiving channels; the 32-path down-conversion module comprises 32 transmitting channels; the 32-path down-conversion module is configured to convert the radio frequency signals in the 32 transmitting channels to fixed intermediate frequency signals and perform corresponding power control and signal conditioning control on each transmitting channel in the 32 transmitting channels; the local oscillator module provides the 32-path up-conversion module and the 32-path down-conversion module with required clock signals and reference signals; the case is configured to load each module and corresponding board in the transmitting-receiving subsystem and supply power to the modules and corresponding boards.

5. The rapid prototyping radar system based on modular design of claim 1, wherein, the intermediate frequency preprocessing subsystem is configured to collect and generate 32 intermediate frequency signals in the transmitting-receiving subsystem; the intermediate frequency preprocessing subsystem comprises one clock synchronization board, two 16-channel synchronous acquisition boards, two 16-channel synchronous playback boards, one optical fiber data transmission board and a case; each board in the intermediate frequency preprocessing subsystem is dynamically reconfigured by an FPGA software reconfiguration mechanism to realize switching and configuration of the boards, wherein the boards include the clock synchronization board, the synchronous acquisition board, the synchronous playback board and the optical fiber data transmission board.

6. The radar rapid prototyping system based on modular design according to claim 5, characterized in that, each 16-channel synchronous acquisition board in the two 16-channel synchronous acquisition boards is configured to synchronously sample the intermediate frequency signals in 16 receiving channels of the intermediate frequency preprocessing subsystem to perform signal processing such as adaptive beam forming, digital down-conversion, FIR filtering and decimation on the intermediate frequency signals; each 16-channel synchronous playback board in the two 16-channel synchronous playback boards is configured to synchronously play the intermediate frequency signals in 16 transmitting channels of the intermediate frequency preprocessing subsystem; based on the synchronously played intermediate frequency signals, conventional radar signals are generated to realize loading support for special waveform countermeasure signals; the optical fiber data transmission board is configured to perform signal processing such as pulse compression, accumulation and constant false alarm rate on Ku dual-polarized signals and Ka signals in the intermediate frequency preprocessing subsystem. The processed signal data is sent to the timing control subsystem, and the data file cached in the intermediate frequency preprocessing subsystem is sent to the high-performance processing subsystem through the optical interface of the optical fiber data transmission board; The clock synchronization board provides the required clock signal and synchronization signal for each board card in the intermediate frequency preprocessing subsystem; The case is used to load each board card in the intermediate frequency preprocessing subsystem, and the power supply process of each board card is performed through the case.

7. The radar rapid prototyping system based on modular design according to claim 1, wherein the main control board runs a Windows operating system and radar line display control software; the radar display control software is used to simulate the flight control computer to send flight parameters and flight commands; the main control board is also used to control the man-machine interface in the timing control subsystem and the radar system; The number of the interface board is 2; the interface board has a plurality of data interfaces for issuing timing control instructions and timing parameters in the timing control subsystem; The high-speed storage board is composed of 16 solid state disk arrays; each solid state disk is 1TB, and is used to store and record working process data in the timing control subsystem; The optical fiber data transmission board is used for high-speed data transmission with the intermediate frequency preprocessing subsystem; The frequency measurement and large dynamic detection module is used for monitoring the transmitted wideband electromagnetic spectrum and large dynamic detection of the wideband dual-polarized echo signal. The high-performance processing subsystem is a high-performance server; 8. The rapid prototyping radar system based on modular design of claim 1, wherein, The high-performance server is built-in with an optical fiber PCIE card; The optical fiber PCIE card receives and stores the radar data collected or preprocessed from the timing control subsystem and the intermediate frequency preprocessing subsystem through the optical fiber interface; The high-performance processing subsystem adopts a semi-real-time mechanism to perform detection tracking, imaging and target recognition processing on the radar data. The amplitude and phase correction module is added to the receiving channel and the transmitting channel in the transmitting and receiving subsystem; 9. The rapid prototyping radar system based on modular design of claim 1, wherein, Through the amplitude and phase correction module and based on the ADBF algorithm, the phase array front-end signal transmitted by the antenna array module in the antenna subsystem is simulated to meet the amplitude and phase consistency of different radar antenna signals in different radar prototypes. ​

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