Shift register, display device, gate driving circuit and driving method

Abstract

The application relates to the technical field of display, in particular to a shift register, a display device, a gate driving circuit and a driving method, which can capture the starting position of a next frame high-definition display area and perform high-definition display area scanning; a shift register comprises an access circuit and an output circuit. The access circuit is electrically connected with a signal storage control end, an access input control end, a storage signal input end, an access signal input end and a pull-up node; the access circuit is configured to, when the shift register corresponds to the starting position of the high-definition display area, input and store the signal received at the storage signal input end in response to the signal received at the storage signal input end and the signal received at the signal storage control end; and the access circuit is further configured to, in response to the stored signal and the signal received at the access input control end, transmit the signal received at the access signal input end to the pull-up node. The application can be applied to the field of 3D display.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to shift registers, display devices, gate driving circuits, and driving methods. Background Technology

[0002] In the display field, GOA (Gate on Array) is a technology that fabricates gate driver ICs on an array substrate. The essence of a GOA circuit is a shift register, which controls the pixel scanning of the display panel line by line through cascaded shift registers, so that the display panel can form a display image.

[0003] The display device uses GOA circuitry, which can effectively reduce costs and improve yield. Summary of the Invention

[0004] This invention provides a shift register, a display device, a gate driving circuit, and a driving method to enable the shift register to initiate the scanning of the next row without cascading signals, to receive and store a signal under the control of an external signal, and to output a scanning signal under the control of that signal. To achieve this objective, the invention adopts the following technical solution:

[0005] On one hand, the present invention provides a shift register, including: an access circuit and an output circuit. The access circuit is electrically connected to a signal storage control terminal, an access input control terminal, a storage signal input terminal, an access signal input terminal, and a pull-up node. The access circuit is configured to input and store a signal received at the storage signal input terminal in response to a signal received at the storage signal input terminal and a signal received at the signal storage control terminal. The access circuit is also configured to transmit a signal received at the access signal input terminal to the pull-up node in response to the stored signal received at the storage signal input terminal and the signal received at the access input control terminal.

[0006] The output circuit is electrically connected to a pull-up node, at least one clock signal terminal, and at least one signal output terminal. The output circuit is configured to transmit signals received at at least one clock signal terminal to at least one signal output terminal in response to a signal from the pull-up node.

[0007] The shift register provided by this invention has an access circuit that can realize a pull-up node for the shift register. Under the control of an external signal, it stores a high-level signal, and then, under the control of the pull-up node, causes the output circuit to output a scan signal. Accordingly, multiple shift registers have two control modes, and multiple shift registers can control the pixels in the display panel to form two scan images in one frame.

[0008] In some embodiments, the access circuit is configured to, when the shift register corresponds to the start position of the next frame of high-definition display area, input and store a signal received at the storage signal input terminal in response to a signal received at the storage signal input terminal and a signal received at the signal storage control terminal; one of the at least one signal output terminal is electrically connected to the storage signal input terminal. In some embodiments, the shift register further includes a reset circuit electrically connected to a pull-up node, a reset control terminal, and a reset voltage signal terminal, and the reset circuit is configured to, in response to a signal received at the reset control terminal, transmit a signal received at the reset voltage signal terminal to the pull-up node.

[0009] In some embodiments, the access circuit includes a signal storage sub-circuit and a signal extraction sub-circuit. The signal storage sub-circuit is electrically connected to a signal storage control terminal, a storage signal input terminal, and a first node. The signal storage sub-circuit is configured to, in response to a signal received at the signal storage control terminal, transmit and store the signal received at the storage signal input terminal to the first node when the shift register corresponds to the starting position of the high-definition display area.

[0010] The signal extraction sub-circuit is electrically connected to the first node, the access input control terminal, and the pull-up node. The signal extraction sub-circuit is configured to transmit the signal received at the access signal input terminal to the pull-up node in response to the signal from the first node and the signal received at the access input control terminal.

[0011] In some embodiments, the signal storage sub-circuit includes a first transistor, a second transistor, and a first capacitor. The control electrodes of both the first and second transistors are electrically connected to a signal storage control terminal. The first electrode of the first transistor is electrically connected to a stored signal input terminal. The second electrode of the first transistor is electrically connected to the first electrode of the second transistor. The second electrode of the second transistor is electrically connected to a first node. The first electrode of the first capacitor is electrically connected to the first node. The second electrode of the first capacitor is electrically connected to a regulated signal terminal.

[0012] In some embodiments, the signal extraction sub-circuit includes a fourth transistor and a fifth transistor, wherein the control electrode of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the access signal input terminal, the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor, the control electrode of the fifth transistor is electrically connected to the access input control terminal, and the second electrode of the fifth transistor is electrically connected to the pull-up node.

[0013] In some embodiments, the reset circuit includes a twelfth transistor, the control electrode of the twelfth transistor is electrically connected to the reset control terminal, the first electrode of the twelfth transistor is electrically connected to the pull-up node, and the second electrode of the twelfth transistor is electrically connected to the reset voltage signal terminal.

[0014] In some embodiments, the output circuit includes a first output circuit and a second output circuit, the clock signal terminal includes a first clock signal terminal and a second clock signal terminal, and the signal output terminal includes a first signal output terminal and a second signal output terminal.

[0015] The first output circuit is electrically connected to the pull-up node, the first clock signal terminal, and the first signal output terminal. The first output circuit is configured to transmit the signal received at the first clock signal terminal to the first signal output terminal in response to the signal of the pull-up node. The first signal output terminal is electrically connected to the stored signal input terminal.

[0016] The first output circuit includes a sixth transistor and a second capacitor. The control electrode of the sixth transistor and the first electrode of the second capacitor are both electrically connected to the pull-up node. The first electrode of the sixth transistor is electrically connected to the first clock signal terminal, and the second electrode of the sixth transistor and the second electrode of the second capacitor are electrically connected to the first signal output terminal.

[0017] The second output circuit is electrically connected to the pull-up node, the second clock signal terminal, and the second signal output terminal. The second output circuit is configured to transmit the signal received at the second clock signal terminal to the second signal output terminal in response to the signal from the pull-up node.

[0018] The second output circuit includes a seventh transistor and a third capacitor. The control electrode of the seventh transistor and the first electrode of the third capacitor are both electrically connected to the pull-up node. The first electrode of the seventh transistor is electrically connected to the second clock signal terminal. The second electrode of the seventh transistor and the second electrode of the third capacitor are electrically connected to the second signal output terminal.

[0019] In some embodiments, the output circuit further includes a first voltage regulator circuit and / or a second voltage regulator circuit. The first voltage regulator circuit is electrically connected to a first voltage regulator input, a pull-up node, and a second node. The second node is also electrically connected to the control electrode of a sixth transistor and the first electrode of a second capacitor. The first voltage regulator circuit is configured to transmit a signal from the pull-up node to the second node in response to a signal received at the first voltage regulator input. The first electrode of the sixth transistor receives a signal from a first clock signal terminal. The first voltage regulator circuit is also configured to interrupt the current path between the pull-up node and the second node in response to a signal received at the first voltage regulator input and a signal from the second node.

[0020] The first voltage regulator circuit includes an eighth transistor. The control terminal of the eighth transistor is electrically connected to the first voltage regulator input terminal, the first terminal of the eighth transistor is electrically connected to the pull-up node, and the second terminal of the eighth transistor is electrically connected to the second node.

[0021] The second voltage regulator circuit is electrically connected to the second voltage regulator input, the pull-up node, and the third node. The third node is also electrically connected to the control electrode of the seventh transistor and the first electrode of the third capacitor. The second voltage regulator circuit is configured to transmit the signal of the pull-up node to the third node in response to the signal received at the second voltage regulator input. The first electrode of the seventh transistor receives the signal at the second clock signal terminal. The second voltage regulator circuit is also configured to interrupt the current path between the pull-up node and the third node in response to the signal received at the second voltage regulator input and the signal of the third node.

[0022] The second voltage regulator circuit includes a ninth transistor. The control terminal of the ninth transistor is electrically connected to the input terminal of the second voltage regulator, the first terminal of the ninth transistor is electrically connected to the pull-up node, and the second terminal of the ninth transistor is electrically connected to the third node.

[0023] In some embodiments, the shift register further includes an input circuit and a cascaded reset circuit. The input circuit is electrically connected to a pull-up input control terminal, a pull-up signal input terminal, and a pull-up node. The input circuit is configured to transmit a signal received at the pull-up signal input terminal to the pull-up node in response to a signal received at the pull-up input control terminal.

[0024] The input circuit includes a tenth transistor. The control electrode of the tenth transistor is electrically connected to the pull-up input control terminal, the first electrode of the tenth transistor is electrically connected to the pull-up signal input terminal, and the second electrode of the tenth transistor is electrically connected to the pull-up node.

[0025] The cascaded reset circuit is electrically connected to the pull-up node, the cascaded reset control terminal, and the reset voltage signal terminal. The cascaded reset circuit is configured to transmit the signal received at the reset voltage signal terminal to the pull-up node in response to the signal received at the cascaded reset control terminal.

[0026] The cascaded reset circuit includes an eleventh transistor. The control terminal of the eleventh transistor is electrically connected to the cascaded reset control terminal, the first terminal of the eleventh transistor is electrically connected to the pull-up node, and the second terminal of the eleventh transistor is electrically connected to the reset voltage signal terminal.

[0027] In some embodiments, the shift register further includes a pull-down control circuit electrically connected to a pull-down signal input, a pull-up node, a pull-down node, and a pull-down voltage signal terminal. The pull-down control circuit is configured to, in response to a signal from the pull-up node and a signal received at the pull-down signal input, transmit a signal received at the pull-down voltage signal terminal to the pull-down node, and, in response to a signal from the pull-down node, transmit a signal received at the pull-down voltage signal terminal to the pull-up node.

[0028] The pull-down control circuit includes a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor. The control electrode and first electrode of the fourteenth transistor are electrically connected to the pull-down signal input terminal, and the second electrode of the fourteenth transistor is electrically connected to the pull-down node. The control electrode of the thirteenth transistor is electrically connected to the pull-down node, the first electrode of the thirteenth transistor is electrically connected to the pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the pull-down voltage signal terminal. The control electrode of the fifteenth transistor is electrically connected to the pull-up node, the first electrode of the fifteenth transistor is electrically connected to the second electrode of the fourteenth transistor, and the second electrode of the fifteenth transistor is electrically connected to the pull-down voltage signal terminal.

[0029] In some embodiments, the shift register further includes a pull-down reset circuit and an output reset circuit. The pull-down reset circuit is electrically connected to the pull-down node, the pull-up input control terminal, the access input control terminal, the first node, the pull-down voltage signal terminal, and the pull-down node. The pull-down reset circuit is configured to transmit the signal received at the pull-down voltage signal terminal to the pull-down node in response to a signal received at the pull-up input control terminal or in response to a signal received at the access input control terminal and a signal from the first node.

[0030] The pull-down reset circuit includes transistors sixteen, seventeen, and eighteen. The control electrode of transistor sixteen is electrically connected to the access input control terminal; its first electrode is electrically connected to the pull-down node; and its second electrode is electrically connected to the fourth node. The control electrode of transistor seventeen is electrically connected to the first node; its first electrode is electrically connected to the fourth node; and its second electrode is electrically connected to the pull-down voltage signal terminal. The control electrode of transistor eighteen is electrically connected to the pull-up input control terminal; its first electrode is electrically connected to the pull-down node; and its second electrode is electrically connected to the pull-down voltage signal terminal.

[0031] The output reset circuit is electrically connected to the signal output terminal, the pull-down voltage signal terminal, and the pull-down node. The output reset circuit is configured to transmit the signal received at the pull-down voltage signal terminal to the signal output terminal in response to the signal at the pull-down node.

[0032] The output reset circuit includes a twentieth transistor and a twenty-first transistor. The control electrode of the twentieth transistor is electrically connected to the pull-down node, the first electrode of the twentieth transistor is electrically connected to the first signal output terminal, and the second electrode of the twentieth transistor is electrically connected to the pull-down voltage signal terminal. The control electrode of the twenty-first transistor is electrically connected to the pull-down node, the first electrode of the twenty-first transistor is electrically connected to the second signal output terminal, and the second electrode of the twenty-first transistor is electrically connected to the pull-down voltage signal terminal.

[0033] In some embodiments, the pull-down reset circuit further includes a discharge circuit electrically connected to the fourth node, the reset control terminal, and the pull-down voltage signal terminal. The discharge circuit is configured to transmit a signal received at the pull-down voltage signal terminal to the fourth node in response to a signal received at the reset control terminal.

[0034] The discharge circuit includes a nineteenth transistor. The control electrode of the nineteenth transistor is electrically connected to the reset control terminal, the first electrode of the nineteenth transistor is electrically connected to the fourth node, and the second electrode of the nineteenth transistor is electrically connected to the pull-down voltage signal terminal.

[0035] On the other hand, the present invention provides a gate driving circuit including a shift register as described in any of the above embodiments.

[0036] The gate drive circuit of the present invention uses the above-mentioned shift register and has the same beneficial effects as the above-mentioned shift register, which will not be described in detail here.

[0037] In some embodiments, the multiple shift registers are divided into at least two shift register groups, each shift register group including at least two shift registers arranged sequentially. The gate drive circuit also includes multiple reset control lines and multiple signal storage control lines. The signal storage control terminal of each shift register in each shift register group is electrically connected to a signal storage control line, and the reset control terminal of each shift register in each shift register group is electrically connected to a reset control line.

[0038] In some embodiments, the multiple shift registers are divided into two cascaded groups. The first signal output terminal of the nth-stage shift register in each cascaded group is electrically connected to the pull-up input control terminal of the (n+1)th-stage shift register. The signal output terminal of the mth-stage shift register in each cascaded group is electrically connected to the first reset signal terminal of the (m-2)th-stage shift register. Here, n is a positive integer greater than or equal to 1, and m is a positive integer greater than or equal to 3.

[0039] In some embodiments, the gate drive circuit includes a plurality of shift registers arranged sequentially, with h adjacent shift registers forming an output group; the odd-numbered output group belongs to the first cascade group, and the even-numbered output group belongs to the second cascade group, where h is a positive integer greater than or equal to 3.

[0040] In some embodiments, the gate drive circuit further includes two clock signal line groups, each clock signal line group being electrically connected to each output group in a cascaded group. Each clock signal line group includes k×h clock signal lines, and each clock signal line in each clock signal line group is connected to a clock signal terminal of each shift register in the output group, where k is a positive integer greater than or equal to 1.

[0041] In another aspect, the present invention provides a display device including a gate driving circuit as provided in any of the embodiments described above.

[0042] The display device of the present invention employs the above-described gate driving circuit and has the same beneficial effects as the above-described gate driving circuit, which will not be described in detail here.

[0043] In another aspect, the present invention provides a driving method for a gate driving circuit as provided in any of the embodiments described above. The gate driving circuit includes a plurality of shift registers, divided into at least two shift register groups, each shift register group including at least two shift registers arranged sequentially. The gate driving circuit also includes a plurality of second reset control lines and a plurality of signal storage control lines. The signal storage control terminal of each shift register in each shift register group is electrically connected to a signal storage control line, and the reset control terminal of each shift register in each shift register group is electrically connected to a reset control line.

[0044] In some embodiments, the driving method includes: each shift register in each shift register group, under the control of a signal transmitted via a signal storage control line electrically connected thereto, inputting and storing a signal received at a storage signal input terminal; and each shift register in each shift register group, under the control of a signal transmitted via a reset control line electrically connected thereto, resetting each shift register.

[0045] The gate driving circuit driving method provided by the present invention can realize multiple input control modes for the shift register, satisfying that the cascaded circuit can control any one of the shift registers to output a scanning signal. Correspondingly, it enriches the control mode of pixels in the display panel, that is, it can control any row of pixels in multiple rows to emit light to form an image, while pixels in other positions are in an off state.

[0046] In some embodiments, the specific image display method of the gate driving circuit provided by the present invention is as follows:

[0047] During the first frame image display stage, each shift register of the gate drive circuit outputs a gate scan signal. Based on the position of the high-definition display area in the second frame image, the shift register electrically connected to the first sub-pixel row of the high-definition display area is determined as the first shift register. When a signal is received at the storage signal input terminal of the first shift register, under the control of the signal storage control line of the gate drive circuit electrically connected to the first shift register, the signal received at the storage signal input terminal is stored in the first shift register.

[0048] The second frame image display stage includes a high-definition display stage and a low-definition display stage. In the high-definition display stage, the first shift register outputs a gate scan signal under the control of signals received at the storage signal input terminal and the access input control terminal. Shift registers electrically connected to the sub-pixels of the high-definition display area sequentially output gate scan signals. In the low-definition display stage, the low-definition display area includes a first low-definition display area and a second low-definition display area, located on opposite sides of the high-definition display area. Multiple shift registers connected to the first low-definition display area output gate scan signals under the control of signals transmitted via the start signal line. Multiple shift registers connected to the second low-definition display area output gate scan signals under the control of cascaded signals output by shift registers connected to the high-definition display area. After scanning the first low-definition display area, multiple shift registers connected to the first low-definition display area are reset. After scanning the second low-definition display area, multiple shift registers connected to the second low-definition display area are reset.

[0049] In the high-definition display stage or the low-definition display stage, according to the position of the high-definition display area of ​​the next frame image, the shift register that is electrically connected to the first sub-pixel row of the high-definition display area among multiple shift registers is determined as the first shift register of the next frame image. The first shift register of the next frame image receives and stores the signal received at the storage signal input terminal.

[0050] During the third frame display phase to the E frame display phase, the steps of the second frame display phase are repeated, where E is a positive integer greater than or equal to 4. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 A structural diagram of a display device provided for an embodiment of the present invention;

[0053] Figure 2 A front view of another display device provided for an embodiment of the present invention;

[0054] Figure 3 A structural diagram of a display panel provided for an embodiment of the present invention;

[0055] Figure 4 A structural diagram of a shift register provided for an embodiment of the present invention;

[0056] Figure 5 A state diagram of a display panel provided for an embodiment of the present invention;

[0057] Figure 6 Another state diagram of the display panel provided for an embodiment of the present invention;

[0058] Figure 7 A circuit diagram of a shift register provided for an embodiment of the present invention;

[0059] Figure 8 A structural diagram of the access circuit provided for an embodiment of the present invention;

[0060] Figure 9 A circuit diagram of an access circuit provided for an embodiment of the present invention;

[0061] Figure 10 A structural diagram of an output circuit provided for an embodiment of the present invention;

[0062] Figure 11 A circuit diagram of an output circuit provided for an embodiment of the present invention;

[0063] Figure 12 A structural diagram of another output circuit provided for an embodiment of the present invention;

[0064] Figure 13 Another structural diagram of another output circuit provided for an embodiment of the present invention;

[0065] Figure 14 A circuit diagram of another output circuit provided for an embodiment of the present invention;

[0066] Figure 15 Structural diagrams of the pull-down control circuit, pull-down reset circuit, and output reset circuit provided for embodiments of the present invention;

[0067] Figure 16 Another structural diagram of a shift register provided for an embodiment of the present invention;

[0068] Figure 17 A structural diagram of the pull-down reset circuit and discharge circuit provided for embodiments of the present invention;

[0069] Figure 18 Circuit diagrams of a pull-down reset circuit and a discharge circuit provided for embodiments of the present invention;

[0070] Figure 19 A circuit diagram of another shift register provided for an embodiment of the present invention;

[0071] Figure 20A diagram showing the connection relationship between the signal storage control terminal and the reset control terminal of the shift register in different shift register groups and the signal lines, provided for embodiments of the present invention;

[0072] Figure 21 A front view of another display device provided as an embodiment of the present invention;

[0073] Figure 22 A state diagram of another display device provided as an embodiment of the present invention;

[0074] Figure 23 Another state diagram of a display device provided for an embodiment of the present invention;

[0075] Figure 24 A front view of another display device provided as an embodiment of the present invention;

[0076] Figure 25 A cascade diagram of shift registers provided for embodiments of the present invention;

[0077] Figure 26 A diagram showing the relationship between shift registers and output groups provided for embodiments of the present invention;

[0078] Figure 27 Another diagram showing the relationship between the shift register and the output group provided for embodiments of the present invention;

[0079] Figure 28 A flowchart of a driving method for a gate driving circuit provided in an embodiment of the present invention;

[0080] Figure 29 A timing diagram of the gate driving circuit provided in the first frame image according to an embodiment of the present invention;

[0081] Figure 30 Another timing diagram of the gate driving circuit provided in the first frame image according to an embodiment of the present invention;

[0082] Figure 31 A flowchart of a gate driving circuit driving method in a low-resolution display stage provided in an embodiment of the present invention;

[0083] Figure 32 Timing diagram of the gate driving circuit in other frames after the first frame image provided in the embodiments of the present invention;

[0084] Figure 33 Timing diagram of the output scanning signal of the gate driving circuit provided in the embodiments of the present invention during the high-definition display stage and the low-definition display stage. Detailed Implementation

[0085] The technical solutions in some embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided by the present invention are within the scope of protection of the present invention.

[0086] The terms "first," "second," etc., can be used to describe various components, but components are not limited to these terms. Terms are only used to distinguish one component from others.

[0087] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components are in physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0088] In addition, in some embodiments, "electrical connection" can refer to either a direct electrical connection or an indirect electrical connection.

[0089] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0090] The transistors used in the circuits provided in the embodiments of the present invention can be thin-film transistors, field-effect transistors (e.g., oxide thin-film transistors) or other switching devices with the same characteristics. In the embodiments of the present invention, thin-film transistors are used as an example for illustration.

[0091] In some embodiments, the control electrode of each transistor used in the shift register is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be structurally symmetrical, they can be structurally indistinguishable; that is, the first and second electrodes of the transistor in the embodiments of the present invention can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first electrode is the source and the second electrode is the drain; for example, when the transistor is an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0092] In the circuit provided in the embodiments of the present invention, nodes such as pull-up nodes and pull-down nodes do not represent actual existing components, but rather represent the junction points of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junction points of related electrical connections in the circuit diagram.

[0093] In embodiments of the present invention, the term "pull-up" refers to charging a node or an electrode of a transistor to increase the absolute value of the voltage level of the node or electrode, thereby enabling the operation of the corresponding transistor (e.g., turning it on). The term "pull-down" refers to discharging a node or an electrode of a transistor to decrease the absolute value of the voltage level of the node or electrode, thereby enabling the operation of the corresponding transistor (e.g., turning it off).

[0094] In embodiments of the present invention, the term "high level" refers to the potential magnitude of a node, a terminal, or an output terminal in a circuit, and this potential is sufficient to at least drive a transistor to turn on or off. For example, a high level can be 3.3V or 5V. Exemplarily, when the gate of a P-type transistor is in a high-level state, the voltage between the source and gate of the P-type transistor is greater than its threshold voltage, and the P-type transistor is in a off state; or when the gate of an N-type transistor is in a high-level state, the voltage between the source and gate of the N-type transistor is greater than its threshold voltage, and the N-type transistor is in a conducting state.

[0095] The term "low level" refers to the potential magnitude of a node, terminal, or output in a circuit, such that it is sufficient to at least drive a transistor to turn on or off. For example, a low level can be 0V. For instance, a P-type transistor is in a conducting state when its gate is at a low level and the voltage between its gate and source is less than its threshold voltage; or an N-type transistor is in a cutoff state when its gate is at a low level and the voltage between its gate and source is less than its threshold voltage.

[0096] In the circuits provided in the embodiments of the present invention, N-type transistors will be used as an example for explanation.

[0097] Some embodiments of the present invention provide a shift register, a gate driving circuit, a driving method thereof, and a display device. The shift register, the gate driving circuit, the driving method thereof, and the display device are described below.

[0098] Some embodiments of the present invention provide a display device that can be any device that displays text or images, whether in motion (e.g., video) or stationary (e.g., still images). More specifically, the embodiments are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) virtual reality (VR) head-mounted displays, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), and other devices capable of achieving stereoscopic visual effects.

[0099] like Figure 1 As shown, in some examples, the above-mentioned display device 1000 may include a frame 100, a display panel 200 disposed within the frame 100, a circuit board, a display driver IC (Integrated Circuit), and other electronic components.

[0100] The display panel 200 described above can be of various types. For example, the display panel 200 may include an array substrate, a light-emitting device, and an encapsulation layer. The substrate of the array substrate can be a glass substrate or a flexible polyimide (PI) substrate. The light-emitting device can be an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro light-emitting diode (Micro LED), etc., and this invention does not specifically limit its application.

[0101] In some embodiments, such as Figure 2 As shown, the display panel 200 includes a display area AA and a peripheral area BB disposed on at least one side of the display area. For example, the peripheral area BB can be located on one, two, or three sides of the display area AA, or the peripheral area BB can be disposed around the display area AA. The display area AA is provided with multiple signal lines and multiple pixels p arranged in an array. Each pixel p also includes a red sub-pixel Rp, a green sub-pixel Gp, and a blue sub-pixel Bp. The multiple signal lines include gate lines G, data lines L, and voltage signal lines V, etc.

[0102] In some embodiments, the gate driving circuit 300 is disposed in the array substrate in the form of a GOA (Gate on Array), for example, the gate driving circuit 300 may be located in the peripheral area BB. Of course, the gate driving circuit 300 may also be disposed in other locations, for example, disposed in the form of a driver chip on the non-display side of the display panel 200, and the present invention is not limited thereto. Each row of pixels p is electrically connected to at least one gate line G, and multiple gate lines G are electrically connected to the gate driving circuit 300. The gate driving circuit 300 is configured to provide scanning signals or light emission control signals to multiple pixels p, and the gate lines G are configured to transmit scanning signals or light emission control signals to multiple pixels p. Multiple pixels p emit light or turn off under the control of scanning signals or light emission control signals. The data line L is configured to transmit data signals to control the brightness of pixels p. The scanning signals or light emission control signals and the data signals complete a top-to-bottom scanning process of multiple rows of pixels p. During the scanning process, multiple rows of pixels p emit light sequentially with different brightness levels, forming a display image within the display area AA.

[0103] In some embodiments, such as Figure 3 As shown, the display device 1000 employs a light field display scheme to achieve a stereoscopic visual effect. Light field display requires that the display area AA of the display panel 200 include a first display mode area and a second display mode area, for example: a first display mode area (e.g., a high-definition display area HD) and a second display mode area (e.g., a low-definition display area LD). Furthermore, the position of the high-definition display area HD is not fixed for each frame. In some examples, in a certain frame of image display, the low-definition display area LD includes a first low-definition display area LD1 and a second low-definition display area LD2, with the high-definition display area HD located between the first low-definition display area LD1 and the second low-definition display area LD2. For example, in each frame of image, pixels p in the high-definition display area HD are scanned, forming a high-definition display image. After scanning in the high-definition display area HD, pixels p in the low-definition display area LD are scanned, forming a low-definition display image. The resolution or pixel count of the low-definition display image is lower than that of the high-definition display image. For example, multiple rows of pixels p in the low-definition display area LD are scanned simultaneously. Of course, the first display mode area and the second display mode area can be interchanged. For example, the first display mode area (e.g., low-definition display area LD) and the second display mode area (e.g., high-definition display area HD).

[0104] It should be noted that "low definition" and "high definition" are relative terms in this patent. Low definition refers to an image with a lower resolution or pixel count than a high definition image. For example, low definition can be an image with a resolution or pixel count equal to or lower than 2K (2K resolution is generally 2048×1080); for example, low definition can be 640*480 or 1920*1080. High definition refers to an image with a resolution or pixel count greater than 2K (2K resolution is generally 2048×1080); for example, 4K (4K resolution is generally 4096×2160), 8K (8K resolution is generally 7,680 × 4,320), etc.

[0105] To achieve the goal of accurately controlling the high-definition display area (HD) to form a high-definition display image and the low-definition display area (LD) to form a low-definition display image in each frame, for example, the shift register of the gate driving circuit 300 corresponding to the high-definition display area (HD) scans line w one by one, and the shift register of the gate driving circuit 300 corresponding to the low-definition display area (LD) scans line o one by one; where w and o are both positive integers, and o > w, for example, w can be 1 and o can be 2. That is to say, the clarity of the display image of the high-definition display area (HD) is relatively higher than that of the display image of the low-definition display area (LD).

[0106] In some related technologies, the gate driving circuit 300 can control the sequential scanning of pixels p in a single row or multiple rows. In the display device 1000 employing a light field display scheme, the high-definition display area HD is located in the center of the display area AA. However, its specific position in each frame is uncertain. During the scanning of the high-definition display area HD, the gate driving circuit 300 described in the related technologies cannot accurately apply an initial signal to the shift register electrically connected to the pixels p of the high-definition display area HD. That is, the shift register electrically connected to the high-definition display area HD in the gate driving circuit 300 described in the related technologies cannot output a scanning signal. Therefore, the high-definition display area HD cannot initiate scanning.

[0107] Based on this, on the one hand, the present invention proposes a shift register 10, a gate driving circuit 300 and its driving method, and a display device 1000.

[0108] The shift register 10 will be described in detail below with reference to the accompanying drawings and embodiments.

[0109] In some embodiments, such as Figure 4 As shown, the shift register 10 includes: an input circuit 1, an access circuit 2, an output circuit 3, a cascaded reset circuit 4, and a reset circuit 5.

[0110] The input circuit 1 is electrically connected to the pull-up input control terminal SC1, the pull-up signal input terminal SI1, and the pull-up node Q. The input circuit 1 is configured to transmit the signal received at the pull-up signal input terminal SI1 to the pull-up node Q in response to the signal received at the pull-up input control terminal SC1.

[0111] Access circuit 2 is electrically connected to signal storage control terminal SW, access input control terminal SC2, storage signal input terminal GN, access signal input terminal SI2 and pull-up node Q. Access circuit 2 is configured to input and store the signal received at storage signal input terminal GN in response to the signal received at signal storage control terminal SW. Access circuit 2 is also configured to transmit the signal received at access signal input terminal SI2 to pull-up node Q in response to the signal at storage signal input terminal GN and the signal received at access input control terminal SC2.

[0112] The output circuit 3 is electrically connected to the pull-up node Q, at least one clock signal terminal CL, and at least one signal output terminal SO. The output circuit 3 is configured to transmit the signal received at at least one clock signal terminal CL to the signal output terminal SO in response to the signal of the pull-up node Q.

[0113] Generally, shift register 10 is used in a gate driving circuit. Multiple shift registers in the gate driving circuit are cascaded sequentially. The shift register at this stage receives the scan signal output from the shift register at the previous stage and controls the output of its own scan signal, which is equivalent to the function implemented by input circuit 1. In the shift register provided in the above embodiment of the present invention, an access circuit 2 is provided. Access circuit 2 enables shift register 10 to change the potential of its pull-up node under the control of an external signal (the signal received at the signal storage control terminal SW), thereby controlling the output circuit to output a scan signal. This external signal is different from the cascaded signal; that is, in a gate driving circuit, any shift register 10 can be controlled to output a scan signal.

[0114] In some embodiments, the access circuit 2 is configured to input and store the signal received at the storage signal input terminal GN in response to the signal received at the storage signal input terminal GN and the signal received at the signal storage control terminal SO when the shift register 10 corresponds to the starting position of the next frame high-definition display area; at least one of the signal output terminals SO is electrically connected to the storage signal input terminal GN.

[0115] It should be noted that, as Figure 5As shown, the starting position of the next frame's high-definition display area indicates the initial row pixel p' of the high-definition display area HD' in the next frame image. The initial row pixel p' includes multiple rows of sub-pixels, and the first row of sub-pixels in the multiple rows of sub-pixels is the initial row sub-pixel. The shift register corresponds to the starting position of the high-definition display area, and this shift register is electrically connected to the initial row sub-pixel. In the display of one frame image, according to the position of the next frame's high-definition display area, when the shift register corresponds to the starting position of the next frame's high-definition display area, the signal received at the signal storage control terminal SW is at a high level, storing the signal at the storage signal input terminal GN, which is equivalent to storing the position of the next frame's high-definition display area in the current frame display. In the display of the next frame image, in response to the stored signal at the storage signal input terminal GN and the signal received at the access input control terminal SC2, the signal received at the access signal input terminal SI2 is transmitted to the pull-up node Q, which is equivalent to releasing the stored signal, causing the potential of the pull-up node Q to go high, realizing the output of the scan signal, and thus starting the scanning of the high-definition display area of ​​the next frame image. The specific process can be found in the description below.

[0116] In some embodiments, the shift register 10 includes at least one signal output terminal SO and at least one clock signal terminal CL, one of the at least one signal output terminal SO being electrically connected to the storage signal input terminal GN of the shift register. For example, the shift register 10 includes a signal output terminal SO, which is electrically connected to the storage signal input terminal GN. That is, in a cascaded circuit using multiple shift registers 10, one signal output terminal SO of the shift register 10 is electrically connected to the storage signal input terminal GN of the same stage shift register 10. The storage signal input terminal GN receives the scan signal output by the signal output terminal SO. In some examples, the pull-up node Q receives the signal transmitted by the input circuit 1 or the access circuit 2. The pull-up node Q is charged to a high level, and the signal received at the clock signal terminal CL is transmitted to the signal output terminal SO. At the same time, the scan signal output by the signal output terminal SO is transmitted to the gate line and the storage signal input terminal GN. The scan signal transmitted through the gate line scans the pixel P. Under the control of the signal storage control terminal SW, the scan signal received by the storage signal input terminal GN is transmitted to the access circuit 2.

[0117] In other embodiments, the storage signal input terminal GN is not connected to the signal output terminal SO, but can be electrically connected to a separate signal line in the gate drive circuit. This signal line is used to output a high-level signal to the storage signal input terminal GN of the shift register when the shift register 10 corresponds to the starting position of the next frame of high-definition display area, so that the shift register, under the control of the signal storage control terminal SW, will transmit the high-level signal received at the storage signal input terminal GN to the access circuit 2.

[0118] like Figure 4 and Figure 5 As shown, multiple shift registers 10, hereinafter referred to as HD shift registers 10a, are electrically connected to pixels p of the high-definition display area HD. The first of the multiple HD shift registers 10a receives a scan signal at the storage signal input terminal GN and a storage control signal at the signal storage control terminal SW. Under these conditions, the HD shift register 10a receives the scan signal received at the storage signal input terminal GN and stores it in the access circuit 2. Before scanning the next frame image, the access input control terminal SC2 receives a second input control signal. Under the control of the scan signal stored in the access circuit 2 and the second input control signal, the signal received at the access signal input terminal SI2 is transmitted to the pull-up node Q, meaning the voltage of the pull-up node Q of the first of the multiple HD shift registers 10a is at a high level. After the clock signal CL of the high-definition shift register 10a receives a high level, the signal output SO can output a scan signal to start the high-definition shift register 10a. After passing through the cascaded circuit, multiple high-definition shift registers 10a complete the scan signal output, and the pixel p located in the high-definition display area HD completes the scan to form a high-definition image.

[0119] Similarly, shift register 10, hereinafter referred to as low-resolution shift register 10b, which is electrically connected to pixel p located in the low-resolution display area LD, does not receive a signal at its signal storage control terminal SW when the storage signal input terminal GN receives a scan signal. Therefore, the access circuit 2 of low-resolution shift register 10b fails to receive the scan signal from it. When the access input control terminal SC2 receives a signal, the access circuit 2 of low-resolution shift register 10b cannot transmit the signal received at the access signal input terminal SI2 to the pull-up node Q, meaning the voltage of the pull-up node Q is low. Simultaneously, to ensure that the signal at the simultaneous pull-up input control terminal SC1 remains low during this stage, the first input circuit 1 cannot transmit the signal from the signal input terminal SI1 to the pull-up node, and the pull-up node remains low. Therefore, the signal output terminal SO of low-resolution shift register 10b fails to output a scan signal, and thus the low-resolution display area will not start scanning to form an image.

[0120] In some embodiments, the access signal input terminal SI2 can be connected to the same signal line as the access input control terminal SC2, meaning that the access signal input terminal SI2 and the access input control terminal SC2 receive the same signal. Of course, the access signal input terminal SI2 can receive a fixed voltage signal, such as a high-level voltage signal VDD; or, the access signal input terminal SI2 can also receive the same signal as the potential signal compensation terminal DI or the pull-up signal input terminal SI1.

[0121] The access circuit 2 can receive and store the scan signals. During the display of one frame of image, during the pixel scanning process of the high-definition display area (HD), w of the multiple shift registers 10 simultaneously output scan signals. That is, during the pixel scanning process of the high-definition display area (HD), the access circuit 2 of w shift registers 10 simultaneously receives scan signals. During the pixel scanning process of the low-definition display area (LD), o of the multiple shift registers 10 simultaneously output scan signals. That is, during the pixel scanning process of the low-definition display area (HD), the access circuit 2 of o shift registers 10 simultaneously receives scan signals.

[0122] In some embodiments, such as Figure 4 and Figure 5 As shown, the cascaded reset circuit 4 is electrically connected to the pull-up node Q, the cascaded reset control terminal RE1, and the reset voltage signal terminal REV. The cascaded reset circuit 4 is configured to transmit the signal received at the reset voltage signal terminal REV to the pull-up node Q in response to the signal received at the cascaded reset control terminal RE1.

[0123] The reset circuit 5 is electrically connected to the pull-up node Q, the reset control terminal RE2, and the reset voltage signal terminal REV. The reset circuit 5 is configured to transmit the signal received at the reset voltage signal terminal REV to the pull-up node Q in response to the signal received at the reset control terminal RE2.

[0124] In some examples, such as Figure 4 and Figure 5 As shown, where, Figure 5 The square dashed box in the image represents the high-definition display area HD' in the next frame, and the shaded area within the square dashed box represents the initial row of pixels p' of the high-definition display area HD' in the next frame. The initial row of pixels p' comprises at least three rows of sub-pixels, each row of sub-pixels being electrically connected to a shift register.

[0125] In a frame of an image, as the pixels of the high-definition display area HD are scanned line by line (w), the signal output terminal SO of the high-definition shift register 10a transmits the scan signal to the storage signal input terminal GN. When the initial row pixel p' of the high-definition display area HD' of the next frame of the image adjacent to the previous frame is located in the high-definition display area HD of the previous frame, the high-definition shift register 10a electrically connected to the initial row pixel p' of the high-definition display area HD' of the next frame receives and stores the storage signal received at the storage signal input terminal GN under the control of the signal storage control terminal SW. Multiple high-definition shift registers 10a simultaneously output w scan signals, that is, the number of shift registers 10a electrically connected to the initial row pixel p' can be w. Here, the initial row pixel p' refers to the pixel that initially emits light during the scanning process of the high-definition display area HD'. Generally, the pixels that initially emit light during the scanning process of the high-definition display area HD' are the first two rows of pixels in the high-definition display area HD', that is, the initial row pixel p' can be the first two rows of pixels in the high-definition display area HD'.

[0126] like Figure 6 As shown, Figure 6 The square dashed box in the image represents the high-definition display area HD' in the next frame, and the shaded part within the square dashed box represents the initial row pixels p' of the high-definition display area HD' in the next frame.

[0127] In one frame of an image, the pixels of the high-definition display area HD are scanned line by line, while the pixels of the low-definition display area LD are scanned line by line. The signal output terminal SO of the low-definition shift register 10b transmits the scan signal to the storage signal input terminal GN. In the next frame of the image, the initial row pixel p' of the high-definition display area HD' is located in the low-definition display area LD of the previous frame of the image. The shift register 10b, which is electrically connected to the initial row pixel p' of the high-definition display area HD' of the next frame of the image, receives the storage signal received at the storage signal input terminal GN and stores it under the control of the storage control signal received at the signal storage control terminal SW.

[0128] During the scanning time of one frame of image, a storage control signal is transmitted to the signal storage control terminal SW at a specific time. This can control a specific shift register 10 to receive and store the scan signal, thereby enabling the control of the position of the initial row pixel p' of the high-definition display area HD in the display area AA. After receiving the clock signal at the clock signal terminal CL of the shift register 10, the high-definition display area HD pixels form a scan.

[0129] In some embodiments, such as Figure 7 As shown, the input circuit 1 includes a tenth transistor T10. The control electrode of the tenth transistor T10 is electrically connected to the pull-up input control terminal SC1, the first electrode of the tenth transistor T10 is electrically connected to the pull-up signal input terminal SI1, and the second electrode of the tenth transistor T10 is electrically connected to the pull-up node Q.

[0130] For example, the pull-up input control terminal SC1 receives a first input control signal. The voltage of the first input control signal is high. The tenth transistor T10 is turned on under the control of the first input control signal and transmits the first input signal received at the pull-up signal input terminal SI1 to the pull-up node Q. The pull-up node Q is charged under the action of the first input signal, and the voltage of the pull-up node Q is high.

[0131] In some cascaded circuits, the pull-up input control terminal SC1 can be electrically connected to the first signal output terminal SO1 of the previous stage shift register, and the pull-up signal input terminal SI1 can be electrically connected to the high-level signal terminal VDD, wherein the signal at the high-level signal terminal VDD remains at a high level.

[0132] In some embodiments, such as Figure 7 As shown, the cascaded reset circuit 4 includes an eleventh transistor T11. The control terminal of the eleventh transistor T11 is electrically connected to the cascaded reset control terminal RE1. The first terminal of the eleventh transistor T11 is electrically connected to the pull-up node Q. The second terminal of the eleventh transistor T11 is electrically connected to the reset voltage signal terminal REV.

[0133] For example, the voltage at the reset voltage signal terminal REV remains low, for example, the voltage at REV is zero. The voltage of the first reset control signal received by the cascaded reset control terminal RE1 is high, and the eleventh transistor T11 is turned on under the control of the first reset control signal. The signal of the pull-up node Q is output to the reset voltage signal terminal REV through the current path of the eleventh transistor T11, and the voltage at the pull-up node Q drops to a low level, thus resetting the voltage of the pull-up node Q and preparing for the next scan. In some cascaded circuits, the cascaded reset control terminal RE1 can be electrically connected to the first signal output terminal SO1 of the shift registers of the first two stages. The reset voltage signal terminal REV can be electrically connected to the low-level signal terminal VGL, and the signal at the low-level signal terminal VGL remains low.

[0134] In some embodiments, such as Figure 8 As shown, the access circuit 2 includes a signal storage sub-circuit 2a and a signal extraction sub-circuit 2b. The signal storage sub-circuit 2a is electrically connected to the signal storage control terminal SW, the stored signal input terminal GN, and the first node N1. The signal storage sub-circuit 2a is configured to transmit the signal received at the stored signal input terminal GN to the first node N1 in response to the signal received at the signal storage control terminal SW.

[0135] The signal extraction sub-circuit 2b is electrically connected to the first node N1, the access input control terminal SC2, and the pull-up node Q. The signal extraction sub-circuit 2b is configured to transmit the signal received at the access signal input terminal SI2 to the pull-up node Q in response to the signal of the first node N1 and the second input control signal received at the access input control terminal SC2, wherein the voltage of the second input control signal is high.

[0136] In some examples, the signal storage sub-circuit 2a receives a scan signal at its storage signal input terminal GN, and under the control of the storage control signal received at the signal storage control terminal SW, the signal storage sub-circuit 2a transmits the scan signal to the first node N1, wherein the voltage of the scan signal is high, that is, the voltage of the first node N1 is high. The signal extraction sub-circuit 2b, under the signal control of the first node N1, transmits the signal received at the access signal input terminal SI2 to the pull-up node Q, wherein the voltage of the second input control signal is high, that is, the voltage of the pull-up node Q is high.

[0137] During the scanning of any frame image, the first node N1 receives and stores the scanning signal transmitted by the storage sub-circuit 2a, and participates in the scanning of the next frame image. During the time period between scanning any frame image and the next frame image, the first node N1 receives and stores the scanning signal, maintains the voltage at a high level, and prepares for scanning the next frame image.

[0138] In some embodiments, such as Figure 7 As shown, the reset circuit 5 includes a twelfth transistor T12. The control terminal of the twelfth transistor T12 is electrically connected to the reset control terminal RE2. The first terminal of the twelfth transistor T12 is electrically connected to the pull-up node Q. The second terminal of the twelfth transistor T12 is electrically connected to the reset voltage signal terminal REV.

[0139] For example, the reset control terminal RE2 receives the second reset control signal. The voltage of the second reset control signal is high. The twelfth transistor T12 is turned on under the control of the second reset control signal, which turns on the current path between the pull-up node Q and the reset voltage signal terminal REV. The voltage of the pull-up node Q is low.

[0140] After the first low-resolution display area LD1 finishes scanning, the reset circuit 5 resets the shift register 10, which is electrically connected to the pixel p located in the first low-resolution display area LD1, interrupting the scanning process of the first low-resolution display area LD1 and preventing the first low-resolution display area LD1 from covering the position of the high-resolution display area HD in the frame image.

[0141] In some embodiments, such as Figure 9As shown, the signal storage sub-circuit 2a includes a first transistor T1, a second transistor T2, and a first capacitor C1. The control terminals of both the first transistor T1 and the second transistor T2 are electrically connected to the signal storage control terminal SW. The first terminal of the first transistor T1 is electrically connected to the storage signal input terminal GN. The second terminal of the first transistor T1 is electrically connected to the first terminal of the second transistor T2. The second terminal of the second transistor T2 is electrically connected to the first node N1.

[0142] The first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the voltage regulator signal terminal VS. For example, the voltage of the voltage regulator signal terminal VS is kept at a low level, such as zero.

[0143] For example, the storage control terminal SW receives a storage control signal, and the storage control signal voltage is high. The first transistor T1 and the second transistor T2 can be turned on under the control of the storage control signal. The first transistor T1 and the second transistor T2 will transmit the scan signal received at the storage signal input terminal GN to the first node N1. The voltage of the scan signal is high, and the voltage at the first node N1 is high.

[0144] In some embodiments, the signal storage sub-circuit 2a further includes a third transistor T3, the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the potential signal compensation terminal, and the second electrode of the third transistor T3 is electrically connected at the junction of the second electrode of the first transistor T1 and the first electrode of the second transistor T2.

[0145] In some examples, such as Figure 9 As shown, the signal storage sub-circuit 2a includes: a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1. The control electrodes of both the first transistor T1 and the second transistor T2 are electrically connected to the signal storage control terminal SW. The first electrode of the first transistor T1 is electrically connected to the storage signal input terminal GN. The second electrode of the first transistor T1 is electrically connected to the first electrode of the second transistor T2. The second electrode of the second transistor T2 is electrically connected to the first node N1. The control electrode of the third transistor T3 is electrically connected to the first node N1. The first electrode of the third transistor T3 is electrically connected to the potential signal compensation terminal DI. The second electrode of the third transistor T3 is electrically connected at the junction of the first electrode of the first transistor T1 and the second electrode of the second transistor T2. For example, the voltage of the potential signal compensation terminal DI can be high, such as 3.3V or 5V.

[0146] The first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the regulated signal terminal VS. After the first node N1 receives and stores the scan signal, the first capacitor C1 assists the first node N1 in storing the signal and maintains the voltage stability at the first node N1.

[0147] When the voltage of the first node N1 is high, the third transistor T3 receives the voltage signal at the potential signal compensation terminal DI and transmits it to the connection point of the first electrode of the first transistor T1 and the second electrode of the second transistor T2 to compensate for the voltage at the connection point of the first electrode of the first transistor T1 and the second electrode of the second transistor T2, so as to avoid the voltage drop at the first node N1 caused by transistor leakage and keep the voltage of the first node N1 stable.

[0148] In some embodiments, such as Figure 9 As shown, the signal extraction sub-circuit 2b includes a fourth transistor T4 and a fifth transistor T5. The control electrode of the fourth transistor T4 is electrically connected to the first node N1, the first electrode of the fourth transistor T4 is electrically connected to the access signal input terminal SI2, the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the fifth transistor T5, the control electrode of the fifth transistor T5 is electrically connected to the access input control terminal SC2, and the second electrode of the fifth transistor T5 is electrically connected to the pull-up node Q.

[0149] For example, signal storage sub-circuit 2a receives and stores the scan signal. The voltage of the first node N1 is high, and the fourth transistor T4 can be turned on under the control of the voltage signal of the first node N1. The access input control terminal SC2 receives the second input control signal. The voltage of the second input control signal is high, and the fifth transistor T5 can be turned on under the control of the second input control signal. When the voltage of the first node N1 is high and the access input control terminal SC2 receives the second input control signal, the signal storage sub-circuit 2a is a conducting circuit. The second input control signal is transmitted to the pull-up node Q through the fourth transistor T4 and the fifth transistor T5 in sequence. The pull-up node Q is charged under the action of the second input control signal, and the voltage of the pull-up node Q is high.

[0150] In some embodiments, such as Figure 10As shown, output circuit 3 includes a first output circuit 3a and a second output circuit 3b. The clock signal terminal CL includes a first clock signal terminal CL1 and a second clock signal terminal CL2. The signal output terminal SO includes a first signal output terminal SO1 and a second signal output terminal SO2. The first output circuit 3a is electrically connected to the pull-up node Q, the first clock signal terminal CL1, and the first signal output terminal SO1. The first output circuit 3a is configured to transmit the signal received at the first clock signal terminal CL1 to the first signal output terminal SO1 in response to the signal from the pull-up node Q. The first signal output terminal SO1 is electrically connected to the stored signal input terminal GN. The second output circuit 3b is electrically connected to the pull-up node Q, the second clock signal terminal CL2, and the second signal output terminal SO2. The second output circuit 3b is configured to transmit the signal received at the second clock signal terminal CL2 to the second signal output terminal SO2 in response to the signal from the pull-up node Q.

[0151] For example, the voltage of the pull-up node Q is high. Under the signal control of the pull-up node Q, the first clock signal terminal CL1 of the first output circuit 3a receives the first clock signal and transmits the first clock signal to the first signal output terminal SO1, and the first signal output terminal SO1 outputs the first scan signal; or, under the signal control of the pull-up node Q, the second clock signal terminal CL2 of the second output circuit 3b receives the second clock signal and transmits the second clock signal to the second signal output terminal SO2, and the second signal output terminal SO2 outputs the second scan signal, wherein the voltages of the first clock signal, the second clock signal, the first scan signal, and the second scan signal are all high.

[0152] In some embodiments, such as Figure 11 As shown, the first output circuit 3a includes a sixth transistor T6 and a second capacitor C2. The control electrode of the sixth transistor T6 and the first electrode of the second capacitor C2 are both electrically connected to the pull-up node Q. The first electrode of the sixth transistor T6 is electrically connected to the first clock signal terminal CL1. The second electrode of the sixth transistor T6 and the second electrode of the second capacitor C2 are electrically connected to the first signal output terminal SO1.

[0153] For example, when the voltage of pull-up node Q is high, the sixth transistor T6 is turned on under the control of pull-up node Q, transmitting the first clock signal received at the first clock signal terminal CL1 to the first signal output terminal SO1, whereby SO1 outputs the first scan signal. Conversely, when the voltage of pull-up node Q is low, the sixth transistor T6 is turned off under the control of pull-up node Q, the first clock signal received at the first clock signal terminal CL1 cannot pass through the sixth transistor T6, and the voltage at the first signal output terminal SO1 is low, for example, zero.

[0154] In some embodiments, such as Figure 11As shown, the second output circuit 3b includes a seventh transistor T7 and a third capacitor C3. The control terminal of the seventh transistor T7 and the first terminal of the third capacitor C3 are both electrically connected to the pull-up node Q. The first terminal of the seventh transistor T7 is electrically connected to the second clock signal terminal CL2. The second terminal of the seventh transistor T7 and the second terminal of the third capacitor C3 are electrically connected to the second signal output terminal SO2.

[0155] For example, when the voltage of pull-up node Q is high, the seventh transistor T7 is turned on under the control of pull-up node Q, transmitting the second clock signal received at the second clock signal terminal CL2 to the second signal output terminal SO2, which outputs the second scan signal. Conversely, when the voltage of pull-up node Q is low, the seventh transistor T7 is turned off under the control of pull-up node Q, the second clock signal received at the second clock signal terminal CL2 cannot pass through the seventh transistor T7, and the voltage at the second signal output terminal SO2 is low, for example, zero.

[0156] In some embodiments, such as Figure 12 and Figure 13 As shown, the first voltage regulator circuit 3c is electrically connected to the first voltage regulator input terminal VR1, the pull-up node Q, and the third node N2. The first voltage regulator circuit 3c is configured to transmit the signal of the pull-up node Q to the second node N2 in response to the signal received at the first voltage regulator input terminal VR1. The first terminal of the sixth transistor T6 receives the signal at the first clock signal terminal CL1. The first voltage regulator circuit 3c is also configured to interrupt the current path between the pull-up node Q and the second node N2 in response to the signal received at the first voltage regulator input terminal VR1 and the signal of the second node N2.

[0157] The second voltage regulator circuit 3d is electrically connected to the second voltage regulator input terminal VR2, the pull-up node Q, and the third node N3. The third node N3 is also electrically connected to the control electrode of the seventh transistor T7 and the first electrode of the third capacitor C3. The second voltage regulator circuit 3d is configured to transmit the signal of the pull-up node Q to the third node N3 in response to the signal received at the second voltage regulator input terminal VR2. The first electrode of the seventh transistor T7 receives the signal at the second clock signal terminal CL2. The second voltage regulator circuit 3d is also configured to interrupt the current path between the pull-up node Q and the third node N3 in response to the signal received at the second voltage regulator input terminal VR2 and the signal of the third node N3.

[0158] For example, the signal at the pull-up node Q controls the conduction or cutoff of the sixth transistor T6 and the seventh transistor T7. For instance, if the voltage at the pull-up node Q is high, it controls the conduction of either the sixth transistor T6 or the seventh transistor T7. If there is leakage at the pull-up node Q, the voltage at the pull-up node Q will drop after the sixth transistor T6 is turned on, which may cause the seventh transistor T7 to fail to conduct.

[0159] When the sixth transistor T6 is turned on, the voltage of the second node N2 in the first voltage regulator circuit 3c is the same as the voltage of the pull-up node Q. The voltage of the first scan signal output terminal SO1 is high. Under the coupling effect of the second capacitor C2, the voltage of the second node N2 is higher than the voltage of the pull-up node Q. Under this condition, the first voltage regulator circuit 3c cuts off the current path between the pull-up node Q and the second node N2, and the voltage of the pull-up node Q remains stable, ensuring that the seventh transistor T7 is turned on sufficiently.

[0160] Similarly, the operation of the second voltage regulator circuit is the same as that of the first voltage regulator circuit, and will not be described in detail here. In some examples, the shift register 10 is equipped with either a first voltage regulator circuit, a second voltage regulator circuit, or both.

[0161] In some embodiments, such as Figure 14 As shown, the first voltage regulator circuit 3c includes an eighth transistor T8. The control terminal of the eighth transistor T8 is electrically connected to the first voltage regulator input terminal VR1, the first terminal of the eighth transistor T8 is electrically connected to the pull-up node Q, and the second terminal of the eighth transistor T8 is electrically connected to the second node N2.

[0162] In some embodiments, such as Figure 14 As shown, the second voltage regulator circuit 3d includes a ninth transistor T9. The control terminal of the ninth transistor T9 is electrically connected to the second voltage regulator input terminal VR2, the first terminal of the ninth transistor T9 is electrically connected to the pull-up node Q, and the second terminal of the ninth transistor T9 is electrically connected to the third node N3.

[0163] In some examples, the signal voltages received at both the first regulated input terminal VR1 and the second regulated input terminal VR2 are high. The control electrode of the eighth transistor T8 or the ninth transistor T9 is turned on under the control of the high level, transmitting the signal from the pull-up node Q to the second node N2 or the third node N3. The voltage at the second node N2 is high, and the sixth transistor T6 is turned on, transmitting the first clock signal received at the first clock signal terminal CL1 to the first signal output terminal SO1. Under the coupling effect of the second capacitor C2, the voltage at the second node N2 is higher than the voltages of the pull-up node Q and the first regulated input terminal VR1. Under this condition, the sixth transistor T6 is turned off, thus interrupting the current path between the pull-up node Q and the second node N2, preventing a voltage drop at the pull-up node Q due to leakage, and maintaining the voltage stability of the pull-up node Q, ensuring the output stability of other output circuits. Similarly, the working principle of the ninth transistor T9 is the same as that of the eighth transistor T8, and will not be elaborated here.

[0164] In some embodiments, such as Figure 15As shown, the shift register 10 also includes a pull-down control circuit 6, which is electrically connected to the pull-down signal input terminal DIN, the pull-up node Q, the pull-down node QB, and the pull-down voltage signal terminal DV. The pull-down control circuit 6 is configured to, in response to a signal from the pull-up node Q and a signal received at the pull-down signal input terminal DIN, transmit the signal received at the pull-down voltage signal terminal DIN to the pull-down node QB; and, in response to a signal from the pull-down node QB, transmit the signal received at the pull-down voltage signal terminal DV to the pull-up node Q.

[0165] In some examples, the voltage of pull-up node Q is high, and the pull-down control circuit 6, under the signal control of pull-up node Q, conducts the current path between pull-down node QB and pull-down voltage signal terminal DV. The voltage of pull-down voltage signal terminal DV is maintained at a low level, and the voltage of pull-down node QB is low. When the current path between pull-down node QB and pull-down voltage signal terminal DV is broken, the pull-down signal input terminal DIN receives the pull-down signal, which is high. Pull-down node QB is charged under the action of the pull-down signal, and the voltage of pull-down node QB rises to a high level. Furthermore, under the signal control of pull-down node QB, the pull-down control circuit 6 conducts the current path between pull-up node QB and pull-down voltage signal terminal DV.

[0166] In some embodiments, such as Figure 7 As shown, the pull-down control circuit 6 includes a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15. The control electrode and first electrode of the fourteenth transistor T14 are both electrically connected to the pull-down signal input terminal DIN, and the second electrode of the fourteenth transistor T14 is electrically connected to the pull-down node QB. The control electrode of the thirteenth transistor T13 is electrically connected to the pull-down node QB, the first electrode of the thirteenth transistor T13 is electrically connected to the pull-up node Q, and the second electrode of the thirteenth transistor T13 is electrically connected to the pull-down voltage signal terminal DV. The control electrode of the fifteenth transistor T15 is electrically connected to the pull-up node Q, the first electrode of the fifteenth transistor T15 is electrically connected to the second electrode of the fourteenth transistor T14, and the second electrode of the fifteenth transistor T15 is electrically connected to the pull-down voltage signal terminal DV.

[0167] In some examples, when the voltage at pull-up node Q is high, the fifteenth transistor T15, under the signal control of pull-up node Q, conducts the current path between pull-down node QB and the pull-down voltage signal terminal DV, maintaining the voltage at pull-down node QB at a low level. When the pull-down signal input terminal DIN receives the pull-down signal and the voltage at pull-down node QB is high, the thirteenth transistor T13, under the signal control of pull-down node QB, conducts the current path between pull-up node Q and the pull-down voltage signal terminal DV, discharging the voltage at pull-up node Q and returning it to a low level. In other words, when the voltage at pull-up node Q is high, the voltage at pull-down node QB is low; or, when the voltage at pull-down node QB is high, the voltage at pull-up node Q is low.

[0168] The voltages between the pull-up node Q and the pull-down node QB are opposite to prevent leakage current from entering the pull-up node Q, which would cause the voltage of the pull-up node Q to rise abnormally and cause the signal output terminal SO of the shift register 10 to output current. This would cause the pixel p electrically connected to the shift register 10 to emit light or flash during the time period that it should be off, which can effectively improve the display quality of the image.

[0169] In some embodiments, such as Figure 15 and Figure 16 As shown, the shift register 10 also includes a pull-down reset circuit 7 and an output reset circuit 8. The pull-down reset circuit 7 is electrically connected to the pull-down node QB, the pull-up input control terminal SC1, the access input control terminal SC2, the first node N1, the pull-down voltage signal terminal DV, and the pull-down node QB. The pull-down reset circuit 7 is configured to transmit the signal received at the pull-down voltage signal terminal DV to the pull-down node in response to a signal received at the pull-up input control terminal SC1 or in response to a signal received at the access input control terminal SC2 and a signal from the first node N1.

[0170] For example, when the pull-up input control terminal SC1 receives the first input control signal, or the access input control terminal SC2 receives the second input control signal, the voltage signal of the first node N1 is at a high level, the current path between the pull-down node QB and the pull-down voltage signal terminal DV is turned on, the voltage of the pull-down node QB drops or remains at a low level, that is, the current path between the pull-up node Q and the pull-down voltage signal terminal DV is turned off. At this time, the pull-up node Q can be boosted after charging. In other words, when the input circuit 1 or the access circuit 2 outputs a signal to the pull-up node Q, the voltage of the pull-up node Q is at a high level.

[0171] The pull-down reset circuit 7 can prepare the input circuit 1 or the access circuit 2 to output a signal to the pull-up node Q, so as to avoid the situation where the voltage of the pull-up node Q remains at a low level after the input circuit 1 or the access circuit 2 outputs a signal to the pull-up node Q when there is a current path between the pull-up node Q and the pull-down voltage signal terminal DV.

[0172] The output reset circuit 8 is electrically connected to the signal output terminal SO, the pull-down voltage signal terminal DV, and the pull-down node QB. The output reset circuit 8 is configured to transmit the signal received at the pull-down voltage signal terminal DV to the signal output terminal SO in response to the signal of the pull-down node QB.

[0173] For example, under the signal control of the pull-down node QB, the output reset circuit 8 conducts the current path between the signal output terminal SO and the pull-down voltage signal terminal DV, which can ensure that the voltage of the signal output terminal SO is maintained at a low level, and prevent the signal output terminal SO from outputting noise signals during the non-output scanning signal stage. Noise signals will interfere with the normal illumination and extinguishing of pixels. The output reset circuit 8 can improve the display quality.

[0174] In some embodiments, such as Figure 7 As shown, the pull-down reset circuit 7 includes a sixteenth transistor T16, a seventeenth transistor T17, and an eighteenth transistor T18. The control electrode of the sixteenth transistor T16 is electrically connected to the access input control terminal SC2; its first electrode is electrically connected to the pull-down node QB; and its second electrode is electrically connected to the fourth node N4. The control electrode of the seventeenth transistor T17 is electrically connected to the first node N1; its first electrode is electrically connected to the fourth node N4; and its second electrode is electrically connected to the pull-down voltage signal terminal DV. The control electrode of the eighteenth transistor T18 is electrically connected to the pull-up input control terminal SC1; its first electrode is electrically connected to the pull-down node QB; and its second electrode is electrically connected to the pull-down voltage signal terminal DV.

[0175] For example, under the control of the first input control signal received at the pull-up input control terminal SC1, the eighteenth transistor T18 conducts the current path between the pull-down node QB and the pull-down voltage signal terminal DV, and the voltage of the pull-down node QB is low after discharge. Alternatively, when the voltage of the first node N1 is high, the seventeenth transistor T17 conducts under the signal control of the first node N1. When the access input control terminal SC2 receives the second input control signal, the sixteenth transistor T16 conducts under the signal control received at the access input control terminal SC2. That is, the sixteenth transistor T16 and the seventeenth transistor T17 conduct the current path between the pull-down node QB and the pull-down voltage signal terminal DV, and the voltage of the pull-down node QB is low after discharge.

[0176] In some embodiments, such as Figure 7 and Figure 19 As shown, the output reset circuit 8 includes a twentieth transistor T20 and a twenty-first transistor T21. The control electrode of the twentieth transistor T20 is electrically connected to the pull-down node QB, the first electrode of the twentieth transistor T20 is electrically connected to the first signal output terminal SO1, and the second electrode of the twentieth transistor T20 is electrically connected to the pull-down voltage signal terminal DV. The control electrode of the twenty-first transistor T21 is electrically connected to the pull-down node QB, the first electrode of the twenty-first transistor T21 is electrically connected to the second signal output terminal SO2, and the second electrode of the twenty-first transistor T21 is electrically connected to the pull-down voltage signal terminal DV.

[0177] For example, when the voltage of the pull-down node QB is high, the twentieth transistor T20 and the twenty-first transistor T21 are turned off under the signal control of the pull-down node QB, and the first signal output terminal SO1 or the second signal output terminal SO2 outputs a scan signal with a high voltage. When the voltage of the pull-down node QB is low, the twentieth transistor T20 and the twenty-first transistor T21 are turned on under the signal control of the pull-down node QB, and the current path between the first signal output terminal SO1 and the second signal output terminal SO2 and the pull-down voltage signal terminal DV is connected, maintaining the voltage of the first signal output terminal SO1 and the second signal output terminal SO2 at a low level.

[0178] In some embodiments, Figure 17 and Figure 19 As shown, the pull-down reset circuit 7 also includes a discharge circuit 8, which is electrically connected to the fourth node N4, the reset control terminal RE2, and the pull-down voltage signal terminal DV. The discharge circuit 8 is configured to transmit the signal received at the pull-down voltage signal terminal DV to the fourth node N4 in response to the signal received at the reset control terminal RE2.

[0179] For example, in a plurality of shift registers 10 electrically connected to pixel P located in the low-resolution display area LD, the voltage of the first node N1 is low, and the seventeenth transistor T17 is cut off under the signal control of the first node N1. When the access input control terminal SC2 receives the second input control signal, the sixteenth transistor T16 is turned on under the control of the second input control signal received at the access input control terminal SC2, that is, the pull-down node QB charges the fourth node N4, causing the voltage at the fourth node N4 to be high. When the fourth node N4 is high, and the sixteenth transistor T16 is in the cut-off state, there may be leakage current, which may affect the voltage at the pull-down node QB, and thus affect the normal output of the output circuit 3. The discharge circuit 8 is turned on under the control of the second reset control signal received at the reset control terminal RE2, and the current path between the fourth node N4 and the pull-down voltage signal terminal DV is turned on, so that the voltage of the fourth node N4 can drop to a low level after discharge. The discharge circuit 8 can keep the voltage of the fourth node N4 at a low level, maintain the voltage stability of the pull-down node QB, and ensure the normal output of the output circuit 3.

[0180] In some embodiments, such as Figure 18 and Figure 19 As shown, the discharge circuit 8 includes a nineteenth transistor T19. The control terminal of the nineteenth transistor T19 is electrically connected to the reset control terminal RE2, the first terminal of the nineteenth transistor T19 is electrically connected to the fourth node N4, and the second terminal of the nineteenth transistor T19 is electrically connected to the pull-down voltage signal terminal DV. The pull-down voltage signal terminal DV can receive a fixed voltage signal, such as a low-level voltage signal. The pull-down voltage signal terminal DV can be electrically connected to the low-level signal terminal VGL, and the signal at the low-level signal terminal VGL remains low; for example, the voltage at the low-level signal terminal VGL can be zero.

[0181] It should be noted that the reset voltage signal terminal REV and the pull-down voltage signal terminal DV can be connected to the low-level signal terminal VGL, and the voltage at the reset voltage signal terminal REV and the pull-down voltage signal terminal DV is zero.

[0182] For example, the reset control terminal RE2 receives the second reset control signal, and the nineteenth transistor T19, under the control of the second reset control signal, turns on the current path between the fourth node N4 and the pull-down voltage signal terminal DV, and the voltage of the fourth node N4 drops to a low level.

[0183] On the other hand, the present invention also provides a gate driving circuit 300, which is described in detail below with reference to the accompanying drawings and embodiments.

[0184] In some embodiments, the gate drive circuit 300 includes a plurality of shift registers 10 as described in any of the above embodiments.

[0185] The gate driving circuit 300 of the present invention can, according to the position of the high-definition display area in the next frame image, provide a high-level signal to the shift register that is electrically connected to the pixel located in the high-definition display area by using an access circuit to pull up the node. This achieves the purpose of controlling the shift register that is electrically connected to the pixel of the high-definition display area in the next frame image to output the scan signal first, and the remaining shift registers to output the scan signal later.

[0186] In some embodiments, such as Figure 21 and Figure 7 As shown, the multiple shift registers 10 are divided into at least two shift register groups GP, and each shift register group GP includes at least two shift registers 10 arranged sequentially. The gate drive circuit 300 also includes multiple reset control lines TRST and multiple signal storage control lines OE. The signal storage control terminal SW of each shift register 10 in each shift register group GP is electrically connected to one signal storage control line OE, and the reset control terminal RE2 of each shift register 10 in each shift register group GP is electrically connected to one reset control line TRST.

[0187] like Figure 21 and Figure 7 As shown, multiple shift registers 10 are divided into two shift register groups GP. The gate drive circuit includes two reset control lines TRST and two signal storage control lines OE. The two shift register groups GP include: a first shift register group GP1 and a second shift register group GP2. Correspondingly, the display panel is divided into an upper half and a lower half. In some examples, the N shift registers included in the gate drive circuit are divided into two groups. The N shift registers are arranged sequentially from the first shift register to the Nth shift register. The first shift register group GP1 includes shift registers from the first shift register to the N / 2th shift register, which correspond to the sub-pixels of the starting row to the middle row of the display device 1000. The second shift register group GP2 includes shift registers from the N / 2+1th shift register to the Nth shift register, which correspond to the sub-pixels of the middle row to the last row of the display device 1000. The first shift register group GP1 controls the pixels of the upper half of the display panel, and the second shift register group GP2 corresponds to the pixels of the lower half of the display panel.

[0188] like Figure 20 As shown, the two signal storage control lines OE include: a first signal storage control line OE1 and a second signal storage control line OE2. The first signal storage control line OE1 is electrically connected to the signal storage control terminal SW of each shift register 10 in the first shift register group GP1; the second signal storage control line OE2 is electrically connected to the signal storage control terminal SW of each shift register 10 in the second shift register group GP2.

[0189] The two reset control lines TRST include: a first reset control line TRST1 and a second reset control line TRST2. The first reset control line TRST1 is electrically connected to the reset control terminal RE2 of each shift register 10 in the first shift register group GP1; the second reset control line TRST2 is electrically connected to the reset control terminal RE2 of each shift register 10 in the second shift register group GP2.

[0190] For example, such as Figure 5 and Figure 6 As shown, multiple low-resolution shift registers 10b electrically connected to pixel p located in the first low-resolution display area LD1 are hereinafter referred to as the first low-resolution shift register 10b1; multiple low-resolution shift registers 10b electrically connected to pixel p located in the second low-resolution display area LD2 are hereinafter referred to as the second low-resolution shift register 10b2. It should be noted that since the position of the high-resolution display area is not fixed in each frame, it is uncertain which shift registers among all the shift registers included in the gate drive circuit are the first low-resolution shift register 10b, the second low-resolution shift register 10b2, or the high-resolution shift registers.

[0191] In most cases, such as Figure 21 and Figure 22 As shown, the high-definition display area HD is located in the middle of the display area AA. After pixel p in the high-definition display area HD completes scanning, HD starts scanning pixel p in the second low-definition display area LD2 through the cascaded relationship of the gate drive circuit 300. Pixel p in the first low-definition display area LD1 starts scanning under the drive of the start signal. When pixel p in the first low-definition display area LD1 scans to the boundary with the high-definition display area HD, multiple first low-definition shift registers 10b1 receive the second reset control signal transmitted by the first reset control line TRST1 electrically connected to them, and perform voltage reset of the pull-up node Q. The first low-definition shift registers 10b1 stop outputting scanning signals, and pixel p in the first low-definition display area LD1 stops scanning. At the same time, the second low-definition shift register 10b2 continues to output scanning signals until the last row of sub-pixels in the second low-definition display area LD2 completes scanning.

[0192] At least two reset control lines TRST are set up. The reset control terminal RE2 of each shift register 10 in each shift register group GP is electrically connected to a reset control line TRST. This enables independent control of the reset operation of each shift register group GP, thereby independently controlling the scanning stop position of the first low-resolution display area LD1 and the second low-resolution display area LD2, avoiding mutual interference between the scanning of pixel p in the first low-resolution display area LD1 and the scanning of pixel p in the second low-resolution display area LD2.

[0193] It should be noted that, as Figure 21 and Figure 23 As shown in the diagram, GP1 is the first shift register group, which is electrically connected to the first reset control line TRST1 and the first signal storage control line OE1. The second shift register group GP2 is electrically connected to the second reset control line TRST2 and the second signal storage control line OE2. This connection relationship is fixed. The high-definition shift register 10a is a shift register electrically connected to the pixel p in the high-definition display area (HD). Its actual position changes in each frame. Therefore, it cannot be determined whether the high-definition shift register 10a and the low-definition shift register 10b are electrically connected to the first reset control line TRST1 and the first signal storage control line OE1, or to the second reset control line TRST2 and the second signal storage control line OE2.

[0194] There may be situations where, for example, the area of ​​the high-definition display area (HD) in a certain frame is small, and its position in the display area AA is too high or too low. For instance, such as... Figure 23 As shown, in a certain frame, the high-definition display area HD is located in the upper half of the display area AA, not in the middle. All the reset control terminals of the high-definition shift registers 10a are electrically connected to the first reset control line TRST1. The reset control terminals of some of the second low-definition shift registers 10b2 are also electrically connected to TRST1, while the reset control terminals of another portion of the second low-definition shift registers 10b2 are electrically connected to TRST2. It is possible that after pixel p in the first low-definition display area LD1 completes scanning, the first low-definition shift register 10b1 receives the first reset control signal transmitted by TRST1 and stops outputting the scanning signal. Correspondingly, the portion of the first low-definition shift registers 10b1 electrically connected to pixel p in the second low-definition display area LD2 does not complete the scanning operation. That is, the voltage of the pull-up node Q is reset by the second reset control signal transmitted by TRST1. In other words, pixel p in the second low-definition display area LD2 is forcibly interrupted before scanning is completed.

[0195] Based on the above, in some other examples, the N shift registers included in the gate drive circuit are divided into more than two groups. For example, the gate drive circuit includes four shift register groups, such as... Figure 19 and Figure 24 As shown, the shift register group GP includes: a first shift register group GP1, a second shift register group GP2, a third shift register group GP3, and a fourth shift register group GP4. The first shift register group GP1, the second shift register group GP2, the third shift register group GP3, and the fourth shift register group GP4 are arranged sequentially from one end of the display device 1000 to the other end, and each first shift register group GP1 includes at least two shift registers 10.

[0196] The reset control line TRST includes: a first reset control line TRST1, a second reset control line TRST2, a third reset control line TRST3, and a fourth reset control line TRST4. The first shift register group GP1 is electrically connected to the first reset control line TRST1, the second shift register group GP2 is electrically connected to the second reset control line TRST2, the third shift register group GP3 is electrically connected to the third reset control line TRST3, and the fourth shift register group GP4 is electrically connected to the fourth reset control line TRST4.

[0197] The gate drive circuit is divided into multiple shift register groups, and multiple reset control lines TRST are set. This ensures that even if the high-definition display area HD is positioned too high or too low in a frame, the scanning of the second low-definition display area LD2 will not be affected when the last row of sub-pixels in the first low-definition display area LD1 is scanned and a reset operation is performed via the reset control line of the shift register group corresponding to the first low-definition display area LD1. In other words, there will be no forced interruption before the scan is completed. Specifically, this avoids the situation where the shift register 10 corresponding to the second low-definition display area LD2, without completing the scan signal output, will not cause its reset circuit to conduct the current path between the pull-up node Q and the reset voltage signal terminal REV under the control of the second reset control signal received at the reset control terminal, resulting in zero voltage at the pull-up node Q and causing the shift register 10 to stop outputting the scan signal.

[0198] In some examples, such as Figure 24 As shown, the number of signal storage control lines OE is the same as the number of reset control lines TRST. Each shift register group GP, which is electrically connected to one reset control line TRST, is electrically connected to one signal storage control line OE.

[0199] During the sequential scanning process of each shift register in each shift register group GP, the high-definition shift register 10a is determined according to the position of the high-definition display area HD of the next frame image. When scanning to the first of the sequentially arranged high-definition shift registers 10a, the signal storage control line OE outputs a storage control signal, which stores the voltage signal received at the storage signal input terminal GN of at least two shift registers in the sequentially arranged high-definition shift registers 10a that are electrically connected to the first two rows of pixels in the high-definition display area into the first node, causing the voltage of the first node N1 to rise to a high level. This process is called capturing the starting row of the high-definition display area HD of the next frame image.

[0200] Multiple signal storage control lines (OE) can prevent the simultaneous output of scanning signals by the first low-resolution shift register 10b1 and the second low-resolution shift register 10b2 during the simultaneous scanning of the first low-resolution display area LD1 and the second low-resolution display area LD2. When multiple signal storage control lines (OE) transmit storage control signals to the first low-resolution shift register 10b1 or the second low-resolution shift register 10b2, it may cause the first node N1 of one of the first low-resolution shift registers 10b1 and the second low-resolution shift register 10b2 to store voltage signals. The voltage of the first node N1 of both shift registers will become high level, that is, when scanning the next frame of image, two high-resolution display areas (HD) will be generated, causing display errors.

[0201] In some embodiments, such as Figure 25 As shown, multiple shift registers 10 are divided into two cascaded groups SRG. The first signal output terminal SO1 of the nth shift register 10 in each cascaded group SRG is electrically connected to the pull-up input control terminal SC1 of the (n+1)th shift register 10.

[0202] The first signal output terminal SO1 of the m-th stage shift register 10 is electrically connected to the first reset signal terminal RE1 of the (m-2)-th stage shift register 10.

[0203] In some examples, the two cascaded groups SRG include: a first cascaded group SRG1 and a second cascaded group SRG2. The first cascaded group SRG1 and the second cascaded group SRG2 each include multiple shift registers 10 arranged sequentially, and their structures can be identical. For example, the scan signal output from the first signal output terminal SO1 of the nth stage shift register 10 of the first cascaded group SRG1 is transmitted to the (n+1)th stage shift register 10. For example, n can be a positive integer such as 1, 2, 3, or 100. That is, the output signal of the shift register 10 controls the voltage of the pull-up node Q of the adjacent next-stage shift register 10 to rise to a high level. Thus, the first cascaded group SRG1 and the second cascaded group SRG2 form a cascaded circuit that scans sequentially.

[0204] It should be noted that the gate drive circuit 300 also includes a start signal line STV. The pull-up input control terminal SC1 of the first-stage shift register 10 of the first cascade group SRG1 and the second cascade group SRG2 is electrically connected to the start signal line. The start signal line STV transmits the start signal to the pull-up input control terminal SC1 of the first-stage shift register 10.

[0205] In some examples, the first signal output terminal SO1 of the m-th stage shift register 10 of the first cascaded group SRG1 is also electrically connected to the first reset signal terminal RE1 of the (m-2)-th stage shift register 10. For example, m can be a positive integer greater than 2, such as 3, 4, or 5. That is, the output signal of shift register 10 controls the voltage of the pull-up node Q of the shift register 10 spaced apart from it to drop to a low level. In this way, each shift register 10 in each cascaded group SRG outputs a scan signal and then stops outputting within the time period of one frame of image.

[0206] It should be noted that the voltage reset at the pull-up node Q of the last two shift registers 10 of each cascaded SRG can be controlled by a reset circuit. That is, after the last two shift registers 10 of each cascaded SRG output the complete scan signal, the last two shift registers 10 receive the second reset control signal to realize the voltage reset at the pull-up node Q.

[0207] It should be noted that, as Figure 25 As shown, the gate drive circuit includes multiple shift registers arranged sequentially from top to bottom. For example, the first shift register, the second shift register, ..., the twelfth shift register ... the Nth shift register in the figure are numbered sequentially according to their position. The sequentially arranged shift registers correspond to the sub-pixel rows arranged sequentially from top to bottom in the display area. In the cascaded group SRG, the first signal output terminal SO1 of the nth stage shift register 10 is electrically connected to the pull-up input control terminal SC1 of the (n+1)th stage shift register 10. This refers to the cascading relationship between shift registers within the cascaded group, for example... Figure 25 The 7th shift register in the first cascade group SRG1 is the fourth-stage shift register. That is, the first signal output terminal SO1 of the 3rd shift register (the third-stage shift register in SRG1) is electrically connected to the pull-up input control terminal SC1 of the 7th shift register (the fourth-stage shift register in SRG1). The cascade relationship of other shift registers is the same as this example, and will not be described in detail here.

[0208] In some embodiments, such as Figure 26 As shown, the gate drive circuit 300 includes multiple shift registers 10 arranged sequentially, and adjacent h shift registers 10 form an output group OG; wherein, the odd-numbered output group OG belongs to the first cascade group SRG1, and the even-numbered output group OG belongs to the second cascade group SRG2, where h is a positive integer greater than or equal to 3.

[0209] For example, the gate driving circuit 300 includes two cascaded groups SRG: a first cascaded group SRG1 and a second cascaded group SRG2. Multiple shift registers 10 of the gate driving circuit 300 are arranged sequentially from one end of the display device 1000 to the other end, and the multiple shift registers 10 are numbered sequentially from one end of the display device 1000 to the other end using positive integers greater than or equal to 1. The gate lines of each shift register 10 are arranged in parallel, and each gate line is electrically connected to a row of sub-pixels.

[0210] In this arrangement, multiple shift registers 10 are arranged sequentially, with every h adjacent shift registers 10 forming an output group OG. For example, h can be 3, meaning the first, second, and third shift registers form the first output group OG1, the fourth, fifth, and sixth form the second output group OG2, and so on; or h can be 4, meaning the first, second, third, and fourth shift registers form the first output group OG1, the fifth, sixth, seventh, and eighth form the second output group OG2, and so on. In the sequentially arranged output groups OG, the odd-numbered output group OG belongs to the first cascade group SRG1, and the even-numbered output group OG belongs to the second cascade group SRG2. In other words, the output groups included in the first cascade group SRG1 and the second cascade group SRG2 are alternately configured.

[0211] In some examples, the subpixels of display panel 100 can be arranged in multiple ways, for example Figure 24 As shown, the display area AA includes multiple pixels p arranged in an array. Each pixel p includes a red sub-pixel Rp, a green sub-pixel Gp, and a blue sub-pixel Bp. The red sub-pixels Rp, Gp, and Bp are arranged in a column direction to form one pixel p. Multiple red sub-pixels Rp are arranged in a row direction, multiple green sub-pixels Gp are arranged in a row direction, and multiple blue sub-pixels Bp are arranged in a row direction.

[0212] h can be 3, meaning that each output group OG is electrically connected to a row of pixels p. The multiple rows of sub-pixels in the display area AA are arranged sequentially from one end of the display area AA to the other using positive integers. That is, the first concatenated group SRG1 is electrically connected to the sub-pixels p in rows 6a-5 to 6a-3, and the second concatenated group SRG2 is electrically connected to the sub-pixels p in rows 6a-2 to 6a. Here, a is a positive integer greater than or equal to 1. For example, a can be 1, and the sub-pixels p in rows 1 to 3 are electrically connected to the first concatenated group SRG1, and the sub-pixels p in rows 4 to 6 are electrically connected to the second concatenated group SRG2; or a can be 2, and the sub-pixels p in rows 7 to 9 are electrically connected to the first concatenated group SRG1, and the sub-pixels p in rows 10 to 12 are electrically connected to the second concatenated group SRG2.

[0213] In other examples, for example Figure 27As shown, the display area AA includes multiple pixels p arranged in an array. Each pixel p includes: a red sub-pixel Rp, a green sub-pixel Gp, a blue sub-pixel Bp, and a white sub-pixel Wp. Specifically, the red sub-pixels Rp, Gp, Bp, and Wp are arranged in a column direction to form one pixel p. Multiple red sub-pixels Rp are arranged in a row direction, multiple green sub-pixels Gp are arranged in a row direction, multiple blue sub-pixels Bp are arranged in a row direction, and multiple white sub-pixels Wp are arranged in a row direction.

[0214] h can be 4, meaning that each output group OG is electrically connected to a row of pixels p. The sub-pixels in the display area AA are arranged sequentially from one end of the display area AA to the other using positive integers. That is, the first concatenated group SRG1 is electrically connected to the sub-pixels p in rows 8a-7 to 8a-4, and the second concatenated group SRG2 is electrically connected to the sub-pixels p in rows 8a-3 to 8a. Here, a is a positive integer greater than or equal to 1. For example, a can be 1, and the sub-pixels p in rows 1 to 4 are electrically connected to the first concatenated group SRG1, and the sub-pixels p in rows 5 to 8 are electrically connected to the second concatenated group SRG2; or a can be 2, and the sub-pixels p in rows 9 to 12 are electrically connected to the first concatenated group SRG1, and the sub-pixels p in rows 13 to 16 are electrically connected to the second concatenated group SRG2.

[0215] Each shift register can have two signal output terminals, that is, each shift register is electrically connected to two scan signal lines G, and the two scan signal lines G are electrically connected to a row of sub-pixels. For example, the first scan signal line G1 is electrically connected to the red sub-pixels Rp that are spaced apart, and the second scan signal line G2 is electrically connected to other red sub-pixels Rp that are spaced apart. This connection method can reduce the number of data lines.

[0216] In some embodiments, the gate drive circuit 300 further includes two clock signal line groups CLG: a first clock signal line group CLG1 and a second clock signal line group CLG2, each clock signal line group being electrically connected to each output group OG in a cascaded group SRG.

[0217] Each clock signal line group (CLG) includes k×h clock signal lines. Each clock signal line in each CLG is electrically connected to a clock signal terminal of each shift register 10 in the output group (OG). Here, k is a positive integer greater than or equal to 1.

[0218] In some examples, shift register 10 includes at least one signal output terminal. The number of signal output terminals of shift register 10 is k. For example, k can be 1, and every adjacent h shift registers 10 form an output group OG. That is, the number of shift registers 10 in an output group OG is h. When h is 3, an output group OG includes 3 clock signal terminals, that is, a clock signal line group includes 3 clock signal lines. When h is 4, an output group OG includes 4 clock signal terminals, that is, a clock signal line group includes 4 clock signal lines. For example, k can be 2, and every adjacent h shift registers 10 form an output group OG. That is, the number of shift registers 10 in an output group OG is h. When h is 3, an output group OG includes 6 clock signal terminals, that is, a clock signal line group includes 6 clock signal lines. When h is 4, an output group OG includes 8 clock signal terminals, that is, a clock signal line group includes 8 clock signal lines.

[0219] In some examples, each clock signal line group (CLG) controls one cascaded group (SRG). The clock signal transmitted through the CLG controls the shift registers 10 of each cascaded group SRG to output scan signals sequentially. Controlling the clock signals transmitted through two CLGs allows the two cascaded group SRGs to alternately output scan signals, achieving line-by-line scanning of the sub-pixels in the display area, thus forming a high-definition display area. Alternatively, the two cascaded groups can output scan signals simultaneously, achieving two-line simultaneous scanning of the sub-pixels in the display area, thus forming a low-definition display area.

[0220] In some embodiments, such as Figure 25 As shown in the figure, only the connection relationship between the shift register and each signal line is illustrated; the arrangement or positional relationship of the shift registers is not specified. Each shift register 10 includes a first output circuit and a second output circuit, meaning each shift register 10 has two clock signal terminals CL: a first clock signal terminal CL1 and a second clock signal terminal CL2; and two output terminals SO: a first signal output terminal SO1 and a second signal output terminal SO2. The two output terminals SO are electrically connected to a row of sub-pixels. When h is 3, each output group OG has six clock signal terminals CL; when h is 4, each output group OG has eight clock signal terminals CL. Therefore, each clock signal line group includes 6 / 8 clock signal lines. Each clock signal line in each clock signal line group is electrically connected to one first clock signal terminal CL1 or one second clock signal terminal CL2 of each shift register 10 in the output group OG.

[0221] For example, each clock signal line group includes six clock signal lines. For instance, among multiple clock signal lines, clock signal lines CLKE1, CLKE2, CLKE3, CLKE4, CLKE5, and CLKE6 form one clock signal line group, while clock signal lines CLKE7, CLKE8, CLKE9, CLKE10, CLKE11, and CLKE12 form another clock signal line group.

[0222] The gate drive circuit 300 includes a first cascaded group SRG1 and a second cascaded group SRG2. Each output group OG includes three shift registers 10, and each shift register 10 includes a first clock signal terminal CL1 and a second clock signal terminal CL2, that is, each output group OG includes three first clock signal terminals CL1 and three second clock signal terminals CL2.

[0223] In the first cascaded group SRG1, the three first clock signal terminals CL1 of each output group OG can be connected one-to-one with the clock signal lines CLKE1, CLKE2 and CLKE3 of a clock signal line group; the three second clock signal terminals CL2 of each output group OG in the first cascaded group SRG1 can be connected one-to-one with the clock signal lines CLKE4, CLKE5 and CLKE6 of a clock signal line group.

[0224] In the second cascaded group SRG2, the three first clock signal terminals CL1 of each output group OG can be connected one-to-one with the clock signal lines CLKE7, CLKE8 and CLKE9 of another clock signal line group; in the first cascaded group SRG1, the three second clock signal terminals CL2 of each output group OG can be connected one-to-one with the clock signal lines CLKE10, CLKE11 and CLKE12 of another clock signal line group.

[0225] It should be noted that the shift register 10 may include only one output circuit. Accordingly, when h is 3, each clock signal line group includes 3 clock signal lines, and when h is 4, each clock signal line group includes 4 clock signal lines. 3 / 4 clock signal lines in each clock signal line group are electrically connected to a clock signal terminal CL of each shift register 10 in the output group OG.

[0226] For example, each clock signal line group includes three clock signal lines. For instance, in a multi-clock signal line group, clock signal lines CLKE1, CLKE2, and CLKE3 form one clock signal line group, and clock signal lines CLKE4, CLKE5, and CLKE6 form another clock signal line group. The three clock signal terminals CL of each output group OG in the first cascade group SRG1 can be connected one-to-one with the clock signal lines CLKE1, CLKE2, and CLKE3 of one clock signal line group.

[0227] In the second cascade group SRG2, the three clock signal terminals CL of each output group OG can be connected one-to-one with the clock signal lines CLKE4, CLKE5 and CLKE6 of another clock signal line group.

[0228] In some embodiments, such as Figure 25 As shown, the gate drive circuit 300 also includes a second input control line CLKA, which is electrically connected to the access input control terminal SC2 of the shift register 10.

[0229] For example, the access input control terminal SC2 of the shift register 10 of the gate drive circuit 300 is electrically connected to the second input control line CLKA. Before the scanning of pixels in the high-definition display area of ​​each frame image begins, the second input control line CLKA transmits a second input control signal to the access input control terminal SC2. Under the control of the second input control signal and the first node signal, the shift register 10, with the voltage of the first node high, writes the second input control signal into the pull-up node. The voltage of the pull-up node is high. After receiving the clock signal at the clock signal terminal of the shift register 10, the output signal terminal outputs the scan signal. Through the cascade circuit of the first cascade group SRG1 and the first cascade group SRG2 and the timing of the control clock signal, the pixels of the display area are scanned line by line to form the high-definition display area.

[0230] It should be noted that, to ensure that the voltage of the pull-up node of the first high-definition shift register in multiple cascaded groups is high during pixel scanning in the high-definition display area, the storage control signal transmitted on the signal storage control line OE should raise the voltage of the first node N1 of at least one shift register 10 in one output group OG of each cascaded group SRG to a high level.

[0231] On the other hand, some embodiments of the present invention provide a driving method for a gate driving circuit. This driving method is applied to the gate driving circuit provided in any of the embodiments of the above-mentioned other aspects. The gate driving circuit includes a plurality of shift registers, divided into at least two shift register groups, each shift register group including at least two shift registers arranged sequentially. The gate driving circuit also includes a plurality of reset control lines and a plurality of signal storage control lines. The signal storage control terminal of each shift register in each shift register group is electrically connected to a signal storage control line, and the reset control terminal of each shift register in each shift register group is electrically connected to a reset control line.

[0232] The driving methods for the gate drive circuit include:

[0233] S1. Each shift register in each shift register group, under the control of the signal transmitted through the signal storage control line electrically connected to it, inputs and stores the signal received at the storage signal input terminal.

[0234] S2. Each shift register in each shift register group is reset under the control of the signal transmitted through the reset control line electrically connected to it.

[0235] In some examples, the signal output terminals of each shift register are electrically connected to the storage signal input terminals. Under the control of the signal transmitted by the signal storage control line, the shift register receives and stores the scan signal output by the signal output terminal. For example, if the signal output terminal outputs a high-level signal, the shift register receives and stores the high-level signal; if the signal output terminal outputs a low-level signal, the shift register receives and stores the low-level signal. Accordingly, the signal of the first node N1 of the shift register can be either high-level or low-level.

[0236] The above method allows shift registers to have multiple input control modes, satisfying the requirement that cascaded circuits can control any one of the shift registers to output a scanning signal. Correspondingly, it enriches the control modes of pixels in the display panel, that is, it can control any row of pixels in multiple rows to emit light to form an image, while pixels in other positions are in an off state.

[0237] To enable cascaded shift registers to interrupt scanning and reset the signals transmitted on the control lines, the shift registers can be reset. Specifically, the pull-up nodes of the shift registers can be reset, allowing the shift registers to stop outputting scan signals from the next shift register after a certain shift register has completed its signal output, under the control of external signals.

[0238] In some embodiments, such as Figure 28 As shown, a specific driving method for a gate driving circuit using the above method is as follows:

[0239] Y1, First frame image display stage

[0240] The first frame image display phase S1 includes:

[0241] Y11, the shift registers of the gate drive circuit output scan signals.

[0242] Y12. Based on the position of the high-definition display area of ​​the second frame image, determine the shift register that is electrically connected to the first two pixel rows of the high-definition display area among multiple shift registers, and use it as the first shift register.

[0243] Y13. When a signal is received at the storage signal input terminal of the first shift register, the signal received at the storage signal input terminal is stored in the first shift register under the control of the signal storage control line of the gate drive circuit electrically connected to the first shift register.

[0244] For example, such as Figure 29 or Figure 30 As shown, during the first frame image display stage, the gate drive circuit controls N sequentially arranged shift registers to output scan signals one by one, or every two shift registers to output scan signals sequentially. Correspondingly, the pixels in the display area of ​​the display panel are scanned sequentially row by row or every two rows.

[0245] Based on the position of the high-definition display area of ​​the second frame image, the high-definition shift registers among the N shift registers can be determined. After all the first low-definition shift registers output scan signals, any high-definition shift register belonging to the first output group in the first cascade group, and any high-definition shift register belonging to the first output group in the second cascade group, are all the first shift registers.

[0246] When the storage signal input terminal of the first shift register belonging to the first cascade group and the second cascade group receives the storage signal, the signal storage control terminal of the first shift register receives the storage control signal and stores the storage control signal to the first node.

[0247] Y2, Second Frame Image Display Stage

[0248] The second frame image display stage S2 includes: a high-definition display stage S21 and a low-definition display stage S22.

[0249] Y21, High-definition display stage,

[0250] The high-definition display stage includes:

[0251] Y21a, the first shift register outputs a scan signal under the control of the signal received at the storage signal input terminal and the signal received at the access input control terminal.

[0252] Y21b and the shift register electrically connected to the sub-pixels of the high-definition display area sequentially output gate scan signals.

[0253] Y21c. In the high-definition display stage, based on the position of the high-definition display area in the next frame image, a shift register that is electrically connected to the first sub-pixel row of the high-definition display area is determined among a plurality of shift registers and used as the first shift register of the next frame image. The first shift register of the next frame image receives and stores the signal received at the storage signal input terminal.

[0254] In some examples, such as Figure 32 and Figure 33 As shown, Figure 32 Timing diagram for transmitting signals on clock signal lines. Figure 33 This is a timing diagram of the signal output terminals. The display panel includes two shift register groups. The shift registers located from one end to the middle of the display panel constitute the first shift register group, and the remaining shift registers constitute the second shift register group. In the two cascaded groups of this display panel, each output group includes three shift registers, and each shift register has two output circuits: a first output circuit and a second output circuit.

[0255] In the gate drive circuit, the storage signal input terminal of the shift register is electrically connected to the signal output terminal of the shift register at this stage. The second input control line transmits the second input control signal, and all shift registers receive the second input control signal. However, only the first shift register, under the control of the storage signal stored in the first node and the second input control signal, transmits the second input control signal to the pull-up node.

[0256] The first and second signal storage control lines transmit signals, and the signal storage control terminals of all shift registers receive signals transmitted by either the first or second signal storage control line. At this time, the signal output terminal of the shift register is at a low level. Therefore, under the control of the signal transmitted by the first or second signal storage control line, the signal storage control terminal of the shift register receives the low-level signal from the signal output terminal and stores it in the first node; that is, the signal of the first node remains low. The first nodes of all shift registers are reset to prepare for storing charge in the first nodes of the shift registers corresponding to the starting position of the high-definition display area in the next frame.

[0257] The six clock signal lines of the first clock signal group output clock signals sequentially. Each shift register in the first output group of the first cascaded group outputs scan signals sequentially, and the pixel rows electrically connected to the first output group of the first cascaded group illuminate. Similarly, the six clock signal lines of the second clock signal group output clock signals sequentially. Each shift register in the first output group of the second cascaded group outputs scan signals sequentially, and the pixel rows electrically connected to the first output group of the second cascaded group illuminate. Likewise, under the control of the alternating clock signals from the two clock signal groups, the output groups of the first and second cascaded groups alternately output scan signals, and the shift registers in each output group output scan signals sequentially. This achieves sequential output of scan signals from the sequentially arranged shift registers, and correspondingly, the sub-pixel rows electrically connected to the shift registers illuminate sequentially, achieving high image clarity in the high-definition display area.

[0258] Y22, Low-resolution display stage;

[0259] like Figure 31 As shown, in the low-definition display stage, the low-definition display area includes a first low-definition display area and a second low-definition display area. The first low-definition display area and the second low-definition display area are respectively located on both sides of the high-definition display area. The low-definition display stage includes:

[0260] Y22a, multiple shift registers connected to the first low-resolution display area output gate scan signals under the control of the signals transmitted on the start signal line.

[0261] Y22b and multiple shift registers connected to the second low-definition display area output gate scan signals under the control of cascaded signals output by shift registers connected to the high-definition display area.

[0262] Y22c: After scanning the first low-resolution display area, under the control of the signal transmitted by the first reset signal line, the multiple shift registers connected to the first low-resolution display area are reset.

[0263] Y22d After scanning the second low-resolution display area is completed, the multiple shift registers connected to the second low-resolution display area are reset under the control of the signal transmitted by the second reset signal line.

[0264] In some examples, such as Figure 30As shown, in the low-definition display stage, the start signal line STV transmits the start signal. The cascaded group belonging to the first shift register group starts to output the scan signal under the control of the clock signal transmitted by the clock signal line. The cascaded group belonging to the second shift register group starts to output the scan signal under the control of the scan signal and clock signal output by the shift register in the high-definition display stage. Specifically, multiple clock signal lines in the first clock signal group transmit clock signals sequentially, and multiple clock signal lines in the second clock signal group transmit clock signals sequentially. Moreover, one clock signal line in the first clock signal group and one clock signal line in the second clock signal group simultaneously output the scan signal. This satisfies the requirement that a row of sub-pixels electrically connected by the first cascaded group and a row of sub-pixels controlled by the second cascaded group emit light simultaneously. In other words, the sub-pixel rows of two rows of pixels in the display panel emit light simultaneously. Correspondingly, the image clarity of the display panel is reduced compared to the high-definition display stage.

[0265] When a pixel in the first low-resolution display area is scanned to the boundary of the high-resolution display area, the corresponding shift register electrically connected to the first low-resolution display area, i.e., the reset control terminal of the first low-resolution shift register, receives the signal transmitted by the first reset control line TRST1, and the first low-resolution shift register completes the reset and stops scanning.

[0266] After the second low-resolution display area completes scanning, the reset control terminal of the second low-resolution shift register receives the signal transmitted by the second reset control line TRST2, and the second low-resolution shift register completes reset and stops scanning.

[0267] In the high-definition display stage Y21 or the low-definition display stage Y21, according to the position of the high-definition display area in the next frame image, a shift register that is electrically connected to the first sub-pixel row of the high-definition display area is determined among the multiple shift registers and used as the first shift register of the next frame image. The first shift register of the next frame image receives and stores the signal received at the storage signal input terminal.

[0268] Y3. During the third frame display stage to the E frame display stage, repeat the steps of the second frame display stage, where E is a positive integer greater than or equal to 4, such as E being 100, 2000, or 3000. Of course, as the video plays, the number of frames displayed is related to the playback time, and E is less than the total number of image frames in a video.

[0269] In some examples, such as Figure 5 and Figure 6As shown, the two starting row pixels of the high-definition display area in the next frame image may be located in the high-definition display area or the low-definition display area of ​​the frame image. For example, in the case of the high-definition display area of ​​the frame image, during the high-definition display stage, when the scanning reaches the starting row pixel, the first signal storage control line or the second signal storage control line transmits a signal to the signal storage control terminal. The shift register electrically connected to the starting row pixel receives the scanning signal output by the shift register under the control of the storage signal and stores it in the first node.

[0270] It should be noted that the transmission of a signal is determined based on whether the starting row pixel is electrically connected to the first or second signal storage control line. For example, if the starting row pixel is electrically connected to the first signal storage control line, then the first signal storage control line transmits a signal; if the starting row pixel is electrically connected to the second signal storage control line, then the second signal storage control line transmits a signal.

[0271] To ensure that both cascaded groups electrically connected to the pixels in the high-definition display area can output scan signals under the control of a clock signal, it is necessary that the signal at the first node N1 of at least one shift register in each cascaded group is high. Therefore, shift registers electrically connected to the two adjacent pixel rows in the high-definition display area need to receive scan signals and store them in the first node N1 under the control of the signal received at the signal storage control terminal. For example, the signal at the first node of the shift register electrically connected to the first and second rows of pixels in the high-definition display area should be high.

[0272] Furthermore, the present invention also provides a display device 1000, such as... Figure 21 , Figure 22 , Figure 23 and Figure 24 As shown, the display device 1000 includes a gate driving circuit as described in any of the above embodiments.

[0273] For example, the display device 1000 can be applied to the field of light field display technology, and can display light field display images. It can distinguish between high-definition display area and low-definition display area as required in the light field display to realize 3D display. The specific implementation method can be referred to the above description of the gate driving circuit and its driving method, which will not be repeated here.

[0274] like Figure 1 As shown, the present invention provides a virtual reality head-mounted display device, including a frame 100 with an opening on one side and a display panel 200 with the display surface facing the opening of the frame 100. In use, the opening of the frame 100 fits against the face, and the eyes can look at the display surface of the display panel 200 through the opening.

[0275] The bezel area of ​​the display panel 200 is provided with the gate driving circuit described in the above embodiment. By controlling the signal timing of each signal line in the gate driving circuit, the display panel 100 forms a stereoscopic visual effect achieved by the light field display scheme, so as to achieve the purpose of viewing 3D images with naked eyes.

[0276] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A shift register, characterized in that, include: An access circuit, electrically connected to a signal storage control terminal, an access input control terminal, a storage signal input terminal, an access signal input terminal, and a pull-up node, is configured to input and store a signal received at the storage signal input terminal in response to a signal received at the storage signal input terminal and a signal received at the signal storage control terminal. The access circuit is also configured to transmit a signal received at the access signal input terminal to the pull-up node in response to a stored signal received at the storage signal input terminal and a signal received at the access input control terminal. Furthermore, the access circuit is configured to input and store a signal received at the storage signal input terminal in response to a signal received at the storage signal input terminal and a signal received at the signal storage control terminal when the shift register corresponds to the start position of the next frame of high-definition display area. An output circuit is electrically connected to the pull-up node, at least one clock signal terminal, and at least one signal output terminal. The output circuit is configured to transmit signals received at the at least one clock signal terminal to the at least one signal output terminal in response to a signal from the pull-up node. One of the at least one signal output terminals is electrically connected to the stored signal input terminal.

2. The shift register according to claim 1, characterized in that, The shift register further includes a reset circuit electrically connected to the pull-up node, the reset control terminal, and the reset voltage signal terminal. The reset circuit is configured to transmit a signal received at the reset voltage signal terminal to the pull-up node in response to a signal received at the reset control terminal.

3. The shift register according to claim 2, characterized in that, The access circuit includes a signal storage sub-circuit and a signal extraction sub-circuit; The signal storage sub-circuit is electrically connected to the signal storage control terminal, the storage signal input terminal and the first node. The signal storage sub-circuit is configured to transmit and store the signal received at the storage signal input terminal to the first node in response to the signal received at the signal storage control terminal when the shift register corresponds to the starting position of the next frame high-definition display area. The signal extraction sub-circuit is electrically connected to the first node, the access input control terminal, the access signal input terminal, and the pull-up node. The signal extraction sub-circuit is configured to transmit the signal received at the access signal input terminal to the pull-up node in response to the signal from the first node and the signal received at the access input control terminal.

4. The shift register according to claim 3, characterized in that, The signal storage sub-circuit includes: a first transistor, a second transistor, and a first capacitor; The control electrodes of the first transistor and the second transistor are both electrically connected to the signal storage control terminal. The first electrode of the first transistor is electrically connected to the stored signal input terminal. The second electrode of the first transistor is electrically connected to the first electrode of the second transistor. The second electrode of the second transistor is electrically connected to the first node. The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the regulated signal terminal. The signal extraction sub-circuit includes a fourth transistor and a fifth transistor. The control electrode of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the access signal input terminal, the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor, the control electrode of the fifth transistor is electrically connected to the access input control terminal, and the second electrode of the fifth transistor is electrically connected to the pull-up node.

5. The shift register according to claim 4, characterized in that, The reset circuit includes a twelfth transistor, the control terminal of which is electrically connected to the reset control terminal, the first terminal of which is electrically connected to the pull-up node, and the second terminal of which is electrically connected to the reset voltage signal terminal.

6. The shift register according to claim 5, characterized in that, The output circuit includes a first output circuit and a second output circuit, the clock signal terminal includes a first clock signal terminal and a second clock signal terminal, and the signal output terminal includes a first signal output terminal and a second signal output terminal. The first output circuit is electrically connected to the pull-up node, the first clock signal terminal, and the first signal output terminal. The first output circuit is configured to transmit the signal received at the first clock signal terminal to the first signal output terminal in response to the signal of the pull-up node. The first signal output terminal is electrically connected to the stored signal input terminal. The second output circuit is electrically connected to the pull-up node, the second clock signal terminal, and the second signal output terminal. The second output circuit is configured to transmit the signal received at the second clock signal terminal to the second signal output terminal in response to the signal of the pull-up node. The first output circuit includes a sixth transistor and a second capacitor. The control terminal of the sixth transistor and the first terminal of the second capacitor are both electrically connected to the pull-up node. The first terminal of the sixth transistor is electrically connected to the first clock signal terminal. The second terminal of the sixth transistor and the second terminal of the second capacitor are electrically connected to the first signal output terminal. The second output circuit includes a seventh transistor and a third capacitor. The control terminal of the seventh transistor and the first terminal of the third capacitor are both electrically connected to the pull-up node. The first terminal of the seventh transistor is electrically connected to the second clock signal terminal. The second terminals of the seventh transistor and the third capacitor are electrically connected to the second signal output terminal.

7. The shift register according to claim 6, characterized in that, The output circuit further includes a first voltage regulator circuit and / or a second voltage regulator circuit; The first voltage regulator circuit is electrically connected to a first voltage regulator input, a pull-up node, and a second node. The second node is also electrically connected to the control electrode of the sixth transistor and the first electrode of the second capacitor. The first voltage regulator circuit is configured to transmit the signal of the pull-up node to the second node in response to a signal received at the first voltage regulator input. The first electrode of the sixth transistor receives a signal at the first clock signal terminal. The first voltage regulator circuit is also configured to interrupt the current path between the pull-up node and the second node in response to the signal received at the first voltage regulator input and the signal of the second node. The second voltage regulator circuit is electrically connected to the second voltage regulator input, the pull-up node, and the third node. The third node is also electrically connected to the control electrode of the seventh transistor and the first electrode of the third capacitor. The second voltage regulator circuit is configured to transmit the signal of the pull-up node to the third node in response to a signal received at the second voltage regulator input. The first electrode of the seventh transistor receives a signal at the second clock signal terminal. The second voltage regulator circuit is also configured to interrupt the current path between the pull-up node and the third node in response to the signal received at the second voltage regulator input and the signal of the third node. The first voltage regulator circuit includes an eighth transistor, the control terminal of the eighth transistor is electrically connected to the first voltage regulator input terminal, the first terminal of the eighth transistor is electrically connected to the pull-up node, and the second terminal of the eighth transistor is electrically connected to the second node; The second voltage regulator circuit includes a ninth transistor, the control terminal of which is electrically connected to the second voltage regulator input terminal, the first terminal of which is electrically connected to the pull-up node, and the second terminal of which is electrically connected to the third node.

8. The shift register according to claim 6 or 7, characterized in that, The shift register also includes: An input circuit is electrically connected to a pull-up input control terminal, a pull-up signal input terminal, and a pull-up node. The input circuit is configured to transmit a signal received at the pull-up signal input terminal to the pull-up node in response to a signal received at the pull-up input control terminal. A cascaded reset circuit is electrically connected to the pull-up node, the cascaded reset control terminal, and the reset voltage signal terminal. The cascaded reset circuit is configured to transmit the signal received at the reset voltage signal terminal to the pull-up node in response to the signal received at the cascaded reset control terminal. The input circuit includes a tenth transistor, the control electrode of the tenth transistor is electrically connected to the pull-up input control terminal, the first electrode of the tenth transistor is electrically connected to the pull-up signal input terminal, and the second electrode of the tenth transistor is electrically connected to the pull-up node. The cascaded reset circuit includes an eleventh transistor, the control terminal of the eleventh transistor is electrically connected to the cascaded reset control terminal, the first terminal of the eleventh transistor is electrically connected to the pull-up node, and the second terminal of the eleventh transistor is electrically connected to the reset voltage signal terminal.

9. The shift register according to claim 8, characterized in that, The shift register further includes a pull-down control circuit, which is electrically connected to the pull-down signal input terminal, the pull-up node, the pull-down node, and the pull-down voltage signal terminal. The pull-down control circuit is configured to, in response to the signal of the pull-up node and the signal received at the pull-down signal input terminal, transmit the signal received at the pull-down voltage signal terminal to the pull-down node, and, in response to the signal of the pull-down node, transmit the signal received at the pull-down voltage signal terminal to the pull-up node. The pull-down control circuit includes a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor. The control electrode and the first electrode of the fourteenth transistor are both electrically connected to the pull-down signal input terminal, and the second electrode of the fourteenth transistor is electrically connected to the pull-down node. The control electrode of the thirteenth transistor is electrically connected to the pull-down node, the first electrode of the thirteenth transistor is electrically connected to the pull-up node, and the second electrode of the thirteenth transistor is electrically connected to the pull-down voltage signal terminal. The control terminal of the fifteenth transistor is electrically connected to the pull-up node, the first terminal of the fifteenth transistor is electrically connected to the second terminal of the fourteenth transistor, and the second terminal of the fifteenth transistor is electrically connected to the pull-down voltage signal terminal.

10. The shift register according to claim 9, characterized in that, The shift register also includes a pull-down reset circuit and an output reset circuit; The pull-down reset circuit is electrically connected to the pull-down node, the pull-up input control terminal, the access input control terminal, the first node, and the pull-down voltage signal terminal. The pull-down reset circuit is configured to transmit the signal received at the pull-down voltage signal terminal to the pull-down node in response to a signal received at the pull-up input control terminal or in response to a signal received at the access input control terminal and a signal from the first node. The output reset circuit is electrically connected to the signal output terminal, the pull-down voltage signal terminal and the pull-down node. The output reset circuit is configured to transmit the signal received at the pull-down voltage signal terminal to the signal output terminal in response to the signal of the pull-down node. The pull-down reset circuit includes a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor; The control electrode of the sixteenth transistor is electrically connected to the access input control terminal, the first electrode of the sixteenth transistor is electrically connected to the pull-down node, the second electrode of the sixteenth transistor is electrically connected to the fourth node, the control electrode of the seventeenth transistor is electrically connected to the first node, the first electrode of the seventeenth transistor is electrically connected to the fourth node, and the second electrode of the seventeenth transistor is electrically connected to the pull-down voltage signal terminal. The control electrode of the eighteenth transistor is electrically connected to the pull-up input control terminal, the first electrode of the eighteenth transistor is electrically connected to the pull-down node, and the second electrode of the eighteenth transistor is electrically connected to the pull-down voltage signal terminal. The output reset circuit includes a twentieth transistor and a twenty-first transistor. The control electrode of the twentieth transistor is electrically connected to the pull-down node, the first electrode of the twentieth transistor is electrically connected to the first signal output terminal, and the second electrode of the twentieth transistor is electrically connected to the pull-down voltage signal terminal. The control electrode of the twenty-first transistor is electrically connected to the pull-down node, the first electrode of the twenty-first transistor is electrically connected to the second signal output terminal, and the second electrode of the twenty-first transistor is electrically connected to the pull-down voltage signal terminal.

11. The shift register according to claim 10, characterized in that, The pull-down reset circuit further includes a discharge circuit, which is electrically connected to the fourth node, the reset control terminal and the pull-down voltage signal terminal. The discharge circuit is configured to transmit the signal received at the pull-down voltage signal terminal to the fourth node in response to the signal received at the reset control terminal. The discharge circuit includes a nineteenth transistor, the control electrode of the nineteenth transistor is electrically connected to the reset control terminal, the first electrode of the nineteenth transistor is electrically connected to the fourth node, and the second electrode of the nineteenth transistor is electrically connected to the pull-down voltage signal terminal.

12. A gate driving circuit, characterized in that, Includes the shift register as described in any one of claims 1 to 11.

13. The gate driving circuit according to claim 12, characterized in that, The plurality of shift registers are divided into at least two shift register groups, each shift register group comprising at least two shift registers arranged in sequence; The shift register also includes a reset circuit, which is electrically connected to the pull-up node, the reset control terminal, and the reset voltage signal terminal. The gate drive circuit also includes multiple reset control lines and multiple signal storage control lines. The signal storage control terminal of each shift register in each shift register group is electrically connected to a signal storage control line, and the reset control terminal of each shift register in each shift register group is electrically connected to a reset control line.

14. The gate driving circuit according to claim 12, characterized in that, The shift register also includes a cascaded reset circuit, which is electrically connected to the pull-up node, the cascaded reset control terminal, and the reset voltage signal terminal. The output circuit includes a first output circuit and a second output circuit, the clock signal terminal includes a first clock signal terminal and a second clock signal terminal, and the signal output terminal includes a first signal output terminal and a second signal output terminal. The multiple shift registers are divided into two cascaded groups, and the first signal output terminal of the nth stage shift register in each cascaded group is electrically connected to the storage signal input terminal of the (n+1)th stage shift register. The first signal output terminal of the shift register of the m-th stage in each cascade group is electrically connected to the cascade reset control terminal of the shift register of the (m-2)-th stage. Where n is a positive integer greater than or equal to 1, and m is a positive integer greater than or equal to 3.

15. The gate driving circuit according to claim 14, characterized in that, The gate drive circuit includes a plurality of shift registers arranged sequentially, with adjacent h shift registers forming an output group; the odd-numbered output group belongs to the first cascade group, and the even-numbered output group belongs to the second cascade group. Where h is a positive integer greater than or equal to 3.

16. The gate driving circuit according to claim 15, characterized in that, The gate drive circuit further includes two clock signal line groups, each clock signal line group being electrically connected to each output group in one of the cascaded groups; Each clock signal line group includes k×h clock signal lines, and each clock signal line in each clock signal line group is electrically connected to one of the clock signal terminals of each shift register in the output group. Where k is a positive integer greater than or equal to 1.

17. A display device, characterized in that, Includes the gate drive circuit as described in any one of claims 12 to 16.

18. A driving method applied to the gate driving circuit as described in any one of claims 12 to 16, characterized in that, include: The gate drive circuit includes a plurality of the shift registers, divided into at least two shift register groups, each shift register group including at least two shift registers arranged in sequence; The gate drive circuit also includes multiple reset control lines and multiple signal storage control lines. The signal storage control terminal of each shift register in each shift register group is electrically connected to a signal storage control line, and the reset control terminal of each shift register in each shift register group is electrically connected to a reset control line. The driving method includes: Each shift register in each shift register group, under the control of the signal transmitted through the signal storage control line electrically connected to it, inputs and stores the signal received at the storage signal input terminal; Each shift register in each shift register group is reset under the control of a signal transmitted through a reset control line electrically connected to it.

19. The driving method for the gate driving circuit according to claim 18, characterized in that, During the first frame image display phase Each shift register of the gate drive circuit outputs a gate scan signal; Based on the position of the high-definition display area of ​​the second frame image, determine the shift register that is electrically connected to the first sub-pixel row of the high-definition display area among the multiple shift registers, and use it as the first shift register; When a signal is received at the storage signal input terminal of the first shift register, under the control of the signal storage control line of the gate drive circuit electrically connected to the first shift register, the signal received at the storage signal input terminal is stored in the first shift register. The second frame image display phase includes: In the high-definition display stage, The first shift register outputs a gate scan signal under the control of the signal received at the storage signal input terminal and the signal received at the access input control terminal; The shift registers electrically connected to the sub-pixels of the high-definition display area sequentially output gate scan signals; During the low-resolution display stage The low-definition display area includes a first low-definition display area and a second low-definition display area, which are located on both sides of the high-definition display area, respectively. Multiple shift registers connected to the first low-resolution display area output gate scan signals under the control of signals transmitted via the start signal line; Multiple shift registers connected to the second low-definition display area output gate scan signals under the control of cascaded signals output from shift registers connected to the high-definition display area; After scanning the first low-resolution display area, the multiple shift registers connected to the first low-resolution display area are reset; After scanning the second low-resolution display area, the multiple shift registers connected to the second low-resolution display area are reset; During the high-definition display stage or the low-definition display stage, based on the position of the high-definition display area in the next frame image, a shift register that is electrically connected to the first sub-pixel row of the high-definition display area is determined among a plurality of shift registers and used as the first shift register of the next frame image. The first shift register of the next frame image receives and stores the signal received at the storage signal input terminal. During the third frame display phase to the E frame display phase, the steps of the second frame display phase are repeated, where E is a positive integer greater than or equal to 4.

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