Multistep quantum ground state shift with reduced number of ancila qubits

Abstract

This invention provides a method and quantum circuit used to perform multi-step quantum ground state shifts. [Solution] With respect to the state vector space, the shift register has a total of N+1 qubits. The last qubit of the entire shift register is a superposition qubit, which allows us to define a superposition of substates. The superposition qubit is used to determine which substates to increment and which to decrement. Even substates to be incremented can be incremented by simply inverting the (i+1)th qubit, i.e., the step qubit. Similarly, odd substates to be decremented can also be decremented. The remaining steps of the quantum circuit are used to rearrange the even substates to be incremented, even substates to be decremented, odd substates to be incremented, and odd substates to be decremented.

Description

[Technical Field]

[0001] The present disclosure (hereinafter referred to as "the Disclosure") relates to a method for performing a multistep quantum ground state shift using a small number of ancilla qubits. The Disclosure also relates to a quantum computer or quantum simulator configured to perform the aforementioned method. The Disclosure further relates to a quantum circuit for performing a multistep quantum ground state shift using a small number of ancilla qubits. Background

[0002] For quantum algorithms to outperform classical computations, the scale of computational operations relative to the size of the problem must be smaller compared to classical algorithms solving the same problem. A desirable property for state-shifting algorithms is that quantum operations (i.e., gates) exhibit logarithmic scaling with respect to the number of internal qubit states. However, the computational complexity of a quantum algorithm varies greatly depending on the problem being solved and the computational approach used. Generally, computational complexity is not necessarily related to the number of tensor product states, and speedups can arise from diverse algorithmic mechanisms spanning multiple different complexity classes.

[0003] Of note is the fact that the state-shifting process is used as a subroutine in multiple quantum algorithms. Currently known quantum shift procedures can be implemented in two configurations: (i) a first configuration using an additional (variable) ancilla register, and (ii) a second configuration that does not use any additional (variable) ancilla registers. In the first configuration, the introduction of a variable ancilla register provides logarithmic dependence. The first configuration is disclosed in U.S. Patent No. 11,694,107. On the other hand, in the second configuration, an ancilla-less approach (e.g., a shift based on the quantum Fourier transform (QFT)) results in an algorithm that scales quadratically with respect to the number of qubits. This makes the complexity poly-logarithmic with respect to the number of states. Shakeel has proposed a QFT-based shift ("Efficient and scalable quantum walk algorithms via the quantum fourier transform", published in Quantum Information Processing 19 (2020)).

[0004] These two configurations have complementary advantages and disadvantages. When implementing state shifts using the second configuration, fewer qubits are needed in the workspace, but the quantum circuit becomes much deeper than in the first configuration. For example, in QFT-based shifts, the number of gates increases quadratically in proportion to the size of the state space. Also, QFT-based shifts rely on precise rotation gates and phase transition gates, which are very sensitive to noise.

[0005] On the other hand, the first configuration has low computational complexity, and the number of gates increases linearly with the size of the state space. Execution time is primarily device-dependent, but it is understandable that execution time will be shorter as lower computational complexity generally requires less computation. While the size of the first configuration increases or decreases linearly, the initial gate cost is high, which significantly impacts computational complexity in practical applications. Furthermore, the process of setting up quantum circuits is quite complex.

[0006] To mitigate the shortcomings of the state-shift algorithm and achieve further improvements, redesign and optimization of the state-shift algorithm are necessary. Abstract

[0007] The present disclosure (hereinafter referred to as "the Disclosure") aims to provide a method for performing a multi-step quantum ground state shift using a small number of ancilla qubits. The Disclosure also aims to provide a quantum computer or quantum simulator configured to perform the aforementioned method. The Disclosure further aims to provide a quantum circuit for performing a multi-step quantum ground state shift using a small number of ancilla qubits. The object of the Disclosure is achieved by the method, quantum computer or quantum simulator, and quantum circuit described in the attached independent claims. Advantageous features are described in the attached dependent claims.

[0008] Throughout this specification and in its claims, phrases such as “equipped with,” “include,” and “possess” do not mean that they include a certain element but not that they include only that element. They do not preclude the existence of other components, items, numbers, or steps that are not expressly disclosed. Furthermore, unless otherwise specified in the context, singular expressions also include plural forms. In particular, where an indefinite article is used in the original text, this specification assumes both singular and plural forms unless otherwise required in the context. [Brief explanation of the drawing]

[0009] [Figure 1]This is a schematic diagram illustrating a part of a method for performing a multi-step quantum ground state shift with a reduced number of ancilla qubits according to embodiments of the present disclosure. [Figure 2A-2C] Detailed diagrams of quantum circuits for performing a multi-step quantum ground state shift with a reduced number of ancilla qubits, according to embodiments of this disclosure, are shown. [Figure 2D] A detailed diagram of an example of a quantum circuit for the case N = 4 and i = 0, according to an embodiment of this disclosure, is shown. [Figure 3] An example of a multi-step quantum ground state shift on a two-dimensional lattice according to an embodiment of this disclosure is shown. [Figure 4] A detailed diagram of a quantum circuit according to an embodiment of the present disclosure is shown. This quantum circuit uses two controlled swap blocks to perform two multistep quantum ground state shifts in two dimensions. [Figure 5] This shows how the number of CX gates in different bidirectional shifts with step size 1 changes with respect to the number of qubits (N) used to encode a one-dimensional lattice. [Figure 6] This shows how the total number of gates in a bidirectional one-dimensional quantum walk with a step size of 1 changes with respect to the number of qubits (N) used to encode the one-dimensional lattice. [Figure 7] This shows how the total number of gates in a 4-direction 2D quantum walk with step size 1 changes with respect to the number of qubits (N) used to encode one side of a 2D lattice. [Figure 8] This paper shows how the total number of gates in a 2D QLBM model for ADE, which uses multiple different shifts for propagation steps, changes with respect to the number of qubits (N) used to encode one side of the 2D lattice. [Figure 9] This is a comparison of circuit fidelity for the number of qubits N used to encode a one-dimensional lattice, showing a comparison of the circuit fidelity of several different bidirectional shifts with a step size of 1. Detailed description of the embodiment

[0010] The following detailed description illustrates embodiments of the present disclosure and methods by which they may be implemented. Although several embodiments for implementing the present disclosure have been disclosed, those skilled in the art will recognize that other embodiments for implementing the present disclosure are also possible.

[0011] According to a first aspect, embodiments of the present disclosure provide a method executed by a quantum computer or a quantum simulator. This method 2 N+1 In a state vector space of the size of, setting a shift register and an ancilla register for a quantum circuit used to perform a multi-step quantum ground state shift, wherein the shift register has a total of N + 1 quantum bits, and the first N quantum bits (q 1, q 2, …q N ) of the shift register form an array register, the last quantum bit (q N+1 ) of the shift register is a superposition quantum bit, and the ancilla register includes a maximum of N - 2 ancilla quantum bits (a1,... a N-2 ), said setting; 2 N+1 For an input state having array sub-states of, regarding the array sub-states where the superposition quantum bit (q N+1 ) is 0 as array sub-states to be incremented, and regarding the array sub-states where the superposition quantum bit (q N+1 ) is 1 as array sub-states to be decremented, dividing the input state into a first subset that is a subset including the array sub-states to be incremented and a second subset that is a subset including the array sub-states to be decremented; In the multi-step quantum ground state shift, when the step size is 2 i , setting the quantum circuit when i < N - 2; including, where the step index i is a non-negative integer less than N, and setting the quantum circuit is The k-th (k=i+1) qubit (q k Substates where ) is 0 are considered even substates, and the k-th qubit (q k By considering substates where ) is 1 as odd substates, the first subset is decomposed into even substates to be incremented and odd substates to be incremented, and the second subset is decomposed into even substates to be decremented and odd substates to be decremented; Remapping the state amplitude of the even substate to be decremented with the state amplitude of the odd substate to be decremented; The kth qubit (q k Substates where ) is 0 are considered even substates, and the k-th qubit (q k By considering a substate where ) is 1 as an odd substate, a recursive process in which k is incremented by 1 in each recursion until k reaches N-2 decomposes the incrementing odd substate into a further incrementing even substate and a further incrementing odd substate, and decomposes the decrementing even substate into a further decrementing even substate and a further decrementing odd substate; Each time recursion occurs, the state amplitude of the even substates targeted for further decrement is remapped to the state amplitude of the odd substates targeted for further decrement; The (N-1)th qubit (q N-1 Substates where ) is 0 are considered even substates, and the N-1th qubit (q N-1 By considering a substate where ) is 1 as an odd substate, the further incrementable odd subset is ultimately decomposed into an even substate and an even substate, and the further decrementable even subset is ultimately decomposed into an even substate and an odd substate; The state amplitude of the even substates subject to further decrement and the state amplitude of the odd substates subject to further decrement are ultimately remapped; The k-th (where k=N-1) qubit (q k With respect to the adjacent decrement target even substates, the size 2 k The amplitude block is swapped, and the size 2 is swapped between adjacent incrementing odd substates. k To swap the amplitude block, the (N-1)th qubit (q) of the array register is used. N-1 ) and the N-2nd ancila qubit of the ancila register (a N-2 ) is used as a control to control the Nth qubit (q N ) and reversing it; Reversing the step of finally remapping the state amplitude of the even substates to be further decremented and the state amplitude of the odd substates to be further decremented; Reverse the step of finally decomposing, provided that the step of finally decomposing and the Nth qubit (q N The step of inverting ) and the step of finally decomposing are to be fused together; The kth qubit (q k With respect to the adjacent decrement target even substates, the size 2 k The amplitude block is swapped, and the k-th qubit (q k Regarding ), between adjacent incrementable odd substates, the size is 2 k To swap the amplitude block, the ki-th ancila qubit (a) of the ancila register k-i ) is used as the control to use the k+1th qubit (q k+1 The inversion of ) where k is equal to N-2, and is decremented by 1 at each inversion of the recursion in the decomposition step by the recursive process until it reaches i+2; Reversing the step of remapping the state amplitude of the even substates to be further decremented with the state amplitude of the odd substates to be further decremented; Reverse the step of decomposition by the aforementioned recursive process, provided that the k+1th qubit (qk+1 The step of inverting and the step of reversing the remapping step are repeated prior to the inversion of each recursion of the decomposition step by the recursive process; The (i+1)th qubit (q) i+1 With respect to the adjacent decrement target even substates, the size 2 i+1 The amplitude block is swapped, and the i+1th qubit (q i+1 Regarding ), between adjacent incrementable odd substates, the size is 2 i+1 To swap the amplitude block, the first ancilla qubit (a1) of the ancilla register is used as the control to swap the i+2th qubit (q i+2 ) and reversing it; Reversing the step of remapping the state amplitude of the even substate to be decremented with the state amplitude of the odd substate to be decremented; Reversing the aforementioned disassembly step; The aforementioned multi-step quantum ground state shift with a step size of 2 i To complete the multistep quantum ground state shift of the state amplitude based on, the i+1th qubit (q i+1 ) and reversing it; It is done by [the specified method].

[0012] According to the second interpretation, one embodiment of the present disclosure provides a quantum computer or quantum simulator configured to perform the method according to the first interpretation described above.

[0013] This disclosure provides the aforementioned method and the aforementioned quantum computer or quantum simulator. The aforementioned method provides a step size of 2, which is a power of 2. iMultistep quantum ground state shifts can be performed using this method. Advantageously, multistep quantum ground state shifts can be performed simultaneously in multiple shift directions with the same computational complexity class as single-step ground state shifts. In this regard, as will be discussed later, certain preparatory steps are performed to ensure the correct superposition of "direction substates." This enables a significant increase in quantum speed. Furthermore, by combining multistep quantum ground state shifts performed using the aforementioned method, it is possible to create multistep quantum ground state shifts of any step size.

[0014] The aforementioned method can be considered a redesign of the first configuration described in the background section. This method significantly reduces the initial gate cost, thereby making parallel shifts competitive with QFT-based shifts even with a small number of qubits, despite having a much simpler conceptual design. In particular, this allows for easy extension to multi-stepping and higher-dimensional lattice shifts.

[0015] One of the key advantages of the aforementioned method is the natural parallelization that arises from the superposition of array substates. The number of qubits in the shift register depends on the size of the state vector space. Specifically, if the size of the state vector space is 2 N+1 In this case, the shift register consists of a total of N+1 qubits. Of these N+1 qubits, the last qubit (q) of the entire shift register N+1 ) is a superposition qubit. This superposition qubit allows us to define a superposition of two array substates that are orthogonal (with respect to increment and decrement). In this respect, in the step of partitioning the input state, the superposition qubit is used to determine which array substates are to be incremented (i.e., the first subset) and which array substates are to be decremented (i.e., the second subset). N+1 Array substates where ) is 0 are considered to be incrementable, and the superposition qubit (qN+1 Array substates where ) is 1 are considered to be subject to decrement. As a result, the number of array substates in the first subset and the number of array substates in the second subset are both 2 N The first subset and the second subset mentioned above are (the first N qubits (q) of the shift register. 1, q 2, ...q N At each array point defined by the fundamental state of the array register (composed of ), there are linked state amplitudes that are shifted "up" and state amplitudes that are shifted "down". This means that there are two layers of state amplitudes on the position space defined by the array register (which can be interpreted as, for example, a regular polygonal grid). This means that the total amount of data in the state vector space is 2 N+1 This means the state amplitude, which is also called the size of the state vector space. Here, the superposition qubits are marked as 0. N The array substates are subject to increment, and the superposition qubit is marked as 1. N The array substates are subject to decrement. Therefore, the first subset of array substates that are subject to increment, and the second subset of array substates that are subject to decrement, refer to a superposition of two probability distributions on the same position space defined by the array register. The array substates of the first subset and the array substates of the second subset are the first N qubits (q) of the array register, i.e., the shift register. 1, q 2, ...q N It is defined using ).

[0016] What is noteworthy is (step size 2 i The even substates subject to incrementing are simply the i+1th qubit (q i+1 The key point is that it can be incremented simply by applying a step that inverts ). This qubit is also called a step qubit. Similarly, (step size 2 i The odd substates that are subject to decrement (in this case) are also the i+1th qubit (qi+1 The (i.e., step qubit) can be decremented by applying the same step of inverting it. The remaining steps in the quantum circuit are used to rearrange the even substates to be decremented and the odd substates to be incremented as follows: the (i+1)th qubit (q i+1 The step of inverting the (i+1) substate is used to rearrange the decremented even substates and incremented odd substates so that a multi-step quantum ground state shift is performed in one step. Notably, since the inverting step essentially deals with the incremented even substates and decremented odd substates, no special rearrangement is required for them. Throughout this specification, the notation "i+1th" refers to the (i+1)th substate. In other words, the parentheses are omitted for convenience and to improve readability. The same notation is used for other similar terms.

[0017] As mentioned above, the number of ancilla qubits in an ancilla register depends on the step size of the multistep quantum ground state shift. The step that is ultimately decomposed and the Nth qubit (q N The technical advantage of combining the step of inverting the result with the step of finally decomposing it is that the number of ancilla qubits in the ancilla qubit register is reduced by one. Therefore, the ancilla register can contain a maximum of N-2 ancilla qubits.

[0018] The aforementioned step of finally decomposing, and the Nth qubit (q N Another technical advantage of merging the step of inverting the gates with the step of finally decomposing them is that the total number of base gates is reduced by the equivalent of seven CX gates. This will be explained in detail in the "Experimental Section" below.

[0019] In embodiments of this specification, the step size is 2 iIt is defined as follows: That is, the step index i is used. This index is a non-negative integer less than N. The number of steps in the method for performing a multi-step quantum ground state shift depends on the step size. In other words, the number of steps in the method depends on the value of the step index i. This will be discussed later.

[0020] For illustrative purposes, the following shows how the quantum circuit is configured in the method described above.

[0021] When i < N-2, the quantum circuit is set up by performing the following steps.

[0022] Decomposing step (#1): The array substates of the first subset (i.e., the array substates to be incremented) are decomposed into even substates and odd substates to be incremented. On the other hand, the array substates of the second subset (i.e., the array substates to be decremented) are decomposed into even substates and odd substates to be decremented. In this respect, the k-th qubit (q k Substates where ) is 0 are considered even substates, and the k-th qubit (q k Substates where ) is 1 are considered odd substates. In this decomposition step, k = i + 1. i + 1 is simply the initial value of k, and as will be described later, the value of k is incremented with each recursion in the subsequent recursive step. k ) is called a partitioned qubit, and k is called the partition index. In the decomposition step (#1), it will be understood that the array substates are partitioned into smaller substates. In each subsequent decomposition, the substates are partitioned into even smaller substates. At the finest level, the smallest substate consists of a single amplitude corresponding to the ground state.

[0023] Remapping step (#2): The state amplitude of the even substate to be decremented is remapped to the state amplitude of the odd substate to be decremented. This remapping is performed on the k-th qubit (q) of the array register. k This does not affect any qubits other than the one being decremented. This remapping can also be described as a step of swapping (flipping) the even substates to be decremented with the odd substates to be decremented. This swapping operation does not affect the data; that is, the data remains held in the state amplitude.

[0024] Recursive decomposing step (#3A): The odd substates targeted for incrementing are recursively decomposed into further even substates targeted for incrementing and further odd substates targeted for incrementing. Similarly, the even substates targeted for decrementing are further decomposed into further even substates targeted for decrementing and further odd substates targeted for decrementing through recursion. In this respect, the k-th qubit (q k Substates where ) is 0 are considered even substates, and the k-th qubit (q k Substates where ) is 1 are considered odd substates. In the recursive decomposition step, with each recursion, the value of k increases by 1 until it reaches N-2. Therefore, this recursive decomposition step depends on the value of i, i.e., when k is (initial value 2 i It runs from (to) N-1 until it reaches N-1.

[0025] Remapping step after each recursion (#4A): After each recursion in the recursive decomposition step (#3A), the state amplitudes of the even substates targeted for further decrement and the state amplitudes of the odd substates targeted for further decrement are remapped. This remapping is performed on the k-th qubit (q) of the array register. k This does not affect any other qubits. As mentioned above, the even substates and odd substates targeted for further decrement are simply swapped while retaining their state amplitude data.

[0026] Final disassembly step (#3B): Further incrementable odd substates are ultimately decomposed into even further incrementable even substates and even further incrementable odd substates. Similarly, further decrementable even substates are ultimately decomposed into even further decrementable even substates and even further decrementable odd substates. In this respect, the (N-1)th qubit (q N-1 Substates where ) is 0 are considered even substates, and the (N-1)th qubit (q N-1 Substates where k is 1 are considered odd substates. In other words, in this final decomposition step, the value of k reaches N-1.

[0027] Final remapping step (#4B): The state amplitudes of the even substates targeted for further decrement and the state amplitudes of the odd substates targeted for further decrement are finally remapped. This final remapping is performed on the N-1 qubit (q) of the array register. N- 1) has no effect on qubits other than 1). As mentioned above, the even substates and odd substates targeted for further decrement are simply swapped while retaining their state amplitude data.

[0028] Inverting step (#5B): The (N-1)th qubit (q) of the array register N-1 ) and the N-2nd ancila qubit of the ancila register (a N-2 Using ) as a control, the Nth qubit (q N ) is inverted. As a result, the k-th qubit (q k With respect to the adjacent decrement target even substates, the size 2 k The amplitude block is swapped, and the size 2 is swapped between adjacent incrementing odd substates. kThe amplitude block is swapped. This inversion step is performed using N-1 as the value of k. The aforementioned swap does not shift the entire quantum state, but only swaps a specific substate at a specific position in the decomposition sequence. This specific position is the N-1th qubit (q N-1 This is defined by ), which will also be referred to as “substate shift” throughout this specification.

[0029] The reversing step (#6B) of the aforementioned final remapping step (#4B): In this step, we reverse the final remapping step (#4B) described above. In other words, we undo the swapping (flipping) performed in step (#4B).

[0030] The reverse step (#7B) of the final decomposition step (#3B): In this step, we reverse the final decomposition step (#3B) described above. The step of reversing the final decomposition step can also be called the final re-composing step.

[0031] Note that the final decomposition step (#3B) and the Nth qubit (q N The step of reversing (#5B) and the step of reversing the final decomposition step (#7B) can be merged. In other words, these steps are performed using a single quantum gate.

[0032] Reversal step (#5A): The k-th ancila qubit of an ancila register (a k-i Using ) as a control, the k+1th qubit (q k+1 This inverts the kth qubit (q). k Regarding ), between adjacent decrement target even substates, the size is 2 k Swapping the amplitude blocks, and also the k-th qubit (q k Regarding ), between adjacent incrementable odd substates, the size is 2 kReplace the amplitude block. This inversion step is executed by substituting N-2 for k as the initial value. Here, the size of the replacement depends on the split index 'k'. Because the quantum gate (also called an inverter) used for inversion is based on the (k+1)-th qubit (q k+1 ).

[0033] The inverter is applied using the (k-i)-th ancilla qubit (a k-i ) in the ancilla register as a control. This means that the above-mentioned replacement does not shift the complete quantum state, but only exchanges specific sub-states at a specific position in the decomposition sequence. This specific position is defined by the k-th qubit (q k ). This is also referred to as "substate shift" throughout this specification.

[0034] As described above, the number of ancilla qubits in the ancilla register depends on the step size of the multi-step quantum ground state shift. For example, when the step size is 1, step size = 2 i = 1, so i is equal to 0 (zero). In this case, the k-th ancilla qubit (a k-i ) refers to the (N-2)-th ancilla qubit (a N-2 ) in the ancilla register. Therefore, a maximum of N-2 ancilla qubits are required. When the step size is large (i.e., when the step size is greater than 1), i becomes greater than 0, so the number of required ancilla qubits decreases. Specifically, the number of required ancilla qubits is N-i-2.

[0035] The reverse step (#6A) of the aforementioned remapping step (#4A): In this step, reverse the above-mentioned remapping step (#4A). That is, reverse the flipping performed in step (#4A).

[0036] Reverse step (#7A) of the decomposition step (#3A) by recursion: In this step, the decomposition step (#3A) by the aforementioned recursive process is reversed by the recursive process. The reverse step of the decomposition step by the recursive process can also be called a step of recursively re - composing. The aforementioned inversion step (#5A) and the reverse step of the aforementioned remapping (#6A) are repeated before each reverse step (#7A) of each recursion of the decomposition step by the recursive process. In other words, the inversion step (#5A) and the remapping reverse step (#6A) are executed before each recursion of the reverse step (#7A) of the decomposition step by the recursive process. The value of k is decremented by 1 for each recursion of step (#7A) until k reaches i + 1.

[0037] Reversal step (#8) before reversing the decomposition step (#1): When the value of k reaches i + 1, using the first ancilla qubit (a1) of the ancilla register as control, the (k + 1)-th qubit (q k+1 )(that is, the (i + 2)-th qubit (q i+2 )) is inverted. Thereby, for the k-th qubit (q k )(that is, the (i + 1)-th qubit (q i+1 ), the amplitude blocks of size 2 k (that is, 2 i+1 ) are swapped between adjacent even sub - states to be decremented, and for the k-th qubit (q k ), the amplitude blocks of size 2 k are swapped between adjacent odd sub - states to be incremented.

[0038] Here, the size of the swap (i.e., sub - state shift) depends on the split index 'k'. Because the quantum gate (i.e., inverter) used for inversion is based on the (k + 1)-th qubit (q k+1 ). When the value of k reaches i + 1, it can be understood that the (k + 1)-th qubit (q k+1 ) points to the (i + 2)-th qubit (q i+2 ) of the array register. The inverter is the k-th ancilla qubit (ak-i Since it is applied using as control, this means that the inverter is applied using the first ancilla qubit (a1) of the ancilla register. This means that the aforementioned exchange does not shift the entire quantum state, but only exchanges a specific substate at a specific position in the decomposition sequence. This specific position is the kth qubit (q k ), that is, the i+1th qubit (q i+1 ) is defined by.

[0039] The reverse step (#9) of the aforementioned remapping step (#2): In this step, the remapping step (#2) described above is reversed. In other words, the swaps performed in step (#2) are reversed. This step is also performed before reversing the decomposition step (#1).

[0040] The reverse step (#10) of the aforementioned disassembly step (#1): In this step, we reverse the decomposition step (#1). The step of reversing the decomposition step can also be called the recomposing step.

[0041] Final reversal step (#11): Step size 2 i To complete the multistep quantum ground state shift of the state amplitude based on, the i+1th qubit (q i+1 This inversion step (#11) inverts the (i.e., step qubit). This final inversion step (#11) completes a multistep quantum ground state shift across all states of the array register prepared by the preceding substate shift sequence (i.e., the preceding inversion step). The final inversion step (#11) inverts the i-th qubit (qi) by a size of 2 between adjacent decrement-targeted even substates. i The amplitude block is swapped, and with respect to the i-th qubit (qi), a size 2 is created between adjacent increment-target odd substates. i Replace the amplitude block.

[0042] Figure 1 is a schematic diagram illustrating a portion of the aforementioned method according to an embodiment of the present disclosure. This portion includes the following steps.

[0043] Step S1.0 is (2 N+1 The aforementioned step is shown, in which the input state p (containing n array substates) is divided into a first subset p+ of array substates to be incremented and a second subset p- of array substates to be decremented. In Figure 1, double lines indicate substates to be incremented, and single lines indicate substates to be decremented.

[0044] Step S1.1 represents the decomposition step (#1) described above. In Figure 1, this "decomposition" is indicated by the term "decompose". In Figure 1, the even substates are the divided qubits (i.e., the k-th qubit q). k ) is marked with respect to the following. Therefore, e(k) represents an even substate and o(k) represents an odd substate. The initial value of k is equal to i+1. That is, decomposition step (#1) starts from decomposition index k = i+1. In Figure 1, dashed lines are used to represent odd substates and solid lines are used to represent even substates.

[0045] Step S1.2 represents the aforementioned remapping (Step #2). In Figure 1, this remapping is indicated by the term "flip". In this specification, "remapping" and "swapping" are used interchangeably. Up to this step, the value of k is i+1.

[0046] Step S1.3 represents the first recursion of the decomposition step (#3A) using the recursive process described above. The value of k increases by 1 with each recursion.

[0047] Step S1.4 represents the aforementioned remapping step (#4A). This is performed after the first recursion of the recursive decomposition step (#3A).

[0048] Step S1.5 represents the second recursion of the aforementioned recursive decomposition step (#3A). The method then continues as described above. For example, step S1.5 is followed by the aforementioned remapping step (#4A). This is executed after the second recursion of the recursive decomposition step (#3A). The recursive decomposition step (#3A) and the remapping step (#4A) are repeated until the partition index 'k' reaches N-2.

[0049] Subsequently, the final decomposition is performed according to the final decomposition step (#3B) described above. During the final decomposition, the value of k is N-1. Then, the final remapping is performed according to the final remapping step (#4B) described above. Then, a controlled inversion is performed according to the inversion step (#5B) described above. The inversion of the final remapping and the inversion of the final decomposition are performed according to the steps (#6B) and (#7B) described above, respectively. As described above, the final decomposition, controlled inversion, and inversion of the final decomposition are fused together into a single quantum gate.

[0050] Subsequently, as described above, controlled inverting is performed recursively to shift the decomposed substates, and the aforementioned series of remapping and decomposition steps are performed in reverse until k reaches i+1 again. However, for simplicity, the method steps performed after step S1.5 are not shown in Figure 1. As shown in Figure 1, the cascade of ancilla qubits in the ancilla register implements pairs of even and odd substates in preparation for a multistep quantum ground state shift.

[0051] The method described above has so far explained the case where i < N-2. Different steps may be performed for other values ​​of step index 'i'. This will be discussed later.

[0052] In some embodiments, the method further comprises, in the case i = N-2, a quantum circuit, The (i+1)th qubit (q) i+1Substates where ) is 0 are considered even substates, and the i+1th qubit (q i+1 By considering substates where ) is 1 as odd substates, the first subset is decomposed into even substates to be incremented and odd substates to be incremented, and the second subset is decomposed into even substates to be decremented and odd substates to be decremented; Remapping the state amplitude of the even substate to be decremented with the state amplitude of the odd substate to be decremented; The (i+1)th qubit (q) i+1 With respect to the adjacent decrement target even substates, the size 2 i+1 The amplitude block is swapped, and the i+1th qubit (q i+1 Regarding ), between adjacent incrementable odd substates, the size is 2 i+1 To swap the amplitude block, the first ancilla qubit (a1) of the ancilla register is used as the control to swap the i+2th qubit (q i+2 ) and reversing it; Reversing the step of remapping the state amplitude of the even substate to be decremented with the state amplitude of the odd substate to be decremented; Reversing the aforementioned disassembly step; 2 i To complete the multistep quantum ground state shift of the state amplitude based on the step size, the i+1th qubit (q i+1 ) and reversing it; This includes setting by [the specified method].

[0053] In particular, when i = N-2, the method is performed as follows:

[0054] The aforementioned decomposition step (#1) is performed. No decomposition by recursion is performed because the initial value k (which is considered to be i+1) becomes N-1. In this step (#1), the array substates of the first subset (i.e., the array substates to be incremented) are decomposed into even substates to be incremented and odd substates to be incremented. On the other hand, the array substates of the second subset (i.e., the array substates to be decremented) are decomposed into even substates to be decremented and odd substates to be decremented. In this respect, the (i+1)th qubit (q i+1 ), that is, the k-th qubit (q k Substates where ) is 0 are considered even substates, and the i+1th qubit (q i+1 ), that is, the k-th qubit (q k A substate where ) is 1 is considered an odd substate.

[0055] Next, the aforementioned remapping step (#2) is performed. In this step, the state amplitudes of the even substates to be decremented and the state amplitudes of the odd substates to be decremented are remapped.

[0056] In particular, if i = N-2, the next step is skipped. Decomposition step by recursion (#3A), Each recursive remapping step (#4A), Final disassembly step (#3B), Final remapping step (#4B), Reversal step (#5B), The final remapping step is reversed (#6B), The final reversal step of disassembly (#7B), Reversal step (#5A), Reversal step of remapping step (#6A), Reverse step of the decomposition step by recursion (#7A).

[0057] The aforementioned inversion step (#8) is performed. Since the value of k is i+1, the first ancilla qubit (a1) of the ancilla register is used as control, and the i+2th qubit (q i+2 ), that is, the k+1th qubit (q k+1 ) is inverted. As a result, the i+1th qubit (q i+1 ), that is, the k-th qubit (q k Regarding ), between adjacent decrement target even substates, size 2 i+1 The amplitude blocks are swapped. Similarly, the i+1th qubit (q i+1 ), that is, the k-th qubit (q k Regarding ), between adjacent odd substates that are subject to increment, size 2 i+1 The amplitude blocks are swapped.

[0058] The aforementioned remapping step (#2) is reversed, and the aforementioned step (#9) is executed.

[0059] Subsequently, the aforementioned step (#10) is performed, which reverses the aforementioned decomposition step (#1).

[0060] Finally, the aforementioned final inversion step (#11) is performed. In this step, 2 i To complete the multistep quantum ground state shift of the state amplitude based on the step size, the i+1th qubit (q i+1 ) can be reversed.

[0061] Depending on the embodiment, the method further extends to the case where i = N-1, 2 i To complete the multistep quantum ground state shift of the state amplitude based on the step size, the i+1th qubit (q i+1 This involves inverting the following to set up the quantum circuit as follows:

[0062] In particular, when i = N-1, only the final inversion step (#11) is performed, and 2 iTo complete the multistep quantum ground state shift of the state amplitude based on the step size, the i+1th qubit (q i+1 ) is inverted. i = N-1 has a size of 2 N+1 This corresponds to the largest possible step size for the state vector space. This corresponds to a step size of 2. i The size of the array register (i.e., 2 N This is because it is exactly half of the original value, and flipping the most significant qubit of an array register corresponds to a two-way shift.

[0063] For illustrative purposes only, an example of a quantum circuit that can be configured for i < N-2 or i = N-2 is shown below. Depending on the embodiment, this quantum circuit comprises the following elements in order: A starting segment with two CX gates; Depending on the embodiment, an intermediate segment having multiple CX gates and multiple 2 control gates; A terminal segment having three CX gates and one X gate.

[0064] Note that a two-controlled gate is also called a Toffoli gate. Also, be aware that the intermediate segment may not be included. This is because, in the case of i = N-2, the quantum circuit does not include an intermediate segment. This intermediate segment corresponds to the next step. Decomposition step by recursion (#3A), Each recursive remapping step (#4A), Final disassembly step (#3B), Final remapping step (#4B), Reversal step (#5B), The final remapping step is reversed (#6B), The final reversal step of disassembly (#7B), Reversal step (#5A), Remapping step step in reverse step (#6A), Reverse step of the decomposition step by recursion (#7A).

[0065] As mentioned earlier, these steps are skipped when i = N-2. That is, when i = N-2, the quantum circuit has the following elements in order: • A starting segment with two CX gates; • A terminal segment with three CX gates and three X gates.

[0066] Depending on the embodiment, the two CX gates of the starting segment are applied in the following order: • The (i+1)th qubit of the array register (q i+1 ) is used as the control corresponding to state |1>, and a CX gate targets the first ancilla qubit (a1) of the ancilla register; • Superposition qubit (q) of a shift register N+1 A CX gate is used, targeting the first ancilla qubit (a1) of an ancilla register, with the control corresponding to state |1>.

[0067] To perform the decomposition step (#1), the first of the two CX gates in the starting segment is applied. As mentioned above, in the decomposition step (#1), the array substates of the first subset (i.e., the array substates to be incremented) are decomposed into even substates to be incremented and odd substates to be incremented. On the other hand, the array substates of the second subset (i.e., the array substates to be decremented) are decomposed into even substates to be decremented and odd substates to be decremented. In this regard, the k-th qubit (q k Substates where ) is 0 are considered even substates, and the k-th qubit (q k Substates where ) is 1 are considered odd substates. In this decomposition step, the value of k is considered to be i+1. Thus, the first CX gate of the start segment is the (i+1)th qubit (q) of the array register. i+1 Use ) as the control.

[0068] To perform the remapping step (#2), the last of the two CX gates in the starting segment is applied. As mentioned above, in the remapping step (#2), the state amplitudes of the even substates to be decremented and the state amplitudes of the odd substates to be decremented are remapped. Therefore, the last CX gate in the starting segment is applied to the superposition qubit (q) of the entire shift register. N+1 Use ) as the control.

[0069] Furthermore, depending on the embodiment, the three CX gates of the terminal segment are applied in the following order: The first ancilla qubit (a1) of the ancilla register is used as the control corresponding to state |1>, and the i+2th qubit (q) of the array register is used. i+2 ) CX gate targeting; • Superposition qubit (q) of a shift register N+1 ) is used as the control corresponding to state |1>, and a CX gate targets the first ancilla qubit (a1) of the ancilla register; • The (i+1)th qubit of the array register (q i+1 ) is used as the control corresponding to state |1>, and a CX gate targets the first ancilla qubit (a1) of the ancilla register; Here, the (i+1)th qubit (q) of the array register i+1 An X-gate is applied to ).

[0070] To perform the inversion step (#8), which is executed before reversing the decomposition step (#1), the first of the three CX gates in the terminal segment is applied in order. As mentioned above, the value of k reaches i+1 again. Therefore, in the inversion step (#8), the first qubit (a1) of the ancilla register is used as control to control the k+1th qubit (q k+1 )(that is, the i+2th qubit (q i+2 )) is inverted. As a result, the i+1th qubit (q i+1Regarding ), between adjacent decrement target even substates, the size is 2 i+1 The amplitude block is swapped, and the (i+1)th qubit (q i+1 Regarding ), between adjacent incrementable odd substates, the size is 2 i+1 The amplitude block is replaced.

[0071] To perform the step (#9) that reverses the state amplitude remapping step (#2), the middle CX gate of the three CX gates in the terminal segment is applied in order. Thus, the middle CX gate of the terminal segment is the superposition qubit (q) of the shift register. N+1 ) is used as control. Notably, the same qubits applied to perform the aforementioned remapping step (#2), namely the superposition qubits of the shift register (q N+1 ) is used as control by the last CX gate of the starting segment.

[0072] To perform step #10 (i.e., the reconstruction step), which reverses the aforementioned decomposition step (#1), the last of the three CX gates in the terminal segment is applied in order. Thus, the last CX gate in the terminal segment is applied to the (i+1)th qubit (q) of the array register. i+1 ) is used as control. Notably, the same qubit that is applied to perform the aforementioned decomposition step (#1), namely the i+1th qubit (q) of the array register, is used. i+1 ) is used as control by the first CX gate of the starting segment.

[0073] The X gate in the terminal segment is applied to perform the final inversion step (#11) described above. As mentioned earlier, in the final inversion step (#11), step size 2 i To complete the multistep quantum ground state shift of the state amplitude according to the (i+1)th qubit (q i+1 ) is inverted. Therefore, the (i+1)th qubit (q) of the array register is inverted. i+1An X-gate is applied to ).

[0074] In some embodiments, the intermediate segment has one or more sets consisting of multiple CX gates and 2 control gates. The multiple CX gates and multiple 2 control gates of the intermediate segment take the form of multiple sets consisting of multiple CX gates and multiple 2 control gates. In this respect, the total number of sets in the intermediate segment depends on the number of recursions of the decomposition step by recursive processing. In other words, the total number of sets in the intermediate segment (and the total number of recursions of the decomposition step by recursive processing) depends on the value of i. This is because the number of increments until k reaches N-2 from the initial value i+1 depends on i.

[0075] Furthermore, the total number of intermediate segment sets exceeds the total number of recursions required for the decomposition steps by one, because the last set of intermediate segments corresponds to the next step. Final disassembly step (#3B), Final remapping step (#4B), Reversal step (#5B), The final remapping step is reversed (#6B), The final reversal step of disassembly (#7B).

[0076] Until k reaches N-2, the given set (among the one or more sets) corresponding to a given recursion contains the following elements in order: • Superposition qubit (q) of a shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The first CX gate uses ) as its target; • The k-th qubit (q) of the array register k ) and the ki-1th ancila qubit of the ancila register (a k-i-1 ) is used as the control corresponding to state |1>, and the ki-th ancilla qubit (a k-iThe first two control gates use ) as their target; • The ki-th ancila qubit of the ancila register (a k-i ) is used as the control corresponding to state |1>, and the k+1th qubit (q) of the array register is used. k+1 The second CX gate uses ) as its target; • The k-th qubit (q) of the array register k ) and the ki-1th ancila qubit of the ancila register (a k-i-1 ) is used as the control corresponding to state |1>, and the ki-th ancilla qubit (a k-i A second control gate that uses ) as its target; • Superposition qubit (q) of a shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The third CX gate, targeting ).

[0077] After each recursion of the recursive decomposition step (#3), the first CX gate is applied to a given set of intermediate segments to perform the remapping step (#4A). In the remapping step (#4A), the state amplitudes of the even substates to be further decremented are remapped to the state amplitudes of the odd substates to be further decremented. To perform the remapping step (#4A), the first CX gate is applied to the superposition qubit (q) of the shift register. N+1 ) is used as control, and the k-th qubit (q) of the array register is used. k It is applied using ) as the target. Note that the value of k also changes with each recursion, making it possible to perform a remapping step on smaller substates.

[0078] To perform the recursive decomposition step (#3A), the first two control gates of a given set of intermediate segments are applied. In the recursive decomposition step (#3A), the incrementing odd substate is recursively decomposed into a further incrementing even substate and a further incrementing odd substate, and the decrementing even substate is recursively decomposed into a further decrementing even substate and a further decrementing odd substate. In this respect, the k-th qubit (q k Substates where ) is 0 are considered even substates, and the k-th qubit (q k Substates where ) is 1 are considered odd substates. In the recursive decomposition step (#3A), with each recursion, the value of k is incremented by 1 until it reaches N-2. In other words, a given set (corresponding to a given recursion) has a unique k value because k is incremented with each recursion. To perform the recursive decomposition step (#3A), the first 2 control gate of a given set of intermediate segments is the k-th qubit (q) of the array register. k ) and the ki-1th ancila qubit of the ancila register (a k-i-1 ) is used as control, and the ki-th ancila qubit (a k-i It is applied using ) as the target.

[0079] The second CX gate in a given set of intermediate segments is applied to perform the inversion step (#5A). In the inversion step (#5A), the ki-th ancilla qubit (a) of the ancilla register is applied. k-i Using ) as a control, the k+1th qubit (q k+1 ) is inverted. As a result, the k-th qubit (q k Regarding ), between adjacent decrement target even substates, the size is 2 k The amplitude blocks are swapped, and the k-th qubit (q k Regarding ), between adjacent incrementable odd substates, the size is 2 kThe amplitude blocks are swapped. The second CX gate in a given set of intermediate segments performs the inversion step (#5A) by setting the ki-th ancila qubit (a) of the ancila register. k-i ) is used as control, and the k+1th qubit (q) of the array register is used. k+1 This is applied using ) as the target. This inversion step is performed with the first set of k equal to N-2, so the second to last set (of the aforementioned two or more sets of the intermediate segment) uses N-2 as the value of k. In the previous sets (of the aforementioned one or more sets of the intermediate segment), the value of k is decremented by 1 until it reaches i+1.

[0080] The second 2-control gate in a given set of intermediate segments is applied to perform the step (#7A) of reversing the decomposition step (#3A) by the recursive process described above. To perform the reconstruction step (#7A), the second 2-control gate in a given set of intermediate segments is applied to the k-th qubit (q) of the array register. k ) and the ki-1th ancila qubit of the ancila register (a k-i-1 ) is used as control, and the ki-th ancila qubit (a k-i It is applied using ) as the target.

[0081] The third CX gate in a given set of intermediate segments is applied to perform the step (#6A) that reverses the aforementioned remapping step (#4A). In order to perform the step (#6A) that reverses the remapping step (#4A), the third CX gate in a given set of intermediate segments is applied to the superposition qubit (q) of the shift register. N+1 ) is used as control, and the k-th qubit (q) of the array register is used. k It is applied using ) as the target. As mentioned above, the value of k is decremented by 1 at each recursion of step (#7A) until k reaches i+1.

[0082] It should be noted that in the intermediate segment described above, one or more sets consisting of multiple CX gates and multiple 2-control gates are not arranged in order. These sets are arranged in a predetermined manner in order to properly execute recursion. For example, the (M+1)th set corresponding to the (M+1)th recursion is placed after the first 2-control gate of the corresponding (M)th set corresponding to the (M)th recursion. This will be explained in relation to Figure 2D below.

[0083] Furthermore, depending on the embodiment, in the intermediate segment, the final set corresponding to the last recursion when k reaches N-1 includes, in order, the following elements: • Superposition qubit (q) of a shift register N+1 ) is used as the control corresponding to state |1>, and the (N-1)th qubit (q) of the array register is used as the control. N-1 ) CX gate targeting; • The (N-1)th qubit q of the array register N-1 and the (N-2)th ancila qubit a of the ancila register N-2 Use as the control corresponding to state |1>, and the Nth qubit q of the array register. N Two control gates that use the target; • Superposition qubit (q) of a shift register N+1 ) is used as the control corresponding to state |1>, and the (N-1)th qubit (q) of the array register is used as the control. N-1 ) CX gate targeting; Here, the last set corresponding to the last recursion is added after the first two control gates of the previous set (i.e., the second to last set) corresponding to the recursion when k reaches N-2.

[0084] In the above, the first CX gate in the last set of intermediate segments is applied to perform the final remapping step (#4B). In the final remapping step (#4B), the state amplitudes of the even substates to be further decremented and the state amplitudes of the odd substates to be further decremented are remapped. To perform the final remapping step (#4B), the first CX gate is applied to the superposition qubit (q) of the shift register. N+1 ) is used as control, and the (N-1)th qubit (q) of the array register is used. N-1 It is applied using ) as the target.

[0085] The second CX gate in the last set of intermediate segments is applied to perform the step (#6B) that reverses the final remapping step (#4B). To perform the step (#6B) that reverses the final remapping step (#4B), the second CX gate in the last set of intermediate segments is applied to the superposition qubit (q) of the shift register. N+1 ) is used as control, and the (N-1)th qubit (q) of the array register is used. N-1 It is applied using ) as the target.

[0086] The two-control gate in the last set of intermediate segments is applied to perform the aforementioned final decomposition step (#3B), inversion step (#5B), and step that reverses the final decomposition step (#7B). In other words, these steps are fused together and performed using a single quantum gate (i.e., two-control gate).

[0087] Referring to Figure 2A-2C, a detailed diagram of a quantum circuit according to an embodiment of the present disclosure is shown. This quantum circuit is executed by a quantum computer or quantum simulator. This quantum circuit is 2 N+1It includes a shift register and an ancilla register used to perform a multistep quantum ground state shift in a state vector space of size n. The shift register has N+1 qubits, and its first N qubits (q 1, q 2, ...q N ) forms an array register, and its last qubit (q N+1 An ancilla register is a superposition qubit. An ancilla register has up to N-2 ancilla qubits (a1, ... a N-2 ) has. This quantum circuit comprises the following elements in order: • Start segment 202 has two CX gates 2021-2022; Depending on the embodiment, an intermediate segment 206 is provided, which has multiple CX gates 2061, 2063, 2065, 2066, 2068 and multiple 2 control gates 2062, 2064, 2067; • A terminal segment 204 having three CX gates 2041-2043 and one X gate 2044.

[0088] Step size 2 in multi-step quantum ground state shift i The quantum circuit is described below. Here, the step index i is a non-negative integer less than N.

[0089] In some embodiments, as shown in Figure 2A, when i < N-2 or i = N-2, the two CX gates 2021-2022 of the starting segment 202 are applied in the following order: • The (i+1)th qubit q of the array register i+1 Using the control corresponding to state |1>, the CX gate 2021 targets the first ancilla qubit a1 of the ancilla register; • Shift register superposition qubit q N+1 Using the control corresponding to state |1>, the CX gate 2022 targets the first ancilla qubit a1 of the ancilla register.

[0090] Depending on the embodiment, as shown in Figure 2A, when i < N-2 or i = N-2, the three CX gates 2041-2043 of the terminal segment 204 are applied in the following order: The first ancilla qubit a1 of the ancilla register is used as the control corresponding to state |1>, and the i+2th qubit q of the array register is used. i+2 CX gate 2041 targeting; • Shift register superposition qubit q N+1 Using the control corresponding to state |1>, CX gate 2042 targets the first ancilla qubit a1 of the ancilla register; • The (i+1)th qubit q of the array register i+1 Using the control corresponding to state |1>, CX gate 2043 targets the first ancilla qubit a1 of the ancilla register; Here, the (i+1)th qubit (q) of the array register i+1 X-gate 2044 is applied to ).

[0091] In some embodiments, when i < N-2, the intermediate segment 206 has one or more sets consisting of multiple CX gates and multiple 2-control gates. The total number of these sets depends on the total number of recursions, where the value of k is initially equal to i+1 and is incremented by 1 with each recursion until it reaches N-2. Figure 2B shows, for illustrative purposes, a specific set corresponding to a particular recursion (however, the set up to k reaching N-2). This particular set comprises, in order, the following elements: • Superposition qubit (q) of a shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The first CX gate 2061 uses ) as its target; • The k-th qubit (q) of the array register k ) and the ki-1th ancila qubit of the ancila register (a k-i-1 ) is used as the control corresponding to state |1>, and the ki-th ancilla qubit (ak-i The first two control gates 2062 use ) as the target; • The ki-th ancila qubit of the ancila register (a k-i ) is used as the control corresponding to state |1>, and the k+1th qubit (q) of the array register is used. k+1 The second CX gate 2063 uses ) as its target; • The k-th qubit (q) of the array register k ) and the ki-1th ancila qubit of the ancila register (a k-i-1 ) is used as the control corresponding to state |1>, and the ki-th ancilla qubit (a k-i The second control gate 2064 uses ) as its target; • Superposition qubit (q) of a shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The third CX gate, 2065, targets ).

[0092] As shown by the dashed line 208, in the intermediate segment 206, the (M+1)th set corresponding to the (M+1)th recursion is added after the first two control gates of the corresponding (M)th set corresponding to the (M)th recursion.

[0093] Referring to Figure 2C, in intermediate segment 206, the final set corresponding to the last recursion when k reaches N-1 contains, in order, the following elements: • Shift register superposition qubit q N+1 Use as the control corresponding to state |1>, and the N-1th qubit q of the array register. N-1 CX gate 2066 targets; • The (N-1)th qubit q of the array register N-1 and the (N-2)th ancila qubit a of the ancila register N-2 Use as the control corresponding to state |1>, and the Nth qubit q of the array register. NTwo control gates 2067 use the target; • Shift register superposition qubit q N+1 Use as the control corresponding to state |1>, and the N-1th qubit q of the array register. N-1 CX gate 2068 targeting; Here, the last set corresponding to the last recursion is added after the first two control gates of the previous set (i.e., the second to last set) corresponding to the recursion when k reaches N-2.

[0094] Figure 2D shows a detail diagram of an example quantum circuit according to an embodiment of the present disclosure for the case N = 4, i = 0, for illustrative purposes only. This exemplary quantum circuit has a size of 2 N+1 = 2 5 = Used to perform multistep quantum ground state shifts in a state vector space of 32. The shift register has a total of 5 qubits, the first 4 of which are (q 1, q 2, q 3, q4) forms an array register, and its last qubit (q5) is a superposition qubit. The ancilla register has two ancilla qubits (a1, a2). The example quantum circuit comprises the following elements in order: • Start segment 202 has two CX gates; • Intermediate segment 206 having two sets, each containing multiple CX gates and multiple 2 control gates; • Termination segment 204 having three CX gates and one X gate.

[0095] As shown in Figure 2D, the two CX gates in the starting segment 202 are applied in the following order: A CX gate that uses the first qubit q1 of an array register as the control bit corresponding to the state |1> and the first anscira qubit a1 of an anscira register as the target; • A CX gate that uses the superposition qubit q5 of the shift register as a control corresponding to state |1> and targets the first anscira qubit a1 of the anscira register.

[0096] As shown in Figure 2D, the three CX gates of the terminal segment 204 are applied in the following order: • A CX gate that uses the first ancilla qubit a1 of the ancilla register as a control corresponding to state |1>, and targets the second qubit q2 of the array register; • A CX gate that uses the superposition qubit q5 of the shift register as a control corresponding to state |1> and targets the first ancilla qubit a1 of the ancilla register; A CX gate that uses the first qubit q1 of an array register as the control bit corresponding to the state |1> and the first anscira qubit a1 of an anscira register as the target.

[0097] Here, the X gate is applied to the first qubit q1 of the array register.

[0098] As shown in Figure 2D, the intermediate segment 206 has two sets, each containing multiple CX gates and multiple 2 control gates. As mentioned earlier, the total number of sets in the intermediate segment 206 depends on the total number of recursions. The value of k is initially equal to 1, and increments by 1 with each recursion until it reaches 2. Therefore, for the first set corresponding to the first recursion and the second set corresponding to the second recursion, the values ​​of k are 2 and 3, respectively.

[0099] As shown in Figure 2D, the first set comprises the following elements in order: The first CX gate 2061a uses the superposition qubit q5 of the shift register as the control corresponding to state |1> and the second qubit q2 of the array register as the target; The first two-control gate 2062a uses the second qubit q2 of the array register and the first ancilla qubit a1 of the ancilla register as controls corresponding to state |1>, and the second ancilla qubit a2 of the ancilla register as the target; The second CX gate 2063a uses the second ancilla qubit a2 of the ancilla register as the control corresponding to state |1>, and the third qubit q3 of the array register as the target; • A second 2-control gate 2064a, using the second qubit q2 of the array register and the first ancilla qubit a1 of the ancilla register as controls corresponding to state |1>, and using the second ancilla qubit a2 of the ancilla register as the target; • A third CX gate 2065a uses the superposition qubit q5 of the shift register as the control corresponding to state |1> and the second qubit q2 of the array register as the target.

[0100] In the intermediate segment 206, the second set is placed after the first two control gates 2062a of the first set. As shown in Figure 2D, the second set comprises the following elements in order: CX gate 2066 uses the superposition qubit q5 of the shift register as the control corresponding to state |1> and the third qubit q3 of the array register as the target; A 2-control gate 2067 uses the third qubit q3 of the array register and the second ancilla qubit a2 of the ancilla register as controls corresponding to state |1>, and the fourth qubit q4 of the array register as the target; CX gate 2068 uses the superposition qubit q5 of the shift register as the control corresponding to state |1> and the third qubit q3 of the array register as the target.

[0101] In the example circuit in Figure 2D, the first step of controlled inverting (corresponding to the 2-controlled gate 2067) is applied to the last qubit q4 of the array register. This is because this inverting step starts at k = N-1 = 3. Therefore, the step size of the first sub-state shift is 2 k = 2 3 = 8. Since the first step of controlled inversion is performed after all decomposition processes have been carried out, the first substate shift applies only to the last substate of the decomposition (i.e., the even and odd substates relating to the third qubit q3).

[0102] Since the value of k after decrement is 2, the second step of controlled inversion (corresponding to CX gate 2063a) is applied to the third qubit q3. Thus, the step size of the second substate shift is 2. 2 = 4. The second substate shift applies only to the even and odd substates related to the second qubit q2.

[0103] Similarly, the third step of controlled inversion (corresponding to CX gate 2041) is applied to the second qubit q2. This is because the value of k is further subtracted to 1. Thus, the step size of the third substate shift is 21 = 2. The third substate shift is applied only to the even and odd substates with respect to the first qubit bit q1.

[0104] Finally, the last inversion step (corresponding to X gate 2044) is performed by applying an X gate to the first qubit, bit q1. This completes a multi-step quantum ground state shift of step size 1 for all states of the array register in this exemplary quantum circuit. In Figures 2A through 2D, each X gate applied to perform the inversion step is enclosed by a dashed line.

[0105] In Figure 2D, the step index i is set to 0 to illustrate multiple recursion using the simplest example of a quantum circuit where the entire shift register consists of only 5 qubits. Based on the generalized implementation of the quantum circuit shown in Figures 2A-2C, it is possible to construct larger and more complex quantum circuits.

[0106] Multistep quantum ground state shifts implemented using such quantum circuits can be used in a variety of quantum algorithms, including quantum random walks and other related quantum applications. Particularly advantageous is that multistep quantum ground state shifts can be implemented as a fundamental building block in discrete quantum random walks and can be adopted in multiple quantum algorithms. For example, multistep quantum ground state shifts are used to implement the propagation step in quantum algorithms such as the Quantum Lattice Boltzmann Method (QLBM) and Quantum Lattice Gas Automata (QLGA).

[0107] In this regard, the method may further include executing a quantum algorithm using a quantum circuit that performs multi-step quantum ground state shifts as a subroutine within the quantum algorithm. In the simplest implementation of the method, the quantum circuit is used to perform multi-step quantum ground state shifts in an orthogonal direction on a polygonal lattice. The quantum circuit can also be used to perform multi-step quantum ground state shifts in a non-orthogonal direction on a polygonal lattice. Such multi-step quantum ground state shifts on polygonal lattices are of interest in several quantum algorithms, such as lattice-based physics solvers used to simulate physical processes. QLBM and QLGA are examples of such lattice-based physics solvers. In particular, the simulation of physical processes frequently involves quantum random walks and related quantum applications. Therefore, the quantum circuit of this disclosure can be used to perform multi-step quantum ground state shifts as a subroutine within a quantum algorithm.

[0108] Quantum algorithms can be used in a variety of practical application fields, and quantum circuits offer a clear computational advantage in diverse application areas such as cryptography and cybersecurity, drug discovery and molecular modeling, materials science and engineering, financial modeling and risk analysis, machine learning and artificial intelligence, climate modeling and environmental analysis. In this regard, quantum algorithms are used to perform simulations of physical processes. Here, the method further includes providing the user with measurements obtained after the simulation of the physical process. The state variables measured depend on the quantum algorithm and the physical process being simulated. Multistep quantum ground state shifts achieve a significant quantum speedup because they can execute multiple shift directions simultaneously at a computational complexity class equivalent to that of single-step ground state shifts. This makes it possible to provide measurement results to the user very quickly. In particular, this allows for the execution of multiple simulations of physical processes with a high degree of parallelism. Due to parallelization, the overall depth of the quantum algorithm becomes shallower compared to quantum algorithms using single-step ground state shifts. Advantageously, such shallow quantum algorithms are simpler to operate and tend to accumulate less noise and error in measurements.

[0109] Next, we will explain how the multistep quantum ground state shift performed using the method described above compares to a quantum random walk and how it can be implemented as part of a quantum random walk. The multistep quantum ground state shift relates to a shift of all states in an array register, which can be called a full data array shift. A quantum random walk, on the other hand, is defined as a superposition of at least two full data array shifts, where the interpretation of the walk probability depends on how the superposition is achieved.

[0110] Figure 3 shows an example of a full data array shift, i.e., a combination of two multistep quantum ground state shifts, which can be interpreted as a positional pattern on a two-dimensional lattice. In this example, the combination of two multistep quantum ground state shifts all states of the array register two steps to the right and one step upward. All states of the array register cover the entire two-dimensional lattice, but for illustrative purposes, some of the ground states are marked as lattice points on the two-dimensional lattice. This can be interpreted as particles existing at those lattice points. A "combination of two multistep quantum ground state shifts" means moving all states on the two-dimensional lattice as shown in Figure 3. This can be interpreted as the movement of particles. Algorithmically, not only the non-trivial marked lattice points but the entire state vector space is moved within the lattice. In the context of performing this combination of two multistep quantum ground state shifts, this movement corresponds to a remapping of state amplitudes. For example, if the ground states are indexed, the increment operator moves the state amplitudes to the next ground state according to the index.

[0111] Multistep quantum ground state transitions can be extended to quantum random walks by defining a superposition of all data in the state vector space on a lattice (each representing a different probability). As an example, consider the case where two multistep quantum ground state transitions are combined with equal weights. This can be interpreted as a uniform probability of a particle moving in either direction. This is just a simple example, but superposition can become complex depending on the embodiment. For example, one particle might have a different probability of appearing anywhere on the lattice, and another particle might have a different probability of moving in exactly the correct direction.

[0112] For simplicity, this specification focuses only on uniform superpositions of various different motions in multistep quantum ground state shifts. The simplest example is uniform symmetric motion, in which case the superpositions are symmetrically paired. This can be interpreted as diffusive motion on a regular lattice. As mentioned earlier, quantum circuits of such uniform symmetric motion are highly efficient due to their inherent parallelizability. This parallelizable uniform symmetric motion is also called a "parallel symmetric shift".

[0113] Throughout this specification, the canonical basis state is assumed to be 0 and 1, and the corresponding tensor product basis state is the bit string q m q m-1 ...assuming q1. Here q j The qubits are ∈{0,1}, and the rightmost bit is the least significant bit. In quantum circuit diagrams, the least significant qubit is displayed at the top. A finite subset of N qubits is used for indexing. Here, it is assumed that the index starts from 1.

[0114] The ground state shift is a Fredholm operator on Hilbert space induced by the tensor product of qubits. In other words, the indexed set of ground states {e j} n j=1 In contrast, the increment operator can be expressed as follows: S+:e j →e j +1

[0115] Furthermore, the decrement operator can be expressed as follows: S-:e j →e j -1

[0116] In a multi-step quantum ground state shift, the sequence of state amplitudes, which are the coefficients of the ground state, is shifted. Therefore, a multi-step quantum ground state shift moves the state amplitudes forward or backward in the index sequence of the ground state.

[0117] TIFF2026104806000001.tif28170

[0118] Furthermore, we assume that the indexing of the ground states is isomorphic to the quotient group Z / nZ, where n is the dimension of the state vector space, and n = 2 N This makes the shift periodic, allowing it to be interpreted as amplitude propagation on a cyclic one-dimensional graph. Of particular note is that in a one-dimensional lattice, the parallel symmetric shift is performed as a bidirectional shift. This interpretation of the parallel symmetric shift can be easily extended to higher dimensions from the perspective of orthogonal lattices, as will be discussed later.

[0119] From this perspective, we consider interpretations of parallel symmetric shifts in r-dimensional lattices (i.e., r = 2 or 3). These interpretations are particularly important in the practical application of quantum circuits. As mentioned above, we assume that parallel symmetric shifts are periodic. However, such periodicity is assumed to be with respect to each spatial dimension, such that the indexing is isomorphic to (Z / nZ)r. Here, this product is the direct product of quotient groups. Also, n is the size of the state vector subspace corresponding to one of the spatial dimensions of the entire state vector space, i.e., the length of the lattice edges of the state vector subspace. For simplification, the interpretation is carried out assuming a square lattice (for r = 2) or a cubic lattice (for r = 3), and that n (i.e., the size of the state vector subspace) is a power of 2. Topologically, such lattices can be interpreted as discrete torus surfaces. Furthermore, the different directions along the different dimensions of these lattices are considered orthogonal simply to refer to the structure of these lattices. Note that the dimensions are irrelevant to the purposes of this specification, and rather the fact that the directions are somewhat independent of each other is important.

[0120] The parallel symmetric shift in the one-dimensional lattice described above can be applied to higher dimensions (i.e., two-dimensional or three-dimensional lattices) by additional arrangement of ground states. In this regard, depending on the embodiment, this method can be applied to at least one additional dimension with a size of 2 i This further includes performing at least one additional multistep quantum ground state shift having (i.e., a power of 2). In some embodiments, the multistep quantum ground state shift and at least one additional multistep quantum ground state shift are performed by sequentially stacking one-dimensional shifts for one dimension and at least one additional dimension, respectively. Such stacking of one-dimensional multistep quantum ground state shifts is performed by considering an array register (i.e., an indexed array of ground states) as corresponding to a stack of multiple one-dimensional data. This ensures the correct superposition of "direction substates". It will be seen that this step can be performed using the steps of the method for the multistep quantum ground state shift (i.e., parallel symmetric shifts for a one-dimensional lattice) described above. In the above, when r = 2, at least one additional dimension includes a single additional dimension, and at least one additional multistep quantum ground state shift includes a single additional multistep quantum ground state shift. Similarly, when r = 3, at least one additional dimension includes two additional dimensions, and at least one additional multistep quantum ground state shift includes two additional multistep quantum ground state shifts.

[0121] The technical advantage of this is that multi-step quantum ground state shifts and at least one additional multi-step quantum ground state shifts can be performed together in the same computational complexity class as a single-step ground state shift. This technical advantage stems from the parallelization of multiple shifts under a single operation. Parallelization makes the overall depth of the quantum circuit for multi-step quantum ground state shifts and at least one additional multi-step quantum ground state shift less than twice the overall depth of the quantum circuit for a single-step ground state shift. Furthermore, it allows for different step sizes at once for different array substates corresponding to different dimensions.

[0122] In an r-dimensional lattice (with dimension r), an array register has rN qubits. Furthermore, to consider simple orthogonal shifts in all dimensions, r superposition qubits are required. Therefore, a shift register must have r(N+1) qubits, with the first rN qubits forming the array register and the last r qubits being superposition qubits. The r superposition qubits enable superposition along all directions of the r-dimensional lattice.

[0123] In other embodiments, multistep quantum ground state shifts and at least one additional multistep quantum ground state shifts are performed by changing the qubit order of the corresponding substates in the multistep quantum ground state shift and at least one additional multistep quantum ground state shift using controlled swap blocks for one dimension and at least one additional dimension, respectively. In other words, only a single one-dimensional shift is performed in these controlled swap blocks. The technical advantage of using controlled swap blocks is that they not only guarantee the correct superposition of "direction substates" but are also efficient in larger lattices. Controlled swap gates increase the overall complexity of the quantum circuit compared to a single one-dimensional shift, but the overall complexity remains linear.

[0124] Figure 4 shows a detailed diagram of a quantum circuit that uses two controlled swap blocks to perform two multistep quantum ground state shifts in two dimensions, according to an embodiment of the present disclosure. The two multistep quantum ground state shifts enable a symmetrically equal shift in four directions on a two-dimensional regular lattice using two controlled swap blocks. Referring to Figure 4, the box labeled "Shift" represents the quantum circuit for performing the multistep quantum ground state shift (i.e., shown in Figures 2A-2C). The first of the two controlled swap blocks is applied before performing the multistep quantum ground state shift, and the second swap block is applied after the multistep quantum ground state shift has been performed.

[0125] Most importantly, the array register has 2N qubits (q 1, q 2, ...q 2N ) has. Here, the quantum circuit for multistep quantum ground state shift is the first half of the array register, i.e., the first N qubits (q) of the array register. 1, q 2, ...q N ) and is applied to the first superposition qubit (c1) of the superposition register. The superposition register has two superposition qubits (c1, c2). Here, the second superposition qubit (c2) is used to provide control over the two uncontrolled swap blocks. In such an implementation, the shift register is an array register (q 1, q 2, ...q 2N It consists of a single register and superposition registers (c1, c2).

[0126] As shown in Figure 4, the first controlled swap block and the second controlled swap block each contain N controlled swap gates. The N controlled swap gates of the first controlled swap block are arranged symmetrically with respect to the N controlled swap gates of the second controlled swap block. In the first controlled swap block, the N controlled swap gates comprise the following elements in order: • The first qubit q1 of the array register and the (N+1)th qubit q of the array register N+1 The first controlled swap gate is applied between the two states, using the second superposition qubit c2 of the superposition register as the control corresponding to state |1>; • The second qubit q2 of the array register and the (N+2)th qubit q of the array register N+2 The second controlled swap gate is applied between the two states, using the second superposition qubit c2 of the superposition register as the control corresponding to state |1>; The same applies to the following... • The Nth qubit q of the array register N and the 2Nth qubit q of the array register 2N The Nth uncontrolled swap gate is applied between the two states, using the second superposition qubit c2 of the superposition register as the control corresponding to state |1>.

[0127] In the second controlled swap block, the N controlled swap gates comprise the following elements in order: • The Nth qubit q of the array register N and the 2Nth qubit q of the array register 2N The first controlled swap gate is applied between the two states, using the second superposition qubit c2 of the superposition register as the control corresponding to state |1>; • The (N-1)th qubit N-1 of the array register and the 2N-1th qubit q of the array register 2N-1The second controlled swap gate is applied between the two states, using the second superposition qubit c2 of the superposition register as the control corresponding to state |1>; The same applies to the following... • The first qubit q1 of the array register and the (N+1)th qubit q of the array register N+1 The Nth uncontrolled swap gate is applied between the two states, using the second superposition qubit c2 of the superposition register as the control corresponding to state |1>. [Experimental Results]

[0128] In practical implementations of quantum circuits that perform multi-step quantum ground state shifts, it is important to understand the complexity of the quantum circuit in terms of the required gates and qubits. In this regard, gate complexity (i.e., the complexity of a quantum circuit based on the number of required gates) has been measured as the number of CX gates relative to the number of qubits. This is because CX gates (i.e., controlled 1-qubit X gates) are often considered fundamental gates and have the highest gate infidelity in today's actual quantum computers.

[0129] The quantum circuits of this disclosure have only X gates, CX gates, and 2-controlled gates (i.e., Toffoli gates). Step size 2 i It is clear that the number of gates in a quantum circuit is maximized when is 1, i.e., i = 0. To calculate the gate complexity of a quantum circuit, we consider several different implementations of the quantum circuit for N>1 and i = 0. Here, the size of the state vector space is i.e., 2 N As the number of elements increases, the size of the array registers also increases.

[0130] In the first case, N = 1, the array register has only one qubit (q1). In this case, i = N-1, and the first implementation of the quantum circuit consists of only one X gate.

[0131] In the second case, N = 2, the array register has two qubits (q1, It has q2). In the second case, i = N - 2, and the second implementation of the quantum circuit consists of five CX gates and one X gate. The configuration of these five CX gates and the X gate in the second case can be considered as a basic configuration for a larger-scale circuit.

[0132] In the third case where N = 3, the array register has three qubits (q 1, q 2, q3). In the third case, when i < N - 2, the third implementation of the quantum circuit, in addition to the five CX gates and X gate of the basic configuration, has two CX gates for performing the final remapping and the inversion of the remapping, and a Toffoli gate that performs the final decomposition, sub-state shift (i.e., inversion), and the inversion of the final decomposition together.

[0133] When i < N - 2 (i.e., when N > 3), each time a qubit is added to the array register, the corresponding implementation of the quantum circuit includes the following: One CX gate for performing an additional sub-state shift, Two Toffoli gates and two CX gates for performing decomposition by recursion, remapping, inversion of the decomposition by recursion, and inversion of the remapping.

[0134] These are provided in addition to the gates in the aforementioned third implementation.

[0135] Using the minimum decomposition that splits the Toffoli gate into six CX gates and several single-qubit gates, the corresponding implementation of the quantum circuit has, in addition to the five CX gates and X gate of the basic configuration and the additional eight CX gates of the third implementation, an additional 15 CX gates. Therefore, the gate complexity (measured by the number of CX gates with respect to the number of qubits) when N > 3 and i = 0 can be expressed as follows: n CX (N) = 15(N) - 32

[0136] Each time a qubit is added to the array register, 15 CX gates are added to the quantum circuit (if N=3 or greater), but each time the step size increases, 15 CX gates are removed from the quantum circuit. Therefore, generally, with a step size of 2... i The gate complexity for (i < N-2 or i = N-2) can be expressed as follows: n CX (N,i) = 15(Ni)-32

[0137] It can be seen that the required number of ancilla qubits is Ni-2.

[0138] Compare the gate complexity of multistep quantum ground state shifts as follows: (i) Shifts based on the quantum Fourier transform proposed by Shakeel ("Efficient and scalable quantum walk algorithms via the quantum fourier transform", Quantum Information Processing 19 (2020)); (ii) The parallel shift method proposed by Budinski et al. (Efficient parallelization of quantum basis state shift, Quantum Science and Technology 8 (2023) 045031).

[0139] In the table below, "QFT" represents (i) above, "Parallel" represents (ii) above, and "Parallel cascade" represents the multistep quantum ground state shift as defined herein. The number of CX gates is calculated using ancilla decomposition and gate cancellation whenever possible. All-to-all connections between qubits are assumed.

[0140] The first table below shows the bidirectional shifts in a one-dimensional lattice, given the number of qubits (N) in the array register and the step size 2. iShows the gate complexity measured as the number of CX gates for []. The number of qubits refers to the number of qubits used to encode the array register. [Table 1]

[0141] Figure 5 shows how the number of CX gates in various bidirectional shifts with a step size of 1 changes with respect to the number of qubits (N) used to encode a 1D lattice. In Figure 5, for the aforementioned (i) (represented by QFT) and the multi-step quantum ground state shift (initially denoted as "Parallel cascade" in the first table but shown as Parallel in Figure 5), it shows how the gate complexity changes.

[0142] The following Table 2 shows the gate complexity measured as the number of CX gates for a 4-directional 2D array shift in a 2D lattice with respect to the number of qubits. In both shift methods, 2D expansion is implemented using a controlled swap block. The number of qubits refers to the number of qubits used to encode one side of the lattice. Therefore, twice this number of qubits is required for the array register. [Table 2]

[0143] The following Table 3 represents the gate complexity measured as the number of CX gates for a 6-directional 3D array shift in a 3D lattice with respect to the number of qubits. 3D expansion is performed using a controlled swap block for all shift methods. The number of qubits refers to the number of qubits used to encode one side of the lattice. Therefore, three times this number of qubits is required for the array register. [Table 3]

[0144] Furthermore, to interpret the gate complexity of multistep quantum ground state shifts in various practical implementations, we compare implementation examples of multistep quantum ground state shifts in quantum random walks with the aforementioned implementation example of (i) (i.e., QFT) in quantum random walks. For simplicity, these implementation examples are interpreted assuming trivial initial states and a quantum coin operator as a Hadamard gate. This Hadamard gate sets the increment and decrement to a uniform superposition. This interpretation transpiles the corresponding quantum circuit using the basis gate set {CX,SX,RZ,ID} designed for the IBM Falcon quantum processor family, Q iskit This is done using the SDK's transpiler with default settings. For simplicity, all-to-all connections between qubits are assumed.

[0145] In this regard, Table 4 below shows the gate complexity for a bidirectional one-dimensional quantum walk, measured as the total number of gates and the number of CX gates relative to the number of qubits. The number of qubits refers to the number of qubits used to encode the array register. [Table 4]

[0146] Figure 6 shows how the total number of gates (i.e., the total number of gates) changes with respect to the number of qubits (N) used to encode the one-dimensional lattice in a bidirectional one-dimensional quantum walk with a step size of 1. Figure 6 shows how the gate complexity changes for (i) above (denoted as QFT) and for a multi-step quantum ground state shift (denoted as "Parallel cascade" in Table 4, but shown as Parallel in Figure 6). A similar pattern is observed when focusing only on the number of CX gates.

[0147] Table 5 below shows the gate complexity for a 2D quantum walk in four directions, measured as the total number of gates and the number of CX gates relative to the number of qubits. In both shift schemes, 2D extension is performed using controlled swap blocks. The number of qubits refers to the number of qubits used to encode one side of the lattice. Array registers require twice this number of qubits. [Table 5]

[0148] Figure 7 shows how the total number of gates (i.e., the total number of gates) changes with respect to the number of qubits (N) used to encode one edge of the lattice in a 4-directional 2D quantum walk with a step size of 1. Figure 7 shows how the gate complexity changes for (i) (denoted as QFT) and for a multistep quantum ground state shift (denoted as "Parallel cascade" in Table 4 and shown as Parallel in Figure 7). A similar pattern is observed when focusing only on the number of CX gates.

[0149] Furthermore, to interpret the gate complexity of multistep quantum ground state shifts in various practical implementations, we compare another implementation example of multistep quantum ground state shifts in the quantum lattice Boltzmann method (QLBM) with another implementation example of (i) (i.e., QFT) in QLBM. QLBM involves steps of collision, propagation, and macroscopics, which are executable, for example, as described in Ljubomir Budinski, "Quantum algorithm for the advection-diffusion equation simulated with the lattice Boltzmann method", Quantum Information Processing (2021). These other implementation examples are interpreted assuming trivial initial states for clarity. This interpretation is performed by transpiling using qiskit's default settings. All-to-all connections between qubits are assumed.

[0150] In this regard, Table 6 below shows the gate complexity measured as the total number of gates and CX gates relative to the number of qubits. For a 2D QLBM model in which the Advection-Diffusion Equation (ADE) is used in the propagation step, the gate complexity measured as the total number of gates and CX gates relative to the number of qubits is shown. In this model, there are five possibilities in the shift direction, one of which implements a steady substate. In both shift schemes, a 2D extension is implemented using controlled swap blocks. The number of qubits refers to the number of qubits used to encode one side of the lattice. Array registers require twice this number of qubits. [Table 6]

[0151] In contrast to two-dimensional quantum walks, the two-dimensional QLBM model for the advection-diffusion equation (ADE) employed for the propagation step requires additional control over steady-state substates. For clarity, note that the effects of initial state preparation are excluded, and trivial initial states are assumed. Also note that the overall complexity scale of this QLBM model depends only on the propagation step, as all other steps of the quantum algorithm are constant for a given physical configuration. QLGA quantum circuits, being structurally similar to QLBMs, follow a similar pattern. This highlights the importance of optimizing multi-step quantum ground state shifts.

[0152] Figure 8 shows how the total number of gates (i.e., the total number of gates) changes with respect to the number of qubits (N) encoding one edge of the lattice in a 2D QLBM model for ADE employed with various shifts for the propagation step. Figure 8 shows how the gate complexity changes for (i) above (denoted as QFT) and multistep quantum ground state shift (denoted as "Parallel cascade" in Table 4 and shown as Parallel in Figure 8).

[0153] For a more detailed analysis, the fidelity of the output distribution obtained from simulations was compared with that of existing quantum devices using superconducting qubits. These simulations considered reported gate errors, readout errors, and the actual qubit connectivity of the quantum devices. 2048 shots were used per simulation to map the distributions of QFT-based shifts and multi-step quantum ground state shifts.

[0154] Figure 9 shows a comparison of circuit fidelity for the number of qubits N used to encode a one-dimensional lattice, and compares the circuit fidelity of several different bidirectional shifts with a step size of 1. The comparison of circuit fidelity relates to a comparison of the mean Hellinger fidelity of these simulations against an ideal distribution, with standard deviations obtained from 20 iterations of simulation. In particular, the Hellinger fidelity is calculated by comparing the total state distribution from noisy device simulations with an ideal, noise-free distribution. These distributions were collected from 2048 shots per simulation and repeated 20 times to obtain the mean Hellinger fidelity and standard deviation. In Figure 9, (i) above is shown as QFT, and the multistep quantum ground state shift is shown as Parallel.

[0155] It is clear that multi-step quantum ground state shifts consistently outperform QFT shifts, even with a small number of qubits. The large deviations in multi-step quantum ground state shifts can be explained by the effect of additional ancilla registers. Increasing the number of shots per simulation should reduce this effect.

Claims

1. A method performed by a quantum computer or quantum simulator, wherein the method is 2 N+1 Setting up a shift register and an ancilla register for a quantum circuit used to perform a multistep quantum ground state shift in a state vector space of size n, wherein the shift register has a total of N+1 qubits, and the first N qubits (q) of the shift register 1， q 2， ...q N ) forms an array register, and the last qubit (q) of the shift register N+1 ) is a superposition qubit, and the ancilla register has up to N-2 ancilla qubits (a 1 , ...a N-2 ) including the setting described above; 2 N+1 For an input state having N+1 array sub - states, regarding the array sub - states where the superposed quantum bit (q N+1 ) is 0 as the array sub - states to be incremented, and regarding the array sub - states where the superposed quantum bit (q N+1 ) is 1 as the array sub - states to be decremented, by dividing the input state into a first subset which is a subset including the array sub - states to be incremented and a second subset which is a subset including the array sub - states to be decremented; In the multi-step quantum ground state shift described above, the step size is 2 i In the case of i < N-2, the quantum circuit is set up accordingly; This includes, however, the step index i is a non-negative integer less than N, and setting up the quantum circuit is, The k-th (k=i+1) qubit (q k Substates where ) is 0 are considered even substates, and the k-th qubit (q k By considering substates where ) is 1 as odd substates, the first subset is decomposed into even substates to be incremented and odd substates to be incremented, and the second subset is decomposed into even substates to be decremented and odd substates to be decremented; Remapping the state amplitude of the even substate to be decremented with the state amplitude of the odd substate to be decremented; The kth qubit (q k Substates where ) is 0 are considered even substates, and the k-th qubit (q k By considering a substate where ) is 1 as an odd substate, a recursive process in which k is incremented by 1 in each recursion until k reaches N-2 decomposes the incrementing odd substate into a further incrementing even substate and a further incrementing odd substate, and decomposes the decrementing even substate into a further decrementing even substate and a further decrementing odd substate; Each time recursion occurs, the state amplitude of the even substates to be further decremented is remapped to the state amplitude of the odd substates to be further decremented; The (N-1)th qubit (q N-1 Substates where ) is 0 are considered even substates, and the N-1th qubit (q N-1 By considering a substate where ) is 1 as an odd substate, the further incrementable odd subset is ultimately decomposed into an even substate and an even substate, and the further decrementable even subset is ultimately decomposed into an even substate and an odd substate; The state amplitude of the even substates subject to further decrement and the state amplitude of the odd substates subject to further decrement are ultimately remapped; The k-th (where k=N-1) qubit (q k With respect to the adjacent decrement target even substates, the size 2 k The amplitude block is swapped, and the size 2 is swapped between adjacent incrementing odd substates. k To swap the amplitude block, the (N-1)th qubit (q) of the array register is used. N-1 ) and the N-2nd ancila qubit of the ancila register (a N-2 ) is used as a control to control the Nth qubit (q N ) and reversing it; Reversing the step of finally remapping the state amplitude of the even substates to be further decremented and the state amplitude of the odd substates to be further decremented; Reverse the step of finally decomposing, provided that the step of finally decomposing and the Nth qubit (q N The step of inverting ) and the step of finally decomposing are to be fused together; The kth qubit (q k With respect to the adjacent decrement target even substates, the size 2 k The amplitude block is swapped, and the k-th qubit (q k Regarding ), between adjacent incrementable odd substates, the size is 2 k To swap the amplitude block, the ki-th ancila qubit (a) of the ancila register k-i ) is used as the control to use the k+1th qubit (q k+1 The inversion of ) where k is equal to N-2, and is decremented by 1 at each inversion of the recursion in the decomposition step by the recursive process until it reaches i+2; Reversing the step of remapping the state amplitude of the even substates to be further decremented with the state amplitude of the odd substates to be further decremented; Reverse the step of decomposition by the aforementioned recursive process, provided that the k+1th qubit (q k+1 The step of inverting and the step of reversing the remapping step are repeated prior to the inversion of each recursion of the decomposition step by the recursive process; The (i+1)th qubit (q) i+1 With respect to the adjacent decrement target even substates, the size 2 i+1 The amplitude block is swapped, and the i+1th qubit (q i+1 Regarding ), between adjacent incrementable odd substates, the size is 2 i+1 To swap the amplitude block, the first ancila qubit (a) of the ancila register 1 ) is used as a control to control the i+2th qubit (q i+2 ) and reversing it; Reversing the step of remapping the state amplitude of the even substate to be decremented with the state amplitude of the odd substate to be decremented; Reversing the aforementioned disassembly step; The aforementioned multi-step quantum ground state shift with a step size of 2 i To complete the multistep quantum ground state shift of the state amplitude based on, the i+1th qubit (q i+1 ) and reversing it; Tested by, method.

2. If i = N-1, the step size is 2 i To complete the multistep quantum ground state shift of the state amplitude based on the i+1 qubit (q i+1 The method according to claim 1, comprising setting the quantum circuit by inverting ).

3. If i = N-2, The (i+1)th qubit (q) i+1 Substates where is 0 are considered even substates, and the (i+1)th qubit (q i+1 By considering substates where ) is 1 as odd substates, the first subset is decomposed into even substates to be incremented and odd substates to be incremented, and the second subset is decomposed into even substates to be decremented and odd substates to be decremented; Remapping the state amplitude of the even substate to be decremented with the state amplitude of the odd substate to be decremented; The (i+1)th qubit (q) i+1 With respect to the adjacent decrement target even substates, the size 2 i+1 The amplitude block is swapped, and the i+1th qubit (q i+1 Regarding ), between adjacent incrementable odd substates, the size is 2 i+1 To swap the amplitude block, the first ancila qubit (a) of the ancila register 1 ) is used as a control to control the i+2th qubit (q i+2 ) and reversing it; Reversing the step of remapping the state amplitude of the even substate to be decremented with the state amplitude of the odd substate to be decremented; Reversing the aforementioned disassembly step; The aforementioned step size 2 i To complete the multistep quantum ground state shift of the state amplitude based on the i+1 qubit (q i+1 ) and reversing it; The method according to claim 1 or 2, comprising setting up the quantum circuit by means of the method.

4. The aforementioned quantum circuits, in order, A starting segment with two CX gates; In some cases, an intermediate segment having multiple CX gates and multiple 2 control gates; A terminal segment having three CX gates and one X gate; The method according to claim 1 or 3, comprising:

5. The two CX gates of the aforementioned starting segment are - The i+1th qubit (q) of the array register i+1 ) is used as the control corresponding to state |1>, and the first ancilla qubit (a) of the ancilla register is used. 1 ) CX gate targeting; - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the first ancilla qubit (a) of the ancilla register is used. 1 ) CX gate targeting; The method according to claim 4, applied in the order of:

6. The three CX gates of the termination segment are - The first ancila qubit (a) of the ancila register 1 ) is used as the control corresponding to state |1>, and the i+2th qubit (q) of the array register is used. i+2 ) CX gate targeting; - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the first ancilla qubit (a) of the ancilla register is used. 1 ) CX gate targeting; - The i+1th qubit (q) of the array register i+1 ) is used as the control corresponding to state |1>, and the first ancilla qubit (a) of the ancilla register is used. 1 ) CX gate targeting; The order in which they are applied is such that the i+1th qubit (q) of the array register is applied. i+1 The method according to claim 5, wherein an X gate is applied to ).

7. The intermediate segment has one or more sets consisting of multiple CX gates and multiple 2-control gates, and the total number of sets in the intermediate segment depends on the total number of recurs in the decomposition step by recursive processing, and the given sets corresponding to a given recursion until k reaches N-2 are, in order, - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The first CX gate uses ) as its target; - The k-th qubit (q) of the array register k ) and the ki-1th ancila qubit of the ancila register (a k-i-1 ) is used as the control corresponding to state |1>, and the ki-th ancilla qubit (a k-i The first two control gates use ) as their target; - The ki-th ancila qubit (a k-i ) is used as the control corresponding to state |1>, and the k+1th qubit (q) of the array register is used. k+1 The second CX gate uses ) as its target; - The k-th qubit (q) of the array register k ) and the ki-1th ancila qubit of the ancila register (a k-i-1 ) is used as the control corresponding to state |1>, and the ki-th ancilla qubit (a k-i A second control gate that uses ) as its target; - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The third CX gate targets ); The method according to any one of claims 4 to 6, wherein the (M+1)th set corresponding to the (M+1)th recursion of the given set is positioned after the first two control gates of the (M)th set corresponding to the (M)th recursion of the given set.

8. In the aforementioned intermediate segment, the last set corresponding to the last recursion when k reaches N-1 is, in order, - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the (N-1)th qubit (q) of the array register is used as the control for state |1>. N-1 ) CX gate targeting; - The (N-1)th qubit q of the array register N-1 and the N-2nd ancila qubit a of the aforementioned ancila register N-2 The control corresponding to state |1> is used, and the Nth qubit q of the array register is used. N Two control gates that use the target; - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the (N-1)th qubit (q) of the array register is used as the control for state |1>. N-1 ) CX gate targeting; The method according to claim 7, wherein the last set corresponding to the last recursion is added following the first two control gates of the previous set corresponding to the recursion when k reaches N-2.

9. Size 2 for at least one additional dimension i The method according to any one of claims 1 to 8, further comprising performing at least one additional multistep quantum ground state shift having

10. The method according to claim 9, wherein the multi-step quantum ground state shift and the at least one additional multi-step quantum ground state shift are performed by sequentially stacking one-dimensional shifts for one dimension and the at least one additional dimension, respectively.

11. The method according to claim 9, wherein the multi-step quantum ground state shift and the at least one additional multi-step quantum ground state shift are performed by changing the qubit order of the corresponding substates in the multi-step quantum ground state shift and the at least one additional multi-step quantum ground state shift using controlled swap blocks for each of the one dimension and the at least one additional dimension, respectively.

12. The method according to any one of claims 1 to 11, comprising executing the quantum algorithm using a quantum circuit that performs the multi-step quantum ground state shift as a subroutine within the quantum algorithm.

13. The method according to claim 12, wherein the quantum algorithm is performed to carry out a simulation of a physical process, and the method further comprises providing the user with measurements obtained after the simulation of the physical process.

14. A quantum computer or quantum simulator configured to perform the method described in any one of claims 1 to 13.

15. A quantum circuit executed by a quantum computer or quantum simulator, wherein the quantum circuit comprises 2 N+1 It includes a shift register and an ancilla register used to perform a multistep quantum ground state shift in a state vector space of size n, wherein the shift register contains N+1 qubits, and the first N qubits (q) of the shift register 1， q 2， ...q N ) forms an array register, and the last qubit (q) of the shift register N+1 ) is a superposition qubit, and the ancilla register has up to N-2 ancilla qubits (a 1 , ...a N-2 ) and the quantum circuit is, in order, A starting segment with two CX gates; Depending on the embodiment, an intermediate segment having a plurality of CX gates and a plurality of 2 control gates; A terminal segment having three CX gates and one X gate; A quantum circuit equipped with these features.

16. In the multi-step quantum ground state shift, when the step size is 2 i however, for the case where the step index i is a non-negative integer less than N If i < N-2 or i = N-2, the two CX gates of the starting segment are - The i+1th qubit (q) of the array register i+1 ) is used as the control corresponding to state |1>, and the first ancilla qubit (a) of the ancilla register is used. 1 ) CX gate targeting; - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the first ancilla qubit (a) of the ancilla register is used. 1 ) CX gate targeting; The quantum circuit according to claim 15, applied in the order of:

17. In the multi-step quantum ground state shift described above, the step size is 2 i In this case, however, the step index i is a non-negative integer less than N, If i < N-2 or i = N-2, the three CX gates of the terminal segment are: ・ Use the first ancilla qubit (a 1 ) of the ancilla register as a control corresponding to the state |1>, and target the (i + 2)-th qubit (q i+2 ) of the array register for a CX gate; - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the first ancilla qubit (a) of the ancilla register is used. 1 ) CX gate targeting; - The i+1th qubit (q) of the array register i+1 ) is used as the control corresponding to state |1>, and the first ancilla qubit (a) of the ancilla register is used. 1 ) CX gate targeting; The order in which they are applied is such that the i+1th qubit (q) of the array register is applied. i+1 The quantum circuit according to claim 15 or 16, wherein an X gate is applied to ).

18. In the multi-step quantum ground state shift described above, the step size is 2 i In this case, however, the step index i is a non-negative integer less than N, If i < N-2, the intermediate segment has one or more sets consisting of multiple CX gates and multiple 2-control gates, the number of sets depends on the total number of recursions, the value of k is initially equal to i+1 and is incremented by 1 with each recurrence until it reaches N-1, and the given sets corresponding to a given recurrence until k reaches N-2 are, in order, - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The first CX gate uses ) as its target; - The k-th qubit (q) of the array register k ) and the ki-1th ancila qubit of the ancila register (a k-i-1 ) is used as the control corresponding to state |1>, and the ki-th ancilla qubit (a k-i The first two control gates use ) as their target; - The ki-th ancila qubit (a k-i ) is used as the control corresponding to state |1>, and the k+1th qubit (q) of the array register is used. k+1 The second CX gate uses ) as its target; - The k-th qubit (q) of the array register k ) and the ki-1th ancila qubit of the ancila register (a k-i-1 ) is used as the control corresponding to state |1>, and the ki-th ancilla qubit (a k-i A second control gate that uses ) as its target; - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the k-th qubit (q) of the array register is used. k The third CX gate targets ); The quantum circuit according to any one of claims 15 to 17, wherein the (M+1)th set corresponding to the (M+1)th recursion of the given set is positioned after the first two control gates of the (M)th set corresponding to the (M)th recursion of the given set.

19. And in the intermediate segment, the last set corresponding to the last recursion when k reaches N-1 is, in order, - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the (N-1)th qubit (q) of the array register is used as the control for state |1>. N-1 ) CX gate targeting; - The (N-1)th qubit q of the array register N-1 and the N-2nd ancila qubit a of the aforementioned ancila register N-2 The control corresponding to state |1> is used, and the Nth qubit q of the array register is used. N Two control gates that use the target; - The superposition qubit (q) of the shift register N+1 ) is used as the control corresponding to state |1>, and the (N-1)th qubit (q) of the array register is used as the control for state |1>. N-1 ) CX gate targeting; The quantum circuit according to claim 18, wherein the last set corresponding to the last recursion is added following the first two control gates of the previous set corresponding to the recursion when k reaches N-2.

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